CN100565830C - Spatial packaging structure and method of manufacturing the same - Google Patents

Spatial packaging structure and method of manufacturing the same Download PDF

Info

Publication number
CN100565830C
CN100565830C CN 200610125646 CN200610125646A CN100565830C CN 100565830 C CN100565830 C CN 100565830C CN 200610125646 CN200610125646 CN 200610125646 CN 200610125646 A CN200610125646 A CN 200610125646A CN 100565830 C CN100565830 C CN 100565830C
Authority
CN
Grant status
Grant
Patent type
Prior art keywords
layer
conductive layer
body
pad
surface
Prior art date
Application number
CN 200610125646
Other languages
Chinese (zh)
Other versions
CN101131947A (en )
Inventor
余国宠
林千琪
王维中
罗建文
苏清辉
郑博仁
黄敏龙
Original Assignee
日月光半导体制造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked

Abstract

一种立体式封装结构及其制造方法,该制造方法包括以下步骤:(a)提供一半导性本体;(b)形成至少一盲孔在该半导性本体上;(c)形成一绝缘层在该盲孔的侧壁上;(d)形成一导电层在该绝缘层上;(e)图案化该导电层;(f)移除该半导性本体下表面的一部分以及该绝缘层的一部份,以暴露出该导电层的一部分;(g)形成一焊料在该导电层的下端;(h)堆叠复数个该半导性本体,并进行回焊;以及(i)切割该堆叠后的半导性本体,以形成复数个立体式封装结构。 A three-dimensional packaging structure and the manufacturing method, the method comprising the steps of: (a) providing a body half of the conductive; (b) at least one blind hole is formed in the semiconducting body; (c) forming an insulating layer on sidewalls of the blind hole; (d) forming a conductive layer on the insulating layer; removing a portion of the insulating layer and the semiconductive surface of the body (f),; (e) patterning the conductive layer part to expose a portion of the conductive layer; (G) is formed at a lower end of the solder layer, conductive; (H) stacking a plurality of the semiconductive body, and reflow; and (i) cutting the stack after the semiconductive body, to form a plurality of three-dimensional package structure. 藉此,该导电层的下端及其上的焊料“插入”下方的半导性本体的导电层所形成的空间中,从而使得该导电层与该焊料的接合更为稳固,并且接合后该立体式封装结构的整体高度可以有效地降低。 Accordingly, the lower end of the solder and the conductive layer on the "Insert" Space conductive layer underneath the semiconducting body being formed so that the engagement of the conductive layer and the solder more stable, and after joining the stereoscopic overall height of the packaging structure can be effectively reduced.

Description

立体式封装结构及其制造方法 Three-dimensional packaging structure and the manufacturing method

技术领域 FIELD

本发明涉及一种封装结构及其制造方法,特别是关于一种立体式封装结构及其制造方法。 The present invention relates to a package structure and a manufacturing method of a package structure and a manufacturing method particularly, to a three-dimensional.

背景技术 Background technique

图1为美国第4,499,65 5号专利所揭示的一种立体式封装结构在回焊前的示意图。 1 is a schematic of U.S. Patent No. 4,499,65 5 discloses a perspective view of the packaging structure before reflow. 该立体式封装结构1包括一第一单元10以及一第二单元20。 The three-dimensional packaging structure 1 comprises a first unit 10 and a second unit 20. 该第一单元10包括一第一半导性本体11、至少一第一孔12、 一第一导电层(conductive layer)13以及一第一焊料(solder)14。 The first unit 10 includes a first semiconductive body 11, at least a first hole 12, a first conductive layer (conductive layer) 13 and a first solder (solder) 14. 该第一半导性本体ll具有一第一表面lll以及一第二表面112, 该第一表面111具有至少一第一焊垫(未图示)以及一第一保护层(protection layer)113, 该第一保护层113暴露出该第一焊垫。 The first semiconductive body ll lll having a first surface and a second surface 112, 111 of the first surface having at least a first pad (not shown) and a first protection layer (protection layer) 113, the first protective layer 113 exposing the first pad. 该第一孔1 2贯穿该第一半导性本体11。 The first through hole 12 of the first semi-conductive body 11. 该第一导电层1 3位于该第一孔1 2的侧壁上,并覆盖该第一焊垫以及该第一保护层113。 The first conductive layer 13 located on a sidewall of the first hole 12 and covering the first pad 113 and the first protective layer. 该第一焊料1 4位于该第一孔12内,并透过该第一导电层13电气连接该第一焊垫。 The first solder 14 is in the first hole 12, and connected to the first pad through the first electrically conductive layer 13. 该第一焊料1 4上端延伸至该第一半导性本体U 的第一表面lll之上方,其下端延伸至该第一半导性本体ll的第二表面112的下方。 The first solder 14 to the upper end extending above the first surface of the first lll semiconductive body U, which is a lower end extending to the second surface of the first semiconductor body below 112 ll.

该第二单元20堆叠在该第一单元IO之上。 The second unit 20 stacked on top of the first unit IO. 该第二单元20包括一第二半导性本体21、至少一第二孔22、 一第二导电层2 3以及一第二焊料2 4。 The second unit 20 comprises a second semiconductive body 21, at least a second aperture 22, a second conductive layer 23 and a second solder 24. 该第二半导性本体21具有一第一表面211以及一第二表面212,该第一表面211具有至少一第二焊垫(未图示)以及一第二保护层2 13,该笫二保护层2 1 3暴露出该第二焊垫。 The second semi-conductive body 21 having a first surface 211 and a second surface 212, the first surface 211 having at least a second pad (not shown) and a second protective layer 213, the two Zi the protective layer 213 to expose the second pad. 该第二孔22贯穿该第二半导性本体2 1。 The second through hole 22 of the second semi-conductive body 21. 该第二导电层23位于该第二孔2 2的侧壁上,并覆盖该第二焊垫以及该第二保护层2 13。 The second conductive layer 23 is located on the sidewall of the second hole 22 and covering the second pad and the second protective layer 213. 该第二焊料2 4位于该第二孑L 22内,该第二焊料24透过该第二导电层2 3电气连接该第二焊垫。 The second solder 24 is located within the second larvae L 22, the second solder 24 is connected to the second pad 23 through the second electrically conductive layer. 该第二焊料24上端延伸至该第二半导性本体2 1的第一表面211的上方,其下端延伸至该第二半导性本体21的第二表面2 1 2的下方。 The upper end of the second solder 24 extends to above the first surface 2 of the 1211 second semiconductive body, the lower end thereof extends to a second surface of the second semi-conductive body 21 is below 212. 该第二焊料2 4的下端对准接触该第一焊料14的上端,经过回焊(reflow)后,使得该第一单元1 0以及该第二单元2 0接合而成为该立体式封装结构1 , 如图2所示。 The lower end of the second solder 24 in contact with an upper end aligned with the first solder 14, after reflow (reflow) passes, such that the first unit 10 and second unit 20 is engaged to the three-dimensional package 1 , as shown in picture 2.

在该立体式封装结构1中,该第一焊料1 4以及该第二焊料24的形成方式是将该第一半导性本体11以及该第二半导性本体21设置在一焊料浴(solder bath)的上方,利用毛细管现象使焊料进入该第一孔1 2以及第二孔22 ,而形成该第一焊料1 4以及该第二焊料24 。 In the three-dimensional structure of a package, the first solder 14 and the second solder 24 is formed so that the first semi-conductive body 11 and the second semi-conductive body 21 disposed in a solder bath (Solder Bath above), the solder by capillary action into the first hole 12 and second holes 22, 14 of the first solder and the second solder 24 is formed.

该立体式封装结构1的缺点如下:由于该第一焊料 The three-dimensional packaging structure 1 disadvantages as follows: Since the first solder

1 4以及该第二焊料24是利用毛细管现象所形成的,因此其上端以及下端均为半圆球状(图1 ),从而使该第一单元1 0以及该第二单元2 0在对准接合时,会增加对准的困难,而且回焊(refiow)后该第一单元IO以及该第二单元 14 and the second solder 24 is formed by capillarity, so the upper and lower ends are semi-sphere (FIG. 1), so that the first unit 10 and the second engagement means 20 when the alignment will increase the difficulty in alignment, and after reflow (refiow) of the first unit and the second unit IO

2 0之间的接合并不稳固。 20 engagement between the shaky. 此外,该等多余的半圆球状的焊料使得该第一单元1 0以及该第二单元2 0接合后,无法有效地降低整体高度。 Further, these extra semispherical solder 10 such that the first unit and the second rear engaging means 20 can not effectively reduce the overall height.

因此,有必要提供一种创新并具进步性的立体式封装结构及其制造方法,以解决上述问题。 Therefore, it is necessary to provide an innovative and having a progressive perspective package structure and a manufacturing method to solve the above problems.

6发明内容 SUMMARY 6

本发明的目的在于提供一种立体式封装结构的制造方法,包括提 Object of the present invention to provide a method of producing a three-dimensional package structure includes a reference to

供一半导性本体(semiconductor body),该半导性本体具有一第一表面以及一第二表面,该第一表面具有至少一焊垫以及一保护层(protection layer), 该保护层暴露出该焊垫,该制造方法进一步包括以下步骤: For half conductive body (semiconductor body), the semiconductive body having a first surface and a second surface, the first surface having at least one pad and a protection layer (protection layer), the protective layer exposes the pad, the manufacturing method further comprising the steps of:

(a)形成至少一盲孔在该半导性本体的第一表面; (b )形成一绝缘层(isolation 1 ayer)在该盲孔的侧 (A) forming a blind hole in at least a first surface of the semiconducting body; (b) forming an insulating layer (isolation 1 ayer) at the side of the blind bore

壁上; Wall;

(c) 形成一导电层(conductive layer), 该导电层覆盖该焊垫、该保护层以及该绝缘层; (C) forming a conductive layer (conductive layer), the conductive layer covers the pad, the protective layer and the insulating layer;

(d) 图案化该导电层; (D) patterning the conductive layer;

(e) 移除该半导性本体第二表面的一部分以及该绝缘层的一部份,以暴露出该导电层的一部分; (E) removing a portion of the insulating layer and the portion of the surface of the second semi-conductive body to expose a portion of the conductive layer;

(f) 形成一焊料在该导电层的下端;以及 (F) she is forming a solder at the lower end of the conductive layer;

(g) 堆叠复数个该半导性本体,并进行回焊(reflow)。 (G) stacking a plurality of the semiconductive body, and reflow (reflow).

与现有技术相比,在本发明中,由于该导电层的下端外露于该半导性本体的第二表面之下,因此在堆叠后的回焊制程中, 该导电层下端连同其焊料"插入"下方的半导性本体的盲孔中,因而使得上下两半导性本体的接合更为稳固,并且接合后该立体式封装结构的整体高度可以有效降低。 Compared with the prior art, in the present invention, since the lower end of the conductive layer exposed beneath a second surface of the semiconductive body, so after the reflow process in a stack, the lower conductive layer, together with its solder " insert "semiconductive body below the blind hole, so that the engagement of the upper and lower halves of the guide body more stable, and the overall height of the three-dimensional packaging structure after the bonding can be effectively reduced.

本发明的另一目的在于提供一种立体式封装结构,包括一第一单 Another object of the present invention is to provide a three-dimensional packaging structure, comprising a first single

元以及一第二单元。 Element and a second unit. 该第一单元包括: 一第一半导性本体、至少一 The first unit comprises: a first semiconductive body, at least a

第一孔、 一第一绝缘层、 一第一导电层以及一第一焊料。 A first hole, a first insulating layer, a first conductive layer and a first solder.

该第一半导性本体具有一第一表面以及一第二表面,该第一表面具有至少一第一坪垫以及一第一保护层,该第一保护层暴露出该 The first semi-conductive body having a first surface and a second surface, the first surface having at least a first floor and a first pad protection layer, the first protective layer to expose the

第一焊垫。 The first pad. 该第一孔贯穿该第一半导性本体。 The first hole through the first semiconductive body. 该第一绝缘层位于该第一孔的侧壁上。 A first insulating layer on the sidewall of the first hole. 该第一导电层覆盖该第一焊垫、部分该第一保护层以及该第一绝缘层,该第一导电层的下端延伸至该第一半导性本体的第二表面的下方。 The first conductive layer covers the first pad, a first portion of the protective layer and the first insulating layer, the lower end of the first conductive layer extends to below the second surface of the first semi-conductive body. 该第一焊料位于该第一孔内,该第一焊料透过该第一导电层电气连接该第一焊垫。 The first solder located at the first hole, the first solder pad connected to the first through the first electrically conductive layer.

该第二单元堆叠在该第一单元之上。 The second unit is stacked on top of the first unit. 该第二单元包括一第二半导性本体、至少一第二孔、 一第二绝缘层以及一第二导电层。 The second unit comprises a second semiconductive body, at least a second hole, a second insulating layer and a second conductive layer. 该第二半导性本体具有一第一表面以及一第二表面,该第一表面具有至少一第二焊垫以及一第二保护层,该第二保护层暴露出该第二焊垫。 The second semi-conductive body having a first surface and a second surface, the first surface having at least a second pad and a second protective layer, the second protective layer to expose the second pad.

该第二孔贯穿该第二半导性本体。 The second through-hole of the second semi-conductive body. 该第二绝缘层位于该第二孔的侧壁上。 The second insulating layer located on a sidewall of the second hole. 该第二导电层覆盖该第二焊垫、部分该第二保护层以及该第二绝缘层,该第二导电层的下端延伸至该第二半导性本体的第二表面的下方,并接触该第一焊料的上端。 The second conductive layer covering the second pad, the second portion of the protective layer and the second insulating layer, the lower end of the second conductive layer extend below the second surface of the second semi-conductive body and the contact the upper end of the first solder.

以下结合附图与实施例对本发明作进一步的说明。 Hereinafter, the present invention will be further described in conjunction with the accompanying drawings and embodiments.

附图说明 BRIEF DESCRIPTION

图1为美国第4,49 9,65 5号专利所揭示的立体式封装结构在回焊前的示意图; FIG 1 is a schematic view of U.S. Patent No. 5 4,49 9,65 perspective disclosed packaging structure before reflow;

图2显示美国第4,49 9,6 5 5号专利所揭示的立体式封装结构在回焊后的示意图; 2 shows a schematic view of U.S. Patent No. 4,49 9,6 55 disclosed in the three-dimensional packaging structure after reflow;

图3显示本发明立体式封装结构的制造方法的第一实施例的流程示意图; Figure 3 shows the flow of the first embodiment of the present invention is a method for producing three-dimensional schematic view of a package structure;

图4至图15显示本发明立体式封装结构的制造方法的第一实施例中各个制程步骤示意图; 4 to 15 show a first embodiment of a method for producing three-dimensional packaging structure of the present invention in a schematic view of the various process steps;

图16显示本发明立体式封装结构的制造方法的第二实施例的流程示意图; 16 shows the flow of the second embodiment of the present invention is a method for producing three-dimensional schematic view of a package structure;

图17至图18显示本发明立体式封装结构的制造方法的第二实施例中部分制程步骤示意图;以及 17 to 18 show a second embodiment of the manufacturing method of the three-dimensional structure of the present invention is packaged in a schematic section processing step; and

图19显示本发明立体式封装结构的剖视示意图。 Figure 19 shows a schematic perspective cross-sectional view of the packaging structure of the present invention.

具体实施方式 detailed description

有关本发明的详细说明以及技术内容,现就结合附图说明如 For detailed description and the technical contents of the present invention, will now be described in conjunction with the accompanying drawings as

下: under:

图3为本发明立体式封装结构的制造方法的第一实施例的流程示意图。 Flow diagram of a first embodiment of a method for producing three-dimensional packaging structure of the present invention FIG. 配合参考图4至图15,显示本发明立体式封装结构的制造方法的第一实施例中各个制程步骤示意图。 With reference to FIGS. 4 to 15, it shows a first embodiment of the present invention is a method for producing three-dimensional packaging structure in each process step FIG. 首先,配合参考图3以及图4,如步骤S301所示,提供一半导性本体(semiconductorbody)31。 First, with reference to FIGS. 3 and 4, as shown in step S301, there is provided a half-conductive body (semiconductorbody) 31. 该半导性本体31可以是一晶圓或是一芯片。 The semiconductive body 31 may be a wafer or a chip. 该半导性本体31具有一第一表面311 以及一第二表面312,该第一表面311具有至少一焊垫32以及一保护层(protection layer)33,该保护层33暴露出该焊垫32。 The semi-conductive body 31 having a first surface 311 and a second surface 312, the surface 311 having at least a first pad 32 and a protection layer (protection layer) 33, the protective layer 33 expose the pads 32 .

接着,配合参考图3以及图5,如步骤S302所示,形成至少一盲孔34 在该半导性本体31的第一表面311。 Next, with reference to FIG. 3 and FIG. 5, as shown in step S302, 34 is formed in the semiconductive body having a first surface 311 of the at least one blind hole 31. 在本实施例中,该盲孔34位于该焊垫32 的旁边。 In the present embodiment, the blind bore 34 is located next to the pad 32. 然而,在其它应用中,该盲孔34可贯穿该焊垫32。 However, in other applications, the blind hole 34 may extend through the pad 32.

接着,配合参考图3以及图6,如步骤S303所示,形成一绝缘层(isolation layer)35在该盲孔34的侧壁上。 Next, with reference to FIGS. 3 and 6, as shown in step S303, forming an insulating layer (isolation layer) 35 in the side wall 34 of the blind bore.

接着,配合参考图3以及图7,如步骤S304所示,形成一导电层(conductive layer)36,该导电层36覆盖该焊垫32、该保护层33以及该绝缘层35。 Next, with reference to FIGS. 3 and 7, as shown in step S304, forming a conductive layer (conductive layer) 36, the conductive layer 36 covers the pad 32, the protective layer 33 and the insulating layer 35. 该导电层36的材料为钛、铜、铜/钬合金或其它金属。 The material of the conductive layer 36 is titanium, copper, copper / holmium alloy or other metal.

接着,配合参考图3以及图8,如步骤S305所示,图案化该导电层36。 Next, with reference to FIGS. 3 and 8, as shown in step S305, the conductive layer 36 is patterned.

接着,配合参考图3以及图9,较佳地,如步骤S306所示,形成一钝化层(passivationlayer)37在该导电层36上,以保护该图案化的导电层36。 Next, with reference to FIG. 3 and FIG. 9, FIG Preferably, as step S306, the formation of a passivation layer (passivationlayer) 37 on the conductive layer 36 to protect the conductive layer 36 is patterned. 该钝化层37可以利用任何现有的方式形成。 The passivation layer 37 may be formed using any conventional manner. 此外,可以理解的是,本步骤为一选择性的步骤。 Further, it is understood that this step is an optional step.

接着,如步骤S307所示,移除该半导性本体31第二表面312的一部分以及该绝缘层35.的一部份,以暴露出该导电层36的一部分。 Subsequently, as shown in step S307, removing the semiconductive body 31 and a second surface portion of the insulating layer 35. The part 312 to expose a portion of the conductive layer 36. 参考图10,在本实施例中,先以背面研磨(backside grinding)的方式研磨该半导性本体31第二表面312,直到该第二表面312与该绝缘层35的下端切齐,即该绝缘层35的下端显露于该第二表面312。 Referring to FIG 10, in the present embodiment, prior to grinding the back surface (backside grinding) grinding the manner semiconductive second surface 312 of the body 31, until the lower end surface 312 of the second insulating layer 35 is cut flush, i.e. the lower insulating layer 35 is exposed to the second surface 312. 接着,再蚀刻该半导性本体31第二表面312以及该绝缘层35的下端,以暴露出该导电层36的下端,此时该导电层36的下端延伸至该半导性本体31的第二表面312的下方,如图ll所示。 Next, the semiconductive then etching the body 31 the lower end surface 312 and a second insulating layer 35 to expose the lower conductive layer 36, in which case the lower end of the conductive layer 36 extends through the body 31 of semiconductive two of the lower surface 312, as shown in FIG ll. 然而, 可以理解的是,在其它应用中,可以不使用该背面研磨的方式,而直接以蚀刻方式加工该半导性本体31第二表面312,以暴露出该导电层36的下端。 However, it will be appreciated that, in other applications, may not be used the way back grinding, is directly processed by etching the second semi-conductive surface 312 of the body 31 to expose the lower conductive layer 36.

接着,配合参考图3以及图12,较佳地,如步骤S308所示,形成一阻绝层(barrier layer)38在该导电层36的下端,该阻绝层38覆盖该暴露的导电层36的下端。 Next, with reference to FIGS. 3 and 12, preferably, as shown in step S308, forming a barrier layer (barrier layer) 38 at the lower end of the conductive layer 36, the barrier layer 38 covers the lower end of the exposed conductive layer 36 . 该阻绝层38可以是镍、铬、铬/铜合金或其它金属。 The resist layer 38 may be a nickel, chromium, chromium / copper alloys or other metals. 可以理解的是, 本步骤为一选对奪性的步骤。 It will be appreciated that this step is a step selected from a pair of wins.

接着,配合参考图3以及图B,如步骤S309所示,形成一焊料39 附着在该导电层36的下端。 Next, with reference to FIG. 3 and FIG. B, as shown in step S309, a solder 39 is formed at a lower end attached to the conductive layer 36. 可以理解的是,该焊料39可以利用例如电镀(plating)或其它现有的方式形成。 It will be appreciated that the solder 39 may be by plating (plating) or other form, for example a conventional manner.

接着,配合参考图3以及图14,如步骤S310所示,堆叠复数个该半导性本体31,其中位于上方的半导性本体31的焊料39对准位于下方的半导性本体31的导电层36所形成的空间。 Next, with reference to FIG. 3 and FIG. 14, as shown in step S310, the stacked plurality of the semiconductive body 31, which is positioned above the conductive semiconductive body 39 is aligned with the solder 31 is positioned below the body 31 of semiconductive spatial layer 36 is formed.

接着,配合参考图3以及图15,如步骤S311所示,进行回焊(reflow) 制程,使得位于上方的半导性本体31的焊料39熔融在下方的半导性本体31的导电层36所形成的空间内,因此上下两半导性本体31透过该导电层36以及该焊料39的熔接而接合在一起。 Next, with reference to FIG. 3 and FIG. 15, in step S311, the reflowing (reflow) process, so that the semiconductive body is located above the solder 39 molten conductive layer underneath the semiconducting body 31 of 36 in 31 a space is formed, the conductive layer 31 through fusion of the solder 36 and 39 is thus joined together upper and lower halves of the guide body. 最后,如步骤S312所示,切割该堆叠后的半导性本体31,以形成复数个立体式封装结构40。 Finally, as shown in step S312, after cutting the semiconductive stack body 31, so as to form a plurality of three-dimensional packaging structure 40. 较佳地,如步骤S313所示,形成至少一焊球43在该立体式封装结构40的下方,该焊球43由位于最下方的半导性本体31内的该导电层36下端的焊料39所形成。 At least one of the solder balls 43 beneath the three-dimensional package structure 40, the lower end 36 of the conductive layer 31 within the solder balls 43 from the semiconductive body positioned lowermost solder Preferably, as shown in step S313, 39 is formed formed. 可以理解的是, 本步骤为一选择性的步骤。 It will be appreciated that this step is an optional step.

图16为本发明立体式封装结构的制造方法的第二实施例的流程示意图。 Flow of the second embodiment of the manufacturing method of FIG. 16 a perspective view of the packaging structure of the present invention. FIG. 本实施例的步骤S401至S409与第一实施例的步骤S301 至S309完全相同。 To step S409 of the first embodiment of the steps of the present embodiment is the same as S401 S301 to S309. 本实施例与该第一实施例不同之处在于:在本实施例的步骤S410切割该半导性本体31,以形成复数个单元41 、 42。 This embodiment differs from the first embodiment in that the embodiment: In this embodiment the step S410 to cut the semiconductive body 31 to form a plurality of cells 41, 42. 接着,步骤S411堆叠该等单元41、 42,其中上下两半导性本体31的该导电层36以及该焊料39互相对准,如图17所示。 Next, step S411 such stacking unit 41, 42, wherein the upper and lower halves of the conductive body 31 of the conductive layer 36 and solder 39 are aligned with each other, shown in Figure 17. 最后,步骤S412进行回焊(reflow), 以形成复数个立体式封装结构40,如图18所示。 Finally, Step S412 reflowing (reflow), to form a plurality of three-dimensional package structure 40, as shown in FIG. 本实施例所制得的该立体式封装结构40(图18)与该第一实施例所制得的该立体式封装结构40(图15)完全相同。 40 (FIG. 18) with the three-dimensional packaging structure of the obtained the first embodiment 40 (FIG. 15) identical to the three-dimensional packaging structure of the present embodiment was prepared.

较佳地,步骤S413形成至少一焊球43在该立体式封装结构40的下方,该悍球43位于最下方的半导性本体31内的该导电层36的下端。 Preferably, at least the lower end of a step S413 solder ball 43 is formed below the perspective view of the packaging structure 40, the ball 43 is located lowermost defended semiconductive body of the conductive layer 36 within the 31. 可以理解的是,本步骤为一选择性的步骤。 It will be appreciated that this step is an optional step. 图19为本发明立体式封装结构的剖视示意图。 Perspective cross-sectional view of the packaging structure 19 of the present invention, FIG. 本图的立体式封装结构5与图15以及图18所示的立体式封装结构40完全相同, 但是为了便于说明,相同元件赋予不同的标号。 This three-dimensional packaging structure of FIG. 5 and FIG. 15 and shown in perspective view in FIG packaging structure 1840 is identical, but for convenience of explanation, the same elements assigned different reference numerals. 该立体式封装结构5包括一第一单元50以及一第二单元60。 The three-dimensional packaging structure unit 5 comprises a first 50 and a second unit 60. 该第一单元50包括一第一半导性本体51、至少一第一孔52、 一第一绝缘层(isolation layer)53、 一第一导电层(conductive layer)54以及一第一焊料55。 The first unit 50 includes a first semiconductive body 51, at least a first hole 52, a first insulating layer (isolation layer) 53, a first conductive layer (conductive layer) 54 and a first solder 55.

该第一半导性本体51为一晶圆或芯片,具有一第一表面511以及一第二表面512,该第一表面511具有至少一第一焊垫513以及一第一保护层514,该第一保护层514暴露出该第一焊垫513。 The first semi-conductive body 51 is a wafer or chip, having a first surface 511 and a second surface 512, 511 of the first surface having at least a first pad 513 and a first protective layer 514, the a first protective layer 514 to expose the first pad 513. 该第一孔52贯穿该第一半导性本体51,在本实施例中,该第一孔52位于该第一焊垫513的旁边。 The first through-hole 52 of the first semi-conductive body 51, in the present embodiment, the first hole 52 is located next to the first pad 513. 然而,在其它应用中,该第一孔52可贯穿该第一焊垫513。 However, in other applications, the first hole 52 may extend through the first pad 513.

该第一绝缘层53位于该第一孔52的侧壁上。 The first insulating layer 53 located on a sidewall of the first hole 52. 该第一导电层54 覆盖该第一焊垫513、部分该第一保护层514以及该第一绝缘层53, 该第一导电层54的下端是相连接的,并延伸至该第一半导性本体51的第二表面512的下方。 The first conductive layer 54 covering the first pad 513, a first portion of the protective layer 514 and the first insulating layer 53, the lower end of the first conductive layer 54 is connected to, and extending to the first semiconductor the lower surface 512 of the second body 51. 较佳地,该第一单元50进一步包括一第一阻绝层(barrierlayer)(未图示),覆盖该第一导电层54的下端。 Preferably, the first unit 50 further comprises a first barrier layer (barrierlayer) (not shown), covering the lower end of the first conductive layer 54. 较佳地,该第一导电层54上方进一步包括一钝化层(passivation layer)(未图示)覆盖该第一导电层54,以保护该第一导电层54。 Preferably, the first conductive layer 54 above further comprising a passivation layer (passivation layer) (not shown) covering the first conductive layer 54, to protect the first conductive layer 54.

该第一焊料55位于该第一孔52内并位于第一导电层54上, 该第一焊料55透过该第一导电层54电气连接该第一焊垫5 13。 The first solder 55 located within the first bore 52 and positioned on the first conductive layer 54, the first solder 55 is connected through the first electrically conductive layer 54 of the first pad 513.

该第二单元60堆叠在该第一单元50之上。 The second unit 60 stacked on top of the first unit 50. 该第二单元60包括一第二半导性本体61、至少一第二孔62、 一第二绝缘层(isolation layer)63以及一第二导电层(conductive layer)64。 The second unit 60 comprises a second semiconductive body 61, at least a second hole 62, a second insulating layer (isolation layer) 63 and a second conductive layer (conductive layer) 64. 该第二半导性本体61为一晶圓或芯片,具有一第一表面61】以及一第二表面6U,该第一表面611具有至少一第二焊垫613以及一第二保护层(protection layer)614,该第二保护层614暴露出该第二焊垫6l3。 The second semi-conductive body 61 is a wafer or chip, having a first surface and a second surface 61] 6U, the first surface 611 having at least one second pad 613 and a second protective layer (Protection layer) 614, the second protective layer 614 to expose the second pad 6l3. 该第二孔62 贯穿该第二半导性本体61,在本实施例中,该第二孔62位亍该第二焊垫613的旁边。 The second through hole 62 of the second semi-conductive body 61, in the present embodiment, the second hole 62 next to the right foot pad 613 second. 然而,在其它应用中,该第二孔62可贯穿该第二焊垫613。 However, in other applications, the second bore 62 may extend through the second pad 613.

该第二绝缘层63位于该第二孔62的侧壁上。 The second insulating layer 63 is located on the sidewall of the second hole 62. 该第二导电层64 覆盖该第二焊垫613、部分该第二保护层614以及该第二绝缘层63, 该第二导电层64的下端是相连接的,并延伸至该第二半导性本体61的第二表面612的下方,并接触该第一焊料55的上端。 The second conductive layer 64 covering the second pad 613, a second portion of the protective layer 614 and the second insulating layer 63, the lower end of the second conductive layer 64 is connected to, and extending to the second semiconductor the lower surface 612 of the second body 61, and contacts the upper end 55 of the first solder. 较佳地, 该第二单元60进一步包括一第二阻绝层(未图示),覆盖该第二导电层64的下端。 Preferably, the second unit 60 further comprises a second barrier layer (not shown), covering the lower end of the second conductive layer 64. 较佳地,该第二导电层64上方进一步包括一钝化层(未图示)覆盖该第二导电层64,以保护该第二导电层64。 Preferably, the second conductive layer 64 above further comprising a passivation layer (not shown) to cover the second conductive layer 64, to protect the second conductive layer 64.

此外,如果需要的话,可以将一第二焊料(未图示)填入该第二孔62内。 Further, if desired, may be a second solder (not shown) is filled into the second bore 62. 因此,在本发明中,该第二孔62可以是空的或是另外再填入该第二焊料。 Accordingly, in the present invention, the second aperture 62 may be an additional empty or fill the second solder. 较佳地,该立体式封装结构5进一步包括至少一焊球43,位于该第一导电层54的下端。 Preferably, the three-dimensional package structure 5 further comprises at least one ball 43, at the lower end of the first conductive layer 54.

与现有技术相比,本发明立体式封装结构5中,由于该第二导电层64的下端及其上的焊料39外露于该第二单元60的第二表面612之下,因此在回焊的制程中,该第二导电层64的下端及其上的焊料39"插入"该第一导电层54所形成的空间内,并且该焊料39熔融在该第一导电层54所形成的空间内而形成该第一焊料55。 Compared with the prior art, the present invention is three-dimensional package structure 5, since the lower end of the second solder layer 64 and conductive 39 is exposed on the second surface 612 beneath the second unit 60, so reflow in the process, the solder on the lower end 64 and second conductive layer 39 "inserted" within the space of the first conductive layer 54 is formed, and the molten solder 39 is formed on the first conductive layer 54 in the space and the first solder 55 is formed. 藉此,可使得该第一导电层54以及该第二导电层64之间的接合更为稳固。 Thereby, it may be such that the first conductive layer 54 and the second conductive layer 64 more stable engagement between the. 此外, 该第一孔52以及该第二孔62可以设计成如图中所示的锥状,以进一步增加上述的接合效果。 In addition, the first hole 52 and second hole 62 may be designed as shown in FIG tapered to further increase the effect of the above-described engagement. 另外,由于该第二导电层64的下端"插入"该第一焊料55中,因此接合后该立体式封装结构5的整体高度可以有效降低。 Further, since the lower end of the second conductive layer 64 "inserted" in the first solder 55, so that the overall three-dimensional packaging structure 5 can effectively reduce the height of the rear engagement.

Claims (9)

  1. 1、一种立体式封装结构的制造方法,包括提供一半导性本体,该半导性本体具有一第一表面以及一第二表面,该第一表面具有至少一焊垫以及一保护层,该保护层暴露出该焊垫,其特征在于:该制造方法进一步包括以下步骤: (a)形成至少一盲孔在该半导性本体的第一表面; (b)形成一绝缘层在该盲孔的侧壁上; (c)形成一导电层,该导电层覆盖该焊垫、该保护层以及该绝缘层; (d)图案化该导电层; (e)移除该半导性本体第二表面的一部分以及该绝缘层的一部份,以暴露出该导电层的一部分; (f)形成一焊料在该导电层的下端; (g)堆叠复数个该半导性本体,并进行回焊;以及(h)切割该堆叠后的半导性本体,以形成复数个立体式封装结构。 1, a method for producing three-dimensional packaging structure, comprising providing a half of the conductive body, the semiconductive body having a first surface and a second surface, the first surface having at least one pad and a protective layer, which the protective layer exposing the pad, wherein: the manufacturing method further comprising the steps of: (a) forming a first surface of at least a blind hole in the semiconducting body; (b) forming the insulating layer in a blind bore on the side walls; (c) forming a conductive layer, the conductive layer covers the pad, the protective layer and the insulating layer; (d) patterning the conductive layer; (e) removing the second semiconductive body a portion of the surface and a portion of the insulating layer to expose a portion of the conductive layer; (f) forming a solder lower end of the conductive layer; (G) stacking a plurality of the semiconductive body, and reflowing ; and after (h) cutting the semiconductive stacked body to form a plurality of three-dimensional package structure.
  2. 2、 如权利要求l所述的制造方法,其特征在于进一步包括一形成至少一焊球在该立体式封装结构的下方的步骤。 2. The manufacturing method according to claim l, characterized in that at least one further step of the solder balls below the three-dimensional structure of the package comprises a formed.
  3. 3、 如权利要求l所述的制造方法,其特征在于该盲孔是位于该焊垫旁或贯穿该焊垫。 3, the manufacturing method as claimed in claim l, characterized in that the blind hole is located beside the pad or through the pads.
  4. 4、 如权利要求l所述的制造方法,其特征在于步骤(d)之后进一步包括一形成一钝化层在该导电层上的步骤,以保护该图案化的导电层。 4, the manufacturing method as claimed in claim l, characterized in that after step (d) further comprises the step of a passivation layer on the conductive layer is formed, and in order to protect the patterned conductive layer.
  5. 5、 如权利要求l所述的制造方法,其特征在于步骤(e)之后进一步包括一形成一阻绝层的步骤,该阻绝层覆盖该暴露的导电层。 5, the manufacturing method as claimed in claim l, characterized in that after step (e) further comprises the step of forming a barrier layer of a conductive layer covering the exposed layer of the denial.
  6. 6、 一种立体式封装结构,包括: 一第一单元,包括:一 第一半导性本体, 具有 一第 一表面 以及一第二表面,该第一 表面具有至少一第 一焊 垫以 及一第 一保护层,该第一保护层 暴露出该第一焊垫 ;至 少一 第一孔 ,贯穿该第一半导性本体 ; 一第一导电层, 覆盖 该第 一焊 以及部分该第一保护层; 以及一第一焊料, 位于 该第 一孔内 ,该第一焊料透过该第一 导电层电气连接该 第一 焊垫 ; 以及一第二单元,堆叠在该第一单元之上,该第二单元包4舌:一第二半导性本体 , 具 有一 第 一表面以及一第二表面, 该第一表面具有至少一 第二 焊垫 以 及一第二保护层,该第二 保护层暴露出该第二焊 垫; 至少 一 第二孔,贯穿该笫二半导 性本体;以及一第二导 电层 ,覆 盖 该第二焊垫以及部分该第 二保护层; 其特征在于: 该第 一单 元 进一步包括 6. A three-dimensional packaging structure, comprising: a first unit, comprising: a first semiconductive body having a first surface and a second surface, the first surface having at least a first pad and a a first protective layer, the first protective layer to expose the first pad; at least a first aperture through the first semi-conductive body; a first conductive layer, covering the first bead and a first portion of the protective layer; and a first solder, located at the first hole, the first solder pad connected to the first through the first electrically conductive layer; and a second unit stacked on top of the first unit, the the second unit 4 of the tongue packet: a second semiconductive body having a first surface and a second surface, the first surface having at least a second pad and a second protective layer, the second protective layer is exposed that the second pad; at least a second aperture, through which two semiconductive Zi body; and a second conductive layer covering the second pad portion and the second protective layer; wherein: the first unit further comprises 第一绝缘层 ,位于该第一孔的侧壁上;该第一导电层覆盖该第一绝缘层并位于该第一孔内,该第一导电层下端是相连接的并突伸出该第一半导性本体的第二表面的下方;该第一焊料位于第一孔内并位于该第一导电层上;该第二单元进一步包括一第二绝缘层,位于该第二孔的侧壁上;该第二导电层覆盖该第二绝缘层并位于该第二孔内, 该第二导电层下端是相连接的并突伸出该第二半导性本体的第二表面的下方,并伸入笫一单元的第一孔与第一焊料的上端接触。 A first insulating layer on a sidewall of the first hole; the first conductive layer covers the first insulating layer and located at the first hole, the lower end of the first conductive layer is connected to the protruding section and the second half of the lower surface of the guide body; located in the first bore and a first solder disposed on the first conductive layer; the second cell further comprises a second insulating layer, a second side wall of the bore on; the second conductive layer covering the second insulating layer and is located in the second bore, the lower end of the second conductive layer is connected to and projecting below the second surface of the second semi-conductive body extends, and the first aperture extends into contact with the undertaking of a unit of the upper end of the first solder.
  7. 7、 权利要求6所述的立体式封装结构,其特征在于该第一孔是位于该第一焊垫旁或者贯穿该第一焊垫,而该第二孔也是位于该第二焊垫旁或者贯穿该第二焊垫。 7, three-dimensional packaging structure according to claim 6, characterized in that the first orifice is located next to the pad or the first through the first pad, and the second aperture is positioned adjacent the second pad or through the second pad.
  8. 8、 如权利要求6或7所述的立体式封装结构,其特征在于该第一单元进一步包括一第一钝化层,覆盖该第一导电层;该第二单元进一步包括一第二钝化层,覆盖该第二导电层。 8, three-dimensional packaging structure as claimed in claim 6 or claim 7, wherein the first unit further comprises a first passivation layer covering the first conductive layer; the second cell further comprises a second passivation layer covering the second conductive layer.
  9. 9、 如权利要求6或7所述的立体式封装结构,其特征在于该第一单元进一步包括一第一阻绝层,覆盖该第一导电层的下端;该第二单元进一步包括一第二阻绝层,覆盖该第二导电层的下端。 A denial of the second unit further comprises a second; 9, three-dimensional packaging structure as claimed in claim 6 or claim 7, wherein the first unit further comprises a first barrier layer, the first conductive layer covering the lower end layer covering the lower end of the second conductive layer.
CN 200610125646 2006-08-25 2006-08-25 Spatial packaging structure and method of manufacturing the same CN100565830C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 200610125646 CN100565830C (en) 2006-08-25 2006-08-25 Spatial packaging structure and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 200610125646 CN100565830C (en) 2006-08-25 2006-08-25 Spatial packaging structure and method of manufacturing the same

Publications (2)

Publication Number Publication Date
CN101131947A true CN101131947A (en) 2008-02-27
CN100565830C true CN100565830C (en) 2009-12-02

Family

ID=39129146

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 200610125646 CN100565830C (en) 2006-08-25 2006-08-25 Spatial packaging structure and method of manufacturing the same

Country Status (1)

Country Link
CN (1) CN100565830C (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859746B (en) 2009-04-07 2012-06-27 宏齐科技股份有限公司 Conductive substrate structure for forming conductive channel by two-sided cutting and manufacturing method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8963316B2 (en) * 2012-02-15 2015-02-24 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5266912A (en) 1992-08-19 1993-11-30 Micron Technology, Inc. Inherently impedance matched multiple integrated circuit module
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US6903442B2 (en) 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts
US20050224921A1 (en) 2001-05-01 2005-10-13 Subhash Gupta Method for bonding wafers to produce stacked integrated circuits
CN1812075A (en) 2004-12-24 2006-08-02 精工爱普生株式会社 Method of manufacturing semiconductor device, semiconductor device, stacked semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5266912A (en) 1992-08-19 1993-11-30 Micron Technology, Inc. Inherently impedance matched multiple integrated circuit module
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US20050224921A1 (en) 2001-05-01 2005-10-13 Subhash Gupta Method for bonding wafers to produce stacked integrated circuits
US6903442B2 (en) 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts
CN1812075A (en) 2004-12-24 2006-08-02 精工爱普生株式会社 Method of manufacturing semiconductor device, semiconductor device, stacked semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859746B (en) 2009-04-07 2012-06-27 宏齐科技股份有限公司 Conductive substrate structure for forming conductive channel by two-sided cutting and manufacturing method thereof

Also Published As

Publication number Publication date Type
CN101131947A (en) 2008-02-27 application

Similar Documents

Publication Publication Date Title
US6740980B2 (en) Semiconductor device
US5898223A (en) Chip-on-chip IC packages
KR101011863B1 (en) Semiconductor package and fabricating?method thereof
US20010008309A1 (en) Interconnection substrate having metal columns covered by a resin film, and manufacturing method thereof
US6765288B2 (en) Microelectronic adaptors, assemblies and methods
US5783870A (en) Method for connecting packages of a stacked ball grid array structure
US7598613B2 (en) Flip chip bonding structure
US6504244B2 (en) Semiconductor device and semiconductor module using the same
US20020149105A1 (en) Flip chip type semiconductor device and method of fabricating the same
US20060202347A1 (en) Through electrode, package base having through electrode, and semiconductor chip having through electrode
US20030173678A1 (en) Semiconductor device and method for fabricating the same
US20060049495A1 (en) Semiconductor package and laminated semiconductor package
KR20010094894A (en) Semiconductor package and its manufacturing method
US20080117608A1 (en) Printed circuit board and fabricating method thereof
US7741152B2 (en) Three-dimensional package and method of making the same
US6911723B2 (en) Multiple die stack apparatus employing T-shaped interposer elements
JPH11297873A (en) Semiconductor device and its manufacture
US7528053B2 (en) Three-dimensional package and method of making the same
US6250606B1 (en) Substrate for semiconductor device, semiconductor device and manufacturing method thereof
US20040227251A1 (en) Semiconductor device and method for fabricating semiconductor device
US7642132B2 (en) Three-dimensional package and method of making the same
JP2006522461A (en) Method for producing a three-dimensional device
JP2009004730A (en) Self matching wafer or chip structure, self matching laminate structure, and manufacturing method thereof
US6743979B1 (en) Bonding pad isolation
JP2006261311A (en) Semiconductor device and its manufacturing method

Legal Events

Date Code Title Description
C06 Publication
C10 Request of examination as to substance
C14 Granted