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CN100539173C - CMOS image sensor and method for forming same - Google Patents

CMOS image sensor and method for forming same Download PDF

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CN100539173C
CN100539173C CN 200710041164 CN200710041164A CN100539173C CN 100539173 C CN100539173 C CN 100539173C CN 200710041164 CN200710041164 CN 200710041164 CN 200710041164 A CN200710041164 A CN 200710041164A CN 100539173 C CN100539173 C CN 100539173C
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cmos
image
sensor
method
forming
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CN101312201A (en )
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徐锦心
虹 朱
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中芯国际集成电路制造(上海)有限公司
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一种CMOS图像传感器,包括至少一个CMOS图像传感器像素单元对,所述CMOS图像传感器像素单元对包括第一像素单元和第二像素单元;CMOS图像传感器中每个所述像素单元包括光电二极管区域和驱动电路区域;其中,驱动电路区域包括有输出晶体管;第一像素单元和第二像素单元的相邻的两个输出晶体管的漏极相连,作为共用输出端。 A CMOS image sensor, a CMOS image sensor comprising at least one pixel unit, pixels of the CMOS image sensor unit cell comprises a first pixel and a second pixel unit; CMOS image sensor in each of the pixel unit includes a photodiode region and a driving circuit region; wherein the driving circuit comprises an output transistor region; a drain connected to the first pixel adjacent to the pixel unit and the second unit of the two output transistors, as a common output terminal. 本发明还给出另一种CMOS图像传感器,通过相邻像素单元共用输出晶体管的输出接触孔和电源接触孔,降低了有效接触孔数量。 The present invention also gives another CMOS image sensor, a common output transistor through contact holes adjacent pixel cell output power and the contact holes, reducing the effective number of contact holes. 这种结构使得能够在没有降低技术节点条件下设计更小尺寸的像素单元,不需要修改外围电路和工艺参数,不会增加掩模和工艺成本,降低了输出电容,提高了填充比和光学路径。 This configuration makes it possible to design technology node does not decrease under conditions pixel unit smaller size, no need to modify process parameters, and a peripheral circuit, and the mask will not increase the process cost, reduced output capacitance, improve the filling ratio and the optical path .

Description

CMOS图像传感器及其形成方法 CMOS image sensor and a method of forming

技术领域 FIELD

本发明涉及半导体技术领域,特别涉及一种CMOS图像传感器及其形成方法。 The present invention relates to semiconductor technology, and particularly relates to a CMOS image sensor and method.

背景技术 Background technique

目前电荷耦合器件(charge coupled device, CCD)是主要的实用化固态图像传感器件,具有读取噪声低、动态范围大、响应灵敏度高等优点,但是CCD 同时具有难以与主流的互补金属氧化物半导体(Complementary - Metal -Oxide - Semiconductor, CMOS)技术相兼容的缺点,即以CCD为基础的图像传感器难以实现单芯片一体化。 Currently a charge coupled device (charge coupled device, CCD) is a major practical solid-state image sensing device having low read noise, wide dynamic range, high sensitivity response, but it is difficult to have both the CCD mainstream complementary metal oxide semiconductor ( Complementary - Metal -Oxide - Semiconductor, CMOS) technology compatible with the disadvantage that a CCD-based image sensor is difficult to achieve single-chip integration. 而CMOS图像传感器(CMOS Image sensor, CIS)由于采用了相同的CMOS技术,可以将像素阵列与外围电路集成在同一芯片上,与CCD相比,CIS具有体积小、重量轻、功耗低、编程方便、易于控制以及平均成本低的优点。 The CMOS image sensor (CMOS Image sensor, CIS) As a result of the same CMOS technology, the pixel array and the peripheral circuit are integrated on the same chip, compared to the CCD, CIS having a small size, light weight, low power consumption, programming convenient, easy to control and the low average cost.

当前,有关CMOS图像传感器的专利申请文件基本集中在如何减小CMOS 图像传感器的暗电流方面,比如通过在隔离结构的外围形成P+型外延层,以减少在隔离结构的边界中产生的电子再结合从而达到减少暗电流的目的,在申请号为200510097488的中国专利申请中还可以发现更多与上述技术方案相关的信息。 Currently, about the CMOS image sensor of the patent application is concentrated in the dark current is how to reduce the CMOS image sensor, such as P + type epitaxial layer is formed by a peripheral spacer structure to reduce the electrons generated in the boundary of the isolation structure recombination thus to decrease dark current, in Chinese Patent application No. 200510097488 can also be found in more information related to the above technical solutions. 现有技术还通过在p型的像素单元阵列区域之下形成n掺杂区以把像素单元区域与外围电路区域进行隔离,以减少暗电流,在专利号为7205584 的美国专利中还可以发现更多与上述技术方案相关的信息。 The prior art also by forming the n-doped region below the pixel unit array to the region of the p-type isolation region pixel cell region and the peripheral circuit, to reduce the dark current as in U.S. Patent No. 7,205,584 can also be found in more and more information related to the above technical solution. 据笔者所知,对于如何减小CMOS图像传感器的像素单元的尺寸目前尚无报道。 As far as I know, how to reduce the pixel cells for CMOS image sensor size is currently no reports.

通常,CMOS图像传感器包括阵列的像素单元,每个像素单元通常包括三个晶体管和一个用于吸收入射光并转换为光电流的光电二极管。 Typically, CMOS image sensors include an array of pixel cells, each pixel cell typically includes three transistors and a converter for absorbing incident light and a photodiode photocurrent. 图1A给出一个三个晶体管的像素单元电路,包括光电二极管PD、第一晶体管T1、第二晶 FIG 1A is given a three transistor pixel circuit unit includes a photodiode PD, a first transistor T1, a second crystal

体管T2和第三晶体管T3,其中光电二极管PD正极接地,负极与第一晶体管T1 的源极相连;第一晶体管T1的栅极与复位控制电路相连(Reset)、漏极与第二晶体管T2的漏极相连且与外围电源电路相连以提供Vdd电压;第二晶体管T2的栅极与光电二极管的负极相连、源极与第三晶体管T3的源极相连;第三晶体管T3的栅极与行选电路(Row select)相连、漏极与输出电路(Output) 相连。 Transistor T2 and the third transistor T3, wherein the cathode of the photodiode PD is grounded, and a source connected to the negative electrode of the first transistor T1; the gate of the first transistor T1 is connected to the reset control circuit (the Reset), the drain of the second transistor T2 and a drain connected to the peripheral circuit connected to provide a power supply voltage Vdd; a gate connected to the anode of the photodiode of the second transistor T2, the source electrode and the source electrode of the third transistor T3 is connected to; third transistor T3, a gate row selection circuit (Row select) a drain connected to the circuit output (output) is connected. 第一晶体管T1 (复位晶体管)用于将光电二极管PD结点电压重置;第二晶体管T2 (源跟随晶体管)用于接收和放大光电二极管结点的电势变化; 第三晶体管T3 (输出晶体管)用于选择读出行。 The first transistor T1 (reset transistor) for the photodiode PD reset voltage node; a second transistor T2 (source follower transistor) for receiving and amplifying the potential change of the photodiode junction; a third transistor T3 (output transistor) for selecting reading travel.

图1A电路的布局设计图如图1B所示,半导体衬底101中形成有用于将有源区隔离的隔离槽102,隔离槽102以外区域为有源区;在有源区形成有光电二极管以及在有源区沿着AA,依次形成复位晶体管、源跟随晶体管和输出晶体管的初f极103、 104、 105;在半导体衬底101中在光电二极管区域形成有深掺杂阱110;复位晶体管和源跟随晶体管漏极共用、源跟随晶体管和输出晶体管的源极共用。 1A the layout of the circuit of FIG. 1B, the active area isolations for isolation grooves 102 formed in the semiconductor substrate 101, isolation trenches 102 a region other than an active region; forming a photodiode in an active region, and along AA, are sequentially formed in the active region of the reset transistor, source follower transistor and the beginning f the output transistor 103, 104, 105; photodiode region formed in the semiconductor substrate 101 doped deep well 110; reset transistor, and the common drain of the source follower transistor, the source follower transistor and the source of the output transistor are shared. 同时,图1C给出图1B的沿AA,处的剖面示意图。 Meanwhile, FIG. 1C is given along AA in FIG. 1B, a schematic cross-sectional view at. 半导体衬底101中形成有隔离槽102以及光电二极管110,在半导体衬底101上形成有复位晶体管、源跟随晶体管以及输出晶体管的栅介质层117、 118及119; 位于栅介质层117、 118及119上的栅极103、 104及105;位于半导体衬底101中的复位晶体管的栅极103两侧的源极106、漏极107,所述复位晶体管的漏极107与源跟随晶体管的漏极共用;位于半导体衬底101中的源跟随晶体管栅极另一侧的源极108,所述源跟随晶体管的源极108与输出晶体管的源极共用,位于半导体衬底101中的输出晶体管栅极另一侧的漏极109。 The semiconductor substrate 101 is formed with an isolation groove 102 and a photodiode 110, a reset transistor formed on the semiconductor substrate 101, source follower transistor gate dielectric layer 117 and an output transistor, 118 and 119; a gate dielectric layer 117, 118 and 119 on the gate 103, 104 and 105; source 103 of the semiconductor substrate on both sides of the gate 101 the reset transistor 106, the drain electrode 107, the drain of the reset transistor 107 and source follower transistor common; a source follower transistor gate on the other side of the semiconductor substrate 101 a source 108, the source follower transistor, the source electrode 108 and the common source of the output transistor, the output transistor gate is located in the semiconductor substrate 101 the drain 109 of the other side. 在半导体衬底101上形成有第一介质层111,结合图1B和1C,在第一介质层111 中对着深掺杂阱110位置处、复位晶体管、源跟随晶体管和输出晶体管的栅极103、 104和105位置处、复位晶体管和源跟随晶体管共用的漏极107以及 Is formed on the semiconductor substrate 101 with a first dielectric layer 111, in conjunction with FIGS. 1B and 1C, toward the deep well 110 doped at a position in the first dielectric layer 111, a reset transistor, source follower transistor and the gate of the output transistor 103 , at positions 104 and 105, the common drain of the reset transistor and source follower transistor 107 and

13输出晶体管的漏极109位置处形成接触孔llOa、 114、 115、 116、 112以及113。 At position 13 of the output transistor 109 the drain contact hole is formed llOa, 114, 115, 116, 112 and 113. 采用现有工艺制备的CMOS图像传感器像素单元具有的面积较大。 Preparation process using conventional CMOS image sensor pixel unit has a larger area.

为了在没有增加光学面积基础上获得更高空间解析率和较高性能, CMOS图像传感器的像素单元数量从352 x 288 (CIF)增加到1600 x 1200 (UXGA)个或者更多,同时像素单元面积由10 x 10pm2降低至2.8 x 2.8pm2甚至更小。 In order to obtain spatially resolved higher rates and higher optical performance without increasing the area based on the number of pixels of the CMOS image sensor unit from the 352 x 288 (CIF) increased to 1600 x 1200 (UXGA) one or more, while the pixel cell area reduced from 10 x 10pm2 to 2.8 x 2.8pm2 even smaller. 但是,CIS设计师采用目前广泛应用的0.18pm技术来设计很小的像素单元(像素单元尺寸小于2.8x2.8^n2)困难较大。 However, CIS 0.18pm designer using the widely used technique to design a small unit pixel (pixel cell size of less than 2.8x2.8 ^ n2) is quite difficult. 主要原因有两个,第一, 随着像素单元尺寸的缩小,如果技术节点相同,像素单元的工作电压相同, 这意味着三个晶体管的阈值电压Vt必须保持在给定的水平,因此,晶体管的沟道长度不能够随着像素单元尺寸的缩小而降低;第二, CMOS图像传感器需要具有与金属线接触的接触孔来传递信号和提供功率,由于工艺技术的限 There are two main reasons, first, with the reduced pixel cell size, if the same technology node, the same as the operating voltage of the pixel unit, which means that the threshold voltage Vt three transistors must be kept at a given level, and therefore, the transistor the channel length can not be reduced as the cell size decreases pixel; second, CMOS image sensors require a contact hole having a contact with the metal wires to transmit signals and provide power, since the limit of technology

制,难以在较小的单元像素面积内对它们进行布线。 System, it is difficult to wire them in a smaller unit pixel area. 发明内容 SUMMARY

本发明解决的问题是现有技术的CMOS图像传感器的像素单元面积较大> 难以获得更高空间解析率和较高性能。 The present invention solves the problem area of ​​the CMOS image sensor pixel unit of the prior art larger> difficult to obtain spatially resolved higher rates and higher performance.

为解决上述问题,本发明提供一种CMOS图像传感器,包括:位于半导体衬底上的至少一个CMOS图像传感器像素单元对,所述CMOS图像传感器像素单元对包括列向相邻的第一像素单元和第二像素单元,所述每个像素单元包括光电二极管区域和驱动电路区域,其中,驱动电路区域形成有输出晶体管,第一像素单元的输出晶体管和第二像素单元的输出晶体管的漏极相连, 作为共用的输出端。 To solve the above problems, the present invention provides a CMOS image sensor, comprising: at least on a semiconductor substrate of a CMOS image sensor pixel unit, the CMOS image sensor including the unit pixel columns adjacent to the first pixel units and a second pixel unit, each of the unit pixel includes a photodiode region and a driver circuit area, wherein the driving circuit region is formed with the output transistor, the output transistor is connected to the drain of the output transistor of the first pixel units and the second pixel unit, as a common output terminal.

所述第一像素单元与第二像素单元关于共用的输出端对称;第一像素单元的输出晶体管的栅极与形成于同一层的多晶硅行选导线相连,且与外围行选电路相连;第一像素单元源跟随晶体管的源极与第一像素单元输出晶体管源极共用;第一像素单元的复位晶体管的漏极与第一像素单元的源跟随晶体管漏极共用、源极位于光电二极管区域内、栅极通过形成于同一层的多晶硅复位导线与外围复位控制电路相连。 The first pixel and the second pixel unit cell symmetry about the common output terminal; gate of the output transistor of the first pixel unit is connected to the polysilicon row select conductor formed on the same layer, and is connected to the peripheral line selection circuit; a first pixel cell source follower transistor and the source electrode of the first common source output transistor pixel cell; drain of the reset transistor of the first pixel unit and the first pixel unit follows the common drain of the transistor, the source electrode is located within the photodiode region, by forming the gate electrode and the reset wire is connected to the peripheral reset control circuit in the same layer of polysilicon.

每个像素单元的多晶硅行选导线与多晶硅复位导线相互平行,且相邻的第一像素单元和第二像素单元的多晶硅行选导线相互平行,多晶硅复位导线相互平行。 Poly row select conductor polysilicon row the first pixel units of each pixel unit is selected from the polysilicon wire and the reset wire are parallel, and adjacent and parallel to each other in the second pixel unit, the reset polysilicon wires parallel to each other.

所述光电二极管区域包括形成于半导体衬底中的与半导体衬底导电类型相反的深掺杂阱、位于深掺杂阱上的与深掺杂阱导电类型相反的浅掺杂区。 The photodiode region is formed in a semiconductor substrate comprising the semiconductor substrate opposite conductivity type deep well doped located deep shallow doping region doped with deep dopant of opposite conductivity type well on the well.

半导体衬底上还形成有第一介质层;在第一介质层中对着第一像素单元和第二像素单元的输出晶体管的共用的输出端处的填充有导电材料的输出接触孔;在第一介质层中分别对着第一像素单元和第二像素单元的深掺杂阱位置处的填充有导电材料的深掺杂阱接触孔;在第一介质层中分别对着第一像素单元和第二像素单元的复位晶体管的漏极位置处的填充有导电材料的电源连接接触孔;在第一介质层中分别对着第一像素单元和第二像素单元的源跟随晶体管的栅极位置处的填充有导电材料的源跟随接触孔。 There is also formed on the semiconductor substrate a first dielectric layer; the dielectric layer filling the first output of the common output transistor of the first pixel unit and the second unit pixel output against the contact hole with a conductive material; first a dielectric layer filling the well at a first location and a second pixel unit of the pixel unit, respectively, against the deep dopant doped deep well contact hole conductive material; respectively in the first dielectric layer opposite the first pixel units and filling position at the drain of the reset transistor of the second pixel unit is connected with a power supply contact hole conductive material; a first dielectric layer, respectively, of the gate against the position of the source follower transistor of the first pixel and the second pixel unit cell It filled with a conductive material to follow the source contact hole.

所述CMOS图像传感器还包括第一介质层上对着输出接触孔位置处的由第一金属层构成的输出金属线,所述输出金属线与外围输出电路相连;第一介质层上对着电源连接接触孔位置处的由第一金属层构成的电源连接金属线;以及由第一金属层构成的把每个CMOS图像传感器像素单元的深掺杂阱接触孔与源跟随接触孔相连的导线。 The CMOS image sensor further includes an output of a metal wire at the first metal layer on the first dielectric layer opposite the output contact hole position, the metal wire and the peripheral output connected to an output circuit; a first dielectric layer into the power a first connection by a metal layer constituting the power supply wire at the contact hole location; and the deep well doped source contact holes each CMOS image sensor pixel unit is composed of the first metal wire layer connected to the contact hole to follow.

所述CMOS图像传感器还包括位于第一金属层上的第二介质层、以及第二介质层中对着每个CMOS图像传感器像素单元对的两个电源连接金属线位置处的填充有导电材料的电源接触孔。 The CMOS image sensor further comprises a second dielectric layer on the first metal layer, and filling of the metal wire connecting position of the second dielectric layer opposite each of the two power units CMOS image sensor pixel with a conductive material power supply contact hole.

所述第二介质层上对着每个CMOS图像传感器像素单元对的两个电源接触孔处形成有由第二金属层构成的电源金属线,所述电源金属线与外围供电电源电路相连。 The dielectric layer is formed on the second power supply line composed of a second metal layer opposite the metal of each power contact hole CMOS image sensor at two pixel units, said metal power lines connected to a peripheral power supply circuit.

相应地,本发明提供一种CMOS图像传感器的形成方法,包括:将位于半导体衬底上的CMOS图像传感器分为至少一个CMOS图像传感器像素单元对区域,所述CMOS图像传感器像素单元对包括列向相邻的第一像素单元和第二像素单元;将每个像素单元分为光电二极管区域和驱动电路区域;在光电二极管区域形成光电二极管;在驱动电路区域形成带有输出晶体管的驱动电路;其特征在于,第一像素单元的输出晶体管和第二像素单元的输出晶体管漏极相连,作为共用输出端。 Accordingly, the present invention provides a method of forming a CMOS image sensor, comprising: a CMOS image sensor will be located on a semiconductor substrate is divided into at least one unit of the CMOS image sensor pixel region, the CMOS image sensor including the unit pixel column direction a first unit and a second pixel adjacent to the pixel unit; units into each pixel photodiode region and a driver circuit region; forming a photodiode in a photodiode region; forming the driver circuit with an output transistor in the driving circuit region; the wherein the output transistor is connected to the drain of the output transistor of the first pixel and the second pixel unit cell, as a common output terminal.

所述第一像素单元与第二像素单元关于共用的输出端对称;第一单元的输出晶体管的栅极通过形成于同一层的多晶硅行选导线与外围行选电路相连;第一单元的源跟随晶体管的源极与第一单元的输出晶体管源极共用;第一单元的复位晶体管的栅极通过形成于同一层的多晶硅复位导线与外围复位控制电路相连、漏极与第一单元的源跟随晶体管漏极共用、源极位于光电二极管区域内。 The first pixel and the second pixel unit cell symmetry about the common output terminal; a first gate of the output transistor is connected by means of a polycrystalline silicon layer formed in the same selected row conductor and a peripheral row selecting circuit; a first source follower unit the common source transistor of the output transistor of the source of the first unit; gate of the reset transistor of the first unit formed by the same layer of polysilicon wires and the peripheral reset the reset control circuit is connected to the drain of the source follower transistor of the first unit common drain, the source is located in the photodiode region.

每个像素单元的多晶硅行选导线与多晶硅复位导线相互平行,且相邻的第一像素单元和第二像素单元的多晶硅行选导线相互平行,多晶硅复位导线相互平行。 Poly row select conductor polysilicon row the first pixel units of each pixel unit is selected from the polysilicon wire and the reset wire are parallel, and adjacent and parallel to each other in the second pixel unit, the reset polysilicon wires parallel to each other.

形成所述光电二极管包括在半导体衬底中形成半导体衬底导电类型相反的深掺杂阱、以及在深掺杂阱上形成与深掺杂阱导电类型相反的戌掺杂区。 Forming said photodiode comprising a semiconductor substrate conductivity type formed in the deep well doped opposite to, and forming a deep well doped opposite to the conductivity type in the doped region Xu deep doped well in the semiconductor substrate.

还包括在半导体衬底上形成第一介质层;在第一介质层中对着每个CMOS图像传感器像素单元对的输出晶体管的共用输出端位置处形成一个填充有导电材料的输出接触孔;在第一介质层中对着每个CMOS图像传感器像素单元对的深掺杂阱位置处形成填充有导电材料的深掺杂阱接触孔;在第一介质层中对着每个CMOS图像传感器像素单元对的复位晶体管的漏极位置处形成填充有导电材料的电源连接接触孔;以及在第一介质层中对着每个CMOS图像传感器像素单元对的源跟随晶体管的栅极位置处形成填充有导电材料的源跟随接触孔。 Further includes a first dielectric layer formed on a semiconductor substrate; position at the common output terminal of the output transistor in the first dielectric layer facing each CMOS image sensor pixel output means for forming a contact hole filled with conductive material is; in a first doped dielectric layer forming a deep well contact hole filled with a conductive material against the deep doped well of the position of each pixel of the CMOS image sensor means; a first dielectric layer facing each CMOS image sensor pixel unit power connection contact hole is filled with a conductive material at a position of the drain of the reset transistor is formed; and a gate electrode formed at a position in the first dielectric layer facing the source of each pixel unit of the CMOS image sensor is filled with a conductive follower transistor following the contact hole of the source material.

还包括在第一介质层上对着输出接触孔位置处形成由第一金属层构成的输出金属线,所述输出金属线与外围输出电路相连;在第一介质层上电源连接接触孔位置处形成由第一金属层构成的电源连接金属线;在第一介质层上 Further comprising a first dielectric layer formed on the opposite position of the output at the output of the contact hole metal wire made of a first metal layer, the metal wire and an output connected to the peripheral circuit output; at the location of the power contact hole connected to the first dielectric layer forming a power supply bonding wires made of a first metal layer; a first dielectric layer on a

采用第一金属层构成的导线把每个CMOS图像传感器像素单元的深掺杂阱接触孔与源跟随接触孔相连。 Using a wire made of the first metal layer doped deep well contact hole to the source of each CMOS image sensor pixel unit is connected to the contact hole is followed.

还包括在第一金属层上形成第二介质层;以及在第二介质层中对着每个CMOS图像传感器像素单元对的两个电源连接金属线位置处形成填充有导电材料的电源接触孔。 Further comprising forming a second dielectric layer on the first metal layer; and a connection wire positions are formed a power contact holes are filled with a conductive material in the second dielectric layer opposite each of the two power CMOS image sensor pixel unit pair.

在第二介质层上对着每个CMOS图像传感器像素单元对的两个电源接触孔上形成由第二金属层构成的电源金属线。 Forming a power supply line composed of a second metal layer opposite the two metal power contact holes each CMOS image sensor pixel units on the second dielectric layer.

本发明还提供一种如上所述CMOS图像传感器的布局方法,包括:至少一个CMOS图像传感器像素单元对,所述CMOS图像传感器像素单元对包括列向相邻的第一像素单元和第二像素单元;CMOS图像传感器像素单元对在行方向上依次排列;同一行方向上的相邻CMOS图像传感器像素单元对的相应像素单元的复位导线、行选导线均相连且平行于行方向;相邻两行CMOS图像传感器像素单元对的复位导线相邻;CMOS图像传感器像素单元对的第一像素单元和第二像素单元具有一个共用输出端且第一像素单元和第二像素单元关于共用的输出端对称;第一像素单元的输出晶体管、源跟随晶体管及复位晶体管的栅极与共用的输出端依次相邻;第一像素单元的栅极与形成于同一层的多晶硅行选导线相连;第一像素单元的复位晶体管的漏极与第一单元的源跟随晶体管漏极共用、源极位于 The present invention further provides a method as described above layout of the CMOS image sensor, comprising: at least one pixel unit of the CMOS image sensor, the CMOS image sensor including the unit pixel columns adjacent to the first pixel and the second pixel unit cell ; CMOS image sensor pixel sequentially arranged in the row direction of the unit; reset wire corresponding pixel CMOS image sensor unit cell of the adjacent pixel on the same row direction are connected to line selection conductors and parallel to the row direction; two adjacent lines of the CMOS image reset conductor sensor adjacent pixel units; a first pixel unit of the CMOS image sensor pixel unit and a second unit pixel having a common output terminal and the first pixel units and the pixel units on the second common output terminal of symmetry; first an output transistor of the pixel unit, and the common gate of the source follower transistor and the output terminal of the reset transistor adjacent sequentially; a first pixel unit is connected to a gate formed in the same layer of polysilicon row select conductor; first pixel unit reset transistor the drain of the source follower transistor of the first unit a common drain, the source is located 光电二极管区域内、栅极与形成于同一层的多晶硅复位导线相连。 The photodiode region, a gate formed in the same layer of polysilicon conductor is connected to the reset.

本发明还提供一种CMOS图像传感器,包括:位于半导体村底上的至少一个CMOS图像传感器像素单元对,所述CMOS图像传感器像素单元对包括列向相邻的第一像素单元和第二像素单元,所述每个像素单元包括光电二极管区域和驱动电路区域,其中,驱动电路区域形成有复位晶体管和输出晶体管,第一像素单元的输出晶体管和第二像素单元的输出晶体管的漏极相连,作为共用的输出端;第一像素单元的复位晶体管的漏极与列向相邻的CMOS图像传感器像素单元对的第二像素单元的复位晶体管的漏极相连,作为共用的供电电源输入端;第二像素单元的复位晶体管的漏极与列向相邻的另一CMOS图像传感器像素单元对的第一像素单元的复位晶体管的漏极相连,作为共用的供电电源输入端。 The present invention also provides a CMOS image sensor, comprising: at least a CMOS image sensor pixel unit located on the semiconductor substrate, said CMOS image sensor including the unit pixel columns adjacent to the first pixel and the second pixel unit cell , each pixel unit includes a photodiode region and a driver circuit area, wherein the driving circuit region is formed with a reset transistor and an output transistor connected to the drain of the output transistor of the output transistor of the first pixel and the second pixel unit cell, as common output terminal; a second drain of the reset transistor and the drain of the pixel cell row reset transistor of the first pixel unit adjacent to the pixel of the CMOS image sensor means is connected to a common power supply input terminal; a second the drain of the reset transistor and the drain of the first unit pixel row reset transistor of a pixel unit to another unit adjacent to the CMOS image sensor pixel is connected to a common power supply input.

所述第一像素单元与第二像素单元关于共用的输出端对称;第一像素单元的输出晶体管的栅极与形成于同一层的多晶硅行选导线相连,且与外围行选电路相连;第一像素单元的源跟随晶体管的源极与第一像素单元的输出晶体管源极共用;第一像素单元的复位晶体管的源极位于第一像素单元的光电二极管区域内;与第一像素单元列向相邻的CMOS图像传感器像素单元对的第二像素单元的复位晶体管的源极位于相应像素单元的光电二极管区域内。 The first pixel and the second pixel unit cell symmetry about the common output terminal; gate of the output transistor of the first pixel unit is connected to the polysilicon row select conductor formed on the same layer, and is connected to the peripheral line selection circuit; a first the source of the source follower transistor in a pixel unit pixel electrode common to the first output transistor and the source unit; a first source of the reset transistor within the pixel cell located at the source of the first photodiode region of the pixel unit; column of the first pixel unit with respect to the a second source of the reset transistor within the pixel unit cell of a CMOS image sensor pixel is located adjacent to a corresponding pixel electrode of the photodiode region unit.

所述CMOS图像传感器像素单元对的第一像素单元和第二像素单元的多晶硅行选导线相互平行。 A first polysilicon row pixel unit of the CMOS image sensor pixel units and the pixel units selected from the second conductor parallel to each other.

所述光电二极管区域包括形成于半导体衬底中的与半导体衬底导电类型相反的深掺杂阱、位于深掺杂阱上的与深掺杂阱导电类型相反的浅掺杂区。 The photodiode region is formed in a semiconductor substrate comprising the semiconductor substrate opposite conductivity type deep well doped located deep shallow doping region doped with deep dopant of opposite conductivity type well on the well.

半导体衬底上还形成有第一介质层;在第一介质层中对着CMOS图像传感器像素单元对的输出晶体管的共用的输出端处的填充有导电材料的输出连 It is further formed with a first dielectric layer on a semiconductor substrate; filled at the output of the common output transistors in the first dielectric layer facing the unit pixel CMOS image sensor with a conductive material to connect the output

18接接触孔;在第一介质层中对着第一像素单元的共用的供电电源输入端位置处的填充有导电材料的电源连接接触孔;在第一介质层中对着第二像素单元 Indirect contact hole 18; a first dielectric layer is filled in at the input terminal of the power supply common to the position facing the first pixel unit electrically conductive material is connected to a power supply contact hole; against the second pixel unit in a first dielectric layer

的共用的供电电源输入端位置处的填充有导电材料的电源连接接触孔;在第一介质层中分别对着第一像素单元和第二像素单元的深摻杂阱位置处的填充有导电材料的深掺杂阱接触孔;在第一介质层中分别对着第一像素单元和第二像素单元的复位晶体管的栅极位置处的填充有导电材料的复位接触孔;以及在第一介质层中分别对着第一像素单元和第二像素单元的源跟随晶体管的栅极位置处的填充有导电材料的源跟随接触孔。 Filled at the power supply input of a power supply position connecting the common contact hole conductive material; in the first dielectric layer facing each well filled deep dopant at a position of the first pixel and the second pixel unit cell with a conductive material deep doped well contact hole; positions are filled at the gate of the reset transistor of the first pixel and the second pixel unit has a reset unit against the contact hole conductive material in the first dielectric layer; and a first dielectric layer respectively against the source unit and the second unit pixel of the first pixel position following the filling at the gate of the transistor with a source of electrically conductive material following the contact hole.

所述CMOS图像传感器还包括第一介质层上对着输出连4妄接触孔位置处的由第一金属层构成的输出连接金属线;第一介质层上对着电源连接接触孔位置处的由第一金属层构成的电源连接金属线;第一介质层上对着复位接触孔位置处的由第一金属层构成的第二导线,所述第二导线与外围复位电路相连;以及由第一金属层构成的把每个像素单元的深掺杂阱接触孔与源跟随接触孔相连的第一导线。 The CMOS image sensor further comprises an output opposite the first metal layer at a position of the contact hole 4 constituting an output connected to the first metal line is connected to jump to the dielectric layer; the dielectric layer at a first contact hole into the power position a first metal layer made of the power supply metal line is connected; a first dielectric layer on the second conductor opposite the contact is reset by a first metal layer composed of the hole position, the second wire is connected to the peripheral reset circuit; and a first the first lead doped deep well contact hole to the source of each pixel unit follows the contact hole is connected to the metal layer.

所述CMOS图像传感器还包括位于第一金属层上的第二介质层、以及第二介质层中对着电源连接金属线和输出连接金属线位置处的填充有导电材料的电源接触孔和输出接触孔。 The CMOS image sensor further comprises a second dielectric layer on the first metal layer, a second dielectric layer and into the power line and an output connected to the metal filler at the wire positions with a conductive material in contact with the power output and the contact hole hole.

所述第二介质层上对着电源接触孔处形成有由第二金属层构成的电源金属线,所述电源金属线与外围供电电源电路相连;所述第二介质层上对着输出接触孔处形成有由第二金属层构成的输出金属线,所述输出金属线与外围输出电路相连。 Said second dielectric layer is formed at the contact hole into the power supply with a metal wire made of a second metal layer, the metal line connected to the power supply and the peripheral power supply circuit; against the output contact hole on the second dielectric layer It is formed at the output of a second metal wire layer of metal, metal wire and the output is connected to the peripheral circuit output.

本发明还提供一种CMOS图像传感器的形成方法,包括:将位于半导体衬底上的CMOS图像传感器分为至少一个CMOS图像传感器像素单元对区域,所述CMOS图像传感器像素单元对包括列向相邻的第一像素单元和第二像素单元;将每个像素单元分为光电二极管区域和驱动电路区域;在光电二极管区域形成光电二极管;在驱动电路区域形成带有复位晶体管和输出晶体管的驱动电路,第一像素单元和第二像素单元的两个输出晶体管的漏极相连,共用一个输出端;第一像素单元的复位晶体管的漏极与列向相邻的CMOS图像传感器像素单元对的第二像素单元的复位晶体管的漏极相连,共用一个供电电源输入端;第二像素单元的复位晶体管的漏极与列向相邻的另一CMOS图像传感器像素单元对的第一像素单元的复位晶体管的漏极相连,共用一个供电电源输入端。 The present invention also provides a method of forming a CMOS image sensor, comprising: a CMOS image sensor will be located on a semiconductor substrate is divided into at least one unit of the CMOS image sensor pixel region, the CMOS image sensor includes pixel units adjacent to each other on a column a first pixel unit and the second unit pixel; units into each pixel photodiode region and a driver circuit region; forming a photodiode in a photodiode region; forming a driving circuit having a reset transistor and the output transistor in the driving circuit region, drains of the two output transistors of the first pixel unit and the second pixel unit is connected to a common output terminal; drain of the reset transistor of the first column of the unit pixel of the CMOS image sensor pixel of adjacent unit pixels of the second the drain of the reset transistor means is connected to a common power supply input terminal; drain of the reset transistor of the second column of the unit pixel reset transistor adjacent to the first pixel unit to another unit of the CMOS image sensor pixel of leakage pole is connected to the common input terminal of a power supply.

所述第一像素单元与第二像素单元关于共用的输出端对称;第一像素单元的输出晶体管的栅极与形成于同一层的多晶硅行选导线相连,且与外围行选电路相连;第一像素单元的源跟随晶体管的源极与第一像素单元的输出晶体管源极共用;第一像素单元的复位晶体管的源极位于第一像素单元的光电二极管区域内;与第一像素单元列向相邻的CMOS图像传感器像素单元对的第二像素单元的复位晶体管的源极位于相应像素单元的光电二极管区域内。 The first pixel and the second pixel unit cell symmetry about the common output terminal; gate of the output transistor of the first pixel unit is connected to the polysilicon row select conductor formed on the same layer, and is connected to the peripheral line selection circuit; a first the source of the source follower transistor in a pixel unit pixel electrode common to the first output transistor and the source unit; a first source of the reset transistor within the pixel cell located at the source of the first photodiode region of the pixel unit; column of the first pixel unit with respect to the a second source of the reset transistor within the pixel unit cell of a CMOS image sensor pixel is located adjacent to a corresponding pixel electrode of the photodiode region unit.

所述CMOS图像传感器像素单元对的第一像素单元和第二像素单元的多晶硅行选导线相互平行。 A first polysilicon row pixel unit of the CMOS image sensor pixel units and the pixel units selected from the second conductor parallel to each other.

形成所述光电二极管包括在半导体衬底中形成半导体衬底导电类型相反的深掺杂阱以及在深摻杂阱上形成与深掺杂阱导电类型相反的浅掺杂区。 Forming the photodiode formed in a semiconductor substrate comprising a semiconductor substrate of opposite conductivity type deep well doped well formed in the deep well doped with a deep well doped opposite to the conductivity type lightly doped region.

还包括在半导体衬底上形成第一介质层;在第一介质层中对着CMOS图像传感器像素单元对的输出晶体管的共用的输出端位置处形成填充有导电材料的输出连接接触孔;在第一介质层中对着第一像素单元的共用的供电电源 Further comprising forming a first dielectric layer on a semiconductor substrate; an output connected to the contact hole is filled with a conductive material at the output terminal of the output transistor of the common position in the first dielectric layer facing the CMOS image sensor pixel unit is formed; the first a first dielectric layer facing the common power supply unit pixel

输入端位置处形成填充有导电材料的电源连接接触孔;在第一介质层中对着第二像素单元的共用的供电电源输入端位置处形成填充有导电材料的电源连 Power connection contact hole is filled with a conductive material is formed at the input end position; the power supply toward the position of the common input terminal of a second power source connected pixel cell is formed with a conductive material filled in the first dielectric layer

4妄接触孔;在第一介质层中分别对着第一像素单元和第二像素单元的深掺杂阱位置处形成填充有导电材料的深摻杂阱接触孔;在第一介质层中分别对着 4 jump contact holes, respectively; deep at opposite positions of the first doped well of the second pixel units and the pixel units formed in the first dielectric layer is filled with a deep dopant well contact hole conductive material; a first dielectric layer, respectively, against

第一像素单元和第二像素单元的复位晶体管的栅极位置处形成填充有导电材 The position of the gate of the reset transistor of the first pixel unit and the second pixel unit is filled with a conductive material is formed

料的复位接触孔;以及在第一介质层中分别对着第一像素单元和第二像素单元的源跟随晶体管的栅极位置处形成填充有导电材料的源跟随接触孔。 Reset the contact hole material; and a position of the gate in the first dielectric layer facing each source unit and the second unit pixel of the first pixel follower transistor is formed is filled with a conductive material to follow the source contact hole.

形成所述CMOS图像传感器还包括在第一介质层上对着输出连接接触孔位置处形成由第一金属层构成的输出连接金属线;在第一介质层上对着电源连接接触孔位置处形成由第一金属层构成的电源连接金属线;在第一介质层 Forming the CMOS image sensor further comprises a front position output connection contact hole is formed on the first dielectric layer connected to the metal lines output by the first metal layer; forming a contact hole in front of the power supply connection location on the first dielectric layer a metal wire connected to the power supply of the first metal layer; a first dielectric layer

上对着复位接触孔位置处形成由第一金属层构成的第二导线,所述第二导线与外围复位电路相连;以及采用第一金属层构成的第一导线把每个像素单元 The facing position is reset at the contact hole forming a second conductor made of a first metal layer, the second conductor is connected to the peripheral reset circuit; and the use of a first wire of the first metal layer each pixel unit

的深掺杂阱接触孔与源跟随4妄触孔相连。 Doped well deep contact holes with the source follower is connected to contact hole 4 jump.

形成所述CMOS图像传感器还包括在第一金属层上形成第二介质层、以及在第二介质层中对着电源连接金属线和输出连接金属线位置处形成填充有导电材料的电源接触孔和输出接触孔。 Forming the CMOS image sensor further comprises a second dielectric layer formed on the first metal layer, and the metal lines and into the power output connection wire positions are formed a power contact holes are filled with conductive material and a second dielectric layer output contact hole.

形成所述CMOS图像传感器还包括在第二介质层上对着电源接触孔处形成由第二金属层构成的电源金属线,所述电源金属线与外围供电电源电路相连;在第二介质层上对着输出接触孔处形成由第二金属层构成的输出金属线,所述输出金属线与外围输出电路相连。 Forming the CMOS image sensor further comprises a power source formed of a second metal wire into the power metal layer at the contact hole on the second dielectric layer, said metal power lines connected to a peripheral power supply circuit; a second dielectric layer on the a contact hole is formed at the output against an output of a second metal wire layer of metal, metal wire and the output is connected to the peripheral circuit output.

本发明还提供一种如上所述CMOS图像传感器的布局方法,包括:至少一个CMOS图像传感器像素单元对,所述CMOS图像传感器像素单元对包括列向相邻的第一像素单元和第二像素单元;CMOS图像传感器像素单元对在行方向上依次排列;同一行方向上的相邻CMOS图像传感器像素单元对的相应像素单元的行选导线均相连且平行于行方向;相邻两行CMOS图像传感器像素单元对的复位晶体管相邻;CMOS图像传感器像素单元对的第一像素单元和第二像素单元具有一个共用的输出端且第一像素单元和第二像素单元关于共用的输出端对称;第一像素单元的输出晶体管、源跟随晶体管及复位晶 The present invention further provides a method as described above layout of the CMOS image sensor, comprising: at least one pixel unit of the CMOS image sensor, the CMOS image sensor including the unit pixel columns adjacent to the first pixel and the second pixel unit cell ; CMOS image sensor pixel sequentially arranged in the row direction of the unit; corresponding row conductor is selected from the CMOS image sensor pixel unit of an adjacent unit pixel on the same row are connected to a direction parallel to the row direction; two adjacent rows of CMOS image sensor pixel unit adjacent pairs of the reset transistor; a first pixel unit of the CMOS image sensor pixel units and the second pixel unit having an output terminal and an output terminal of the first pixel unit and the second unit pixel with respect to a common shared symmetric; a first pixel unit an output transistor, a reset transistor and source follower crystal

体管的栅极与共用输出端依次相邻;第一像素单元的栅极与形成于同一层的多晶硅行选导线相连;第一像素单元的复位晶体管的漏极与列向相邻的CMOS图像传感器像素单元对的第二像素单元的复位晶体管的漏极相连,作为共用的供电电源输入端;第二像素单元的复位晶体管的漏极与列向相邻的另一CMOS图像传感器像素单元对的第一像素单元的复位晶体管的漏极相连,作为共用的供电电源输入端。 The output of the common gate transistor adjacent turn; a first pixel unit is connected to a gate formed in the same layer of polysilicon row select conductor; drain of the reset transistor of the first column to the pixel unit adjacent to the CMOS image drain of the reset transistor of the second pixel unit of the sensor pixel unit is connected to a common power supply input terminal; a second drain of the reset transistor and the column pixel cell to another adjacent pixel CMOS image sensor cell pairs drain of the reset transistor is connected to the first pixel unit, as a common power supply input.

与现有技术相比,本发明具有以下优点:本发明通过把CMOS图像传感器像素单元对两个输出晶体管的漏极相连,共用一个输出端,每个像素单元对减少了一个输出接触孔和减少输出金属线,从而减小了输出电容,增加了读出速度,同时可以获得更好的图像质量和更小的像素单元面积,具有更大的设计驱动电路区域的晶体管的空间自由,更大的填充比和更好的光学路径;本发明还通过采用多晶硅作为行选导线和复位导线与外围行选电路和复位电路相连,每个像素单元进一步减少了两个接触孔,减少了两个金属线,可以获得更好的图像质量。 Compared with the prior art, the present invention has the following advantages: the present invention by the CMOS image sensor pixel units coupled to the drain of the two output transistors, a common output terminal, each pixel output unit reduces the contact hole and a reduction output the metal wire, thereby reducing the output capacitance, increasing the readout speed can be obtained while better image quality and a smaller cell area of ​​the pixel, having a greater design freedom drive transistor circuit region, the greater the and better filling ratio of the optical path; the present invention is selected by using polysilicon as a row conductor and a conductor connected to the reset line selection circuit and the peripheral circuit reset, each pixel cell further reduces the two contact holes, reducing the two metal lines , you can get better image quality.

本发明还通过把CMOS图像传感器像素单元对的第一像素单元的输出晶体管、第二像素单元的输出晶体管的漏极相连,同时把第一像素单元的复位晶体管的漏极与列向相邻的像素单元对的第二像素单元的复位晶体管的漏极相连,共用一个电源输入端;把第二像素单元的的复位晶体管的漏极与列向的另一相邻像素单元对的第一像素单元的复位晶体管的漏极相连,共用一个电源输入端,每三个像素单元减少了两个接触孔,减少了两个金属线,减小了输出电容,增加了读出速度,同时可以获得更好的图像质量和更小的像素单元面积,具有更大的设计驱动电路区域的晶体管的空间自由;本发明还通过采用多晶硅作为行选导线与外围行选电路相连,每一个像素单元进一步减少了一个接触孔,减少了一个金属线,可以获得更好的图像质量。 The present invention also by means of the output transistor of the first CMOS image sensor pixel unit of the pixel, is connected to the drain of the output transistor of the second pixel unit, while the drain of the reset transistor of the first pixel unit to an adjacent column reset transistor connected to the drain of the second pixel units in pixel units, a common power input terminal; pixel cell to another adjacent drain of the reset transistor in the second pixel unit to the column of first pixel units the drain of the reset transistor is connected to a common power input terminal, each of the three pixel units reduces two contact holes, reducing the two metal lines to reduce the output capacitance, increasing the readout speed can be obtained at the same time better image quality and smaller cell area of ​​the pixel, the transistor having a larger free space design of the drive circuit region; the invention also row selecting circuit coupled to the peripheral by using polysilicon as a row selecting wire, each pixel unit is further reduced a a contact hole, a metal wire is reduced, better image quality can be obtained. 附图说明 BRIEF DESCRIPTION

图1A是CM0S图像传感器的电路结构; CM0S FIG. 1A is a circuit configuration of the image sensor;

图1B是现有技术的CMOS图像传感器的掩模版图; FIG 1B is a mask layout of the CMOS image sensor of the prior art;

图1C是现有技术的CMOS图像传感器的沿AA,剖面结构示意图; 1C is a prior art CMOS image sensor along AA, a schematic cross-sectional configuration;

图2A、图3A、图4A、图5A、图6A、图7A、图8A、图9A、图10A Figures 2A, 3A, FIG. 4A, 5A, FIG. 6A, 7A, FIG. 8A, 9A, 10A

是本发明的一个实施例的形成CMOS图像传感器的剖面结构示意图; It is a schematic cross-sectional structure of a CMOS image sensor formed according to an embodiment of the present invention;

图2B、图3B、图4B、图5B、图6B、图7B、图8B、图9B、图10B是本发明的一个实施例的形成CMOS图像传感器采用的掩模版图; FIG. 2B, FIG. 3B, FIG. 4B, 5B, and 6B, and 7B, and 8B, FIGS. 9B, 10B is formed in a mask layout using the CMOS image sensor according to the embodiment of the present invention;

图3C、图4C、图5C、图6C、图7C、图8C、图9C、图10C是本发明一个实施例的形成CMOS图像传感器采用的掩^f莫版图叠加; 3C, the to Figure 4C, 5C, the to Figure 6C, 7C, the to Figure 8C, 9C, the cover 10C is ^ f Mo map superimposed forming a CMOS image sensor according to an embodiment of the present invention is employed;

图11是本发明的一个实施例的CMOS图像传感器的布局示意图; 11 is a schematic layout of a CMOS image sensor according to an embodiment of the present invention;

图12A、图13A、图14A、图15A是本发明的另一实施例的形成CMOS 图像传感器的剖面结构示意图; FIG. 12A, FIG. 13A, 14A, 15A is a schematic cross-sectional structure of a CMOS image sensor formed according to another embodiment of the present invention;

图12B、图13B、图14B、图15B是本发明的另一实施例的形成CMOS 图像传感器采用的掩模版图; 12B, the to Figure 13B, 14B, a mask layout 15B is formed using a CMOS image sensor according to another embodiment of the present invention;

图13C、图14C、图15C是本发明的另一实施例的形成CMOS图像传感器采用的掩模版图叠加; 13C, the FIG. 14C, 15C are formed in the CMOS image sensor according to the mask layout using the superposition of a further embodiment of the present invention;

图16是本发明的另一实施例的CMOS图像传感器的布局示意图。 16 is a schematic layout of a CMOS image sensor according to another embodiment of the present invention.

具体实施方式 detailed description

本发明通过把CMOS图像传感器的列向相邻的像素单元对的第一像素单元和第二像素单元的输出晶体管的漏极相连,共用一个输出接触孔;或者通 The present invention is connected to the drain of the output transistor via a first column of a CMOS image sensor pixel unit of the pixel adjacent to the pixel unit and the second unit, the output of a common contact hole; or by

过把CMOS图像传感器像素单元对的第一像素单元和第二像素单元的输出晶体管的漏极相连共用一个输出接触孔,同时把第一像素单元的复位晶体管的漏极与列向相邻的CMOS图像传感器像素单元对的第二像素单元的复位晶体管的漏极相连共用一个电源接触孔,4巴第二像素单元的复位晶体管的漏极与 Through the drain output transistor of the first CMOS image sensor pixel unit of the pixel unit and the pixel units coupled to the second output share a contact hole, while the drain of the reset transistor of the first pixel unit to an adjacent column CMOS drain of the reset transistor of the second pixel unit of the image sensor pixel unit is connected to a common power supply contact hole, the drain of the reset transistor 4 and the second pixel unit bar

列向的另一相邻CMOS图像传感器像素单元对的第一像素单元的复位晶体管的漏极相连共用一个电源接触孔。 The column reset transistor to the drain of the first CMOS image sensor pixel unit of another adjacent unit pixels share one power source is connected to the contact hole. 在没有降低技术节点条件下,本发明减少了接触孔、减少使用的金属层,从而减少了像素单元的面积。 In the absence of reduction under technology node, the present invention reduces the contact hole, the metal layer is reduced, thereby reducing the area of ​​the pixel unit. 本发明所述的列向与行向为相互垂直的两个方向,是相对来;兑。 Column and rows according to the present invention, the two directions perpendicular to each other, to a relative; against. 本发明的实施例中给出的CMOS图像传感器的为三个晶体管结构,本发明同样适用于四个晶体管的CMOS图像传感器,在此不应过多限制本发明的保护范围。 CMOS image sensor according to embodiments of the present invention is given in three transistor structure, the present invention is equally applicable to a CMOS image sensor including four transistors, this should not unduly limit the scope of the present invention.

本发明首先给出一种形成CMOS图像传感器方法的实施例,包括:把CMOS图像传感器分为至少一个CMOS图像传感器像素单元对区域,所述CMOS图像传感器像素单元对包括第一像素单元区域和第二像素单元区域; 每个像素单元分为光电二极管区域和驱动电路区域;在光电二极管区域形成光电二极管;在驱动电路区域形成带有输出晶体管的驱动电路;第一像素单元和第二像素单元列向相邻的两个输出晶体管的漏极相连,共用一个输出端。 The present invention presents a first embodiment of an image forming CMOS sensor method, comprising: a CMOS image sensor, the CMOS image sensor is divided into at least one region of the pixel unit, the CMOS image sensor pixel unit of the first region and the second pixel unit comprises two pixel cell region; and each pixel unit is divided photodiode region and a driver circuit region; forming a photodiode in a photodiode region; forming the driver circuit with an output transistor in the driving circuit region; a first pixel unit and the second unit pixel row the two output transistors adjacent to the drain is connected to a common output terminal.

图2A、图3A、图4A、图5A、图6A、图7A、图8A、图9A、图10A 是本发明的一个实施例的形成CMOS图像传感器的剖面结构示意图;图2B、 图3B、图4B、图5B、图6B、图7B、图8B、图9B、图IOB是本发明的一个实施例的形成CMOS图像传感器采用的掩模版图;图3C、图4C、图5C、 图6C、图7C、图8C、图9C、图IOC是本发明的一个实施例的形成CMOS 图像传感器采用的掩模版图叠加;下面参照附图加以说明,本发明的实施例中的半导体衬底均为p型,当然,半导体衬底还可以为n型,在此不应过多限制本发明的保护范围。 Figures 2A, 3A, FIG. 4A, 5A, FIG. 6A, 7A, FIG. 8A, 9A, 10A is a schematic cross-sectional structure of forming a CMOS image sensor according to an embodiment of the present invention; FIG. 2B, FIG. 3B, FIG. . 4B, 5B, and 6B, and 7B, and 8B, FIGS. 9B, and mask layout IOB is a CMOS image sensor forming an embodiment of the present invention is employed; FIG. 3C, 4C, and. 5C,. 6C, 7C, 8C, the 9C, the mask layout is superimposed FIG. IOC forming a CMOS image sensor of the present invention, an embodiment is employed; be described with reference to the drawings, embodiments of a semiconductor substrate of the present invention are p-type , of course, it may also be an n-type semiconductor substrate, which should not unduly limit the scope of the present invention.

首先,参照图2A,提供半导体衬底201,在半导体衬底201内定义出有源区并且对有源区进行隔离形成隔离槽202,形成所述隔离槽202为本技术领 First, referring to FIG. 2A, a semiconductor substrate 201, the definition of an active region in the semiconductor substrate 201 and active region 202 is formed for isolating the isolation groove, the groove 202 forming the isolation collar technique of the present

24域人员公知技术,在此不作赘述。 24 domain well known art, and will not be repeated herein. 隔离槽202构成隔离区域IA和IB。 Isolation trench isolation region 202 constituting IA and IB. 半导体衬底201上隔离区域以外区域为有源区。 The semiconductor substrate 201 other than the region on the isolation region is an active region. 由图2A给出的一个CMOS图像传感器像素单元对包括第一像素单元区域(IIA + IIIA)和第二像素单元区域(IIB + IIIB),所述第一像素单元又包括光电二极管区域IIA (图中虚线框内)和驱动电路区域niA,第二像素单元区域又包括光电二极管区域IIB (图中虚线框内)和驱动电路区域IIIB,本实施例给出的驱动电路为由三个晶体管包括复位晶体管、源跟随晶体管和输出晶体管组成。 A CMOS image sensor pixel unit given in FIG 2A including a first pixel unit (IIA + IIIA) and a second unit pixel region (IIB + IIIB), the first unit pixel includes a photodiode region and IIA (FIG. within the dashed box) and a drive circuit region niA, and the second region comprises a pixel unit (within the dashed box in the figure) and a drive circuit region IIIB photodiode region IIB, driving circuit of the present embodiment are given by three transistors including a reset transistor, a source follower transistor and the output transistors.

参照图2B为定义有源区的掩模版图,图中有源区包括光电二极管所在区域和驱动电路的区域。 Referring to FIG. 2B is a mask layout of the active region defined in FIG active region includes a photodiode Area and the driving circuit region. 虚线框210a和210b为光电二极管所在区域,有源区的其余部分为驱动电路区域。 Dashed boxes 210a and 210b of the photodiode Area, the rest of the active region of the driving circuit region. 图2A即为图2B的沿直线B-B'处的剖面图。 Figure 2A cross-sectional view along line B-B 'of the FIG. 2B is the.

参照图3A,在半导体衬底201上驱动电路区域形成栅介质层和多晶硅层, 所述多晶硅层作为栅极,根据复位晶体管、源跟随晶体管和输出晶体管所在区域,分别形成第一像素单元的复位晶体管的栅介质层230a、源跟随晶体管的栅介质层231a和第二像素单元的复位晶体管的斥册介质层230b、源跟随晶体管的栅介质层231b、输出晶体管的栅介质层232b;形成第一像素单元的复位晶体管的栅极203a、源跟随晶体管的栅极204a、输出晶体管的栅极205a和第二像素单元的复位晶体管的栅极203b、源跟随晶体管的栅极204b、输出晶体管的栅极205b。 3A, a driving circuit region on the semiconductor substrate 201 is formed a gate dielectric layer and the polysilicon layer, the polysilicon layer as a gate electrode, the reset transistor, source follower transistor and a region where the output transistor, the reset of the first pixel units are formed the gate dielectric layer of the transistor 230a, the dielectric layer volumes repellent reset transistor gate dielectric layer 231a and the second pixel unit of the source follower transistor 230b, the gate dielectric layer of the source follower transistor 231b, the output transistor gate dielectric layer 232b; forming a first the gate of the reset transistor pixel cell 203a, the gate of the source follower transistor 203b of the reset gate 204a, the gate of the output transistor 205a and the second pixel cell transistor, a gate of the source follower 204b, the output transistor of the transistor 205b.

参照图3B,为在驱动电路区域形成晶体管的栅介质层和栅极采用的掩模版300,图3C为图3B和图2B的掩模版图叠加,以便于对照。 3B, the gate dielectric layer and a gate driver circuit transistor is formed in the region 300 using the reticle, FIG. 3C is a superposition of a mask layout of FIG. 2B and FIG. 3B, in order to control. 由图3C可以看出,依次相邻的图形203a、 204a、 205a相应于第一像素单元的复位晶体管、 源跟随晶体管和输出晶体管的栅极;依次相邻的图形203b、 204b和205b相应于第二像素单元的复位晶体管、源跟随晶体管和输出晶体管的栅极。 As it can be seen from the 3C, the successively adjacent pattern 203a, 204a, 205a corresponding to the reset transistor in the first pixel unit, the source follower transistor and the gate of the output transistor; sequentially adjacent pattern 203b, 204b and 205b corresponding to the first two pixel cell reset transistor, a source follower transistor and the gate of the output transistor. 另外, 由形成于多晶硅栅的同一层的多晶硅构成的复位导线203a,和203b,把第一像素单元和第二像素单元的复位晶体管的栅极与外围复位控制电路相连;由形成于多晶硅栅的同一层的多晶硅构成的行选导线205a,和205b,把第一4象素单元和第二像素单元的输出晶体管的栅极与外围输出电路相连。 Further, composed of polysilicon is formed on the polysilicon gate layer of the same reset wire 203a, and 203b, is connected to the gate of the reset transistor of the first pixel and the second pixel units and the peripheral units reset control circuit; is formed on the polysilicon gate row select conductor in the same layer of polysilicon 205a, and 205b, is connected to the gate of the output transistor of the first unit and the second pixel 4 pixel units and the peripheral circuit output. 每个像素单元 Each pixel unit

的多晶硅行选导线与多晶硅复位导线相互平行,且相邻的第一像素单元和第二像素单元的多晶硅行选导线相互平行,多晶硅复位导线相互平行。 Polycrystalline polysilicon row line selected from the polysilicon wires and the reset wire parallel and adjacent to the first pixel unit and the second pixel unit is selected from the wires parallel to each other, reset the polysilicon wires parallel to each other. 本实施例采用多晶硅作为行选导线和复位导线与外围行选电路和复位电路相连,每个像素单元减少了两个接触孔,减少了两个金属线。 Example polycrystalline silicon as the present embodiment and the reset row select conductor wire connected to the peripheral circuit and the selected row reset circuit, each pixel unit reduces the two contact holes, reducing the two metal lines.

参照图4A,在半导体衬底201内形成与半导体衬底导电类型相反的深掺杂阱210a和210b,形成深摻杂阱210a和210b为本技术领域人员公知技术, 作为本发明的一个实施方式,采用光刻胶层保护半导体衬底201的驱动电路区域IIIA和IIIB以及隔离区域IA和IB,然后进行n型的深离子注入。 4A, a semiconductor substrate 201 formed in the semiconductor substrate of opposite conductivity type doped deep wells 210a and 210b, form deep 210a and 210b doped well known to those skilled art known techniques, as an embodiment of the present invention. using the drive circuit region 201 and the isolation region IIIA and IIIB IA and IB photoresist layer to protect the semiconductor substrate, and then an n-type ion implantation depth. 深离子注入之后形成的深掺杂阱210a和210b与半导体衬底201 (p型)之间构成PN结,形成光电二极管。 Deep doped wells 210a and 210b constituting the PN junction between the semiconductor substrate 201 (p-type) formed after deep ion implantation, forming a photodiode.

图4B为形成深摻杂辨210a和210b采用的掩模版图400,参照图4C,为掩模版图200、 300和400的叠加,图形210a和210b为深掺杂阱的掩模图形。 4B is formed deep dopant resolution mask layout 400 employed 210a and 210b, 4C, the superposition of a mask layout 200, 300, and 400, graphics mask patterns 210a and 210b as well deep dopant.

参照图5A,在深掺杂阱210a和210b上对应形成与之导电类型相反的浅掺杂区233a和233b;在驱动电路区域IIIA形成浅扩散区206a,、 207a,、 208a,; 在驱动电路区域IIIB形成浅扩散区206b,、207b,、208b,以及驱动电路区域IIIA 和IIIB的共用浅扩散区209,。 5A, a correspondingly formed opposite conductivity type with lightly doped regions 233a and 233b on the deep doped wells 210a and 210b; shallow diffused regions formed in the driving circuit region IIIA 206a ,, 207a ,, 208a ,; driving circuit IIIB region forming a shallow diffusion region 206b ,, 207b ,, 208b, and the common drive circuit shallow diffusion region 209 ,. IIIA and IIIB 其中浅扩散区206a,和206b,分别为驱动电路区域IIIA和IIIB的复位晶体管的浅掺杂源区,所述浅扩散区206a,和206b,分别与深掺杂阱210a和210b相连;浅扩散区207a,和207b,分别为驱动电路区域IIIA和IIIB的复位晶体管与源跟随晶体管的共用浅掺杂漏区;浅扩散区208a, 和208V分别为驱动电路区域IIIA和IIIB的源跟随晶体管和输出晶体管的共用浅摻杂源区;浅扩散区209,为第一像素单元和第二像素单元的输出晶体管的共用浅掺杂漏区。 Wherein shallow diffusion regions 206a, and 206b, respectively, as a light doped source area of ​​the driving circuit region IIIA and IIIB of the reset transistor, said shallow diffusion regions 206a, and 206b, respectively, with the deep doped wells 210a and 210b are connected; shallow diffused region 207a, and 207b, respectively, driving the reset transistor and the source follower transistor common circuit region lightly doped drain regions of IIIA and IIIB; shallow diffusion regions 208a, and 208V respectively, the driving transistor and the source follower output circuit region of IIIA and IIIB a common lightly doped source region of the transistor; common 209, a first output transistor of the pixel unit and the second unit pixel shallow lightly doped drain diffusion region. 形成所述深掺杂阱210a、 210b和形成浅扩散区206a,、 207a,、 208a,、 209,、 208b,、 207b,和206b,为本技术领域人员公知技术。 The doped well is formed deep 210a, 210b, and forming a shallow diffusion regions 206a ,, 207a ,, 208a ,, 209 ,, 208b ,, 207b, and 206b, the present techniques well known to the art. 形成的浅掺杂区233a和233b与深掺杂阱210a和210b由于导电类型相反,构成PN结,在半导体衬底201表面形成PIN,用于定扎半导体衬底201表面的可动电荷,防止CMOS图像传感器产生暗电流。 Lightly doped regions 233a and 233b formed deep doped wells 210a and 210b have opposite conductivity type to form a PN junction, PIN formed on the surface of the semiconductor substrate 201, the semiconductor substrate 201 for a given bar may be movable surface charge, to prevent CMOS image sensor dark current.

参照图5B为形成浅掺杂区233a和233b以及形成源/漏浅扩散区206a,、 207a,、 208a,、 209,、 208b,、 207b,和206b,所采用的掩模版图500,为了简化图示,本实施例仅给出一个掩模版图以示意。 Referring to FIG. 5B to form lightly doped regions 233a and 233b and the source / drain shallow diffusion regions 206a ,, 207a ,, 208a ,, 209 ,, 208b ,, mask layout 207b, and 206b, employed 500 is formed, in order to simplify illustrated, the present embodiment provides only a schematic mask layout. 图5B中虚线示意性分割出浅扩散区206a,、 207a,、 208a,、 209,、 208b,、 207b,和206b,。 5B schematically in dashed lines in FIG segmented shallow diffused regions 206a ,, 207a ,, 208a ,, 209 ,, 208b ,, 207b, and 206b ,. 图5C为以往采用的部分掩^f莫版图叠加,放在一起以便于对照。 5C is a portion of a conventional mask layout using the overlay Mo ^ f, so as to control together. 图5A为图5C沿直线BB,处的剖面图。 5A is a sectional view of FIG. 5C along a straight line BB, of FIG.

参照图6A,首先在半导体衬底201上的第一像素单元的复位晶体管的栅极203a、源跟随晶体管的栅极204a、输出晶体管的栅极205a和第二像素单元的复位晶体管的栅极203b、源跟随晶体管的栅极204b、输出晶体管的栅极205b的两侧形成侧墙,所述形成侧墙的目的为防止后续进行源/漏极离子注入工艺时导致晶体管的源/漏极之间的穿透(lateral diffiision)或者后续形成硅化物工艺时,栅极与浅扩散区之间发生短接。 6A, the first gate of the reset transistor of the first pixel units 201 on the semiconductor substrate 203a, the reset source follower transistor gate 204a, the gate of the output transistor 205a and the second pixel cell transistor gate 203b both sides of the gate 204b, the gate of the output transistor of the source follower transistor 205b formed spacer, the spacer object to prevent the subsequent formation of a source / cause between the source / drain of the transistor when the drain ion implantation process when penetration (lateral diffiision) or a subsequent silicide formation process, the occurrence of short between the gate and the shallow diffused regions. 本发明给出一个比较优化的实施方式,包括,在半导体衬底201上沉积第一氧化硅层,然后沉积氮化硅层,然后再形成第二氧化硅层,所述第一氧化硅层、氮化硅层和第二氧化硅层组成了ONO层,然后采用现有的蚀刻技术(etch-back)依次蚀刻第二氧化硅层、 氮化硅层和第一氧化硅层形成复位晶体管、源跟随晶体管和输出晶体管的側墙。 The present invention gives a more optimal embodiment, comprises, on a semiconductor substrate, depositing a first silicon oxide layer 201 and then depositing a silicon nitride layer, and then forming a second silicon oxide layer, the first silicon oxide layer, silicon nitride layer and a second silicon oxide layer consisting of an ONO layer, and then etching using the prior art (etch-back) etching the second silicon oxide layer sequentially, a first silicon nitride layer and silicon oxide layer is formed a reset transistor, a source follower transistor and the output transistor of the spacer.

然后在半导体衬底201中的第一像素单元的复位晶体管的栅极203a、源跟随晶体管的栅极204a、输出晶体管的栅极205a和第二像素单元的复位晶体管的栅极203b、源跟随晶体管的栅极204b、输出晶体管的栅极205b的两侧进行源/漏极离子注入,所述源/漏极离子注入的离子与形成深掺杂阱210a和210b的深离子注入的离子类型相同,即为n型离子。 The gate of the reset transistor 203a and a first pixel cell in a semiconductor substrate 201, the gate of the reset transistor gate 203b 204a, the gate of the output transistor 205a and the second pixel unit of the source follower transistor, a source follower transistor gate 204b, 205b on both sides of the gate of the output transistor of a source / drain ion implantation, the source / drain ion implantation to form deep dopant ions with the same depth of the ion trap 210a and 210b implanted ion type, that is, n-type ions. 由于复位晶体管的源极与深掺杂阱相连接,复位晶体管的源极不需要进行注入,因此图中未示出。 Since the source of the reset transistor is connected with the deep doped well, the reset transistor source need not be injected, and therefore not shown in FIG. 进行源/漏极离子注入之后,形成第一像素单元和第二像素单元的复位晶体管 After the source / drain ion implantation, forming a first reset transistor and a second pixel unit of the pixel unit

和源跟随晶体管的共用漏极207a和207b、源跟随晶体管和输出晶体管的共用源极208a和208b以及第一像素单元和第二像素单元的输出晶体管的共用漏极209即共用的输出端。 Common drain and source follower transistor 207a and 207b, source electrodes 208a and 208b and follow the common drain of the output transistor of the first pixel unit and the pixel unit 209 i.e. the second common source transistor and the common output terminal of the output transistor.

参照图6B为形成源/漏极采用的掩才莫版图600,图形207a、 207b与复位晶体管和源跟随晶体管的共用漏极207a和207b相对应,图形208a、 208b与源跟随晶体管和输出晶体管的共用源极208a和208b相对应,图形209与输出晶体管的共用漏极209及共用的输出端对应,图6B中虚线示意性分割出源/漏极207a、 207b、 208a、 208b和209。 Referring to FIG. 6B to form Mo mask layout before the source / drain 600 used, graphics 207a, 207b of the reset transistor and source follower transistor common drain 207a and 207b corresponds to pattern 208a, 208b and the source follower transistor and the output transistor common source 208a and 208b corresponds to pattern 209 common drain of the output transistor and the common output terminal 209 corresponds to the broken line in FIG. 6B schematically divided source / drain electrodes 207a, 207b, 208a, 208b and 209. 参照图6C,为以往采用的部分掩模版图的叠加,放在一起以便于对照。 Together 6C, the superimposed portion of the mask used in the conventional layout, in order to control. 图6A为图6C沿BB,处的剖面图。 FIG 6A is a sectional view along the 6C BB, at.

参照图7A,进行上述步骤之后,在半导体衬底201上形成第一介质层216。 After 7A, the above-described steps, a first dielectric layer 216 is formed on the semiconductor substrate 201. 形成所述第一介质层216为本技术领域人员公知技术。 Forming the first dielectric layer 216 known to those skilled art known techniques. 然后在第一介质层216 中对着每个CMOS图像传感器像素单元对的输出晶体管的两个漏极209位置处形成一个填充有导电材料的输出接触孔214;在第一介质层216中对着每个CMOS图像传感器像素单元对的深掺杂阱位置处形成两个深掺杂阱接触孔212a和212b;在对着复位晶体管的漏极207a和207b位置处形成填充有导电材料的两个电源连接接触孔213a和213b;在对着源跟随晶体管的栅极位置处分别形成填充有导电材料的源跟随接触孔215a和215b,由于剖面示意图中未切到源跟随接触孔215a和215b,因此图中以虚线示之。 An output filled with conductive material in contact hole 214 is then formed at two opposite positions of the output transistor 209 the drain of each CMOS image sensor pixel unit in the first dielectric layer 216; in front of the first dielectric layer 216 at a deep location of each doped well CMOS image sensor pixel unit forming two doped well deep contact holes 212a and 212b; two power drain is formed at the opposite position of the reset transistor 207a and 207b is filled with a conductive material connecting the contact holes 213a and 213b; formed at the opposite position of the source follower transistor gate are filled with a conductive material to follow the source contact holes 215a and 215b, due to the uncut source follower schematic cross-sectional view of the contact holes 215a and 215b, and therefore FIG. it is shown in dashed lines.

图7B为第一介质层216上的输出接触孔214、深掺杂阱接触孔212a和212b、电源连接接触孔213a和213b、以及源跟随接触孔215a和215b的掩模版图700。 7B is an output contact hole on the first dielectric layer 216 214, a deep well doped contact holes 212a and 212b, the contact holes 213a and power supply 213b is connected, and a source follower contact holes 215a and 215b of the mask layout 700. 图7C为上述掩模版图的叠加。 7C is superimposed on the mask layout. 图7A为图7C沿BB,处剖面图。 FIG. 7A to FIG 7C is along BB, the cross-sectional view of FIG.

参照图8A,在第一介质层216上形成第一金属层,然后在第一金属层上形成第一光刻胶层,第一光刻胶层上对着输出接触孔214、深掺杂阱接触孔212a和212b、电源连接接触孔213a和213b、以及源跟随4妄触孔215a和215b 定义出相应金属线的图形,以第一光刻胶层为掩模图形化第一金属层,分别形成输出金属线217c、电源连接金属线217b和217d,所述输出金属线217c 与外围输出电路相连;采用第一金属层构成的导线217a和217e分别把深掺杂阱接触孔212a、 212b与源跟随接触孔215a、 215b对应相连。 8A, the first metal layer is formed on the first dielectric layer 216, a first photoresist layer is then formed on the first metal layer, the first photoresist layer toward the output contact hole 214, the deep well doped the contact holes 212a and 212b, the contact holes 213a and power supply 213b is connected, and jump pattern corresponding metal wire 4 and the contact hole 215a 215b define a source follower, the first photoresist layer as a mask to pattern the first metal layer, respectively, the metal wire forming the output 217c, 217b and the power connection metal line 217d, the metal wire 217c is connected to the output peripheral output circuit; wire 217a and the first metal layer 217e using the deep dopant are well contact holes 212a, 212b with the source Follow the contact holes 215a, 215b connected to the corresponding. 所述输出金属线217c把列向像素单元对的输出接触孔相连作为输出端。 The output of the contact hole metal line 217c to the pixel unit as an output terminal coupled to the column.

图8B为第一金属层图形化的掩模版图800,掩模版图800中图形217a 和217e、 217b和217d及217c分别与导线217a和217e、电源连接金属线217b 和217d及输出金属线217c相对应。 8B is a first metal layer patterned mask layout 800, 800 in the mask layout pattern 217a and 217e, 217b and 217c, and 217d and 217e, respectively, with the wires 217a, 217b and the power connection metal line 217d and the output line 217c metal phase correspond. 图8C为以往部分掩模版图叠加,以便于对照,图8A即为图8C沿BB,方向的剖面图。 8C is a portion of a conventional mask layout superimposed, so as to control, that is, a cross-sectional view of FIG 8C 8A along BB, direction.

参照图9A,在第一介质层216以及图形化的第一金属层上形成第二介质层218。 9A, the second dielectric layer 218 is formed on the first dielectric layer 216 and a first metal layer is patterned. 在第二介质层218中对着每个CMOS图像传感器像素单元对的电源连接金属线217b和217d位置处形成填充有导电材料的电源接触孔213a,和213b,。 In the second dielectric layer 218 into the power unit of each pixel of the CMOS image sensor is connected to the metal line 217b and 217d are formed a power contact location hole filled with a conductive material 213a, and 213b ,. 形成电源接触孔213a,和213b,的具体工艺参照上述形成输出接触孔214、深掺杂阱接触孔212a和212b、电源连接接触孔213a和213、以及源跟随接触孔215a和215b的形成工艺。 In particular the process of forming a power contact holes 213a, 213b, and, by referring to the output of the contact hole 214 is formed, the deep well doped contact holes 212a and 212b, the contact holes 213a and power supply connector 213, and a source follower formation process of the contact holes 215a and 215b.

图9B为形成电源接触孔213a,和213b,的掩模版图900,图形213a'和213b, 与电源接触孔213a,和213b,相对应。 9B is formed a power contact hole 213a, and 213b, the mask layout 900, graphics 213a 'and 213b, a power supply contact hole 213a, and 213b, correspond. 图9C为以往部分掩才莫版图的叠加,以便于对照,图9A为图9C沿B-B'方向的剖面图。 9C is a part of a conventional mask was superimposed Mo layout, to facilitate comparison, FIG. 9A to FIG 9C is a cross-sectional view along B-B 'direction.

参照图10A,在第二介质层218上形成第二金属层,然后在第二金属层上形成第二光刻胶层,第二光刻胶层上对着电源接触孔213a,和213b,位置处定义出相应电源金属线图形,以第二光刻胶层为掩模蚀刻第二金属层,形成电源金属线219,所述电源金属线219把电源接触孔213a,与213b,相连且与外围电源电路相连。 10A, a second metal layer formed on the second dielectric layer 218, and a second photoresist layer on the second metal layer, the second photoresist layer into the power contact holes 213a, and 213b, the position defined at the corresponding power supply metal line patterns, a second photoresist layer as a mask in etching the second metal layer, the metal power lines 219, 219 of the power supply metal line contact hole 213a, and 213b, and is connected with the peripheral It is connected to a power supply circuit. 图10B为第二金属层图形化的掩模版图1000,掩模版图1000中图形219 与图10A中的电源金属线219相对应。 10B is a second metal layer patterned mask layout 1000, 1000 in the mask layout pattern 219 of FIG. 10A corresponds to the power supply metal line 219. 图IOC为以往部分掩模版图叠加,以便于对照,图IOA即为图10C沿BB,方向的剖面图。 FIG. IOC is a conventional mask layout portion overlay, so as to control a cross-sectional view in FIG. 10C is the IOA BB, direction.

基于上述工艺实施后,形成本发明的CMOS图像传感器,如图IOA所示, 包括:位于半导体衬底上的至少一个CMOS图像传感器像素单元对,所述CMOS图像传感器像素单元对包括列向相邻的第一像素单元(IIA + IIIA)和第二像素单元(IIB + IIIB),所述每个像素单元包括光电二极管区域IIA或IIB 和驱动电路区域IIIA或IIIB,其中,驱动电路区域形成有输出晶体管,第一像素单元(IIA + IIIA)的输出晶体管和第二像素单元(IIB + IIIB)的输出晶体管的漏极214相连,作为共用的输出端。 On a semiconductor substrate at least one pixel unit of the CMOS image sensor, the CMOS image sensor including the pixel unit adjacent to the columns: After the above process embodiments, the CMOS image sensor formed according to the present invention, as shown in FIG IOAs, including those based on a first pixel unit (IIA IIIA +) and the second pixel unit (IIB + IIIB), said each unit pixel includes a photodiode region IIA or IIB or IIIA and a drive circuit region IIIB, wherein the driving circuit region is formed with an output drain of the transistor, the first pixel unit (IIA + IIIA) of the output transistor and the second pixel unit (IIB + IIIB) of the output transistor 214 connected as a common output terminal.

本发明还给出CMOS图像传感器的布局方法实施例。 The method of the present invention also gives a layout of a CMOS image sensor embodiment. 如图11为CMOS 图像传感器的布局图1100,包括:至少一个CMOS图像传感器像素单元对, 所述CMOS图像传感器像素单元对包括列向相邻的第一像素单元和第二像素单元;CMOS图像传感器像素单元对在行方向上依次排列;同一行方向上的相邻CMOS图像传感器像素单元对的相应像素单元的复位导线、行选导线均相连且平行于行方向;相邻两行CMOS图像传感器像素单元对的复位导线相邻;CMOS图像传感器像素单元对的第一像素单元和第二像素单元具有一个共用的输出端214且第一像素单元和第二像素单元关于共用的输出端214对称;第一像素单元的输出晶体管的栅极205a、源跟随晶体管的栅极204a及复位晶体管的冲册极203a与共用的输出端214依次相邻;第一像素单元的输出晶体管的栅极与形成于同一层的多晶硅行选导线205a,相连;第一像素单元的复位晶体管的漏极与第一单元 11 is a layout diagram of a CMOS image sensor 1100, comprising: at least one pixel unit of the CMOS image sensor, the CMOS image sensor including the unit pixel columns adjacent to the first pixel and the second pixel unit cell; CMOS image sensor pixel units are sequentially arranged in the row direction; reset wire corresponding pixel CMOS image sensor unit cell of the adjacent pixel on the same row direction are connected to line selection conductors and parallel to the row direction; two adjacent rows of the CMOS image sensor pixel units reset adjacent wires; an output of the first CMOS image sensor pixel unit of the pixel unit and a second unit pixel having a common output terminal 214 and the first pixel units and the pixel units on the second end 214 of a common symmetry; a first pixel gate means output transistor 205a, the gate of the source follower red book reset transistor 204a and transistor 203a and the common output terminal 214 sequentially adjacent; gate of the output transistor of the first pixel unit is formed in the same layer polysilicon row selecting wire 205a, is connected; drain of the reset transistor of the first pixel unit and the first unit 源跟随晶体管漏极共用、源极位于光电二极管区域内、栅极与形成于同一层的多晶硅复位导线203a,相连。 The common drain of the source follower transistor, the source electrode is located within the photodiode region, and the polysilicon gate electrode layer is formed on the same reset wire 203a, is connected.

本发明还给出另外一种CMOS图像传感器的形成方法,包括:将位于半导体衬底上的CMOS图像传感器分为至少一个CMOS图像传感器像素单元对区域,所述CMOS图像传感器像素单元对包括列向相邻的第一像素单元和第二像素单元;将每个像素单元分为光电二极管区域和驱动电路区域;在光电二极管区域形成光电二极管;在驱动电路区域形成带有复位晶体管和输出晶体管的驱动电路,第一像素单元和第二像素单元的两个输出晶体管的漏极相连,共用一个输出端;第一像素单元的复位晶体管的漏极与列向相邻的CMOS 图像传感器像素单元对的第二像素单元的复位晶体管的漏极相连,共用一个供电电源输入端;第二像素单元的复位晶体管的漏极与列向相邻的另一CMOS图像传感器像素单元对的第一像素单元的复位晶体管的漏极相连,共用一个供电电源输入端。 The present invention also gives another method of forming a CMOS image sensor, comprising: a CMOS image sensor will be located on a semiconductor substrate is divided into at least one unit of the CMOS image sensor pixel region, the CMOS image sensor including the unit pixel column direction adjacent to the first pixel unit and the second pixel units; units into each pixel photodiode region and a driver circuit region; forming a photodiode in a photodiode region; forming a driver with the reset transistor and the output transistor in the driving circuit region two transistors connected to the drain of the output circuit, a first pixel unit and the second pixel units, a common output terminal; drain of the reset transistor of the first column of the pixel unit adjacent to the CMOS image sensor pixel unit of the drain of the reset transistor is connected to two pixel elements share one power supply input terminal; a first reset transistor and the drain of the pixel unit of the second row reset transistor of a pixel unit of the CMOS image sensor to another cell adjacent to the pixel a drain connected to a common power supply input.

参照图12A,为本发明的另外一种CMOS图像传感器的结构示意图。 Further reference to schematic structural diagram of a CMOS image sensor 12A, the present invention. 图12A给出两个CMOS图像传感器像素单元对的剖面图,图12B给出两个CMOS 图像传感器像素单元对的模版图的叠加。 FIG. 12A gives a sectional view of two of the CMOS image sensor of the pixel unit, is given in FIG. 12B to FIG template overlay two pixel CMOS image sensor unit pair. 图12A为图12B沿CC,处的剖面图。 FIG. 12A FIG. 12B is a sectional view along CC, at. 图12B中的虚线框内为一个CMOS成像传感器像素单元对,沿着列向所述CMOS图像传感器包括第一像素单元(图中标号含b部分)和第二像素单元(图中标号含c部分)。 Within the dashed box of FIG. 12B is a CMOS imaging sensor pixel units including a first pixel unit (including reference section b in the figure) and the second pixel unit to the CMOS image sensor along the column (reference numeral in FIG containing portion c ). 为清楚显示与相邻CMOS成像传感器像素单元对连接关系,沿着列向两侧分别图示出相邻CMOS图像传感器像素单元对的第二像素单元(图中标号含a部分)和另一相邻CMOS图像传感器像素单元对的第一像素单元(图中标号含d部分)。 For clarity CMOS image sensors adjacent pixel units connection relationship, the column of the second pixel, respectively illustrating a CMOS image sensor pixel unit adjacent to the unit (including a reference portion in the figure) with respect to the sides and further o a first pixel unit of the CMOS image sensor pixel unit (in the figure contains reference section d).

结合图12A和12B,可以看出,半导体衬底301中形成隔离槽302即构成隔离区域;隔离区域以外为有源区。 In conjunction with FIGS. 12A and 12B, it can be seen, a semiconductor substrate 301 forming an isolation groove 302 constitute isolation region; isolation region outside an active region. 在CMOS图像传感器像素单元对的有源区分别形成光电二极管以及第一像素单元和第二像素单元的复位晶体管的栅极303b和303c、源跟随晶体管的姗极304b和304c、输出晶体管的栅极305b 和305c。 Gates forming a photodiode and a reset transistor of the first pixel and the second pixel unit cell in the active region of the CMOS image sensor pixel unit of the gate 303b and 303c, Shan electrode of the source follower transistor 304b and 304c, the output transistor 305b and 305c.

所述输出晶体管的栅极与外围行选电路通过多晶硅行选导线305b,和305c,相连;同时形成与第一像素单元相邻的CMOS图像传感器像素单元对的第二像素单元的复位晶体管的栅极303a、源跟随晶体管的栅极3(Ha及输出晶体管的栅极305a,所述输出晶体管的栅极与外围行选电路通过多晶硅行选导线305a,相连;同时还形成与第二像素单元相邻的另一CMOS图像传感器像素单元对的第一像素单元的复位晶体管的栅极303d、源跟随晶体管的栅极3(Hd 及输出晶体管的栅极305d,所述输出晶体管的栅极与外围行选电路通过多晶硅行选导线305d,相连。 Gate of the output transistor of the peripheral circuit is selected by the row line selected from the polysilicon conductor 305b, and 305c, are connected; simultaneously forming a gate of a reset transistor of the second pixel unit adjacent to the first pixel CMOS image sensor pixel unit cell pairs electrode 303a, (Ha gate 3 and the gate of the output transistor of the source follower transistor 305a, the gate of the output transistor and the peripheral circuit by a polysilicon row line selected from the group selected from the conductors 305a, connected; also formed with the second pixel unit with a first gate of the reset transistor 303d pixel CMOS image sensor unit according to another unit adjacent to the pixel, the gate of source follower 3 (305d Hd gate transistor and an output transistor, the gate of the output transistor and the peripheral line row select circuit is selected from polycrystalline silicon conductor 305d, are connected.

在CMOS图像传感器像素单元对的光电二极管区形成深掺杂阱306b及306c;在与第一像素单元相邻CMOS图像传感器像素单元对第二像素单元形成深掺杂阱306a和在与第二像素单元相邻的另一CMOS图像传感器像素单元对的第一像素单元形成深掺杂阱306d;在CMOS图像传感器像素单元对的笫一像素单元和第二像素单元形成复位晶体管与源跟随晶体管的共用漏极313b 和313c、形成源跟随晶体管与输出晶体管的共用源极314b和314c、形成第一像素单元和第二像素单元的两个输出晶体管的共用漏极315;其中,漏极313b 为第一像素单元的复位晶体管、源跟随晶体管和与^目邻的CMOS成像传感器像素单元对的第二像素单元的复位晶体管、源跟随晶体管所共用;漏极313c 为第二像素单元的复位晶体管、源跟随晶体管和与之相邻的另一CMOS成像传感器像素单元对的第一像素单元的复位晶体管、源 Forming a deep well doped 306b and 306c in the photodiode region of the pixel unit of the CMOS image sensor; deep doped well 306a and the second pixel in a CMOS image sensor pixel unit adjacent to the first pixel unit is formed on the second pixel unit another CMOS image sensor pixel unit of the first pixel units adjacent cells forming a deep well doped 306d; forming a reset transistor and the source follower transistor in a pixel unit Zi CMOS image sensor pixel unit of the pixel unit and the second common 313C and the drain 313b, form a common source follower transistor with a source electrode of the output transistor 314b and 314c, 315 form a common drain of two output transistors of the first pixel and the second pixel unit cell; wherein the first drain electrode 313b a reset transistor of the pixel unit, the reset transistor of the second unit pixel source follower transistor and a CMOS image sensor pixel unit adjacent to the ^ purposes, common to the source follower transistor; the drain of the reset transistor 313c is the second pixel unit, the source follower a first transistor and a reset transistor of the pixel cells adjacent to another pixel cell for CMOS image sensors, the source 随晶体管所共用。 Shared with the transistors.

同时在与第一像素单元相邻的CMOS成像传感器像素单元对的第二像素单元形成源跟随晶体管与输出晶体管共用的源极314a和输出晶体管的漏极 A source follower transistor are formed simultaneously with the common source of the output transistor 314a and the drain electrode of the output transistor in the second pixel unit adjacent to the first pixel CMOS imaging sensor pixel unit cell pairs

316, 在与第二像素单元相邻的另一CMOS成像传感器像素单元对的第一像素单元形成源跟随晶体管与输出晶体管共用的源极314d和输出晶体管的漏极 316, is formed in the first pixel unit and the CMOS image sensors other pixel unit adjacent to the second pixel units of the source follower transistor and the common source of the output transistor and the output transistor drain 314d

317。 317.

在半导体衬底301上形成第一介质层320,在第一介质层320中,对着CMOS图像传感器像素单元对的深掺杂阱306b和306c中形成接触孔307b和307c;对着复位晶体管栅极位置处形成复位接触孔303b,和303c,;对着复位晶体管的漏极位置处形成电源连接接触孔311和309;对着源跟随晶体管的栅极位置处形成源跟随接触孔304b,和304c,,对着输出晶体管的共用漏极位置处形成输出连接接触孔310。 The first dielectric layer 320, a first dielectric layer 320, against the CMOS image sensor pixel unit 306b and 306c doped wells deep contact holes 307b and 307c is formed on the substrate 301 is formed on the semiconductor; against the reset transistor gate a reset electrode formed at a position of the contact hole 303b, and 303c ,; opposite positions at the drain of the reset transistor is formed in the contact holes 311 and connected to the power supply 309; position is formed in front of the gate of the source follower transistor, the source follower contact hole 304b, and 304c ,, against common drain at a position of the output transistor forms an output connected to the contact hole 310. 同时在与第一像素单元相邻的CMOS图像传感器像素单元对的第二像素单元的深掺杂阱306a处形成深掺杂阱接触孔307a; 对着复位晶体管栅极位置处形成复位接触孔303a,;对着对着源跟随晶体管的栅极位置处形成源跟随接触孔304a';对着输出晶体管的漏极位置处形成输出连接接触孔312。 Doped well deep contact holes 307a are formed simultaneously in a deep doped well of the second pixel unit 306a of the pixel unit adjacent to the first pixel unit of the CMOS image sensor; a front gate of the reset transistor resetting the position of the contact hole 303a is formed ,; at opposite position opposing the gate of the source follower transistor is a source follower is formed a contact hole 304a '; position against the drain of the output transistor at the output connected to the contact hole 312 is formed.

同样地,在与第二像素单元相邻的另一CMOS图像传感器像素单元对的第一像素单元的深掺杂阱306d处形成深摻杂阱接触孔307d;对着复位晶体管栅极位置处形成复位接触孔303d,;对着源跟随晶体管的栅极位置处形成源跟随接触孔304d,;对着输出晶体管的漏极位置处形成输出连4妄接触孔308。 Similarly, the deep well doped deep contact holes 307d formed in the doped well of the first pixel units 306d of the second cell adjacent to another pixel CMOS image sensor pixel units; a reset transistor gate is formed at a position facing a contact hole 303d ,; reset gate is formed at a position facing the source of the source follower transistor follower contact hole 304d ,; opposite positions at the drain of the output transistor of the output connector 4 is formed a contact hole 308 to jump. 图12A中所述复位接触孔303a,、 303b,、 303c,和303d,、源跟随接触孔304b,、 304c, 、 304a,和304d,由于截面没有切到,因此虚线图示于图12A中。 FIG. 12A reset the contact hole 303a ,, 303b ,, 303c, 303d ,, a source follower, and a contact hole 304b ,, 304c,, 304a, and 304d, due to the cross-section is not cut, and therefore shown in dashed lines in FIG. 12A.

在半导体衬底301中形成上述结构的具体工艺请参照图2A、图3A、图4A、图5A、图6A、图7A、图8A、图9A、图10A及图2B、图3B、图4B、 图5B、图6B、图7B、图8B、图9B、图10B和图3C、图4C、图5C、图6C、 图7C、图8C、图9C、图IOC及其相关工艺描述。 Specific process of forming the structure in a semiconductor substrate 301 Referring to FIGS. 2A, 3A, FIG. 4A, 5A, FIG. 6A, 7A, FIG. 8A, 9A, 10A and FIGS. 2B, FIGS. 3B, 4B, the FIGS. 5B, 6B, and 7B, and 8B, FIGS. 9B, 10B and 3C, 4C, and 5C, 6C, 7C, the to Figure 8C, 9C, the process described in FIG. IOC and related FIGS.

参照图13A,在第一介质层320上形成第一金属层,然后在第一金属层上形成光刻胶层,第一光刻胶层上对着深掺杂阱接触孔307a、 307b、 307c、 307d和源跟随接触孔304a,、 304b,、 304c,、 304d,位置定义出第一导线把深掺杂阱接触孔与源跟随接触孔对应相连;对着复位接触孔303a,、 303b,、 303c, 及303d,位置处定义出第二导线形状与外围复位电路相连;对着电源连接接触孔311和309位置处定义出电源连接金属线形状;对着输出连接接触孔312、 310及308位置处定义输出连接金属线。 13A, the first dielectric layer is formed on the first metal layer 320, a photoresist layer is then formed on the first metal layer, a first photoresist layer over the doped well against the deep contact holes 307a, 307b, 307c , 307d and the source follower contact hole 304a ,, 304b ,, 304c ,, 304d, defining a first position of the wire contact hole deep well doped source follower connected to the corresponding contact hole; reset against a contact hole 303a ,, 303b ,, 303c, and 303d, at a position defining a peripheral shape of the second conductor is connected to the reset circuit; defines the power supply connection metal line shape in front of the power supply connected to the contact holes 311 and 309 positions; output connector against the contact holes 312, 310 and 308 positions defined output connection metal wire. 以光刻胶层为掩模蚀刻第一金属层, 分别形成第一导线307a,、 307b,、 307c,和307d,;形成第二导线303a"、 303b"、 Etching the photoresist layer as a mask in a first metal layer, forming a first conductor 307a ,, 307b ,, 307c, and 307d ,; forming a second conductor 303a ", 303b",

33303c"和303d";形成电源连接金属线309'和311,;形成输出连接金属线308,、 310,和312'。 33303c "and 303d"; in power connection 309 'and 311 are formed ,; output bonding wires 308,, 310, and 312' of metal wire. 图13A中所述第一导线303a"、 303b"、 303c"和303d"由于截面没有切到,因此图中以虛线表示。 FIG. 13A of the first wire 303a ", 303b", 303c "and 303d" because the cross section is not cut, and therefore shown in dashed lines in FIG.

图13B为第一金属层图形化的掩模版图1300,掩模版图1300中图形303a"、 303b"、 303c"和303d"分别与第二导线303a"、 303b"、 303c"和303d" 相对应;图形307a,、 307b,、 307c,和307d,分别与第一导线307a,、 307b,、 307c, 和307d,相对应;图形308'、 310,和312,分别与输出连接金属线308,、 310,和312'相对应;图形309,和311'分别与电源连接金属线309'和311,相对应。 13B is a first metal layer patterned mask layout 1300, 1300 in the mask layout pattern 303a ", 303b", 303c "and 303d", respectively, and the second conductor 303a ", 303b", 303c "and 303d" corresponds ; pattern 307a ,, 307b ,, 307c, and 307d, respectively, a first wire 307a ,, 307b ,, 307c, and 307d, corresponds; graphic 308 ', 310, and 312 are connected to the metal line 308 and the output ,, 310, and 312 'correspond; graphic 309, and 311' are connected to metal lines 309 'and 311 to the power source, respectively. 图13C为以往部分掩^f莫版图叠加,以便于对照,图13A即为图13C沿CC,方向的剖面图。 13C is a sectional view of FIG. 13A FIG. 13C in the CC, the direction that is part of a conventional mask layout superimposed Mo ^ f, in order to control, FIG.

参照图14A,在第一介质层320以及由第一金属层构成的输出金属线和电源连接金属线以及导线上形成第二介质层321;在第二介质层321中对着每个CMOS图像传感器像素单元对的输出连接金属线308,、 310,和312,位置处形成填充有导电材料的输出接触孔308"、 310,,和312";在对着电源连接金属线309'和311,位置处形成电源接触孔309"和311"。 Referring to FIG 14A, the second dielectric layer 321 formed on the first dielectric layer 320 and the metal line and the power supply output comprising a first metal layer on the metal wire and a wire connection; a second dielectric layer 321 opposite each of the CMOS image sensor the output of the pixel cell connected to the metal line 308,, 310, and 312, the output of the contact hole is filled with a conductive material is formed at a position 308 ', 310,, and 312 "; the metal lines into the power connector 309' and 311, the position of a contact hole 309 formed at the power "and 311."

图14B为形成输出接触孔308"、 310"和312"和形成电源接触孔309"和311"的掩模版图1400,图形308"、 310"和312"与输出接触孔308"、 310"和312"相对应;掩模版图1400中图形309"和311"与电源接触孔309"和311" 相对应。图14C为以往部分掩模版图的叠加,以便于对照,图14A为图14C 沿C-C'方向的剖面图。 14B is formed in the contact hole 308 output ", 310" and 312 "and a contact hole 309 formed in the power" and 311 "in a mask layout 1400, pattern 308", 310 "and 312" and the output of the contact hole 308 ', 310 ", and 312 "corresponds; mask layout pattern 1400 309." and 311 "and the power supply contact hole 309" and 311 "corresponding to FIG. 14C is a portion of the mask layout is a conventional overlay, in order to control, FIG. 14A FIG. 14C is in the C FIG sectional -C 'direction.

参照图15A,在第二介质层321上形成第二金属层,然后在第二金属层上形成第二光刻胶层,第二光刻胶层上对着电源接触孔309"和311"位置处定义出相应金属线图形,对着输出接触孔308"、 310"和312"位置处定义出相应金属线图形,然后以第二光刻胶层为掩模蚀刻第二金属层,分别形成第一像素羊元的和与第一像素单元相邻的CMOS图像传感器的第二像素单元共用的电源金属线311,"以及第二像素单元的以及与第二像素单元相邻的另一CMOS 图像传感器的第一像素单元共用的电源金属线309,";形成第一像素单元和第二像素单元共用的输出金属线310,,,以及与CMOS图像传感器像素单元对两側相邻的输出金属线312,"和308",。所述电源金属线311",和309",相连成一条金属线与外围供电电源电路相连,所述输出金属线308",、 310",以及312", 相连成另一条金属线与外围输出 15A, a second metal layer formed on the second dielectric layer 321, and a second photoresist layer on the second metal layer, the contact hole 309 into the power "and 311" position on the second photoresist layer define the respective metal line pattern, a contact hole 308 opposite output ", 310" and 312 at the position "defines a corresponding metal line pattern and the second photoresist layer as a mask to etch the second metal layer, are formed of a second pixel unit and the pixel unit adjacent to the first pixel of the CMOS image sensor elements common sheep power metal lines 311, "and a second unit pixel CMOS image sensor and the other pixel unit adjacent to the second a first pixel power units sharing metal line 309 "; forming a first pixel unit and the second pixel unit common output line 310 ,,, metal and a CMOS image sensor pixel unit adjacent to the output sides of the metal line 312 "and 308" of the power supply metal line ,. 311 ", and 309" is connected to a metal power supply lines connected to the peripheral circuit, the output of the metal wire 308 ',, 310', and 312 ", is connected to another a metal wire and the peripheral output 电路相连,如图15B所示。 Circuit is connected, as shown in FIG. 15B.

图15B为形成电源金属线311,"、 309,"和输出金属线308,"、 310,"以及312",的掩模版图1500,图15C为以往部分掩模版图的叠加,以便于对照,图15A为图15C沿C-C'方向的剖面图。 15B is forming a power supply metal line 311 ", 309," and the output of the metal wire 308, "310" and 312 ", the mask layout 1500, FIG. 15C is a portion of the mask layout is a conventional overlay, in order to control, FIG 15A is a cross-sectional view 'direction of FIG 15C along line C-C.

基于以上工艺实施后最终形成的CMOS图像传感器如图15A所示,包括至少一个CMOS图像传感器像素单元对,所述CMOS图像传感器像素单元对包括第一像素单元和第二像素单元;每个所述像素单元包括光电二极管区域和驱动电路区域;其中,驱动电路区域包括有复位晶体管和输出晶体管;第一像素单元和第二像素单元的两个输出晶体管的漏极相连,共用一个输出端; 第一像素单元的复位晶体管的漏极与列向相邻的CMOS图像传感器像素单元对的第二像素单元的复位晶体管的漏极相连,共用一个供电电源输入端;第 , Includes at least one pixel unit of the CMOS image sensor, the CMOS image sensor pixel unit comprises a first pixel unit and the second unit pixel CMOS image sensor based on the procedure described above in FIG. 15A finally formed; each photodiode region including the pixel unit and the driving circuit region; wherein the region driving circuit includes a reset transistor and an output transistor; the drain of the output transistor of the first two pixel units and the second pixel unit is connected to a common output terminal; a first drain of the reset transistor of the second pixel units and the drain of the reset transistor of the pixel columns of the adjacent cell of the CMOS image sensor pixel unit is connected to a common power supply input terminal; a second

二像素单元的复位晶体管的漏极与列向相邻的另一CMOS图像传感器像素单元对的第一像素单元的复位晶体管的漏极相连,共用一个供电电源输入端。 Drain of the reset transistor of the first pixel unit and the drain of the reset transistor column two of the pixel unit to another unit adjacent to the CMOS image sensor pixel is connected to a common power supply input.

本发明还给出如上所述CMOS图像传感器的布局方法实施例,如图16 为CMOS图像传感器的布局图1600,包括:至少一个CMOS图像传感器像素单元对,所述CMOS图像传感器像素单元对包括列向相邻的第一像素单元和第二像素单元;CMOS图像传感器像素单元对在行方向上依次排列;同一行方向上的相邻CMOS图像传感器像素单元对的相应像素单元的行选导线均相连且平行于行方向;相邻两行CMOS图像传感器像素单元对的复位晶体管相邻。 Embodiments of the invention further gives a CMOS image sensor layout method described above, as shown in FIG. 16 is a layout of a CMOS image sensor 1600, comprising: at least one pixel unit of the CMOS image sensor, the CMOS image sensor including the unit pixel columns CMOS image sensors are sequentially arranged in the row direction of the pixel unit;; adjacent to the first pixel unit and the second unit pixel row selected from the pixel corresponding conductor elements of the CMOS image sensor pixel unit adjacent on the same row direction are connected in parallel and in the row direction; two lines of the reset transistor CMOS image sensor pixel unit of an adjacent neighbor. 图16中虚线框内为一个CMOS图像传感器像素单元对,CMOS图像传感器像素单元对的第一像素单元和第二像素单元具有一个共用的输出端 The dashed box in FIG. 16 is a CMOS image sensor pixel units, the first unit pixel of the CMOS image sensor pixel unit and a second unit pixel having a common output terminal

310且第一像素单元和第二像素单元关于共用的输出端310对称;第一像素单元的输出晶体管的栅极305b、源跟随晶体管的栅极304b及复位晶体管的栅极303a与共用的输出端310依次相邻;第一像素单元的输出晶体管的栅极与形成于同一层的多晶硅行选导线305b,相连;第一像素单元的复位晶体管的漏极与列向相邻的CMOS图像传感器像素单元对的第二像素单元的复位晶体管的漏极相连,作为共用的供电电源输入端,并形成有电源连接接触孔311;第二像素单元的复位晶体管的漏极与列向相邻的另一CMOS图像传感器像素单元对的第一像素单元的复位晶体管的漏极相连,作为共用的供电电源输入端, 并形成有电源连接接触孔309。 Unit 310 and the first pixel and the second pixel output unit 310 symmetrical about the common terminal; a gate of the output transistor 305b of the first pixel unit, the gate of the source follower output terminal 303a and 304b to a common reset transistor gate transistor 310 adjacent turn; the gate of the output transistor of the first pixel unit formed in the same layer of polysilicon line selection conductors 305b, connected; drain of the reset transistor of the first column to the pixel unit adjacent to the CMOS image sensor pixel unit the drain of the reset transistor is connected to a second pixel unit, as a common power supply input terminal, and a contact hole is formed with a power connection 311; the drain of the reset transistor of the second pixel units and the column adjacent to the other CMOS drain of the reset transistor of the first pixel unit of the image sensor pixel unit is connected to the power supply as a common input terminal, and is formed with a contact hole 309 connected to the power supply.

本发明给出的CMOS成像传感器像素单元对通过同一列像素单元共用电源接触孔或者输出接触孔降低了有效接触孔数量。 CMOS image sensor pixel unit of the present invention is given by the same common power contact hole pixel unit or an output contact hole reduces the effective number of contact holes. 这种结构使得能够在没有降低技术节点条件下设计更小尺寸的像素单元。 This structure enables the pixel unit can be designed in a smaller size is not reduced under conditions technology node. 不需要任何外围电路修改和工艺参数的修改,也不会增加掩模的成本和制造成本。 A peripheral circuit without any modification to modify and process parameters, does not increase the manufacturing cost and the cost of the mask. 更少的接触孔意味着更小的输出电容,更大的填充比和更好的光学路径,本发明的技术可以应用与四个晶体管的CIS结构中。 Less contact hole means a smaller output capacitance, greater than the filling and better optical paths, the techniques of this invention may be applied to the structure in which four transistors CIS.

采用本发明技术制备的CMOS图像传感器具有较小的像素单元尺寸,根据当前0.18jtmiCMOS图像传感器设计MJ'j设计的三个晶体管的CMOS图像传感器结构面积为2.4x2.4nm2,由于同一列的相邻像素单元的输出接触孔共用或者电源接触孔和输出接触孔两者都共用,获得较高的光电二极管面积的填充因子(fill factor)。 The present invention is prepared using art CMOS image sensor has a pixel smaller cell size, the area of ​​the CMOS image sensor structure of three transistors of the current image sensor is designed MJ'j 0.18jtmiCMOS designed for 2.4x2.4nm2, for the same adjacent row output unit pixel contact hole or a common power supply contact hole and both outputs are shared contact hole, the area of ​​the photodiode to obtain a higher fill factor (fill factor). 同时本发明仅使用两层金属层,使得微透镜能够把入射光聚焦在更小的光电二极管上以保证较好的量子效率和避免串绕,获得更好的图像质量。 While the invention using only two metal layers, so that the microlenses able to focus incident light on the photodiode smaller in order to ensure a better quantum efficiency, and to avoid crosstalk, better image quality is obtained.

虽然本发明己以较佳实施例披露如上,但本发明并非限定于此。 While the present invention has disclosed the preferred embodiments described above, but the present invention is not limited thereto. 任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。 Anyone skilled in the art, without departing from the spirit and scope of the present invention, various changes or modifications may be made, and therefore the scope of the present invention reference should be made to the scope defined by the claims.

Claims (34)

  1. 1. 一种CMOS图像传感器,包括:位于半导体衬底上的至少一个CMOS图像传感器像素单元对,所述CMOS图像传感器像素单元对包括列向相邻的第一像素单元和第二像素单元,所述每个像素单元包括光电二极管区域和驱动电路区域,其中,驱动电路区域形成有输出晶体管,其特征在于,第一像素单元的输出晶体管和第二像素单元的输出晶体管的漏极共用,作为共用的输出端。 1. A CMOS image sensor, comprising: at least on a semiconductor substrate of a CMOS image sensor pixel unit, the CMOS image sensor including the unit pixel columns adjacent to the first pixel and the second pixel unit cell, the each said pixel unit includes a photodiode region and a driver circuit area, wherein the driving circuit region is formed with the output transistor, wherein the common drain of the output transistor of the output transistor of the first pixel and the second pixel unit cell, as a common an output terminal.
  2. 2. 根据权利要求1所述的CMOS图像传感器,其特征在于:所述第一像素单元与第二像素单元关于共用的输出端对称;第一像素单元的输出晶体管的栅极与形成于同一层的多晶硅行选导线相连,且与外围行选电路相连;第一像素单元源跟随晶体管的源极与第一像素单元输出晶体管源极共用;第一像素单元的复位晶体管的漏极与第一像素单元的源跟随晶体管漏极共用、源极位于光电二极管区域内、栅极通过形成于同一层的多晶硅复位导线与外围复位控制电路相连。 The CMOS image sensor according to claim 1, wherein: the first pixel and the second pixel unit cell symmetry about a common output terminal; gate of the output transistor of the first pixel unit is formed in the same layer polysilicon line selection conductors are connected, and is connected to the peripheral line selection circuit; a first pixel source follower transistor cell source electrode and the first common source output transistor pixel cell; drain of the reset transistor of the first pixel with the first pixel units source follower transistor cells share a drain, a source located within the photodiode region, a gate wire and connected by a peripheral reset control circuit formed in the same polysilicon layer reset.
  3. 3. 根据权利要求2所述的CMOS图像传感器,其特征在于:每个像素单元的多晶硅行选导线与多晶硅复位导线相互平行,且相邻的第一像素单元和第二像素单元的多晶硅行选导线相互平行,多晶硅复位导线相互平行。 3. CMOS image sensor according to claim 2, characterized in that: the polysilicon row select conductor for each pixel cell and reset the polysilicon wires parallel to each other, and the first unit and the second pixel adjacent to the pixel cell line selected from the polysilicon parallel wires, parallel wires polysilicon reset.
  4. 4. 根据权利要求3所述的CMOS图像传感器,其特征在于:所述光电二极管区域包括形成于半导体衬底中的与半导体村底导电类型相反的深摻杂辨、 位于深掺杂阱上的与深掺杂阱导电类型相反的浅掺杂区。 4. CMOS image sensor according to claim 3, wherein: said photodiode region formed in a semiconductor substrate comprising a semiconductor substrate opposite to the conductivity type deep dopant identified, located on the deep doped well lightly doped well region of the opposite conductivity type doped deep.
  5. 5. 根据权利要求4所述的CMOS图像传感器,其特征在于: 半导体衬底上还形成有第一介质层;在第一介质层中对着第一像素单元和第二像素单元的输出晶体管的共用的输出端处的填充有导电材料的输出接触孔;在第一介质层中分别对着第一像素单元和第二像素单元的深掺杂阱位置处的填充有导电材料的深掺杂阱接触孔;在第一介质层中分别对着第一像素单元和第二像素单元的复位晶体管的漏极位置处的填充有导电材料的电源连接接触孔;在第一介质层中分别对着第一像素单元和第二像素单元的源跟随晶体管的栅极位置处的填充有导电材料的源跟随接触孔。 The CMOS image sensor according to claim 4, wherein: a first dielectric layer is further formed on a semiconductor substrate; a first dielectric layer opposite the first pixel unit and a second output transistor of the pixel unit filled at the output of the output common contact hole conductive material; in the first dielectric layer facing each well filled deep dopant at a first location and a second pixel unit of the pixel unit with a conductive material doped well deep contact hole; positions are filled at the drain of the reset transistor of the first pixel and the second pixel unit has a power unit against the contact hole connecting the conductive material in the first dielectric layer; the dielectric layer, respectively, against the first section filling a pixel at the position of the gate unit and the second source follower transistor of the pixel unit has a source of electrically conductive material following the contact hole.
  6. 6. 根据权利要求5所述的CM0S图像传感器,其特征在于:所述CMOS图像传感器还包括第一介质层上对着输出接触孔位置处的由第一金属层构成的输出金属线,所述输出金属线与外围输出电路相连;第一介质层上对着电源连接接触孔位置处的由第一金属层构成的电源连4妻金属线;以及由第一金属层构成的把每个CMOS图像传感器像素单元的深掺杂阱接触孔与源跟随接触孔相连的导线。 6. The image sensor as claimed in claim CM0S 5, wherein: the CMOS image sensor further includes an output line of the first metal dielectric layer opposite the first metal layer outputted at the contact hole position configuration, the metal wire and the output is connected to the peripheral circuit output; a first dielectric layer on the front of the power metal layer made of a first power supply connection at the position of the contact hole metal line connected wife 4; and each of the CMOS image composed of the first metal layer a contact hole deep well doped source follower wire sensor pixel unit connected to the contact hole.
  7. 7. 根据权利要求6所述的CMOS图像传感器,其特征在于:所述CMOS图像传感器还包括位于第一金属层上的第二介质层、以及第二介质层中对着每个CMOS图像传感器像素单元对的两个电源连接金属线位置处的填充有导电材料的电源接触孔。 7. The CMOS image sensor according to claim 6, wherein: the CMOS image sensor further includes a second dielectric layer on the first metal layer, and a second dielectric layer facing each CMOS image sensor pixel cells with two power connection wire positions of the power supply contact hole conductive material.
  8. 8. 根据权利要求7所述的CMOS图像传感器,其特征在于:所述第二介质层上对着每个CMOS图像传感器像素单元对的两个电源接触孔处形成有由第二金属层构成的电源金属线,所述电源金属线与外围供电电源电路相连。 8. The CMOS image sensor according to claim 7, wherein: said formed with a second metal layer opposite the two contact holes at each power CMOS image sensor pixel units on the second dielectric layer power metal lines, metal lines connected to the power supply and the peripheral power supply circuit.
  9. 9. 一种CMOS图像传感器的形成方法,包括: 将位于半导体衬底上的CMOS图像传感器分为至少一个CMOS图像传感器像素单元对区域,所述CMOS图像传感器像素单元对包括列向相邻的第一像素单元和第二像素单元;将每个像素单元分为光电二极管区域和驱动电路区域;在光电二极管区域形成光电二极管;在驱动电路区域形成带有输出晶体管的驱动电路;其特征在于,第一像素单元的输出晶体管和第二像素单元的输出晶体管漏极共用,作为共用输出端。 9. A method of forming a CMOS image sensor, comprising: a CMOS image sensor will be located on a semiconductor substrate is divided into at least a CMOS image sensor pixel unit of area, including the adjacent first column of the CMOS image sensor pixel unit a second pixel units and the pixel units; units into each pixel photodiode region and a driver circuit region; forming a photodiode in a photodiode region; forming the driver circuit with an output transistor in the driving circuit region; wherein the first the common drain of the output transistor of the output transistor of the pixel unit and the second pixel unit, as a common output terminal.
  10. 10. 根据权利要求9所述的CMOS图像传感器的形成方法,其特征在于:所述第一像素单元与第二像素单元关于共用的输出端对称; 第一单元的输出晶体管的栅极通过形成于同一层的多晶硅行选导线与外围4亍选电^各相连;第一单元的源跟随晶体管的源极与第一单元的输出晶体管源极共用; 第一单元的复位晶体管的栅极通过形成于同一层的多晶硅复位导线与外围复位控制电路相连、漏极与第一单元的源跟随晶体管漏极共用、源极位于光电二才及管区域内。 10. A method of forming a CMOS image sensor according to claim 9, wherein: the first pixel and the second pixel unit cell symmetry about a common output terminal; a first gate of the output transistor is formed in the cell by is selected from the same layer of polysilicon wires and the peripheral line 4 is connected to each of the right foot is selected from electrically ^; the source of the output transistor of the source follower transistor of the first cell and the first cell of the common electrode; a first gate of the reset transistor is formed in the cell by the same polysilicon layer and the reset wire is connected to the peripheral reset control circuit, a source follower drain of the first unit common drain of the transistor, the source is located in the tube and only the photodiode area.
  11. 11. 根据权利要求10所述的CMOS图像传感器的形成方法,其特征在于:每个像素单元的多晶硅行选导线与多晶硅复位导线相互平行,且相邻的第一像素单元和第二像素单元的多晶硅行选导线相互平行,多晶硅复位导线相互平行。 11. A method of forming a CMOS image sensor according to claim 10, wherein: each pixel element is a polysilicon line is selected from the polysilicon wire and the reset wire are parallel, and the cell adjacent to the first pixel and the second pixel unit poly row select conductor parallel to each other, reset the polysilicon wires parallel to each other.
  12. 12. 根据权利要求11所述的CMOS图像传感器的形成方法,其特征在于:形成所述光电二极管包括在半导体衬底中形成半导体衬底导电类型相反的深掺杂阱、以及在深掺杂阱上形成与深掺杂阱导电类型相反的浅掺杂区。 12. The method of forming a CMOS image sensor 11 according to claim wherein: forming the photodiode comprises forming a semiconductor substrate of opposite conductivity type doped well of a deep well in a semiconductor substrate doped well deep formed deep well doped opposite to the conductivity type lightly doped region.
  13. 13. 根据权利要求12所述的CMOS图像传感器的形成方法,其特征在于: 还包括在半导体衬底上形成第一介质层;在第一介质层中对着每个CMOS图像传感器像素单元对的输出晶体管的共用输出端位置处形成一个填充有导电材料的输出接触孔;在第一介质层中对着每个CMOS图像传感器像素单元对的深掺杂阱位置处形成填充有导电材料的深掺杂阱接触孔;在第一介质层中对着每个CMOS图像传感器像素单元对的复位晶体管的漏极位置处形成填充有导电材料的电源连接接触孔;以及在第一介质层中对着每个CMOS图像传感器像素单元对的源跟随晶体管的栅极位置处形成填充有导电材料的源跟随接触孔。 13. A method of forming a CMOS image sensor as claimed in claim 12, characterized in further comprising: forming a first dielectric layer on a semiconductor substrate; a first dielectric layer facing each CMOS image sensor pixel units of at the common output terminal of the output transistor forms the output position of a contact hole filled with a conductive material; forming a doped conductive material is filled deep at the deep doped well against the position of each pixel of the CMOS image sensor means in a first dielectric layer heteroaryl well contact hole; forming a power connection contact hole is filled with a conductive material in a position facing the drain of the reset transistor at each pixel cell of the CMOS image sensor in the first dielectric layer; and against each of the first dielectric layer a source of a CMOS image sensor pixel unit to follow the position of the gate of the transistor forming a source follower with a conductive material filled contact hole.
  14. 14. 根据权利要求13所述的CMOS图像传感器的形成方法,其特征在于: 还包括在第一介质层上对着输出接触孔位置处形成由第一金属层构成的输出金属线,所述输出金属线与外围输出电路相连;在第一介质层上电源连接"^妄触孔位置处形成由第一金属层构成的电源连接金属线;在第一介质层上采用第一金属层构成的导线把每个CMOS图像传感器像素单元的深掺杂阱接触孔与源跟随接触孔相连。 14. A method of forming a CMOS image sensor according to claim 13, characterized in that: further comprising a metal wire forming an output of the first metal layer opposite the contact hole at the output location on the first dielectric layer, the output metal lines connected to the peripheral circuit output; power connector "^ a connection from the power of the first metal layer at the jump wire contact hole locations on the first dielectric layer; a first metal conductor layer formed on the first dielectric layer using the deep well doped source contact holes each CMOS image sensor pixel unit is connected to the contact hole is followed.
  15. 15. 根据权利要求14所述的CMOS图像传感器的形成方法,其特征在于:还包括在第一金属层上形成第二介质层;以及在第二介质层中对着每个CMOS图像传感器像素单元对的两个电源连接金属线位置处形成填充有导电材料的电源接触孔。 14 15. A method for forming a CMOS image sensor according to claim, characterized in that: further comprising a second dielectric layer formed on the first metal layer; and a second dielectric layer facing each CMOS image sensor pixel unit the connection of the two power supply wire positions forming a contact hole filled with a conductive material.
  16. 16. 根据权利要求15所述的CMOS图像传感器的形成方法,其特征在于:在第二介质层上对着每个CMOS图像传感器像素单元对的两个电源接触孔上形成由第二金属层构成的电源金属线。 15 16. A method for forming a CMOS image sensor according to claim, wherein: the second metal layer is formed is constituted by the two opposite power supply contact holes each CMOS image sensor pixel units on the second dielectric layer the power metal lines.
  17. 17. —种如权利要求1所述CMOS图像传感器的布局方法,其特征在于,包括: 至少一个CMOS图像传感器像素单元对,所述CMOS图像传感器像素单元对包括列向相邻的第一像素单元和第二像素单元;CMOS图像传感器像素单元对在行方向上依次排列;同一行方向上的相邻CMOS图像传感器像素单元对的相应像素单元的复位导线、行选导线均相连且平行于行方向;相邻两行CMOS图像传感器像素单元对的复位导线相邻; CMOS图像传感器像素单元对的笫一像素单元和第二像素单元具有一个共用输出端且第一像素单元和第二像素单元关于共用的输出端对称;第一像素单元的输出晶体管、源跟随晶体管及复位晶体管的栅极与共用的输出端依次相邻;第一像素单元的栅极与形成于同一层的多晶硅行选导线相连;第一像素单元的复位晶体管的漏极与第一单元的源跟随晶体管漏极共 17. - The method of the kind of layout. 1 The CMOS image sensor as claimed in claim, characterized in that it comprises: at least one pixel unit of the CMOS image sensor, the CMOS image sensor pixel unit includes a first unit pixel columns adjacent to each and a second pixel unit; CMOS image sensor pixel sequentially arranged in the row direction of the unit; reset wire corresponding pixel CMOS image sensor unit cell of the adjacent pixel on the same row direction are connected to line selection conductors and parallel to the row direction; phase o two reset rows leads CMOS image sensor pixel of adjacent unit; Zi, a CMOS image sensor pixel unit of the pixel unit and a second pixel output unit having a common output terminal and the first pixel and the second pixel units on a common unit symmetrical end; the output transistor of the first pixel unit, the output of the source follower transistor and the gate of the common reset transistor adjacent turn; a first pixel unit is connected to a gate formed in the same layer of polysilicon row select conductor; first a source follower transistor drain of the reset transistor of the pixel unit and the first unit co 、源极位于光电二极管区域内、栅极与形成于同一层的多晶硅复位导线相连。 Source located within the photodiode region, and the polysilicon gate electrode is formed in the same layer of wires is connected to the reset.
  18. 18. —种CMOS图像传感器,包括:位于半导体衬底上的至少一个CMOS图像传感器像素单元对,所述CMOS图像传感器像素单元对包括列向相邻的第一像素单元和第二像素单元,所述每个像素单元包括光电二极管区域和驱动电路区域,其中,驱动电路区域形成有复位晶体管和输出晶体管,其特征在于,第一像素单元的输出晶体管和第二像素单元的输出晶体管的漏极相连,作为共用的输出端;第一像素单元的复位晶体管的漏极与列向相邻的CMOS图像传感器像素单元对的第二像素单元的复位晶体管的漏极相连,作为共用的供电电源输入端;第二像素单元的复位晶体管的漏极与列向相邻的另一CMOS图像传感器像素单元对的第一像素单元的复位晶体管的漏极相连,作为共用的供电电源输入端。 18. - kind of the CMOS image sensor, comprising: at least on a semiconductor substrate of a CMOS image sensor pixel unit, the CMOS image sensor pixel unit of the first pixel and the second pixel unit comprises a unit to an adjacent column, the each said pixel unit includes a photodiode region and a driver circuit area, wherein the driving circuit region is formed with a reset transistor and an output transistor, wherein the output transistor is connected to the drain of an output transistor of the first pixel and the second pixel unit cell , as a common output terminal; a second transistor connected to the drain of the reset drain of the reset transistor of the pixel cells of the first column of the pixel unit adjacent to the CMOS image sensor pixel unit, as a common power supply input terminal; drain of the reset transistor of the first pixel unit and the drain of the reset transistor of the second column of the pixel unit to another unit adjacent to the CMOS image sensor pixel is connected to a common power supply input.
  19. 19. 根据权利要求18所述的CMOS图像传感器,其特征在于: 所述第一像素单元与第二像素单元关于共用的输出端对称;第一像素单元的输出晶体管的栅极与形成于同一层的多晶硅行选导线相连,且与外围行选电路相连;第一像素单元的源跟随晶体管的源极与第一像素单元的输出晶体管源极共用;第一像素单元的复位晶体管的源极位于第一像素单元的光电二极管区域内;与第一像素单元列向相邻的CMOS图像传感器像素单元对的第二像素单元的复位晶体管的源极位于相应像素单元的光电二极管区域内。 19. CMOS image sensor according to claim 18, wherein: the first pixel and the second pixel unit cell symmetry about a common output terminal; gate of the output transistor of the first pixel unit is formed in the same layer polysilicon line selection conductors are connected, and is connected to the peripheral line selection circuit; source of the source follower transistor of the first unit pixel electrode common electrode of the output transistor of the first source pixel unit; the source of the reset transistor of the first pixel units located on the pole the photodiode region of a pixel unit; source of the reset transistor in the second pixel unit adjacent to the CMOS image sensor pixel unit and the first pixel electrode is located in the cell row corresponding to the photodiode region of the pixel unit.
  20. 20. 根据权利要求19所述的CMOS图像传感器,其特征在于:所述CMOS图像传感器像素单元对的第一像素单元和第二像素单元的多晶硅行选导线相互平行。 20. The CMOS image sensor as claimed in claim 19, wherein: the first pixel cell row of the polysilicon CMOS image sensor pixel units and the pixel units selected from the second conductor parallel to each other.
  21. 21. 根据权利要求20所述的CMOS图像传感器,其特征在于:所述光电二极阱、位于深掺杂阱上的与深掺杂辨导电类型相反的浅掺杂区。 21. CMOS image sensor according to claim 20, wherein: said photodiode well, located deep doped deep dopant conductivity type opposite to distinguish shallow doping region on well.
  22. 22. 根据权利要求21所述的CMOS图像传感器,其特征在于: 半导体衬底上还形成有第一介质层;在第一介质层中对着CMOS图像传感器像素单元对的输出晶体管的共用的输出端处的填充有导电材料的输出连接接触孔;在第一介质层中对着第一像素单元的共用的供电电源输入端位置处的填充有导电材料的电源连接接触孔;在第一介质层中对着第二像素单元的共用的供电电源输入端位置处的填充有导电材料的电源连接接触孔;在第一介质层中分别对着第一像素单元和第二像素单元的深摻杂阱位置处的填充有导电材料的深掺杂阱接触孔;在第一介质层中分别对着第一像素单元和第二像素单元的复位晶体管的栅极位置处的填充有导电材料的复位接触孔;以及在第一介质层中分别对着第一像素单元和第二像素单元的源跟随晶体管的栅极位置处的填充有导电材料的源 22. The CMOS image sensor according to claim 21, further comprising: a first dielectric layer formed on a semiconductor substrate; output common output transistors in the first dielectric layer facing the CMOS image sensor pixel units of filled at the end of a conductive material connected to an output contact hole; filled in the first dielectric layer at the location of the power supply input terminal of the first pixel unit share a power supply connected to the contact against the hole conductive material; a first dielectric layer filled at the power supply input terminal of the second pixel position of the common power supply unit against the connection contact hole conductive material; a first dielectric layer, respectively, against the deep doped well of the first pixel and the second pixel unit cell filling at a position deep doped well contact hole conductive material; a first dielectric layer filling position at the gate of the reset transistor and the first pixel unit, respectively, against the second pixel unit has a reset contact hole conductive material ; and filling at a position in the first gate dielectric layer, respectively, against the source of the first pixel unit and the second unit pixel source follower transistor has a conductive material 随接触孔。 With the contact hole.
  23. 23. 根据权利要求22所述的CMOS图像传感器,其特征在于:所述CMOS图像传感器还包括第一介质层上对着输出连接接触孔位置处的由第一金属层构成的输出连接金属线;第一介质层上对着电源连接接触孔位置处的由第一金属层构成的电源连接金属线;第一介质层上对着复位接触孔位置处的由第一金属层构成的第二导线,所述第二导线与外围复位电-各相连;以及由第一金属层构成的把每个像素单元的深摻杂阱接触孔与源跟随接触孔相连的笫一导线。 23. A CMOS image sensor according to claim 22, wherein: the CMOS image sensor further includes an output comprising a first metal layer on the first dielectric layer facing the output connection at the contact hole connecting the metal line position; a first dielectric layer into the power supply position at the contact hole of the first metal layer made of a metal wire is connected; a first dielectric layer on the second conductor opposite the contact is reset by the first metal layer composed of the hole position, the second lead with a peripheral reset - each connected; deep dopant and the well contact hole to the source of each pixel unit constituted by the first metal wire layer connected to a follower Zi contact hole.
  24. 24. 根据权利要求23所述的CMOS图像传感器,其特征在于:所述CMOS图像传感器还包括位于第一金属层上的第二介质层、以及第二介质层中对着电源连接金属线和输出连接金属线位置处的填充有导电材料的电源接触孔和输出接触孔。 24. The CMOS image sensor according to claim 23, wherein: the CMOS image sensor further includes a second dielectric layer on the first metal layer and the second dielectric layer into the power line and an output metal filling connection wire positions of the contact holes with a power output of the contact hole and electrically conductive material.
  25. 25. 根据权利要求24所述的CMOS图像传感器,其特征在于:所述第二介质层上对着电源接触孔处形成有由第二金属层构成的电源金属线,所述电源金属线与外围供电电源电路相连;所述第二介质层上对着输出接触孔处形成有由第二金属层构成的输出金属线,所述输出金属线与外围输出电路相连。 25. The CMOS image sensor according to claim 24, wherein: forming the metal power lines are composed of the second metal layer opposite the power contact hole on the second dielectric layer, the metal wire and the peripheral power power supply circuit is connected; output is formed of a metal wire against the output of the second metal layer at the contact hole on the second dielectric layer, the metal wire and output peripheral output circuit.
  26. 26. —种CMOS图像传感器的形成方法,包括: 将位于半导体衬底上的CMOS图像传感器分为至少一个CMOS图像传感器像素单元对区域,所述CMOS图像传感器像素单元对包括列向相邻的第一像素单元和第二像素单元;将每个像素单元分为光电二极管区域和驱动电路区域;在光电二极管区域形成光电二极管;在驱动电路区域形成带有复位晶体管和输出晶体管的驱动电路, 其特征在于,第一像素单元和第二像素单元的两个输出晶体管的漏极相连,共用一个输出端;第一像素单元的复位晶体管的漏极与列向相邻的CMOS图像传感器像素单元对的第二像素单元的复位晶体管的漏极相连,共用一个供电电源输入端;第二像素单元的复位晶体管的漏极与列向相邻的另一CMOS图像传感器像素单元对的第一像素单元的复位晶体管的漏极相连,共用一个供电电源输入端。 26. - The method of forming a CMOS image sensor types, comprising: a CMOS image sensor will be located on a semiconductor substrate is divided into at least one unit of the CMOS image sensor pixel region, the CMOS image sensor includes a pixel unit adjacent to the first column a second pixel units and the pixel units; units into each pixel photodiode region and a driver circuit region; forming a photodiode in a photodiode region; forming a driving circuit having a reset transistor and the output transistor in the driving circuit region, characterized in in that the drain of the output transistor of the first two pixel units and the second pixel unit is connected to a common output terminal; a first drain of the reset transistor of the first column of the pixel unit adjacent to the pixel of the CMOS image sensor unit the drain of the reset transistor is connected to two pixel elements share one power supply input terminal; a first reset transistor and the drain of the pixel unit of the second row reset transistor of a pixel unit of the CMOS image sensor to another cell adjacent to the pixel a drain connected to a common power supply input.
  27. 27. 根据权利要求26所述的CMOS图像传感器的形成方法,其特征在于: 所述第一像素单元与第二像素单元关于共用的输出端对称;第一像素单元的输出晶体管的栅极与形成于同一层的多晶硅行选导线相连,且与外围行选电路相连;第一像素单元的源跟随晶体管的源极与第一像素单元的输出晶体管源极共用;第一像素单元的复位晶体管的源极位于第一像素单元的光电二极管区域内;与第一像素单元列向相邻的CMOS图像传感器像素单元对的笫二像素单元的复位晶体管的源极位于相应像素单元的光电二极管区域内。 27. The method of forming the 26 CMOS image sensor as claimed in claim, wherein: the first pixel and the second pixel unit cell symmetry about the common output terminal; and a gate forming the output transistor of the first pixel unit is selected from the same row conductor polysilicon layer is connected, and is connected to the peripheral line selection circuit; the source of the output transistor of the source follower transistor of the first pixel unit and the first pixel unit common electrode; the source of the reset transistor of the first pixel unit the photodiode region of the pixel unit positioned in the first electrode; a source of the reset transistor Zi two pixel elements adjacent to the pixel of the CMOS image sensor unit and the first pixel electrode is located in the cell row corresponding to the photodiode region of the pixel unit.
  28. 28. 根据权利要求27所述的CMOS图像传感器的形成方法,其特征在于:所述CMOS图像传感器像素单元对的第一像素单元和第二像素单元的多晶硅行选导线相互平行。 28. A method of forming a CMOS image sensor according to claim 27, wherein: the first pixel cell row of the polysilicon CMOS image sensor pixel units and the pixel units selected from the second conductor parallel to each other.
  29. 29. 根据权利要求28所述的CMOS图像传感器的形成方法,其特征在于:形成所述光电二极管包括在半导体衬底中形成半导体衬底导电类型相反的深掺杂阱以及在深掺杂阱上形成与深掺杂阱导电类型相反的浅掺杂区。 29. The method of forming the 28 CMOS image sensor as claimed in claim, wherein: forming the photodiode comprises forming a semiconductor substrate doped with the opposite conductivity type deep well in the semiconductor substrate and the well in the deep dopant forming a deep well doped shallow doped region of the opposite conductivity type.
  30. 30. 根据权利要求29所述的CMOS图像传感器的形成方法,其特征在于:还包括在半导体衬底上形成第一介质层;在第一介质层中对着CMOS图像传感器像素单元对的输出晶体管的共用的输出端位置处形成填充有导电材料的输出连^妄接触孔;在第一介质层中对着第一像素单元的共用的供电电源输入端位置处形成填充有导电材料的电源连接接触孔;在第一介质层中对着第二像素单元的共用的供电电源输入端位置处形成填充有导电材料的电源连接接触孔;在第一介质层中分别对着第一像素单元和第二像素单元的深掺杂阱位置处形成填充有导电材料的深掺杂阱接触孔;在第一介质层中分别对着第一像素单元和第二像素单元的复位晶体管的栅极位置处形成填充有导电材料的复位接触孔;以及在第一介质层中分別对着第一像素单元和第二像素单元的源跟随晶体管的栅 30. A method of forming a CMOS image sensor according to claim 29, characterized in further comprising: forming a first dielectric layer on a semiconductor substrate; a first output transistor in the dielectric layer against the CMOS image sensor pixel units of at the output of the common position is formed with a conductive material filled in the contact hole jump ^ output connector; power filled with conductive material are formed in front of the position of the power supply input terminal of the first pixel unit share in the first dielectric layer connected to the contact aperture; a first dielectric layer formed in opposite positions at the power supply input terminal of the common power supply unit connected to the second pixel contact hole filled with a conductive material; in the first dielectric layer, respectively, against the first unit and the second pixel deep doped well contact hole is filled with a conductive material at a deep position of the pixel unit doped well is formed; in front of the gate transistor of the first pixel position of the reset unit and the second pixel unit is formed in a first dielectric layer filling each reset the contact hole with a conductive material; and a source, respectively facing the first pixel unit and the second pixel unit in a first follower transistor gate dielectric layer 位置处形成填充有导电材料的源跟随接触孔。 The source follower contact hole filled with a conductive material is formed at a position.
  31. 31. 根据权利要求30所述的CMOS图像传感器的形成方法,其特征在于:形成所述CMOS图像传感器还包括在第一介质层上对着输出连接接触孔位置处形成由第一金属层构成的输出连接金属线;在第一介质层上对着电源连接接触孔位置处形成由第一金属层构成的电源连接金属线;在第一介质层上对着复位接触孔位置处形成由第一金属层构成的第二导线,所述第二导线与外围复位电路相连;以及采用第一金属层构成的第一导线4巴每个像素单元的深掺杂阱接触孔与源跟随接触孔相连。 31. The method of forming a CMOS image sensor according to claim 30, characterized in that: forming the CMOS image sensor further comprises an output connected to the first front dielectric layer at a contact hole formed at a position of the first metal layer is composed of a output bonding wires; power connection is formed of a metal wire against a first metal layer of the power supply connected to the contact hole location on the first dielectric layer; forming a first metal contact hole is reset at opposite positions on a first dielectric layer a second conductor layer composed of a second reset circuit connected to the peripheral conductor; and the use of a deep well doped with a source contact hole 4 bar of each pixel unit of the first conductor layer composed of a first metal follower connected to the contact hole.
  32. 32. 根据权利要求31所述的CMOS图像传感器的形成方法,其特征在于:形成所述CMOS图像传感器还包括在第一金属层上形成第二介质层、以及在第二介质层中对着电源连接金属线和输出连接金属线位置处形成填充有导电材料的电源接触孔和输出接触孔。 32. The method of claim 31 is formed of a CMOS image sensor as claimed in claim, wherein: forming the CMOS image sensor further comprises a second dielectric layer formed on the first metal layer, and a second dielectric layer opposite the power supply bonding wires and output connections are formed at the wire positions and an output power contact hole contact hole filled with a conductive material.
  33. 33. 根据权利要求32所述的CMOS图像传感器的形成方法,其特征在于:形成所述CMOS图像传感器还包括在第二介质层上对着电源接触孔处形成由第二金属层构成的电源金属线,所述电源金属线与外围供电电源电路相连; 在第二介质层上对着输出接触孔处形成由第二金属层构成的输出金属线,所述输出金属线与外围输出电路相连。 33. The method of forming a CMOS image sensor according to claim 32, characterized in that: the power supply of metal forming the second metal layer of the CMOS image sensor further comprises forming a contact hole opposing the power supply on the second dielectric layer line, the power supply metal line is connected to the peripheral power supply circuit; output formed of a metal wire against the output of the second metal layer at the contact hole on the second dielectric layer, the metal wire and output peripheral output circuit.
  34. 34. —种如权利要求18所述CMOS图像传感器的布局方法,其特征在于,包括:至少一个CMOS图像传感器像素单元对,所述CMOS图像传感器像素单元对包括列向相邻的第一像素单元和第二像素单元;CMOS图像传感器像素单元对在行方向上依次排列;同一行方向上的相邻CMOS图像传感器像素单元对的相应像素单元的行选导线均相连且平行于行方向;相邻两行CMOS图像传感器像素单元对的复位晶体管相邻;CMOS图像传感器像素单元对的第一像素单元和第二像素单元具有一个共用的输出端且第一像素单元和第二像素单元关于共用的输出端对称;第一像素单元的输出晶体管、源跟随晶体管及复位晶体管的栅极与共用输出端依次相邻;第一像素单元的栅极与形成于同一层的多晶硅行选导线相连; 第一像素单元的复位晶体管的漏极与列向相邻的CMOS图像传感器像素单元对的第 34. - The method of claim 18 is a layout of a CMOS image sensor as claimed in claim species, wherein, comprising: at least one pixel unit of the CMOS image sensor, the CMOS image sensor including the unit pixel columns adjacent to the first pixel units and a second pixel unit; CMOS image sensor pixel sequentially arranged in the row direction of the unit; corresponding row conductor is selected from the CMOS image sensor pixel unit of an adjacent unit pixel on the same row are connected to a direction parallel to the row direction; two adjacent rows a reset transistor of the pixel unit adjacent to the CMOS image sensor; a first pixel unit of the CMOS image sensor pixel unit and a second unit having an output pixel and the first pixel and the second pixel unit cell of a common symmetrical about a common output terminal ; first unit pixel output transistor, and the gate of the source follower transistor and the common output terminal of the reset transistor adjacent sequentially; a gate connected to the first pixel unit is formed in the polysilicon layer of the same row select conductor; first pixel unit the drain of the reset transistor and the row of adjacent unit pixels of the CMOS image sensor 像素单元的复位晶体管的漏极相连,作为共用的供电电源输入端;第二像素单元的复位晶体管的漏极与列向相邻的另一CMOS图像传感器像素单元对的第一像素单元的复位晶体管的漏极相连,作为共用的供电电源输入端。 Connected to the drain of the reset transistor of the pixel unit, as a common power supply input terminal; drain of the reset transistor of the second pixel units and the other column of the CMOS image sensor pixel unit adjacent to the first pixel unit of the reset transistor a drain connected to the power supply as a common input.
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US6847399B1 (en) 1998-03-23 2005-01-25 Micron Technology, Inc. Increasing readout speed in CMOS APS sensors through block readout

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US6847399B1 (en) 1998-03-23 2005-01-25 Micron Technology, Inc. Increasing readout speed in CMOS APS sensors through block readout

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