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一用于测试集成电路的插座的制作方法及所述插座

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Publication number
CN100538369C
CN100538369C CN 200380109299 CN200380109299A CN100538369C CN 100538369 C CN100538369 C CN 100538369C CN 200380109299 CN200380109299 CN 200380109299 CN 200380109299 A CN200380109299 A CN 200380109299A CN 100538369 C CN100538369 C CN 100538369C
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socket
method
making
perform
testing
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CN 200380109299
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CN1745307A (zh )
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伊戈尔·K·汉德罗斯
加埃唐·L·马蒂厄
卡尔·V·雷诺兹
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佛姆费克托公司
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R3/00Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals
    • G01R1/0408Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0433Sockets for IC's or transistors
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals
    • G01R1/0408Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0433Sockets for IC's or transistors
    • G01R1/0483Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/06Measuring leads; Measuring probes
    • G01R1/067Measuring probes
    • G01R1/073Multiple probes
    • G01R1/07307Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07364Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
    • G01R1/07378Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch using an intermediate adapter, e.g. space transformers
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2855Environmental, reliability or burn-in testing
    • G01R31/286External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01055Cesium [Cs]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
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    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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Abstract

本发明揭示一种可廉价制造且可易于插入插座内的互连结构。该互连结构是通过如下方式来制造:形成一带有空腔的牺牲衬底,该牺牲衬底上覆盖有一带有对应于所述空腔的开孔的掩膜材料。通过沉积导电材料来实施第一电镀工艺,然后耦接各开孔中的导线并通过沉积更多导电材料来实施另一电镀工艺。通过首先移除掩膜材料和牺牲衬底来完成该互连结构。将导线中与现在形成的触点结构相对的端部耦接至一板。为完成该插座,将一支撑器件耦接至该板来固定受测试集成电路。

Description

一用于测试集成电路的插座的制作方法及所述插座

技术领域

本发明涉及一种用于集成电路的插座。更具体而言,该插座是一测试或老 化插座,其用于将集成电路连接至用于最终测试的测试仪或用于老化的老化板。

背景技术

半导体芯片测试是半导体制造中一项重要的作业。在半导体芯片制造工艺 的不同阶段中会实施不同种类的测试。例如,当在圆片上已制作出半导体芯片 但还未切割及封装时,可在圆片级上实施初始测试。这些初始测试可有助于在 实施更昂贵且耗时的封装步骤之前识别缺陷芯片。在初始测试后,切割圆片并 封装单个半导体芯片。然后,在芯片级上实施更精密的测试和老化作业,以评 估单个半导体芯片或成组的多个芯片。

一种用于实施测试和老化作业的技术是将单个芯片掷入插座中。不幸的是, 传统插座存在若干局限性。传统插座可能制造昂贵且有些不可靠。有些传统插 座也使用弹簧针作为触点元件。这种弹簧针不可靠且非摩擦闭合。弹簧针还会

限制插座中互连结构的间距。例如,弹簧针小于40密耳的间距变得在机械上难 于制造且过于昂贵。

因此,人们需要一种带有一通过落入式、插入式或类似连接来耦接的易于 插入的互连结构的老化插座测试器件。该互连结构也需要通过一低廉的制造工 艺来制造。

发明内容

本发明的实施例纟是供一种方法,其包括如下步骤:在一牺牲衬底上制作元 件(例如,空腔),利用牺牲衬底中的元件制作一触点结构,利用触点结构制作一互连结构,及利用互连结构制作一测试板。本发明的其它实施例提供一种通 过这种方法制成的老化插座。

本发明的又一些实施例提供一种用于测试集成电路板的系统。该系统包括 一插座。该插座包括一板、 一制造成可插入该插座内的互连结构,该互连结构 耦接至所述板。该互连结构包括一衬底和第一及第二焊垫,第一及第二焊垫耦 接至该衬底且通过贯穿该衬底的通路相互耦接,第二焊垫将该互连结构耦接至 所述板。互连结构还包括耦接至第一焊垫的弹性触点,在测试期间,这些弹性 触点与集成电路相互作用。该插座还包括一耦接至该板的支撑结构,该支撑结 构会确保在测试期间集成电路板与弹性触点之间的接触。

本发明的其他实施例、特征及优点、以及本发明各种实施例的结构和操作, 将在下文中参照附图加以详细说明。

附图说明

附图显示本发明的实例性实施例,其并入本文中并构成本说明书的一部分, 这些附图与本说明 一起进一 步用来解释本发明的原理并使相关领域的技术人员 能够制作及利用本发明。

图1A和1B分别显示根据本发明的实施例, 一受测试倒装芯片半导体的侧

牙见图和仰3见图。

图2A和2B分别显示根据本发明的实施例, 一牺牲衬底的横截面图和仰视图。

图3A和3B分别显示带有掩膜材料的图2A和2B所示牺牲衬底的横截面图 和仰视图。

图4A、 4B、 4C和4D显示根据本发明的实施例,形成一测试插座的处理步骤。

图5A和5B显示根据本发明的实施例,形成测试插座的又一些处理步骤。 图6显示根据本发明的实施例,形成测试插座的再一些处理步骤。图7显示根据本发明的实施例,用于在圆片上测试复数个器件的复数个插座。

图8显示一流程图,其描述一种根据本发明的实施例制造插座的总体方法。 图9显示一流程图,其描述图8中方法的更详细的方法步骤。 现在将参照附图描述本发明的实例性实施例。在附图中,相同参考编号表

示完全相同或在功能上相同的元件。此外,参考编号的最左側的数位表示首次

出现该参考编号的图。

具体实施方式

本发明的实施例提供一种可廉价制造且易于插入插座内的互连结构。该互 连结构通过如下方式来制造:形成一带有空腔的牺牲衬底,该牺牲衬底覆盖有 一具有对应于这些空腔的开孔的掩膜材料。通过沉积导电材料来实施第一电镀 工艺,然后耦接这些开孔中的导线并通过沉积更多导电材料实施另一电镀工艺。 通过首先移除掩膜材料和牺牲衬底来完成该互连结构。将各导线中与现在形成 的触点结构相对的端部耦接至一板。为完成该插座,将一支撑器件耦接至该板 以固定受测试集成电路。

集成电路半导体

图1A-1B分别显示根据本发明的实施例, 一待测半导体芯片IOO(例如,集 成电路(IC))的侧视图和仰视图。半导体芯片IOO可已封装或未封装。半导体 芯片100可以是(但不限于) 一带有焊球触点102 (例如,"受控塌陷芯片连接" (也称作"C4"))的倒装芯片半导体。通常,可使用任一类型的半导体芯片和 触点。

互连结构制造工艺

图2-6显示根据本发明的实施例制造一插座600 (图6 )的互连结构(例如, 瓷片)514 (图5)的工艺。 . 图2A-2B分别显示根据本发明的实施例的牺牲衬底200的横截面图和仰视图。牺牲衬底200可以是可在其中形成元件(例如,空腔)202的任意材料。顾 名思义,牺牲衬底200可从最终结构溶解掉、蚀刻掉或以其它方式移除掉。在 某些实施例中,可使用一铜制或铝制薄片或箔作为牺牲衬底200。在其它实施例 中,可使用硅、陶瓷、钛-鴒、及类似材料作为牺牲衬底200。如图所示,在牺 牲衬底200中形成空腔202。在各种实施例中,可以通过压花、蚀刻或类似的方 式形成空腔202。将看到,空腔202对应于半导体芯片IOO上的触点102。

图3A-3B分别显示根据本发明的实施例涂覆有掩膜材料300的牺牲衬底200 的横截面图和仰视图。在某些实施例中,掩膜材料300可以是光阻材料。如图 所示,在掩膜材料300中形成开孔302。这些开孔302-暴露出在图2中形成的空 腔202。

图4A-4D显示根据本发明的实施例的附加处理步骤。在图4A中,在开孔302 中沉积或电镀导电材料400。在某些实施例中,导电材料400可以是硬质材料、 金属材料、及/或导电性材料。例如,导电材料400可以是铑材料及钇钴合金。 将看到,导电材料400形成一用于在测试期间接触半导体芯片100的触点尖402。 尽管图中显示具有两个延伸部分,但是根据不同规格和实施例的需要,触点尖 402可以有一个或多个延伸部分。在其它实施例中,触点尖402可以由复数种分 层材料制成,例如一软金层、 一镍层及一硬金层。在其它实施例中,其它材料 的非穷尽性清单可包括:银、4巴、柏、铑、导电性氮化物、导电性碳化物、钨、 钛、钼、铼、铟、锇、难熔金属或类似材料。在本说明书的后文中,将使用术 语导电材料400,且该术语意欲包括一种或多种材料,且如果多于一种材料,则 其包括分层材料。导电材料400可以使用任一合适的方法沉积于开孔302中。 在各种实施例中,沉积方法可以是电镀、物理或化学气相沉积、賊射或类似方 法。形成触点尖402的层可以类似方式沉积。

虽然图中未示,但是在各种实施例中,可以在沉积导电材料400之前在开 孔302中沉积一释脱材料。使用释脱材料利于从牺牲衬底200最终移除由导电 材料400形成的触点结构506 (图5B)。在某些实施例中,释脱层可以是铝层。在另一些实施例中,尽管图中也未示出,然而在沉积导电材料400前,也可在 开孔302中沉积一由导电材料组成的种子层。在又一些实施例中,在沉积掩膜 材料300之前,可在整个牺牲衬底200上沉积种子层作为一毯覆层。如果使用 电镀来沉积导电材料400,则种子层可利于电镀。

图4B显示根据本发明的实施例,在每个开孔302中一导线404结合至导电 材料400。可使用众所周知的导线结合技术来结合导线404。导线结合技术的一 个实例见颁与Eldridge等人的第5, 601, 740号美国专利.,其全文以引用方式并 入本文中。在某些实施例中,导线404可以由相对软的、可易于定形的材料制 成,而在其它实施例中可使用其它种类的材料。可用于导线404的材料的实例 包括金、铝、铜、铀、铅、锡、铟、它们的合金、或类似材料。在某些实施例 中,导线404的直径可处于0. 25至10密耳范围内。应了解,导线404可以具 有其它形状的截面,例如矩形或4壬何其它形状。

图4C显示使用第二导电材料406电镀的导线404和导电材料400。在某些 实施例中,导电材料406比构成导线404的材料硬,以加强触点结构506 (图 5B)。合适材料的一些实例包括镍、铜、焊料、铁、钴、锡、硼、磷、铬、钨、 钼、铋、铟、铯、锑、金、铅、锡、银、铑、把、柏、钌、它们的合金、或类 似材料。在某些实施例中,导电材料406的厚度可以为0. 2至10密耳。导电材 料406可以使用任一合适的方法沉积于导线404上。在各种实施例中,沉积方 法包括电镀、物理或化学气相沉积、溅射或类似方法。用于丝焊一导线然后过 电镀所述导线的实例性方法阐述于颁与Khandros的第5, 476, 211号美国专利、 颁与Khandros等人的第5, 917, 707号美国专利及颁与Eldridge等人的第 6, 336,269号美国专利中,这些美国专利的全文均以引用方式并入本文中。

图4D显示在已移除掩膜材料300后的工艺。

图5A-5B显示4艮据本发明的实施例的附加处理步骤。图5A显示借助耦接材 料504将带有导电涂层406的导线404的自由端500耦接至一布线村底502。在 各种实施例中,可以通过布线、钎焊、铜焊或类似方法实现耦接。在耦接带有导电涂层406的导线404的自由端500这一步骤中包括加热处理的实施例中, 导线404和触点结构506 (图5B)也可进^f亍热处理。这样的一个实例见颁与Chen 等人的第6, 150, 186号美国专利,其全文以引用方式并入本文中,且该美国专 利揭示了热处理弹簧触点结构的方法。

图5B显示根据本发明的实施例,布线衬底502的构造。布线衬底502可以 是一陶瓷村底,其在布线衬底502的对置面上具有焊垫508和510。可以借助贯 穿布线村底502的通路512耦接焊垫508与510。在其它实施例中,布线衬底 502可以是印刷电路板或印刷线路板。也如图5B所显示,牺牲衬底200被移除, 这可以通过蚀刻、溶解或以类似的方式处理形成牺牲衬底200的材料奉实现。 带有触点元件506、焊垫508、 510及通路512的布线衬底502的另一用语是互 连结构514。在某些实施例中,可使用互连结构514制作一测试或老化插座600 (图6)。在各种实施例中,互连结构514可以是一易于插入插座600或任何其 它插座内的模块式互连结构、落入式互连结构、插入式互连结构、或类似结构。

根据本发明制作互连结构514的工艺的其它优点在于,该工艺低廉且可以 单独对一互连结构实施。通过这种方式,可以在形成插座前识别出并移除有缺 陷的互连结构。该工艺的其它优点在于,可以廉价方式制造及大量生产具有以 小于40密耳(包括约10密耳或更小)的微小间距布置的触点元件的互连结构。 因此,该工艺是一种用于生产微小间距插座的可靠且廉价的技术。

插座形成工艺

图6显示根据本发明的实施例的插座600,其中互连结构514耦接并用导线 电连接至板602 (例如,测试板或插座板)。在某些实施例中,板602可包括一 带有铰接闭合器件606的支撑结构604,以在测试期间固定集成电路(IC) 100。 在各种实施例中,板602可以是测试板或老化板。互连结构514可以任何合适 的方式电连接至板602,例如通过钎焊608、引脚(未示出)或任何其它种类的 触点。例如,引脚可以与对应的孔(未示出)形成摩擦配合。在替代实施例中, 板602可以是一自身插入或以其它方式附装至一更大测试系统(未示出)的插座板。

图7显示根据本发明的一带有耦接至板702的多个互连结构700的实施例。 虽然图中显示带有多个IC 100,但是在其它实施例中,也可以测试一个带有许 多球触点102的IC 100。在该实施例中,根据球触点102的构造,通过以不同 的构造将复数个互连结构700耦接至板702来建造一用于接触IC 100的弹簧触 点704的阵列。如上文所述,在各种实施例中,板702可以是测试板或老化板, 且可以将复数个类似于604的支撑结构(为方便起见,图7中未示)围绕互连 结构700固定至板702。

制造互连结构和插座的方法

图8显示根据本发明的实施例制造插座的方法800。在步骤802中,形成一 牺牲衬底,该牺牲衬底带有根据需要形成于衬底中的任意种类或数量的元件。 例如,可如图2所示形成空腔。在步骤804中,基于牺牲衬底形成电镀导线。 这可通过参照图3-4所描述的各种方法来实现。在步骤806中,基于电镀导线 形成互连结构。这可通过参照图5所描述的各种方法来实现。在步骤808中, 基于互连结构形成插座。这可通过参照图6和图7所描述的各种方法来实现。

图9显示一流程图,其描述了一种才艮据本发明的实施例制作插座的更详细 的方法900。在步骤902中,在一牺牲衬底(例如,衬底200 )中形成空腔(例 如,元件或空腔202 )。在步骤904中,在牺牲村底上沉积一掩膜材料(例如, 掩膜材料300 )。在步骤906中,在掩膜材料中形成对应于空腔的开孔(例如, 开孔302 )。在步骤908中,在开孔中沉积或电镀导电材料(例如,导电材料400 )。 在步骤910中,将导线(例如,导线404 )耦接至导电材料。在步骤912中,在 导线和第一导电材料上沉积或电镀第二导电材料(例如,导电材料406 )。在步 骤914中,移除掩膜材料。在步骤916中,使用一耦接材料(例如,耦接材料 504 )将带有导电材料的导线的尖端(例如,尖端500 )耦接至一布线衬底(例 如,布线村底502 )。在步骤918中,移除牺牲衬底以形成一互连结构(例如, 互连结构514或700 )。在步骤920中,将互连结构耦接至一板(例如,板602或702 )以形成一插座(例如,插座600 )。 结论

尽管上文中已描述了本发明的各种实施例,然而应了解,这些实施例仅以 举例形式而非限定形式给出。相关领域的技术人员易知,可对其在形式上和细 节上作出各种变化,此并不背离本发明的精神和范围。因此,本发明的广度和 范围不应受限于上文所说明的任一实例性实施例,而应根据下文权利要求书及 其等价内容来界定。

Claims (50)

1、一种制作用于测试集成电路的插座的方法,其包括如下步骤:在一牺牲衬底中制作触点元件,所述牺牲衬底包含将形成所述触点元件的尖端的空腔;通过将所述触点元件附装至一支撑电路径线的布线衬底、将所述电路径线连接至远离所述尖端的所述触点元件的末端、然后移除所述牺牲衬底,制作一互连结构;及制作一插座板,所述插座板经配置用于固定一自一晶圆上切割的用于测试目的的半导体芯片,其中制作所述插座板包括将所述互连结构附装至所述插座板。
2、 如权利要求1所述的方法,其中所述制作触点元件的步骤包括如下步骤:在所述牺牲衬底中为每一触点元件制作多个空腔;及在将形成所述触点元件的所述尖端的所述空腔中提供一导电材料。
3、 如权利要求2所述的方法,其进一步包括压花所述牺牲衬底以实施所述制作空腔步骤的步骤。
4、 如权利要求2所述的方法,其进一步包括蚀刻所述牺牲衬底以实施所述制作空腔步骤的步骤。
5、 如权利要求1所述的方法,其进一步包括由铜形成所述牺牲衬底的步骤。
6、 如权利要求1所述的方法,其进一步包括由铝形成所述牺牲衬底的步骤。
7、 如权利要求1所述的方法,其进一步包括由硅形成所述牺牲衬底的步骤。
8、 如权利要求l所述的方法,其进一步包括由陶瓷形成所述牺牲衬底的步骤。
9、 如权利要求1所述的方法,其进一步包括由钛-钨形成所述牺牲衬底的步骤。
10、 如权利要求1所述的方法,其中所述制作触点元件的步骤包括如下步骤:在所述牺牲衬底上沉积掩膜材料;在所述掩膜材料中形成对应于所述触点元件的开孔;在所述开孔中沉积第一导电材料;在所述开孔中的每一开孔中,将一导线结合至所述第一导电材料; 在所述导线上沉积第二导电材料;及移除所述掩膜材料。
11、 如权利要求10所述的方法,其进一步包括利用光阻材料作为所述掩膜材料的步骤。
12、 如权利要求IO所述的方法,其进一步包括使用硬金属材料作为所述第一导电材料的步骤。
13、 如权利要求IO所述的方法,其进一步包括使用铑材料作为所述第一导电材料的步骤。
14、 如权利要求IO所述的方法,其中所述沉积第一导电材料的步骤包括如下步骤:沉积一软金层;沉积一镍层;及沉积一硬金层。
15、 如权利要求IO所述的方法,其中所述沉积第一导电材料的步骤包括使用电镀来实施所述沉积的步骤。
16、 如权利要求IO所述的方法,其中所述沉积第一导电材料的步骤包括使用气相沉积来实施所述沉积的步骤。
17、 如权利要求IO所述的方法,其中所述沉积第一导电材料步骤包括进行溅射来实施所述沉积的步骤。
18、 如权利要求IO所述的方法,其进一步包括在实施所述沉积第一导电材料步骤之前,在所述开孔中沉积一释脱材料的步骤。
19、 如权利要求18所述的方法,其中所述沉积一释脱材料的步骤包括使用铝作为所述释脱材料的步骤。
20、 如权利要求10所述的方法,其进一步包括在实施所述沉积第一导电材料步骤之前,在所述开孔中沉积一种子层的步骤。
21、 如权利要求IO所述的方法,其进一步包括在实施所述沉积掩膜材料步骤之前,在所述牺牲衬底上沉积一种子层的步骤。
22、 如权利要求IO所述的方法,其中所述结合一导线的步骤包括使用软的可定形材料作为所述导线的步骤。
23、 如权利要求IO所述的方法,其中所述结合一导线的步骤包括使用金作为所述导线的步骤。
24、 如权利要求IO所述的方法,其中所述结合一导线的步骤包括使用铝作为所述导线的步骤。
25、 如权利要求IO所述的方法,其中所述结合一导线的步骤包括使用铜作为所述导线的步骤。
26、 如权利要求IO所述的方法,其中所述结合一导线的步骤包括使用铂作为所述导线的步骤。
27、 如权利要求IO所述的方法,其中所述结合一导线的步骤包括使用铅作为所述导线的步骤。
28、 如权利要求IO所述的方法,其中所述结合一导线的步骤包括使用锡作为所述导线的步骤。
29、 如权利要求IO所述的方法,其中所述结合一导线的步骤包括使用铟作为所述导线的步骤。
30、 如权利要求IO所述的方法,其中所述结合一导线的步骤包括使用合金作为所述导线的步骤。
31、 如权利要求10所述的方法,其进一步包括使用一比用于所述导线的材料更硬的材料作为所述第二导电材料以加强一触点元件的步骤。
32、 如权利要求IO所述的方法,其中所述制作一互连结构的步骤包括如下 步骤:将所述导线的自由端耦接至所述布线衬底。
33、 如权利要求32所述的方法,其中所述耦接步骤包括使用布线将所述导 线的所述自由端耦接至所述布线衬底的步骤。
34、 如权利要求32所述的方法,其中所述耦接步骤包括使用铜焊将所述导 线的所述自由端耦接至所述布线衬底的步骤。
35、 如权利要求32所述的方法,其中所述耦接步骤包括使用加热技术将所 述导线的所述自由端耦接至所述布线衬底的步骤。
36、 如权利要求32所述的方法,其进一步包括通过如下方式形成所述布线衬底的步骤:将第一和第二焊垫耦接至一衬底的对置面;及使用贯穿所述衬底的通路互连所述第一和第二焊垫,以形成所述电路径线。
37、 如权利要求36所述的方法,其中所述形成所述布线衬底的步骤包括使 用 一 陶瓷材料形成所述衬底的步骤。
38、 如权利要求1所述的方法,其中所述制作所述插座板的步骤进一步包 括将所述互连结构耦接至一板的步骤。
39、 如权利要求38所述的方法,其进一步包括将一支撑结构耦接至所述板 以将所述半导体芯片完全固定于一由所述插座板形成的插座内的步骤。
40、 如权利要求1所述的方法,其中所述制作一互连结构的步骤包括制作复数个互连结构,每一互连结构均包括一具有触点元件的布线衬底,且其中所 述制作一插座板的步骤包括将所述插座板配置成支撑复数个自 一晶圓切割的半导体芯片以同时接触所述复数个互连结构。
41、 一种用于测试一集成电路的系统,其包括: 一插座,其包括:一板;一制造成可插入所述插座内的互连结构,所述互连结构耦接至所述板,所述互连结构包括: 一衬底,第一和第二焊垫,其耦接至所述衬底且通过贯穿所述衬底的通路 相互耦接,所述第二焊垫将所述互连结构耦接至所迷板,及弹性触点,其耦接至所述第一焊垫,每一所述弹性触点包括: 一具有导电涂层的导线,其在一第一端耦接到所述第一焊垫中的一个;和多个从耦接到所述具有导电涂层的导线的一第二端的一触点 尖端伸出的延伸部分,所迷多个延伸部分以相互足够接近地方式间 隔开以使得每个尖端接触所述集成电路的一个相同终端;一支撑结构,其保证在所述测试期间所述集成电路与所述弹性触点之 间的接触。
42、 如权利要求41所述的系统,其中所述互连结构是一插入至所述插座内的模块式互连结构。
43、 如权利要求41所述的系统,其中所述互连结构是一落入至所述插座内的落入式互连结构。
44、 如权利要求41所述的系统,其中所述互连结构是一插入至所述插座内的插入式互连结构。
45、 如权利要求41所述的系统,其中所述插座包括复数个所述互连结构。
46、 如权利要求1所述的方法,其进一步包括如下步骤:将一支撑结构附 装至所述插座板,以在测试期间将所述半导体芯片抵靠所述触点元件固定于所 述插座板中,所述支撑结构由一铰链连接至所述插座板。
47、 如权利要求l所述的方法,其进一步包括如下步骤: 将所述互连结构包含于一由所述插座板形成的空腔内,所述插座板包括一底部构件及两个侧部构件,所述两个侧部构件附装至所述底部构件以形成所述空腔;及使用一通过一铰链附装至所述插座板的一侧部构件的顶部构件将所述半导 体芯片固定于所述插座板的所述空腔中,以保证在测试期间接触所述触点元件 的尖端。
48、 如权利要求47所述的方法,其中所述半导体芯片为封装的。
49、 如权利要求l所述的方法,其进一步包括如下步骤: 对所述半导体芯片实施老化测试,其中所述半导体芯片由所述插座板支撑。
50、 一种制作用于测试集成电路的插座的方法,其包括如下步骤: 在一衬底上提供一包括弹性触点元件的互连结构;制作一插座,其经配置以固定用于测试的自一晶圓切割的半导体芯片; 将所述互连结构附装至所述插座,以在将所述半导体芯片放置于所述插座 中时,所述半导体芯片的多个触点可接触所述弹性触点元件;及对所述半导体芯片实施老化测试,其中所述半导体芯片支撑于所述插座中。
CN 200380109299 2002-12-06 2003-12-02 一用于测试集成电路的插座的制作方法及所述插座 CN100538369C (zh)

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