CN100533803C - Circuit structure of organic thin film transistor with dual-gate and its use - Google Patents

Circuit structure of organic thin film transistor with dual-gate and its use Download PDF

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Publication number
CN100533803C
CN100533803C CNB2006100791427A CN200610079142A CN100533803C CN 100533803 C CN100533803 C CN 100533803C CN B2006100791427 A CNB2006100791427 A CN B2006100791427A CN 200610079142 A CN200610079142 A CN 200610079142A CN 100533803 C CN100533803 C CN 100533803C
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China
Prior art keywords
gate
double
terminal
film transistor
coupled
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CNB2006100791427A
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Chinese (zh)
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CN101071845A (en
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王右武
王怡凯
贡振邦
萧智文
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财团法人工业技术研究院
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Abstract

The invention provides a circuit structure with double-gate organic TFT (thin film transistor) and its application. And the invention covers a protection layer on an organic TFT structure with a bottom gate to act as the other gate insulating layer and then locally forms a metal layer on the protection layer to act as the other gate and then completes a double-gate structure and applies it to electronic circuit design. Thus, it can regulate starting voltage of organic TFT corresponding to gate and benefit to change characteristic of the organic TFT to improve signal transmission accuracy.

Description

The circuit structure and the application thereof of tool double-gate utmost point OTFT

Technical field

The invention relates to a kind of circuit structure with machine thin-film transistor; Particularly relevant for a kind of circuit structure of tool double-gate utmost point OTFT.

Background technology

Present OTFT is because of the non-impurity-doped processing procedure, and (threshold voltage) is uncontrollable for the start voltage of transistor component, often depends on surface condition, the organic semi-conductor purity of assembly, with the material behavior of gate pole and gate insulation layer.This start voltage value V ThOften excessive, reach more than 10 volts, on applications of electronic circuitry, not only power consumption but also cause certain droop loss, the distortion that causes signal to transmit.Figure 1A and Figure 1B are existing two kinds of inverter circuit structure schematic diagrames that use OTFT, wherein the existing inverter of Figure 1A comprises one first reinforced N channel transistor (enhanced type NMOS), 10 and 1 second reinforced N channel transistor 12, and this second reinforced N channel transistor 12 is OTFT.Owing to have this second reinforced N channel transistor 12 in this inverter, can be between the drain end 16 of the output 14 of this inverter and this second reinforced transistor 12 generation one V ThPressure drop, and make the output signal value of this output 14 be offset, the distortion that causes signal to transmit, and because of the OTFT start voltage is big, this distortion more shape is serious.Therefore, in order to reduce start voltage and to improve the correctness that signal transmits, before inverter circuit designs of adopting Figure 1B more, this inverter is to comprise a reinforced N channel transistor 10a and a vague and general type N channel transistor (depletion type NMOS) 12a, and this vague and general type N channel transistor 12a is an OTFT.This vague and general type N channel transistor 12a is by because the interface between its metal gate and its N channel region carries out surface treatment, with this vague and general type N channel transistor 12a of realization.When the inverter circuit of using Figure 1B designs design of drive circuit in a display panels, because in the existing display panels processing procedure, be to form the thin-film transistor component of drive circuit area and pixel region thin-film transistor component simultaneously as switch module, so when carrying out surface treatment for the metal gate of the OTFT of drive circuit area and the interface between the channel region, when making these organic thin transistors become vague and general type, the thin-film transistor of this pixel region also can become vague and general type simultaneously, will cause the misoperation of pixel region switch module thus.

In view of the above, demand providing a kind of OTFT circuit structure of improvement urgently, too high to solve the OTFT start voltage, cause that signal transmits the problem of distortion on the applications of electronic circuitry.

Summary of the invention

Main purpose of the present invention provides a kind of circuit structure of tool double-gate utmost point OTFT, can be beneficial to the characteristic that changes this OTFT by this double-gate electrode structure, and then improves the correctness that signal transmits.

Another object of the present invention provides a kind of circuit structure of tool double-gate utmost point OTFT, but start voltage by this this OTFT of double-gate electrode structure modulation, adjust the output characteristic of the arithmetic element of using this circuit structure by this, to meet the demand of electronic circuit.

According to above-described purpose, the invention provides a kind of double-gate utmost point OTFT modular construction, it comprises a substrate, one first gate, one first gate insulation layer, a pair of source electrode and drain, an organic semiconductor active layer, one second gate insulation layer and one second gate.This first gate is to be formed in this substrate, this first gate insulation layer is to be formed on this first gate, this is to source electrode and drain, be to be formed on this first gate insulation layer, this organic semiconductor active layer is to be formed at this to source electrode and drain top and formation one organic semiconductor channel region between this is to source electrode and drain, this second gate insulation layer is to be formed on this organic semiconductor active layer, reaching this second gate is to be formed on this second gate insulation layer, and this second gate is to share this to source electrode and drain and this organic semiconductor channel region with this first gate.

In the double-gate electrode structure that above-mentioned first gate and second gate are formed, the start voltage of this double-gate utmost point OTFT is the result by this first gate and this second gate individual voltages comprehensive function, therefore can reach the purpose that reduces another gate start voltage by by regulation and control one gate voltage.

Moreover the present invention can be a reinforced transistor or a vague and general transistor npn npn with the characteristic that changes this OTFT by by the start voltage of adjusting this second gate also.

On the other hand, the invention provides a kind of circuit structure of tool double-gate utmost point OTFT, it comprises a thin-film transistor component and a pair of gate thin-film transistor component; This thin-film transistor component is to have a gate terminal, one first source terminal, one first drain end and one the one a N channel region, and this gate terminal is to be coupled to an input and this first drain end is to be coupled to an output; This double-gate electrode film transistor assembly is to have one first gate terminal, one second source terminal, one second drain end, one the 2nd N channel region and one second gate terminal, wherein this first gate terminal and this second gate terminal are shared this second source terminal, this second drain end and the 2nd N channel region, this first gate terminal is to be coupled to this second drain end, this second gate terminal is to be coupled to a bias voltage, and this second source terminal is to be coupled to this output.

By the foregoing circuit structure, can adjust the bias voltage size of this second gate terminal, so that this double-gate electrode film transistor assembly becomes a vague and general type (depletion type) N channel transistor assembly, thus, this circuit structure can be designed to have a kind of inverter of a reinforced N channel transistor assembly and a vague and general type N channel double-gate gated transistors assembly.

In addition, the invention provides another kind of inverter circuit design, it comprises a thin-film transistor component, is to have a gate terminal, one first source terminal, one first drain end and one the one a P channel region, and this gate terminal is to be coupled to an input and this first source terminal is to be coupled to an output; And a pair of gate thin-film transistor component, be to have one first gate terminal, one second source terminal, one second drain end, one the 2nd P channel region and one second gate terminal, wherein this first gate terminal and this second gate terminal are shared this second source terminal, this second drain end and the 2nd P channel region, this first gate terminal is to be coupled to this second source terminal, this second gate terminal is to be coupled to a variable bias, and this second drain end is to be coupled to this output.By adjusting the bias voltage size of this second gate terminal, so that this double-gate electrode film transistor assembly becomes a vague and general type (depletion type) P channel transistor assembly, thus, this inverter circuit design promptly has a reinforced P channel transistor assembly and a vague and general type P channel double-gate gated transistors assembly.

But double-gate utmost point OTFT of the present invention has the characteristic of simple structure and modulation, and its fabrication steps simply is easy to reach, and has economic worth.

Description of drawings

Figure 1A is an existing inverter circuit structure schematic diagram;

Figure 1B is another existing inverter circuit structure schematic diagram;

Fig. 2 A is the structural section schematic diagram of a specific embodiment of double-gate electrode film transistor of the present invention;

Fig. 2 B is a kind of inverter circuit structure schematic diagram with Fig. 2 A double-gate electrode film transistor;

Fig. 2 C is the another kind of inverter circuit structure schematic diagram with Fig. 2 A double-gate electrode film transistor; And

Fig. 3 is the present invention's one display pannel circuit structure block schematic diagram.

The conventional letter of major part:

The 10----first reinforced N channel transistor

The reinforced N channel transistor of 10a----

The 12----second reinforced N channel transistor

The vague and general type P channel transistor of 12a----

14----output 16----drain end

20----substrate 21----first gate

The 22----first gate insulation layer 23----source/drain

The 24----organic semiconductor active layer

24a----N type organic semiconductor channel region

The 25----second gate insulation layer 26----second gate

The reinforced thin-film transistor component of 200----N channel

201----gate terminal 202----first source terminal

The 203----first drain end 204----the one N channel region

205----input 206----output

The reinforced thin-film transistor component of 200c----P channel

The 201c----gate terminal 202c----first drain end

The 203c----first source terminal 204c----the one P channel region

205c----input 206c----output

30----viewing area 32----drive circuit area

400----N channel double-gate electrode film transistor assembly

The 401----first gate terminal 402----second source terminal

The 403----second drain end 404----the 2nd N channel region

405----second gate terminal

400c----P channel double-gate electrode film transistor assembly

The 401c----first gate terminal 402c----second drain end

The 403c----second source terminal 404c----the 2nd P channel region

405c----second gate terminal

Embodiment

The present invention is on the OTFT structure of gate at the bottom of the tool; cover the last layer protective layer, as another gate insulation layer, local again another metal level of formation is on this protective layer with this protective layer; with as another gate, to finish the OTFT structure of a tool double-gate utmost point.In the OTFT structure of this tool double-gate utmost point, the aforementioned double-gate utmost point is to share a pair of source electrode and a drain and an organic semiconductor channel region (organicsemiconductor channel), the start voltage of this OTFT is its first gate and second gate start voltage sum total, so, can adjust the start voltage that reduces this OTFT by its double-gate electrode structure.Moreover, can be by bias voltage by control second gate, and then control this OTFT and be operating as vague and general type (depletiontype) or reinforced (enhanced type).Further, the present invention can utilize aforementioned double-gate electrode structure in the special circuit part, and the start voltage of modulation OTFT, by output characteristic, to meet the demand of electronic circuit with the adjustment arithmetic element.

Below will be by cooperate appended graphicly described in detail by specific embodiment for double-gate utmost point OTFT modular construction of the present invention and application thereof.

Fig. 2 A is the structural section schematic diagram of a specific embodiment of double-gate utmost point OTFT assembly of the present invention.In this specific embodiment, this double-gate utmost point OTFT assembly is to comprise a substrate 20, one first gate 21, one first gate insulation layer 22, a pair of source electrode and drain 23, an organic semiconductor active layer 24, one second gate insulation layer 25 and one second gate 26; This first gate 21 is one first metal gate, is to be formed in this substrate 20, and this first gate insulation layer can be one deck silicon nitride (silicon nitride, SiN x) insulating barrier is to be formed on this first gate 21; this comprises second metal to source electrode and drain 23 is to be formed on this first gate insulation layer 22; this organic semiconductor active layer (organic active semiconductorlayer) the 24th is formed at this to source electrode and drain 23 tops and formation one organic semiconductor channel region 24a between this is to source electrode and drain 23; this second gate insulation layer 25 can be one deck silicon nitride dielectric layer; it is to be formed on this organic semiconductor active layer 24; and this second gate insulation layer 25 also can be positioned at first gate 21 of its below as a protective layer with protection; source electrode and drain 23 and organic semiconductor active layer 24.This second gate 26 is that one the 3rd metal level is to be formed on this second gate insulation layer 25.This second gate 26 is shared this to source electrode and drain 23 and this organic semiconductor channel region 24a with this first gate 21.

In this specific embodiment, by bias voltage V by this second gate 26 of control g, can change the characteristic of this double-gate utmost point OTFT, make it become vague and general type or reinforced N channel transistor.Moreover the start voltage of this double-gate utmost point OTFT is indivedual start voltage sum totals of first gate 21 and second gate 26, can be opened voltage the beginning of this OTFT by this double-gate electrode structure and reduce.

Fig. 2 B is a kind of inverter circuit structure schematic diagram with double-gate utmost point OTFT assembly of Fig. 2 A.This inverter circuit structure is to comprise reinforced thin-film transistor component 200 of a N channel and the vague and general type double-gate of N channel electrode film transistor assembly 400.The reinforced thin-film transistor component 200 of this N channel is to have a gate terminal 201, one first source terminal (V Ss) 202,1 first drain end 203 and one the one N channel region 204, this gate terminal 201 is to be coupled to an input 205 and this first drain end 203 is to be coupled to an output 206.This double-gate electrode film transistor assembly 400 is to be a pair of gate OTFT, and it has one first gate terminal 401, one second source electrode 402, one second drain (V Dd) 403,1 the 2nd N channel region 404 and one second gate terminal 405, wherein this first gate terminal 401 is shared this second source electrode 402, this second drain 403 and the 2nd N channel region 404 with this second gate terminal 405, this first gate terminal 401 is to be coupled to this second drain 403, and this second gate terminal 405 is to be coupled to a variable bias V g, and this second source electrode 402 is to be coupled to this output 206.

In this inverter circuit structure, this second gate terminal 405 is to be coupled to an adjustable bias voltage V g, therefore can pass through by adjusting this bias voltage V gSize, this double-gate utmost point OTFT assembly 400 of modulation becomes a vague and general type N channel transistor.When this double-gate utmost point OTFT assembly 400 is during for a vague and general type N passage double-gate gated transistors, the inverter shown in Fig. 2 B promptly has a reinforced N channel transistor and a vague and general type N passage double-gate gated transistors.In this inverter circuit structure, because this second drain end (V Dd) 403 and this output 206 between do not have V ThPressure drop produce, so the output signal value of this output 206 can be comparatively near actual signal value, and then can solve the problem of signal transmission distortion.Further, this double-gate utmost point OTFT assembly 400 also can have lower start voltage.

Fig. 2 C is the another kind of inverter circuit structure schematic diagram with double-gate utmost point OTFT assembly of Fig. 2 A.This inverter circuit structure is to comprise reinforced thin-film transistor component 200c of a P channel and the vague and general type double-gate of P passage electrode film transistor assembly 400c.The reinforced thin-film transistor component 200c of this P channel has a gate terminal 201c, one first drain end (V Dd) 202c, one first source terminal 203c and one the one P channel region 204c, this gate terminal 201c is coupled to an input 205c and this first source terminal 203c is coupled to an output 206c.This double-gate electrode film transistor assembly 400c is a pair of gate OTFT, and it has one first gate terminal 401c, one second drain end 402c, one second source terminal (V Ss) 403c, one the 2nd p channel region 404c and one second gate terminal 405c, wherein this first gate terminal 401c and this second gate terminal 405c share this second drain end 402c, this second source terminal 403c and the 2nd P channel region 404c, this first gate terminal 401c is coupled to this second source terminal 403c, and this second gate terminal 405c is coupled to a variable bias V g, and this second drain end 402c is coupled to this output 206c.

In this inverter circuit structure, this second gate terminal 405c is coupled to an adjustable bias voltage V g, therefore can pass through by adjusting this bias voltage V gSize, this double-gate utmost point OTFT assembly of modulation 400c becomes a vague and general type P channel transistor.When this double-gate utmost point OTFT assembly 400c is during for a vague and general type P passage double-gate gated transistors, the inverter shown in Fig. 2 C promptly has a reinforced P channel transistor and a vague and general type P passage double-gate gated transistors.In this inverter circuit structure, because this second source terminal (V Ss) there is not V between 403c and this output 206c ThPressure drop produce, so the output signal value of this output 206c can be comparatively near actual signal value, and then can solve the problem of signal transmission distortion.Further, this double-gate utmost point OTFT assembly 400c also can have lower start voltage.

Fig. 3 is an application examples schematic diagram of the inverter circuit structure of Fig. 2 B.Fig. 3 is a display pannel circuit structure block schematic diagram, and it comprises a viewing area 30 and one drive circuit zone 32.This viewing area 30 has plural single gate column of transistors (not shown), and each should list gate column of transistors be to comprise a plurality of single gate transistors for the switch module of doing individual pixel.This drive circuit area 32 is to have a plurality of inverter assemblies shown in Fig. 2 B, the output of each this inverter assembly be coupled to one should list gate column of transistors, to drive the transistor switch assembly in this list gate column of transistors.The circuit of display driving of Fig. 3 is the inverter circuit design of adopting Fig. 2 B, and the drive signal that this drive circuit is sent is not easy distortion, can drive individual pixel smoothly.Moreover, because this double-gate electrode film transistor 400 in this inverter is the bias voltage V that utilize this second gate 405 of control gSize, this double-gate electrode film transistor 400 of modulation becomes vague and general type N channel transistor, with regard to the processing procedure angle, the thin-film transistor processing procedure of this drive circuit can't have influence on the processing procedure of single gate thin-film transistor of pixel region, and then influence the characteristic of these single gate thin-film transistors, so can improve the fine ratio of product of display pannel.Similarly, the circuit of display driving of Fig. 3 also can adopt the inverter circuit design of Fig. 2 C.

The above is specific embodiments of the invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the following claim.

Claims (3)

1. the circuit structure of a tool double-gate utmost point OTFT is characterized in that, comprising:
One reinforced thin-film transistor component is to have a gate terminal, one first source terminal, one first drain end and one the one a N channel region, and this gate terminal is to be coupled to an input and this first drain end is to be coupled to an output; And
A pair of gate thin-film transistor component, be to have one first gate terminal, one second source terminal, one second drain end, one the 2nd N channel region and one second gate terminal, wherein this first gate terminal and this second gate terminal are shared this second source terminal, this second drain end and the 2nd N channel region, this first gate terminal is to be coupled to this second drain end, this second gate terminal is to be coupled to a variable bias, so that this double-gate electrode film transistor assembly is adjusted into vague and general transistor npn npn assembly, reaching this second source terminal is to be coupled to this output.
2. the circuit structure of tool double-gate utmost point OTFT as claimed in claim 1 is characterized in that, described this double-gate electrode film transistor assembly is a tool double-gate utmost point OTFT.
3. the circuit structure of a tool double-gate utmost point OTFT is characterized in that, comprising:
One reinforced thin-film transistor component is to have a gate terminal, one first source terminal, one first drain end and one the one a P channel region, and this gate terminal is to be coupled to an input and this first source terminal is to be coupled to an output; And
A pair of gate thin-film transistor component, be to have one first gate terminal, one second source terminal, one second drain end, one the 2nd P channel region and one second gate terminal, wherein this first gate terminal and this second gate terminal are shared this second source terminal, this second drain end and the 2nd P channel region, this first gate terminal is to be coupled to this second source terminal, this second gate terminal is to be coupled to a variable bias, so that this double-gate electrode film transistor assembly is adjusted into vague and general transistor npn npn assembly, reaching this second drain end is to be coupled to this output.
CNB2006100791427A 2006-05-10 2006-05-10 Circuit structure of organic thin film transistor with dual-gate and its use CN100533803C (en)

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CN100533803C true CN100533803C (en) 2009-08-26

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102591083A (en) * 2012-03-20 2012-07-18 深圳市华星光电技术有限公司 Charge share-type pixel structure

Families Citing this family (6)

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CN102544369A (en) * 2011-12-28 2012-07-04 北京交通大学 Organic thin film transistor with composite structure
CN103762251B (en) * 2014-01-22 2016-03-30 中山大学 A kind of bigrid photo tft, image element circuit and pel array
CN104092448B (en) * 2014-06-18 2017-05-31 京东方科技集团股份有限公司 Comparator, display base plate and display device
CN104795496A (en) * 2015-04-08 2015-07-22 深圳市华星光电技术有限公司 Bigrid device and manufacturing method thereof
CN106298883A (en) 2015-06-04 2017-01-04 昆山工研院新型平板显示技术中心有限公司 A kind of thin film transistor (TFT) and preparation method thereof
CN105609502A (en) * 2016-02-29 2016-05-25 深圳市华星光电技术有限公司 Complementary type thin film transistor and manufacturing method therefor

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Publication number Priority date Publication date Assignee Title
US20050270079A1 (en) * 2004-06-03 2005-12-08 Kuo-Ji Chen Input buffer structure with single gate oxide

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050270079A1 (en) * 2004-06-03 2005-12-08 Kuo-Ji Chen Input buffer structure with single gate oxide

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102591083A (en) * 2012-03-20 2012-07-18 深圳市华星光电技术有限公司 Charge share-type pixel structure
CN102591083B (en) * 2012-03-20 2014-11-19 深圳市华星光电技术有限公司 Charge share-type pixel structure

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