CN100527398C - Bump structure for a semiconductor device and method of manufacture - Google Patents

Bump structure for a semiconductor device and method of manufacture Download PDF

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Publication number
CN100527398C
CN100527398C CN 200510064958 CN200510064958A CN100527398C CN 100527398 C CN100527398 C CN 100527398C CN 200510064958 CN200510064958 CN 200510064958 CN 200510064958 A CN200510064958 A CN 200510064958A CN 100527398 C CN100527398 C CN 100527398C
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conductive
direction
bump
non
facing
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CN 200510064958
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CN1684253A (en )
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Samsung Electronics Co Ltd
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Description

半导体器件的凸点结构和制造方法 Bump structure of a semiconductor device and manufacturing method

技术领域 FIELD

本发明涉及半导体器件的凸点结构和制造方法。 The present invention relates to a bump structure and manufacturing method of a semiconductor device. 背景技术 Background technique

存在多种用于在半导体芯片或封装和电路板或其它衬底之间提供电连 There are a variety for providing electrical connection between the semiconductor chip and the package or the circuit board or other substrate,

接的不同技术。 Connection of different technologies. 在许多这些技术中的现在的潮流是使用焊料凸点(solder bump)以形成电连接来取代引线接合(wiringbonding)。 The trend in many of these techniques are now using solder bumps (solder bump) to form an electrical connection to replace wire bonding (wiringbonding). 例如,在如带载封装(TCP)、膜上芯片(COF)和玻璃上芯片(COG)的技术中使用凸点。 For example, using bumps as in the tape carrier package (TCP), chip on film (COF) and chip on glass (COG) technique. 如TCP和COF的技术被更广泛地称为带式自动焊接(TAB )。 The TCP and the COF technique is more widely known as tape automated bonding (TAB).

虽然通过允许在坪料凸点之间的间隔比引线接合之间的间隔减小,凸点提供了优于引线接合的优点,但是甚至凸点技术也面临凸点之间的间隔上的潜在的限制。 Although reduced by allowing the spacing between the bumps floor material than the interval between the wire bonding, bump provides advantages over wire bonding, bump technology but even face potential on the spacing between the bumps limit. 例如,在COG技术中,半导体芯片(例如液晶显示器驱动器集成电路(IC)封装)可以直接焊接到LCD基板上。 For example, in the COG technique, the semiconductor chip (e.g., a liquid crystal display driver integrated circuit (IC) package) can be welded directly to the LCD substrate. 在该技术中,在LCD 基板的焊盘和驱动器IC封装的相关凸点之间设置ACF (各向异性导电膜) 带以形成电连接。 In this technique, provided ACF (anisotropic conductive film) with correlation between bump pads and the LCD driver IC package substrate to form an electrical connection. ACF带包含在绝缘材料中嵌入的导电颗粒。 ACF tape embedded in the insulating material contained in the conductive particles. 导电颗粒在LCD基板的焊盘和焊料凸点之间提供电连接。 Conductive particles provide the electrical connection between the pad and the solder bump LCD substrate. 但是当凸点之间的间隙变小时,在ACF带中的颗粒可以提供凸点之间的电连接;因此造成短路。 However, when the gap between the bump becomes smaller, the particles in the ACF tape may provide the electrical connection between the bump; thus causing a short circuit.

发明内容 SUMMARY

本发明提供了一种去除在半导体芯片或封装的焊料凸点之间的间隔上的障碍物的凸点结构。 The present invention provides a method for removing a bump structure on the spacer between the solder bump of the semiconductor chip or package obstacle. 如此,本发明允许更小和更薄的半导体器件。 Thus, the present invention allows for smaller and thinner semiconductor devices.

在一示范性实施例中,沿衬底在第一方向上排列多个凸点结构。 In an exemplary embodiment, a plurality of bumps arranged structures along the substrate in a first direction. 每个凸点结构在第一方向上的宽度大于相继排列的凸点结构的间距。 Each bump structure width in a first direction is greater than the pitch of the bump structures arranged sequentially. 该间距可以认为是在衬底沿第一方向相继排列的凸点结构的相对侧壁的平面之间的测量的间隙。 The gap spacing can be considered measured between opposing sidewalls of the bump structures plane of a substrate successively in a first direction. 至少一个凸点结构具有在第一方向上面对的非导电侧壁。 At least one non-conductive bump structures having a side wall facing the first direction. 因为该侧壁为非导电的,在该凸点和相邻于非导电侧壁的凸点之间设置的导电颗粒不会在两个凸点之间形成短路。 Since the sidewall is non-conductive, conductive particles between the bump and the bump adjacent to the non-conductive sidewalls disposed a short circuit is not formed between the two bumps. 在一示范性实施例中,每个凸点结构具有至少一非导电侧壁面向第一方向。 In an exemplary embodiment, each of the bump structures having at least one non-conductive sidewalls facing a first direction.

在另一示范性实施例中,每个凸点结构具有两个相对面对的非导电侧壁面向第一方向。 In another exemplary embodiment, each of the non-conductive bump structures having two opposite facing side walls facing a first direction.

在再一示范性实施例中,每个凸点结构具有一非导电侧壁面向第一方向和一导电侧壁面向第一方向,使得导电侧壁不面对另一凸点结构的导电侧壁。 In another exemplary embodiment, each of the bump structures having a first direction and facing a conductive sidewalls facing a first direction, such that the conductive side wall that does not face another conductive sidewalls of a non-conductive bump structures sidewall .

在又一示范性实施例中,凸点结构阵列从第一型至第二型交替。 In yet another exemplary embodiment, an array of bump structures alternately from a first type to a second type. 第一型的凸点结构具有两个相对面对的非导电侧壁面向第一方向,而第二型的凸点结构具有两个相对面对的导电侧壁面向第一方向。 Bump structures having a first type of electrically non-conductive two opposite facing side walls facing a first direction, the bump structures having a second conductivity type facing two opposite side walls facing a first direction.

对于上述实施例的任意一个,可以沿衬底在第二方向上彼此偏移地设置相继排列的凸点结构。 For any of the above embodiments may be arranged in the second direction of the bump structures are successively arranged offset from one another along the substrate.

本发明的示范性实施例也包括多个沿衬底第一方向上排列的凸点和多个在第二方向上形成的导电线。 Exemplary embodiments of the present invention also includes a first electrically conductive lines arranged in a plurality of directions and a plurality of bumps formed along the substrate in the second direction. 每个导电线与凸点之一相关,而且每个导电 Each conductive lines associated with one of the bumps, and each of the conductive

线设置在相关凸点的顶表面和凸点的两个相对面对的侧壁之上;两个相对面对的侧壁面对第二方向。 Line is disposed above the top surface and two sidewall bumps associated opposite facing bumps; two facing side walls facing opposite the second direction. 每个导电线从两个相对面对的侧壁的每个在衬底上延伸。 Each conductive lines extending from each of two opposite facing side walls on the substrate. 因此,导电线有助于保持相关凸点附着于衬底。 Thus, the conductive wire helps to keep the relevant bump attached to the substrate.

其它本发明的示范性实施例提供了形成上述实施例的方法。 Other exemplary embodiments of the present invention provides a method of forming the above-described embodiments.

附图说明 BRIEF DESCRIPTION

从以下给出的详细描述和附图,本发明将变得明显易懂。 From the detailed description given below and the accompanying drawings, the present invention will become apparent. 附图中,相似的元件由相似的附图标记指示。 Drawings, like elements are indicated by like reference numerals. 只通过说明的方法给出详细描述和附图,而因此不用于本发明的限制。 Given only by the accompanying drawings and the detailed description of the method described, and thus are not intended to limit the present invention.

图1图示了本发明的示范性实施例的具有凸点结构的半导体器件; The semiconductor device of FIG. 1 illustrates an exemplary embodiment of the present invention having a bump structure;

图2图示了在图1所示的衬底沿线II-II的剖面图; FIG 2 illustrates a cross-sectional view of the substrate along line II-II shown in Figure 1;

图3图示了在图1所示的衬底沿线III-III的剖面图; FIG 3 illustrates a sectional view along line III-III of the substrate shown in FIG. 1;

图4图示了本发明的示范性实施例的具有凸点结构的半导体器件; The semiconductor device of FIG. 4 illustrates an exemplary embodiment of the present invention having a bump structure;

图5图示了在图4所示的衬底沿线VV的剖面图; FIG 5 illustrates a sectional view along the substrate of FIG. 4 VV;

图6图示了本发明的示范性实施例的具有凸点结构的半导体器件; FIG 6 illustrates a semiconductor device having a bump structure of an exemplary embodiment of the present invention;

图7图示了在图4所示的衬底沿线vn-vn的剖面图; FIG 7 illustrates a cross-sectional view along line vn-vn in the substrate shown in Figure 4;

图8图示了本发明的示范性实施例的具有凸点结构的半导体器件;图9图示了具有三组凸点结构的半导体器件的俯-f见图; 图10A-15B图示了本发明的凸点结构的制造方法的实施例,其中图10A、 11A、 12、 13A、 14和15A表现在制造工艺期间的衬底的剖面图,而图IOB、 IIB、 13B和15B表现在制造工艺期间的村底的俯视图。 The semiconductor device having a bump structure 8 illustrates an exemplary embodiment of the present invention; FIG. 9 illustrates a semiconductor device having a plan -f see three bump structure; FIGS. 10A-15B illustrate the present embodiment of the manufacturing method of the bump structures of the present invention, wherein FIG. 10A, 11A, 12, 13A, 14 and 15A showed cross-sectional view of the substrate during the manufacturing process, and FIG. IOB, IIB, 13B and 15B in a manufacturing process performance top view of the bottom of the village period.

具体实施方式 Detailed ways

本发明提供一种去除半导体芯片或封装的焊料凸点之间的间隔上的障碍物的凸点结构。 The present invention provides a method for removing obstacles on the bump structures spacing between solder bumps of the semiconductor chip or package. 如此,本发明允许更小和更薄的半导体器件。 Thus, the present invention allows for smaller and thinner semiconductor devices. 首先,将描述几个本发明的结构实施例,随后描述本发明的形成凸点结构的方法。 First, a configuration of several embodiments of the present invention will be described, a method of forming a bump structure of the present invention described later.

第一结构实施例 First embodiment Structure

图1图示了本发明的示范性实施例的具有凸点结构的半导体器件。 FIG 1 illustrates a structure of a semiconductor device having a bump of the present invention, an exemplary embodiment. 如所示,在衬底200上的绝缘层202上在由双向箭头A指示的第一方向上排列凸点结构100。 As shown, the insulating layer 200 on the substrate 202 on the bump structures 100 are arranged in a first direction indicated by the double arrow A. 每个凸点结构100包括非导电凸点102。 Each bump structure 100 includes a non-conductive bump 102. 非导电凸点102具有两个面对第一方向的相对面对的侧壁104和两个面对第二方向的相对面对的侧壁106,第二方向基本垂直于第一方向,由双向箭头B指示。 Two non-conductive bump 102 having a first facing direction opposite facing side walls 104 and two second facing side walls facing opposite the direction 106, a second direction substantially perpendicular to the first two-way direction, the indicated by arrow B.

在一示范实施例中,每个凸点102具有2至30/mi的高度H、 10至50/mi 的宽度Wb和20至200/mi的长度Lb。 In an exemplary embodiment, each of the bumps 102 having 2 to 30 / mi of height H, a length of a width of 10 to 50 / mi of Wb and 20 to 200 / mi of Lb.

每个凸点结构IOO也包括在与之相关的凸点102的顶表面和在第二方向上面对的每个侧壁106上设置的导电层108。 Each bump structure also includes a conductive layer 108 IOO provided on the top surface of the bumps associated with each side wall 102 and 106 facing in the second direction. 在凸点102上的导电层108形成导电线110的一部分,导电线110从一侧壁104在衬底200上方延伸较短距离,而从另一侧壁106在衬底200上方延伸较长距离。 Conductive layer 108 is formed on a portion of the bumps 102, conductive lines 110 of conductive line 110 extends a short distance above the substrate 200 from a side wall 104, while the other side wall 106 extending above the substrate 200 a long distance . 如所示,导电线110 在第二方向上延伸。 As shown, the conductive lines 110 extend in the second direction. 导电线110的较长延伸通向相关的芯片焊盘204,其中导电层110电连接于相关的焊盘204。 Conductive lines extending long leads 204 associated with the die pad 110, wherein the conductive layer 110 is connected to the associated pad 204. 可以理解,焊盘204提供导电线110 和在衬底200上形成的电路(未示出)之间的电连接。 It will be appreciated, the pad 204 to provide conductive lines 110 and the circuit formed on the substrate 200 (not shown) electrically connected between.

图2图示了在图1所示的衬底沿线II-II的剖面图而图3图示了在图l所 Figure 2 illustrates a cross-sectional view of the substrate along line II-II in FIG. 1 and FIG. 3 are illustrated in Figure l

示的衬底沿线ni-ni的剖面图。 Ni-ni sectional view along the line of the substrate shown. 虽然为了清晰的目的在图i中未显示,本发 Although not shown for clarity in FIG i, the invention

明的该实施例的凸点结构还包括在衬底200的一部分上形成的钝化层180, 如图2和3所示。 Ming bump structure of this embodiment further includes a passivation layer 180 is formed on a portion of the substrate 200, as shown in Figures 2 and 3.

图2显示了图1中的相邻凸点结构IOO之间的间距PG。 Figure 2 shows the spacing between adjacent bump structures PG in FIG. 1 IOO. 间距PG是两个凸点结构之间的距离;且更具体地,可以是在衬底200或钝化层180沿第一方向上在相继排列的凸点结构IOO的相对侧壁104所在的平面之间测量的的宽度Wb大于间距PG。 PG is the spacing distance between the two bump structures; more specifically, may be a planar substrate in a first direction 200 or the passivation layer 180 are successively arranged bump structures IOO 104 located opposite sidewalls measured width Wb is greater than the spacing between the PG. 例如,间距 For example, the pitch

PG可以大约为10/xm。 PG may be about 10 / xm.

因为间距PG小于凸点结构lOO的宽度Wb,当使用例如ACF带时,可 Because the gap is smaller than the width Wb of the bump structures PG lOO when using e.g. ACF tape, may

能会发生短路。 Short circuit can occur. 但是,因为凸点结构IOO面向第一方向的侧壁104为非导电 However, since the bump structures 104 facing in a first direction IOO sidewall of non-conductive

的,所以防止了此类短路。 And so we prevent such a short circuit. 因此,本发明提供了去除在半导体芯片或封装的 Accordingly, the present invention provides for the removal of a semiconductor chip or package

焊料凸点之间的间隔上的障碍物的凸点结构。 Bump structures obstacle on the spacing between the solder bumps. 如此,本发明允许更小和更薄 Thus, the present invention allows for smaller and thinner

的半导体器件。 The semiconductor device.

第二结构实施例 The second embodiment of the structure

图4图示了本发明的示范性实施例的具有凸点结构的半导体器件,而图5图示了在图4所示的衬底沿线VV的剖面图。 Figure 4 illustrates with exemplary embodiments of the present invention, the bump structure of a semiconductor device, and FIG 5 illustrates a sectional view along line VV in the substrate shown in FIG. 4. 如所示,图4的实施例除了凸点结构之外与图1的实施例相同。 As shown, the embodiment of FIG. 4 in addition to the bump structures same as the embodiment of FIG. 在图4的实施例中,每个凸点结构100, 与图1所示的凸点结构IOO相同,只是导电层108覆盖了相同的在第一方向上面对的侧壁104之一。 In the embodiment of Figure 4, each of the bump structure 100 and bump structures shown in FIG. 1 IOO identical, except one of the conductive layer 108 covers the same in the first direction facing side walls 104. 如此, 一凸点结构IOO的导电侧壁104面对另一凸点结构100的非导电侧壁104。 Thus, a conductive bump structures IOO sidewall 104 facing the other side wall 104 of a non-conductive bump structures 100.

因为在第一方向上面对的凸点结构100的侧壁104之一是非导电的,所 Because one of the side wall 104 of a non-conductive bump structures 100 facing in a first direction, and the

间的间隔上的障碍物的凸点结构。 Bump structure obstacles on the interval between. 如此,本发明允许更小和更薄的半导体器件。 Thus, the present invention allows for smaller and thinner semiconductor devices.

第三结构实施例 The third embodiment of the structure

图6图示了本发明的示范性实施例的具有凸点结构的半导体器件,而图 FIG 6 illustrates a semiconductor device having a bump structure according to the present exemplary embodiment of the invention, and FIG.

7图示了在图6所示的衬底沿线vn-vn的剖面图。 7 illustrates a substrate as shown in FIG. 6 a sectional view along line vn-vn's. 如所示,图6的实施例 As shown, the embodiment of FIG. 6

除了凸点结构之外与图1的实施例相同。 In addition to the embodiment of FIG bump structures the same as in Example 1. 在图6的实施例包括交替的两种类型的凸点结构。 The bump structures comprising alternating two types in the embodiment of FIG. 第一型凸点结构IOO与图1所示的凸点结构IOO相同。 The first type bump and the bump structure IOO IOO structure shown in FIG. 1 the same. 第二型凸点结构IOO"与图1所示的凸点结构IOO相同,除了导电层108覆盖在第一方向上面对的两个侧壁104之外。但是,因为凸点结构的两个类型沿衬底200的第一方向交替,第二型凸点结构IOO,,的导电侧壁104面对第一型凸点结构IOO的非导电侧壁104。因此避免了短路。因此,本发明提供了去除在半导体芯片或封装的焊料凸点之间的间隔上的障碍物的凸点结构。如此,本 The second type bump structure IOO "bump structures shown in the same FIG. 1 IOO, in addition to two side walls 108 cover 104 facing in a first direction than the conductive layer. However, because two of the bump structures type substrate 200 along a first direction alternately, a second type of electrically conductive bump structures ,, IOO nonconductive sidewall 104 facing the first side wall 104. the type of the bump structures IOO thus avoiding a short circuit. Accordingly, the present invention providing bump structures were removed on the spacing between the solder bump of the semiconductor chip or package obstacle. thus, the present

发明允许更小和更薄的半导体器件。 Invention allows for smaller and thinner semiconductor devices. 第四结构实施例 The fourth embodiment of the structure

图8图示了本发明的示范性实施例的具有凸点结构的半导体器件。 The semiconductor device of FIG. 8 illustrates an exemplary embodiment of the present invention having a bump structure. 如所 As

ii示,图8中的凸点结构与图1所示的凸点结构相同,除了相继排列的凸点结构在第二方向上从彼此偏移之外。 ii shown, bump bump structures and the same structure shown in FIG. 1 in FIG. 8, except that the bump structures are successively arranged in the second direction from the outside offset from each other. 更具体地,凸点结构100被分为两组。 More specifically, the bump structures 100 are divided into two groups. The first

一组中的凸点结构100-1具有比第二组中的凸点结构100-2短的导电线110, 且第一组的凸点结构100-1与第二组的凸点结构100-2在第一方向上交替。 Bump structures having a group 100-1 of the bump structures 100-2 shorter than the second set of conductive lines 110, and the first group of bump structures bump structures 100-1 and the second group 100 2 in the first direction alternately.

应当理解,如图8所示,偏移凸点结构100进一步有助于防止可能的短路。 It should be appreciated that, as shown in FIG offset bump structures 100 further assist in preventing a possible short circuit 8. 因为连续的凸点结构100没有排成一行,短路不易发生,且因为排成一行的凸点结构之间的间隙大(例如,大于20/mi),短路不易发生。 Because continuous bump structures 100 is not aligned, a short circuit hardly occurs, and because of the large gap between the bump structures arranged in a row (e.g., greater than 20 / mi), a short circuit hardly occurs.

虽然使用图1的凸点结构IOO显示和描述图8的实施例,但是应当理解该实施例可以结合在前描述的实施例的任意一个凸点结构。 Although FIG. 1 IOO bump structures shown and described embodiment of Figure 8, it should be understood that this embodiment may be combined with any of the preceding embodiments described a bump structures.

另外,虽然已经图示了两组排成一行的凸点结构,但是应当理解可以形成多于两组凸点结构,每个从其它的组偏移。 Further, although two bump structures has been illustrated in a line, it should be understood that more than two groups may form a bump structures, each offset from the other group. 图9图示了具有三组凸点结构100的半导体器件的俯视图。 9 illustrates a top view of a semiconductor device having three sets of bump structures 100.

方法实施例 Example embodiments

接下来,将描述本发明的具有凸点结构的半导体器件的制造方法。 Next, a method of manufacturing a semiconductor device having a bump structure of the present invention will be described. 只为了举例的目的,将参照图1所示的凸点结构IOO的制造描述该方法。 For purposes of example only, the method will be described with reference to FIG IOO manufacturing a bump structures shown in Figure 1. 将参照图10A-15B描述该方法,其中图IOA、 IIA、 12、 13A、 14和15A表现在制造工艺期间的衬底的剖面图,而图IOB、 IIB、 13B和15B表现在制造工艺期间的衬底的俯视图。 With reference to the description of FIG. 1OA-15B, wherein FIG IOA, IIA, 12, 13A, 14 and 15A a cross-sectional view of the substrate during performance of the manufacturing process, and FIG. IOB, IIB, 13B and 15B performance during the manufacturing process a top view of the substrate.

如图IOA和iOB所示,工艺由具有芯片焊盘204形成于其上的衬底200 开始。 As shown in FIG. IOA and IOB, process 204 is formed on the substrate having thereon a chip pad 200 begins. 为了清晰的目的,只显示了单一的芯片焊盘。 For clarity, only a single die pad. 同样,为了清晰,未显示芯片焊盘204电连接的器件、电路等。 Likewise, for clarity, not shown device, circuit 204 is electrically connected to the die pad. 第一钝化层202形成于衬底200上且被构图以暴露芯片焊盘204的部分225。 The first passivation layer 202 is formed on the substrate 200 and is patterned to expose the die pad 204 portion 225. 第一钝化层202可以是SiN、 Si02 或SiN+Si02,且可以由化学气相沉积(CVD)形成。 The first passivation layer 202 may be a SiN, Si02 or SiN + Si02, and may be formed by a chemical vapor deposition (CVD).

之后,例如,通过旋涂在衬底上形成如聚酰亚胺、BCB(苯并环丁烷)、 PBO(聚苯唑)、光敏树脂等的介电层。 Then, for example, a dielectric layer such as polyimide, BCB (benzocyclobutene), a PBO (poly oxacillin), a photosensitive resin or the like by spin coating on the substrate. 介电层可以形成至2-30pm的厚度。 The dielectric layer may be formed to a thickness of 2-30pm. 然后,使用掩模构图介电层以形成如图IIA和图IIB所示的非导电凸点102。 Then, using a mask to form a patterned dielectric layer as shown in FIG IIA and IIB illustrated in a non-conductive bump 102. 凸点102可以具有2-30]Lim的高度,且可以具有10-50/xm的宽度和50-200iLmi 的长度。 2-30 may have bumps 102] Lim height, and may have a width of 10-50 / xm and a length of 50-200iLmi. 在一示范实施例中,宽度是20/mi且长度是100Mm。 In an exemplary embodiment, a width of 20 / mi and a length of 100Mm.

如图12所示,在—于底200上形成第一金属层140。 As shown in FIG. 12, - a first metal layer 140 formed on the bottom 200. 第一金属层140可以具有0.05-l^m的厚度。 The first metal layer 140 may have a thickness of 0.05-l ^ a m. 第一金属层140可以由任何具有良好粘接性能和低电阻的金属形成,如TiW、 Cr、 Cu、 Ti、 Ni、 NiV、 Pd、 Cr/Cu、 TiW/Cu、TiW/Au、 NiV/Cu等。 The first metal layer 140 may be formed from any metal having good adhesive properties and low resistance, such as TiW, Cr, Cu, Ti, Ni, NiV, Pd, Cr / Cu, TiW / Cu, TiW / Au, NiV / Cu Wait. 同样,第一金属层140可以通过压力气相沉积(PVD )、 电镀或无电镀(electrolessplating)工艺等形成。 Also, the first metal layer 140 may, electroplating or electroless plating (electrolessplating) formed by press process or the like vapor deposition (PVD).

之后,如图13A和13B所示,在衬底200上形成光致抗蚀剂图案150。 Thereafter, as shown in FIG 13A and 13B, a photoresist pattern 150 is formed on the substrate 200. 光致抗蚀剂图案150形成如图13B所示的掩模。 The photoresist pattern 150 is formed in the mask shown in Figure 13B. 使用该掩模,在由该掩模暴露的衬底200的部分上形成第二金属层160。 Using the mask, a second metal layer 160 is formed on a portion of the substrate 200 exposed by the mask. 第一和第二金属层140和160 形成导电层108和导电线110。 First and second metal layers 140 and 160 conductive layer 108 and the conductive lines 110 are formed.

第二金属层160可以形成至l-10/mi的厚度。 The second metal layer 160 may be formed to a thickness of l-10 / mi of. 在一示范实施例中,第一和第二金属层140和160的总厚度小于10/mi。 In an exemplary embodiment, the total thickness of the first and second metal layers 140 and 160 is less than 10 / mi. 第二金属层160可以通过例如电镀由Au、 Ni、 Cu、 Pd、 Ag、 Pt等或这些金属的多层形成。 The second metal layer 160 may be formed by electroplating a plurality of layers, for example, Au, Ni, Cu, Pd, Ag, Pt, or the like of these metals.

之后,如图14所示,去除光致抗蚀剂图案150,保持凸点结构100电连接于焊盘204。 Thereafter, as shown in FIG. 14, the photoresist pattern is removed 150, holding structure 100 is electrically connected to the bump pads 204. 然后第二钝化层180可以形成于衬底200上且被构图以暴露凸点结构100,如图15A和15B所示。 Then the second passivation layer 180 may be formed on the substrate 200 and is patterned to expose the bump structures 100, as shown in FIG. 15A and 15B. 第二钝化层可以为聚酰亚胺、BCB、 PBO、光敏树脂等,且可以由旋涂工艺涂覆。 The second passivation layer may be a polyimide, BCB, PBO, a photosensitive resin or the like, and may be coated by a spin coating process.

如上描述的凸点结构和制造方法可以应用于任何使用凸点的技术,如带载封装(TCP)、膜上芯片(COF)和玻璃上芯片(COG)。 Bump structure and manufacturing method as described above may be applied using any technique bumps, such as a tape carrier package (TCP), chip on film (COF) and chip on glass (COG). 而且,如上描述 Further, as described above

显示器(LCD)驱动器集成电路(IC)封装)。 Display (LCD) driver integrated circuit (IC) package).

如此描述本发明,显然本发明可以以许多的方法改变。 Having thus described the present invention, that the invention may be varied in many way. 这样的改变不认为是背离本发明,且所有这样的改变意在包括于本发明的范围内。 Such variations are not regarded as a departure from the invention, and all such modifications are intended to be included within the scope of the invention.

Claims (48)

  1. 1. 一种半导体器件,包括:沿衬底在第一方向上排列的多个凸点结构,每个凸点结构在第一方向上的宽度大于相继排列的凸点结构之间的间距并且包括非导电凸点和至少设置在所述非导电凸点的顶表面上的导电层,以及至少一个凸点结构的非导电凸点具有面向第一方向并且对外暴露的侧壁,其中,彼此相邻且彼此面对的面向第一方向的所述侧壁中的至少一个对外暴露。 1. A semiconductor device, comprising: a structure of the substrate along a plurality of bumps arranged in a first direction, the width of each of the bump structures in a first direction is greater than the spacing between the bump structures comprises successively arranged and and at least a non-conductive bumps disposed on a top surface of the non-conductive bump to a conductive layer, and at least one non-conductive bump having a bump structure faces a first direction and outside the exposed sidewalls, wherein adjacent to each other and at least one exposed outside the side wall facing the first direction of facing each other.
  2. 2. 如权利要求1所述的半导体器件,其中每个凸点结构的非导电凸点具有至少一个面向所述第一方向并且对外暴露的侧壁。 2. The semiconductor device according to claim 1, wherein the non-conductive bump bump structures each having at least a first direction and facing the outside exposed sidewall.
  3. 3. 如权利要求2所述的半导体器件,其中每个凸点结构的非导电凸点具有两个面向所述第一方向并且对外暴露的相对面对的侧壁。 3. The semiconductor device according to claim 2, wherein each of the non-conductive bump having a bump structure in the first direction and the two outside faces of the side walls opposite the exposed face.
  4. 4. 如权利要求3所述的半导体器件,其中在每个凸点结构中,所述导电层设置于所述非导电凸点的顶表面和至少一个面对第二方向的侧壁上,所述导电层从面对所述第二方向的侧壁在所述衬底的一部分上在第二方向上延伸。 4. The semiconductor device according to claim 3, wherein each bump in the structure, the conductive layer disposed on a top surface of the non-conductive bump and at least one sidewall facing the second direction, the said conductive layer extends from the side wall facing the second direction on a portion of said substrate in a second direction.
  5. 5. 如权利要求4所述的半导体器件,其中每个导电层电连接于所述衬底上的相关焊盘,设置所述相关焊盘分离开所述相关凸点结构。 5. The semiconductor device according to claim 4, wherein each conductive layer is electrically connected to the associated pads on the substrate, the relevant pad is provided separate from said correlation bump structures.
  6. 6. 如权利要求4所述的半导体器件,其中每个导电层至少包括下金属层和上金属层。 6. The semiconductor device according to claim 4, wherein each conductive layer comprises at least a lower metal layer and upper metal layers.
  7. 7. 如权利要求4所述的半导体器件,其中相继排列的凸点结构沿所述村底在所述第二方向上从彼此偏离。 7. The semiconductor device according to claim 4, wherein the bump structures are successively arranged along the bottom from the village offset from each other in the second direction.
  8. 8. 如权利要求7所述的半导体器件,其中所述第二方向基本垂直于所述第一方向。 8. The semiconductor device according to claim 7, wherein said second direction is substantially perpendicular to the first direction.
  9. 9. 如权利要求2所述的半导体器件,其中每个凸点结构的非导电凸点具有一个面向所述第一方向并且对外暴露的侧壁和一个面向所述第一方向并且被所述导电层覆盖的侧壁,使得其面向所述第一方向并且被所述导电层覆盖的所述侧壁不面对另一凸点结构的非导电凸点的面向所述第一方向并且被所述导电层覆盖的所述侧壁。 9. The semiconductor device according to claim 2, wherein each of the non-conductive bump bump structures having a first direction of said first direction and facing the outside and the exposed sidewall and oriented by the conductive layer covering the sidewall, such that it is facing the first direction and the side wall of the conductive layer covers the first direction not facing the non-conductive bump to another bump structures facing and being the the conductive layer covers the sidewall.
  10. 10. 如权利要求9所述的半导体器件,其中在每个凸点结构中,所述导电层设置于所述非导电凸点的顶表面和至少一个面对第二方向的侧壁上,所述导电层从面对所述第二方向的侧壁在所述衬底的一部分上在第二方向上延伸。 10. The semiconductor device according to claim 9, wherein each of the bump structure, the conductive layer disposed on a top surface of the non-conductive bump and at least one sidewall facing the second direction, the said conductive layer extends from the side wall facing the second direction on a portion of said substrate in a second direction.
  11. 11. 如权利要求10所述的半导体器件,其中每个导电层电连接于所述衬底上的相关焊盘,设置所述相关焊盘分离开所述相关凸点结构。 11. The semiconductor device according to claim 10, wherein each conductive layer is electrically connected to the associated pads on the substrate, the relevant pad is provided separate from said correlation bump structures.
  12. 12. 如权利要求10所述的半导体器件,其中每个导电层至少包括下金属层和上金属层。 12. The semiconductor device according to claim 10, wherein each conductive layer comprises at least a lower metal layer and upper metal layers.
  13. 13. 如权利要求10所述的半导体器件,其中相继排列的凸点结构沿所述衬底在所述第二方向上从;波此偏离。 13. The semiconductor device according to claim 10, wherein the bump structures are successively arranged along the substrate in the second direction; this departing from the wave.
  14. 14. 如权利要求13所述的半导体器件,其中所述第二方向基本垂直于所述第一方向。 14. The semiconductor device according to claim 13, wherein said second direction is substantially perpendicular to the first direction.
  15. 15. 如权利要求1所述的半导体器件,其中凸点结构的阵列从第一型至第二型交替,所述第一型的凸点结构的非导电凸点具有两个相对面对的面向所述第一方向并且对外暴露的侧壁,而所述第二型的凸点结构的非导电凸点具有的每个侧壁被所述导电层覆盖。 15. The semiconductor device according to claim 1, wherein the array structure of alternating bumps to a second type from the first type, the first type of the non-conductive bump having a bump structure facing the two opposite facing the first direction and the external exposed sidewall, and the second type of the non-conductive bump having a bump structure of each side wall is covered with the conductive layer.
  16. 16. 如权利要求15所述的半导体器件,其中在每个凸点结构中,所述导电层设置于所述非导电凸点的顶表面和所述非导电凸点的至少一个面对第二方向的侧壁上,所述导电层从面对所述第二方向的侧壁在所述衬底的一部分上在第二方向上延伸。 At least a second face 16. The semiconductor device according to claim 15, wherein each of the bump structure, the conductive layer disposed on a top surface of the non-conductive bump and the non-conductive bump direction on the side wall of the conductive layer extending in a second direction from the second side wall facing direction on a portion of said substrate.
  17. 17. 如权利要求16所述的半导体器件,其中每个导电层电连接于所述衬底上的相关焊盘,设置所述相关焊盘分离开所述相关凸点结构。 17. The semiconductor device according to claim 16, wherein each conductive layer is electrically connected to the associated pads on the substrate, the relevant pad is provided separate from said correlation bump structures.
  18. 18. 如权利要求16所述的半导体器件,其中每个导电层至少包括下金属层和上金属层。 18. The semiconductor device according to claim 16, wherein each conductive layer comprises at least a lower metal layer and upper metal layers.
  19. 19. 如权利要求16所述的半导体器件,其中相继排列的凸点结构沿所述衬底在所述第二方向上从彼此偏离。 19. The semiconductor device according to claim 16, wherein the bump structures are successively arranged along the substrate offset from each other in the second direction.
  20. 20. 如权利要求19所述的半导体器件,其中所述第二方向基本垂直于所述第一方向。 20. The semiconductor device according to claim 19, wherein said second direction is substantially perpendicular to the first direction.
  21. 21. 如权利要求1所述的半导体器件,其中在每个凸点结构中,所述导电层设置于所述非导电凸点的顶表面和所述非导电凸点的至少一个面对第二方向的侧壁上,所述导电层从面对所述第二方向的侧壁在所述衬底的一部分上在所述第二方向上延伸。 21. The semiconductor device according to claim 1, wherein each of the bump structure, the conductive layer disposed on a top surface of the non-conductive bump and said at least one non-conductive bump to a second face direction on the side wall of the conductive layer extending in a direction from the second sidewall facing the second direction on a portion of said substrate.
  22. 22. 如权利要求21所述的半导体器件,其中每个导电层电连接于所述村底上的相关焊盘,设置所述相关焊盘分离开所述相关凸点结构。 22. The semiconductor device according to claim 21, wherein each conductive layer is electrically connected to the associated pads on the bottom of the village, the relevant pad is provided separate from said correlation bump structures.
  23. 23. 如权利要求21所述的半导体器件,其中每个导电层至少包括下金属层和上金属层。 23. The semiconductor device according to claim 21, wherein each conductive layer comprises at least a lower metal layer and upper metal layers.
  24. 24. 如权利要求23所述的半导体器件,其中所述下金属层具有0.05至l(am的厚度,且所述上金属层具有1至10pm的厚度。 24. The semiconductor device according to claim 23, wherein the lower metal layer has 0.05 to l (am thickness, and the upper metal layer having a thickness of 1 to 10pm.
  25. 25. 如权利要求23所述的半导体器件,其中所述下金属层包括TiW、 Cr、 Cu、 Ti、 Ni、 NiV、 Pd、 Cr/Cu、 TiW/Cu、 TiW/Au、 NiV/Cu的至少一种, 而且所述上金属层包括Au、 Ni、 Cu、 Pd、 Ag和Pt的至少一种。 At least 25. The semiconductor device according to claim 23, wherein the lower metal layer comprises TiW, Cr, Cu, Ti, Ni, NiV, Pd, Cr / Cu, TiW / Cu, TiW / Au, NiV / Cu is one of the upper and the metal layer comprises Au, Ni, Cu, Pd, Ag and Pt is at least one.
  26. 26. 如权利要求1所述的半导体器件,其中设置相继排列的凸点结构沿衬底在第二方向上从彼此偏离。 26. The semiconductor device according to claim 1, wherein the bump structures arranged successively disposed along the substrate in the second direction offset from each other.
  27. 27. 如权利要求26所述的半导体器件,其中所述第二方向基本垂直于所述第一方向。 27. The semiconductor device according to claim 26, wherein said second direction is substantially perpendicular to the first direction.
  28. 28. 如权利要求1所述的半导体器件,其中所述凸点结构具有10至50iim 的宽度。 28. The semiconductor device according to claim 1, wherein the bump structures having a width of 10 to 50iim.
  29. 29. 如权利要求1所述的半导体器件,其中每个非导电凸点具有2-30(im 的高度。 29. The semiconductor device according to claim 1, wherein each of the non-conductive bump having 2-30 (im height.
  30. 30. 如权利要求1所述的半导体器件,其中在每个凸点结构中,所述导电层设置在两个相对面对的面对第二方向的侧壁上,且所述导电层从两个相对面对的侧壁的每一个在衬底上延伸。 A conductive layer disposed on a side wall facing a second direction opposite two faces, and from the conductive layer 30. The two semiconductor device according to claim 1, wherein each of the bump structure, the each one opposing facing side walls extending on the substrate.
  31. 31. 如权利要求1所述的半导体器件,其中每个非导电凸点包括聚酰亚胺、苯并环丁烷、聚苯唑和光敏树脂之一。 31. The semiconductor device according to claim 1, wherein each of the non-conductive bump comprises benzocyclobutane, one polybenzazole and polyimide photosensitive resin.
  32. 32. —种半导体器件,包括:多个非导电凸点,沿衬底在第一方向上排列,每个非导电凸点在所述第一方向上具有的宽度大于相继排列的凸点之间的间距;多个导电线,在第二方向上形成,每个导电线与非导电凸点之一相关, 每个导电线设置于相关的所述非导电凸点的顶表面和所述非导电凸点的两个相对面对的面对所述第二方向的侧壁上并且暴露出至少一个面对所述第一方向的所述非导电凸点的侧壁,以及每个导电线从两个相对面对的侧壁的每一个在所述衬底上延伸,其中,彼此相邻且彼此面对的面对所述第一方向的所述侧壁中的至少一个对外暴露。 32. - semiconductor device, comprising: a plurality of non-conductive bumps, are arranged along the substrate in a first direction, each having a non-conductive bump in the first direction is greater than the width between successive bumps arranged pitch; a plurality of conductive lines formed in a second direction, each of the conductive lines associated with one of the non-conductive bumps, each conductive line is disposed on the top surface of the associated non-conductive and the non-conductive bump the sidewall on the sidewall of the non-conductive bumps facing two opposite faces of the bumps in the second direction and exposing the at least a face of said first direction, and each of the two conductive lines exposing each of at least one outside facing side walls extending relatively on said substrate, wherein adjacent to each other and the facing side walls facing each other in the first direction.
  33. 33. —种半导体器件,包括:多个非导电凸点,沿衬底在第一方向上排列,每个非导电凸点在所述第一方向上具有的宽度大于相继排列的凸点之间的间距;和多个导电线,在第二方向上形成,每个导电线与非导电凸点之一相关, 每个导电线设置于相关的所述非导电凸点的顶表面和相关的所述非导电凸点的一个面对所述第二方向的侧壁上并且暴露出至少一个面对所述第一方向的所述非导电凸点的侧壁,且每个导电线从面对第二方向的侧壁在所述衬底上延伸,其中,^皮此相邻且^:此面对的面对所述第一方向的所述侧壁中的至少一个对外暴露。 33. - semiconductor device, comprising: a plurality of non-conductive bumps, are arranged along the substrate in a first direction, each having a non-conductive bump in the first direction is greater than the width between successive bumps arranged pitch; and a plurality of conductive lines formed in a second direction, each of the conductive lines associated with one of the non-conductive bumps, each conductive line is disposed on the top surface of the associated non-conductive bump and the associated said non-conductive bumps on a side wall facing a second direction and exposing the at least one sidewall of the first direction facing the non-conductive bump, and the first face of each conductive wire from two side walls extending in the direction of the substrate, wherein the skin adjacent thereto and ^ ^: exposing at least one of the external faces of the side walls facing this in the first direction.
  34. 34. —种形成半导体器件的方法,包括:形成多个凸点结构,所述凸点结构沿衬底在第一方向上排列,每个凸点结构在所述第一方向上具有的宽度大于相继排列的凸点结构之间的间距并且包括非导电凸点,和至少一个凸点结构的非导电凸点具有面对所述第一方向并且对外暴露的侧壁,其中,彼此相邻且彼此面对的面对所述第一方向的所述侧壁中的至少一个对外暴露。 34. - The method of forming a semiconductor device types, comprising: a structure forming a plurality of bumps, the bump structures are arranged along the substrate in a first direction, each of the bump structures has a width in the first direction is greater than the spacing between the bump structures are successively arranged and comprises a non-conductive bump, and at least one non-conductive bump having a bump structure facing the first direction and outside the exposed sidewalls, wherein adjacent to each other and to each other exposing at least one of the external faces of the side walls of the first direction facing the.
  35. 35. 如权利要求34所述的方法,其中形成步骤包括: 形成多个非导电凸点,所述非导电凸点沿所述衬底在所述第一方向上排列;和在第二方向上形成与每个非导电凸点相关的导电线,每个导电线设置于相关的所述非导电凸点的顶表面和相关的所述非导电凸点的面对所述第二方向的侧壁上,且每个导电线从面对所述第二方向的所述侧壁在衬底上延伸。 35. The method according to claim 34, wherein the forming step includes: forming a plurality of non-conductive bumps, the bumps along the non-conductive substrate are arranged in the first direction; and a second direction associated with each side wall forming a non-conductive bump to conductive wires, each conductive wire provided on the top surface of the associated non-conductive bump and the associated non-conductive bumps facing the second direction, on, and each of said conductive lines extending from the side wall facing the second direction on the substrate.
  36. 36. 如权利要求34所述的方法,其中所述形成所述多个非导电凸点的步骤包括:在所述衬底上旋涂非导电凸点材料;且构图所述非导电凸点材料以形成所述多个非导电凸点。 36. The method according to claim 34, wherein the forming the plurality of non-conductive bumps comprises: spin-coated on the substrate in a non-conductive bump material; and patterning the non-conductive bump material to form said plurality of non-conductive bumps.
  37. 37. 如权利要求36所述的方法,其中每个非导电凸点包括聚酰亚胺、 苯并环丁烷、聚苯唑和光敏树脂之一。 37. The method according to claim 36, wherein each of the non-conductive bump comprises benzocyclobutane, one polybenzazole and polyimide photosensitive resin.
  38. 38. 如权利要求36所述的方法,其中所述构图步骤形成所述多个非导电凸点使得每个非导电凸点具有10至50(im的宽度。 38. The method according to claim 36, wherein said step of patterning said plurality of non-conductive bumps are formed such that each non-conductive bump having from 10 to 50 (the width of the im.
  39. 39. 如权利要求36所述的方法,其中所述构图步骤形成所述多个非导电凸点使得每个非导电凸点具有2-30jim的高度。 39. The method according to claim 36, wherein said step of patterning said plurality of non-conductive bumps are formed such that each non-conductive bump having a height 2-30jim.
  40. 40. 如权利要求35所述的方法,其中每个导电线至少包括下金属层和上金属层。 40. The method according to claim 35, wherein each conductive line comprises at least a lower metal layer and upper metal layers.
  41. 41. 如权利要求40所述的方法,其中所述下金属层具有0.05至ljim的厚度,且所述上金属层具有1至10pm的厚度。 41. The method according to claim 40, wherein the lower metal layer has a thickness of 0.05 to ljim, and the upper metal layer having a thickness of 1 to 10pm.
  42. 42. 如权利要求40所述的方法,其中所述下金属层包括TiW、 Cr、 Cu、 Ti、 Ni、 NiV、 Pd、 Cr/Cu、 TiW/Cu、 TiW/Au、 NiV/Cu的至少一种,而且所述上金属层包括Au、 Ni、 Cu、 Pd、 Ag和Pt的至少一种。 42. The method according to at least one of claim 40, wherein the lower metal layer comprises TiW, Cr, Cu, Ti, Ni, NiV, Pd, Cr / Cu, TiW / Cu, TiW / Au, NiV / Cu is species, and the upper metal layer comprises Au, Ni, Cu, Pd, Ag and Pt is at least one.
  43. 43. 如权利要求40所述的方法,其中所述形成导电线的步骤包括: 形成所述下金属层;和用上金属层材料电镀所述下金属层以形成所述上金属层。 43. The method according to claim 40, wherein said step of forming conductive lines comprising: forming said lower metal layer; and spend the material of the plated metal layer to form the lower metal layer on the metal layer.
  44. 44. 如权利要求34所述的方法,其中每个凸点结构的非导电凸点至少具有一个面对所述第一方向并且对外暴露的侧壁。 44. The method according to claim 34, wherein the non-conductive bump bump structures each having at least one of said first direction and facing the external exposed sidewall.
  45. 45. 如权利要求34所述的方法,其中每个凸点结构的非导电凸点具有两个相对面对的面对所述第一方向并且对外暴露的侧壁。 45. The method according to claim 34, wherein each of the non-conductive bump having a bump structure facing the first direction and two opposite facing side walls exposed outside.
  46. 46. 如权利要求34所述的方法,其中每个凸点结构的非导电凸点具有一个面对所述第一方向并且对外暴露的侧壁和一个面对所述第一方向并且被导电层覆盖的侧壁,使得其面对所述第一方向并被所述导电层覆盖的所述侧壁不面对另一凸点结构的非导电凸点的面对所述第一方向并被所述导电层覆盖的所述侧壁。 46. ​​The method according to claim 34, wherein each of the non-conductive bump having a bump structure and the conductive layer is exposed outside a side wall facing the first direction and a facing direction of the first and covering the sidewall facing the first direction such that said sidewall and said conductive layer is covered with a non-conductive bump does not face another bump structures facing the first direction and the said conductive layer covering the sidewall.
  47. 47. 如权利要求34所述的方法,其中所述凸点结构的阵列从第一型至第二型交替,所述第一型的凸点结构的非导电凸点具有两个相对面对的面对所述第一方向并且对外暴露的侧壁,而所述第二型的凸点结构的非导电凸点的每个侧壁都被导电层覆盖。 47. The method according to claim 34, wherein the bump array from the first type alternating configuration to a second type, the first type of the non-conductive bump bump structures having two opposite facing the external face of the first direction and the exposed side wall and each side wall structure of the non-conductive bump to bump the second type are covered with a conductive layer.
  48. 48. —种形成半导体器件的方法,包括:形成多个非导电凸点,所述非导电凸点沿衬底在第一方向上排列,每个非导电凸点在所述第一方向上具有的宽度大于相继排列的凸点之间的间距; 和在第二方向上形成多个导电线,每个导电线与非导电凸点之一相关,每个导电线设置于相关的所述非导电凸点的顶表面和相关的所述非导电凸点的面对所述第二方向的侧壁上并且暴露出至少一个面对所述第一方向的所述非导电凸点的侧壁,且每个导电线从面对第二方向的所述侧壁在衬底上延伸,其中,彼此相邻且彼此面对的面对所述第一方向的所述侧壁中的至少一个对外暴露。 48. - The method of forming a semiconductor device types, comprising: forming a plurality of non-conductive bumps, said non-conductive bumps are arranged along the substrate in a first direction, each having a non-conductive bump in the first direction a width larger than the spacing between the successive bumps are arranged; a plurality of conductive lines formed in a second direction, each of the conductive lines associated with one of the non-conductive bumps, conductive lines disposed on each of the associated non-conductive on the side wall and top surface of the bumps associated with the non-conductive bumps facing the second direction and exposing the at least a direction facing the first sidewall of the non-conductive bump, and exposing at least one outside each of the conductive lines extending from the side wall facing the second direction on the substrate, wherein adjacent to each other and the facing side walls facing each other in the first direction.
CN 200510064958 2004-04-14 2005-04-12 Bump structure for a semiconductor device and method of manufacture CN100527398C (en)

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US11091869 US20050233569A1 (en) 2004-04-14 2005-03-29 Bump structure for a semiconductor device and method of manufacture

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