CN100514632C - Stack type semiconductor packaging structure - Google Patents

Stack type semiconductor packaging structure Download PDF

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Publication number
CN100514632C
CN100514632C CN 200610127421 CN200610127421A CN100514632C CN 100514632 C CN100514632 C CN 100514632C CN 200610127421 CN200610127421 CN 200610127421 CN 200610127421 A CN200610127421 A CN 200610127421A CN 100514632 C CN100514632 C CN 100514632C
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China
Prior art keywords
substrate
chip
package structure
low modulus
conductor package
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CN 200610127421
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Chinese (zh)
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CN101145555A (en
Inventor
卢勇利
李政颖
叶荧财
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN 200610127421 priority Critical patent/CN100514632C/en
Publication of CN101145555A publication Critical patent/CN101145555A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Abstract

A stackable semiconductor package structure is provided, which comprises a first substrate, a chip, a low modules film, a second substrate, a plurality of first wires, and a first packaging adhesive. The chip is positioned on the first substrate. The low modules film is positioned on the chip. The second substrate is positioned on the low modules film, and the area of the low modules film can be regulated according to the area of the second substrate, to support the second substrate. The first wire is electrically connected with the first substrate and the second substrate. The first packaging adhesive exposes the partial solder pad of the second substrate. Therefore, during the wire bonding operation, the suspension part of the second substrate doesn't swing or vibrate and the area of the second substrate can be increased to store more elements. Additionally, the thickness of the second substrate can be reduced so s to reduce the total thickness of the stackable semiconductor package structure.

Description

Stackable semi-conductor package structure
Technical field
The present invention relates to a kind of Stackable semi-conductor package structure, particularly relate to a kind of Stackable semi-conductor package structure that includes low modulus film (Low Modules Film).
Background technology
Please refer to Fig. 1, be the cross-sectional schematic of existing Stackable semi-conductor package structure.Existing Stackable semi-conductor package structure 1 comprises first substrate 11, chip 12, sept (Spacer) 13, second substrate 14, a plurality of first leads 15 and first adhesive material 16.
First substrate 11 has first surface 111 and second surface 112.Chip 12 has first surface 121 and second surface 122, the second surface 122 of chip 12 utilizes mucigel 17 to be attached on the first surface 111 of first substrate 11, and the first surface 121 of chip 12 utilizes a plurality of second leads 18 to be electrically connected to the first surface 111 of first substrate 11.Sept 13 is attached on the first surface 121 of chip 12.The second surface 142 that second substrate 14 has first surface 141 and second surface 142, the second substrates 14 is attached on this sept 13, has a plurality of first weld pads 143 and a plurality of second weld pad 144 on the first surface 141 of second substrate 14.Therefore the area of second substrate 14 need utilize sept 13 to do support with the meeting of the overlooking sight area greater than chip 12, is pressed onto second lead 18 to prevent second substrate 14.
First lead 15 is electrically connected the first surface 111 of first weld pad, 143 to first substrates 11 of second substrate 14.First adhesive material 16 coats first surface 111, chip 12, second lead 18, sept 13, part second substrate 14 and first lead 15 of first substrate 11, and expose second weld pad 144 on the first surface 141 of second substrate 14, and form sealing opening (Mold Area Opening) 19.Under normal conditions, existing Stackable semi-conductor package structure 1 can repeatedly be put another encapsulating structure 20 or other element again in sealing opening 19, and wherein the soldered ball 201 of encapsulating structure 20 is electrically connected second weld pad 144 of second substrate 14.
The shortcoming of existing Stackable semi-conductor package structure 1 is as follows.At first, sept 13 is a plate body, and it cuts into required size in advance, is attached on behind the gluing on the chip 12 again, and second substrate 14 is attached on the sept 13 more afterwards, and above-mentioned steps is not only complicated, and easy fitted not.Secondly, sept 13 can not touch second lead 18, so its area must be less than the area of chip 12, yet because the area of second substrate 14 can be greater than the area of chip 12, therefore second substrate, 14 some part can extend outside the sept 13, and form overhanging portion.Under normal conditions, first weld pad 143 can be positioned at overhanging portion (being the periphery of sept 13 or chip 12 relative positions), and the distance definition between the relative position at the edge of first weld pad 143 and sept 13 is unsettled length L 1, show under thickness T the situation 1 three times or more of unsettled length L 1 through experiment greater than second substrate 14, when routing (Wire Bonding) operation, overhanging portion has the situation of rocking or shaking, and is unfavorable for carrying out the routing operation.What is more, when the routing operation, second substrate 14 is subjected to downward stress when too big, can cause second substrate 14 break (crack).Secondly, owing to have and above-mentionedly rock, shake or the situation of breaking, therefore overhanging portion can not be oversize, makes the area of second substrate 14 be restricted, thereby be limited to the arrangement space of second weld pad 144 on the first surface 141 that sealing opening 19 exposes second substrate 14.At last, in order to reduce the above-mentioned situation of rocking, shaking or breaking, the thickness of second substrate 14 can not be too thin, therefore can't effectively reduce the integral thickness of existing Stackable semi-conductor package structure 1.
Therefore, be necessary to provide a kind of Stackable semi-conductor package structure of innovating and having progressive, to address the above problem.
Summary of the invention
Main purpose of the present invention is to provide a kind of Stackable semi-conductor package structure.
For realizing described purpose, the present invention includes first substrate, chip, low modulus film (Low ModulesFilm), second substrate, a plurality of first leads and first adhesive material.First substrate has first surface and second surface.Chip is positioned at the first surface of first substrate, and is electrically connected to the first surface of first substrate.The low modulus film is positioned on the chip.Second substrate is positioned on the low modulus film, second substrate has first surface and second surface, have a plurality of first weld pads and a plurality of second weld pad on the first surface of second substrate, the area of low modulus film can be adjusted according to the area of second substrate, to support second substrate.First lead is electrically connected the first surface of first weld pad to the first substrate of second substrate.First adhesive material coats first surface, chip, low modulus film, part second substrate and first lead of first substrate, and exposes second weld pad on the first surface of second substrate.
A kind of Stackable semi-conductor package structure that the invention provides is when the routing operation, the overhanging portion of second substrate does not have and rocks, shakes or the situation of breaking, and the area of second substrate can strengthen, to place more multicomponent, in addition, the thickness of second substrate can reduce, and then reduces the thickness of Stackable semi-conductor package structure integral body.
The present invention's purpose feature and advantage will be elaborated in conjunction with the accompanying drawings with embodiment.
Description of drawings
Fig. 1 is the cross-sectional schematic of existing Stackable semi-conductor package structure;
Fig. 2 is the cross-sectional schematic of first embodiment of Stackable semi-conductor package structure of the present invention;
Fig. 3 is the cross-sectional schematic of second embodiment of Stackable semi-conductor package structure of the present invention;
Fig. 4 is the cross-sectional schematic of the 3rd embodiment of Stackable semi-conductor package structure of the present invention;
Fig. 5 is the cross-sectional schematic of the 4th embodiment of Stackable semi-conductor package structure of the present invention.
Wherein, description of reference numerals is as follows:
1 existing Stackable semi-conductor package structure
2 first embodiment of the invention Stackable semi-conductor package structures
3 second embodiment of the invention Stackable semi-conductor package structures
4 third embodiment of the invention Stackable semi-conductor package structures
5 fourth embodiment of the invention Stackable semi-conductor package structures
Embodiment
Please refer to Fig. 2, be the cross-sectional schematic of first embodiment of Stackable semi-conductor package structure of the present invention.Stackable semi-conductor package structure 2 comprises first substrate 21, chip 22, low modulus film (LowModules Film) 23, second substrate 24, a plurality of first leads 25 and first adhesive material 26.
First substrate 21 has first surface 211 and second surface 212.Chip 22 has first surface 221 and second surface 222, the second surface 222 of chip 22 utilizes mucigel 27 to be attached on the first surface 211 of first substrate 21, and the first surface 221 of chip 22 utilizes a plurality of second leads 28 to be electrically connected to the first surface 211 of first substrate 21.Low modulus film 23 is positioned on the first surface 221 of this chip 22.The second surface 242 that second substrate 24 has first surface 241 and second surface 242, the second substrates 24 is attached on the low modulus film 23, has a plurality of first weld pads 243 and a plurality of second weld pad 244 on the first surface 241 of second substrate 24.
In the present embodiment, low modulus film 23 is the thermosetting resin of adhesive tape (Tape) pattern, and its composition comprises resin (comprising epoxy resin (Epoxy Resin) and phenol resin (Phenol Resin)), acryl rubber (Acrylic Rubber) and silicon inserts (Si Filler).The employed low modulus film 23 of present embodiment is that (Hitachi Chemical Co. Ltd.) produces, and product type is FH-WP in Hitachi Chemical Company Ltd..Low modulus film 23 has higher coefficient of elasticity (Elastic Modulus) after solidifying (Curing), and can support this second substrate 24.Because low modulus film 23 itself promptly has tackness, so its execution mode is earlier low modulus film 23 to be formed on the second surface 242 of second substrate 24, places on the first surface 221 of chip 22 again, is cured afterwards to get final product again.Yet the level height that is noted that low modulus film 23 its upper surface 231 after curing will be higher than the highest point of second lead 28.
First lead 25 is electrically connected the first surface 211 of first weld pad, 243 to first substrates 21 of second substrate 24.First adhesive material 26 coats first surface 211, chip 22, second lead 28, low modulus film 23, part second substrate 24 and first lead 25 of first substrate 21, and expose second weld pad 244 on the first surface 241 of second substrate 24, and form sealing opening 29.Under normal conditions, Stackable semi-conductor package structure 2 can repeatedly be put another encapsulating structure 30 or other element again in sealing opening 29, and wherein the soldered ball 301 of encapsulating structure 30 is electrically connected second weld pad 244 of second substrate 24.
Please refer to Fig. 3, be the cross-sectional schematic of second embodiment of Stackable semi-conductor package structure of the present invention.The Stackable semi-conductor package structure 3 of present embodiment and the Stackable semi-conductor package structure 2 of first embodiment are roughly the same, and wherein similar elements is given identical numbering.Not existing together of the Stackable semi-conductor package structure 3 of present embodiment and the Stackable semi-conductor package structure 2 of first embodiment only is the size of second substrate 24 and low modulus film 23.Second substrate 24 of present embodiment is slightly larger than second substrate 24 of first embodiment, and the area of low modulus film 23 can be adjusted according to the area of this second substrate 24, be that low modulus film 23 can extend to the area that approaches second substrate 24, and covered section second lead 28.Low modulus film 23 has low-down modulus (Module) when chance is hot, be enough to absorb the stress of second lead 28, and can not impact to second lead 28.So can have the support effect more preferable, therefore can support second substrate 24 of large-size than first embodiment.In the present embodiment, first weld pad 243 is positioned at the periphery of chip 22 relative positions, distance definition between the relative position at the edge of first weld pad 243 and chip 22 is unsettled length L 2, because the support of low modulus film 23, make under thickness T the situation 2 three times or more of unsettled length L 2, when the routing operation, do not have the situation of rocking and take place greater than second substrate 24.
Please refer to Fig. 4, be the cross-sectional schematic of the 3rd embodiment of Stackable semi-conductor package structure of the present invention.The Stackable semi-conductor package structure 4 of present embodiment and the Stackable semi-conductor package structure 2 of first embodiment are roughly the same, and wherein similar elements is given identical numbering.Not existing together of the Stackable semi-conductor package structure 4 of present embodiment and the Stackable semi-conductor package structure 2 of first embodiment only is the size of low modulus film 23.In the present embodiment, the area of second substrate 24 is greater than the area of chip 22, and the area of low modulus film 23 can be adjusted according to the area of this second substrate 24, that is to say, low modulus film 23 extends to 242 of the second surfaces of the first surface 211 of first substrate 21 and second substrate 24, and coats second lead 28 and chip 22 fully.So can have the support effect more preferable, can prevent that two substrates 24 from rocking when the routing operation, and can use the second big and thin substrate 24 than second embodiment.
Please refer to Fig. 5, be the cross-sectional schematic of the 4th embodiment of Stackable semi-conductor package structure of the present invention.Stackable semi-conductor package structure 5 comprises first substrate 51, chip 52, low modulus film 53, second substrate 54, a plurality of first leads 55 and first adhesive material 56.
First substrate 51 has first surface 511 and second surface 512.Chip 52 has first surface 521 and second surface 522, and the second surface 522 of chip 52 is to cover the first surface 511 that crystal type is attached to first substrate 51.Low modulus film 53 is positioned on the first surface 521 of chip 52.The second surface 542 that second substrate 54 has first surface 541 and second surface 542, the second substrates 54 is attached on the low modulus film 53, has a plurality of first weld pads 543 and a plurality of second weld pad 544 on the first surface 541 of second substrate 54.
First lead 55 is electrically connected the first surface 511 of first weld pad, 543 to first substrates 51 of this second substrate 54.First adhesive material 56 coats first surface 511, chip 52, low modulus film 53, part second substrate 54 and first lead 55 of first substrate 51, and exposes second weld pad 544 on the first surface 541 of second substrate 54, and forms sealing opening 59.Under normal conditions, Stackable semi-conductor package structure 5 can repeatedly be put another encapsulating structure 60 or other element again in sealing opening 59, and wherein the soldered ball 601 of encapsulating structure 60 is electrically connected second weld pad 544 of these second substrates 54.
Similarly, low modulus film 53 can with the low modulus film 23 the same areas that extend near second substrate 54 shown in Figure 3, or low modulus film 53 also can equally with low modulus film shown in Figure 4 23 extend to 542 of the second surfaces of the first surface 511 of first substrate 51 and second substrate 54.
The foregoing description only is explanation principle of the present invention and effect thereof, but not in order to restriction the present invention.Therefore, person skilled in the art scholar can make amendment to the foregoing description without prejudice to spirit of the present invention and change.Interest field of the present invention claims as described later is listed.

Claims (10)

1, a kind of Stackable semi-conductor package structure is characterized in that, comprising:
One first substrate has a first surface and a second surface;
One chip is positioned at the first surface of this first substrate, and is electrically connected to the first surface of this first substrate;
One low modulus film (Low Modules Film) is positioned on this chip;
One second substrate, be positioned on this low modulus film, this second substrate has a first surface and a second surface, have a plurality of first weld pads and a plurality of second weld pad on the first surface of this second substrate, the area of this low modulus film is adjusted according to the area of this second substrate, to support this second substrate;
A plurality of first leads are electrically connected the first surface of this first weld pad of this second substrate to this first substrate; And
One first adhesive material coats first surface, this chip, this low modulus film, this first lead and this second substrate of part of this first substrate, and exposes this second weld pad on the first surface of this second substrate.
2, Stackable semi-conductor package structure as claimed in claim 1, it is characterized in that, more comprise a plurality of second leads, in order to be electrically connected the first surface of this chip and this first substrate, this chip is attached on the first surface of this first substrate, and the level height of the upper surface of low modulus film is higher than the highest point of this second lead.
3, Stackable semi-conductor package structure as claimed in claim 2 is characterized in that, the area of this second substrate is greater than this area of chip, and this low modulus film extends to this second lead, and this second lead of covered section.
4, Stackable semi-conductor package structure as claimed in claim 2, it is characterized in that, the area of this second substrate is greater than this area of chip, this low modulus film extends between the second surface of the first surface of this first substrate and this second substrate, and coats this second lead and this chip fully.
5, Stackable semi-conductor package structure as claimed in claim 1 is characterized in that, this chip is with on the first surface that covers crystal type and be attached to this first substrate.
6, Stackable semi-conductor package structure as claimed in claim 5, it is characterized in that, the area of this second substrate is greater than this area of chip, and this low modulus film extends between the second surface of the first surface of this first substrate and this second substrate, and coats this chip fully.
7, Stackable semi-conductor package structure as claimed in claim 1 is characterized in that, this low modulus film is an adhesive tape pattern.
8, Stackable semi-conductor package structure as claimed in claim 1 is characterized in that, this low modulus film is a thermosetting resin.
9, Stackable semi-conductor package structure as claimed in claim 1 is characterized in that, this first weld pad is positioned at the periphery of this chip relative position.
10, Stackable semi-conductor package structure as claimed in claim 9 is characterized in that, the distance definition between the relative position at the edge of this first weld pad and this chip is a unsettled length, and this unsettled length is greater than the thickness of this second substrate more than three times.
CN 200610127421 2006-09-13 2006-09-13 Stack type semiconductor packaging structure Active CN100514632C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 200610127421 CN100514632C (en) 2006-09-13 2006-09-13 Stack type semiconductor packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 200610127421 CN100514632C (en) 2006-09-13 2006-09-13 Stack type semiconductor packaging structure

Publications (2)

Publication Number Publication Date
CN101145555A CN101145555A (en) 2008-03-19
CN100514632C true CN100514632C (en) 2009-07-15

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CN101145555A (en) 2008-03-19

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