CN100499169C - Structure of thin-film transistor and method of manufacturing same - Google Patents

Structure of thin-film transistor and method of manufacturing same Download PDF

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CN100499169C
CN100499169C CN 200410068279 CN200410068279A CN100499169C CN 100499169 C CN100499169 C CN 100499169C CN 200410068279 CN200410068279 CN 200410068279 CN 200410068279 A CN200410068279 A CN 200410068279A CN 100499169 C CN100499169 C CN 100499169C
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amorphous silicon
formed
silicon
film transistor
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CN1630097A (en )
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陈东佑
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友达光电股份有限公司
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Abstract

一种薄膜晶体管(Thin Film Transistor,TFT),系利用间隔层(Spacer Layer)隔绝含氮的绝缘层和NI接合区,以使漏电流量降低,提升TFT组件的电子稳定性。 A thin film transistor (Thin Film Transistor, TFT), based using spacer layer (Spacer Layer) isolated from the nitrogen-containing insulating layer and the bonding area NI, so that the leakage flow rate decreases, to enhance the stability of the electronic components of the TFT. 其中,在背沟道蚀刻式TFT组件中,间隔层,例如是氧化层,系形成于沟道区间的侧壁,用以隔开氮化硅保护层和NI接合区。 Wherein the back channel etch TFT device, the spacer layer, e.g. an oxide layer, formed on the channel-based side wall section, and the protective layer to the silicon nitride NI spaced lands. 在蚀刻停止式TFT组件中,间隔层则形成于蚀刻停止层的两侧,用以隔绝氮化硅蚀刻停止层和NI接合区。 Etch stop TFT device, the spacer layer is formed on both sides of the etch stop layer for the silicon nitride etch stop layer isolated and NI lands.

Description

薄膜晶体管的结构及其制造方法 Structure and manufacturing method of a thin film transistor

技术领域 FIELD

本发明涉及一种薄膜晶体管的结构及其制造方法,且特别涉及一种可降低漏电流的薄膜晶体管结构及其制造方法。 The present invention relates to a structure and a method for manufacturing a thin film transistor, and more particularly to a thin film transistor structure and method capable of reducing leakage current.

背景技术 Background technique

随着半导体工艺技术的蓬勃发展,工艺组件越来越小,其集成电路的积集度增加。 With the rapid development of semiconductor process technology, process components become smaller and smaller, increase its product set of integrated circuits. 然而,在微缩组件的同时,也要顾虑到工艺組件的稳定性, However, while the miniature components, but also take into consideration the stability of the process components,

例如在TFT组件关闭时,不能产生过量的漏电流(LeakageCurrent), For example, when the component is off TFT, leakage current is not excessive (LeakageCurrent),

以薄膜晶体管为例,其中一种传统结构的剖面示意图如图1所示。 A thin film transistor as an example, wherein a schematic cross-sectional view of a conventional structure shown in Fig. 首先,于基板102上方沉积第一金属层(First Metal Layer),并利用光刻与蚀刻技术图案化第一金属层,以形成栅极104。 First, the substrate 102 is deposited above the first metallic layer (First Metal Layer), and by using photolithography and etching techniques patterned first metal layer to form a gate 104. 常见的金属层材料例如是纯铝、 钼(Mo)、铝钕合金(AlNd)、或由此组成的复合层。 Common metallic material such as a layer of pure aluminum, molybdenum (Mo), aluminum neodymium (AlNd), or a composite layer of the resulting composition.

接着,于栅极104上方形成栅极绝缘层106。 Next, over the gate electrode 104 is formed on the gate insulating layer 106. 然后利用沉积、光刻和蚀刻工艺,依序形成非晶硅层(Amorphous Silicon Layer,简称a-Si Layer)108 与奥姆接触层(Ohmic Contact Layer) 110,例如是n型非晶硅层(n十a-Si Layer) 于栅极绝缘层106的上方。 Then using deposition, photolithography and etching processes, an amorphous silicon layer are sequentially formed (Amorphous Silicon Layer, referred to as a-Si Layer) 108 and the ohmic contact layer (Ohmic Contact Layer) 110, for example, an n-type amorphous silicon layer ( ) above the n + a-Si layer gate insulating layer 106.

接着,沉积第二金属层,如钛、钼、铬、铝等金属,于整个基板102 之上,利用光刻与蚀刻工艺,对该金属层进行图案化的步骤,以形成漏极112与源极113。 Then, depositing a second metal layer, such as titanium, molybdenum, chromium, metal such as aluminum, over the entire substrate 102 using a photolithography and etching process, a step of patterning the metal layer to form the drain 112 and the source pole 113. 并在栅极104上方的金属层中,形成暴露非晶硅层108的沟道114。 And the metal layer 104 above the gate electrode, the channel 114 formed in the exposed amorphous silicon layer 108. 此沟道114隔开漏极112及源极113。 This channel 114 spaced apart from drain 112 and the source 113.

然后,沉积保护层116于整个基板102之上,此保护层116,例如是氮化硅(SiN》层,系覆盖漏极112及源极113并填满沟道114。另外,藉由光刻与蚀刻步骤,可于保护层116中形成另一开口(未显示)以暴露漏极ll2。 最后,透明电极层(未显示)覆盖于保护层116之上,并填满暴露至漏极ll2 的开口,同样的,再利用光刻与蚀刻工艺,图案化此透明电极层。 Then, the protective layer 116 is deposited over the entire substrate 102, the protective layer 116, for example, a silicon nitride "layer (the SiN, the drain lines 112 and the source cover 113 and fill channel 114. Further, by photolithography and an etching step, the protective layer 116 may be formed in another opening (not shown) to expose the drain ll2. Finally, a transparent electrode layer (not shown) overlying the protection layer 116 exposed to the drain and fill the ll2 opening the same, then using photolithography and etching process, patterning the transparent electrode layer.

由于非晶硅层系为不含外来杂质的半导体层,又称为本征非晶硅半导体层(Intrinsic a-Si Layer)。 Since the amorphous silicon layer containing no foreign matter-based semiconductor layer, amorphous silicon semiconductor layer (Intrinsic a-Si Layer), also known as intrinsic. 而n型非晶硅层110与本征非晶硅半导体层108之间的接触称为NI接合(Junction)。 And the n-type amorphous silicon layer 110 in contact between the intrinsic amorphous silicon semiconductor layer 108 and the engagement referred NI (Junction). 在传统结构中,电子容易自NI接合往沟道114中的保护层116流动,而造成漏电流(LeakageCurrent)过量的问题, 影响了组件的电性稳定度。 In the conventional structure, since the electrons are easily bonded to NI protective layer 116 of the channel 114 in the flow, causing the problem of excessive leakage current (LeakageCurrent), affecting the stability of the electrical components.

发明内容 SUMMARY

有鉴于此,本发明的目的就是在提供一种薄膜晶体管的结构及其制造方法,利用层间隔层(spacerlayer),以使漏电流量降低,提升组件的电子稳定性。 In view of this, the object of the present invention is to provide a structure and method for manufacturing a thin film transistor, using a spacer layer (spacerlayer), so that the leakage flow rate decreases, to enhance the stability of the electronic components.

根据本发明的目的,系提出一种薄膜晶体管(ThinFilmTransistor,TFT), 包括:基板(Substrate),其上形成绝缘表面;沟道区间(Channel Region),形成于基板的绝缘表面上方,且沟道区间具有本征非晶硅半导体层(Intrinsic Amorphous Semiconductor Layer);漏极与源极,位于沟道区间有两侧,该对漏极与源极分别有可导电的本征非晶硅半导体区;间隔层,形成于可导电的本征非晶硅半导体区的侧壁处;和绝缘层,形成于沟道区间内。 The object of the present invention, the system provides a thin film transistor (ThinFilmTransistor, TFT), comprising: a substrate (Substrate,), which is formed on an insulating surface; channel interval (Channel Region), formed over the insulating surface of the substrate, and the channel section having an intrinsic amorphous silicon semiconductor layer (intrinsic amorphous semiconductor layer); the drain and the source of the channel section has two sides of the drain and source has an electrically conductive intrinsic amorphous silicon semiconductor region, respectively; spacer layer, formed on the sidewall of the electrically conductive intrinsic amorphous silicon semiconductor region; and an insulating layer formed on the channel section. 其中, 间隔层隔绝了绝缘层与可导电的本征非晶硅半导体区的直接接触。 Wherein the spacer layer is cut off from direct contact with an electrically conductive insulating layer of intrinsic amorphous silicon semiconductor region.

根据本发明的目的,再提出一种薄膜晶体管的制造方法,包括步骤如下:提供基板,基板上有绝缘表面;形成非晶硅半导体层(Amorphous SemiconductorLayer)于绝缘表面上;形成导电层于非晶硅半导体层上,其中非晶硅半导体层与导电层形成接合层(Junction Layer);图案化导电层以形成沟道区间,并断开接合层使图案化的导电层与非晶硅半导体层之间形成对应的接合区;形成间隔层于接合区的侧壁;和形成绝缘层于沟道区间内。 The object of the present invention, further provides a method for manufacturing a thin film transistor, comprising the steps of: providing a substrate having an insulation surface on a substrate; forming an amorphous silicon semiconductor layer (Amorphous SemiconductorLayer) on an insulating surface; a conductive layer formed of amorphous a silicon semiconductor layer, wherein the amorphous silicon semiconductor layer and the conductive layer forming the bonding layer (Junction layer); patterned conductive layer to form a channel section, and disengaged layer patterned conductive layer and the amorphous silicon semiconductor layer formed between the corresponding engagement region; forming a sidewall spacer on the bonding region; and forming an insulating layer on the channel section. 其中,该间隔层系隔绝了该绝缘层与该接合区的直接接触。 Wherein the spacer layer is cut off line of the insulating layer and in direct contact with the bonding region.

为让本发明的上述目的、特征、和优点能更明显易懂,下文特举较佳实施例,并配合所附图式,作详细说明如下。 In order to make the above-described object of the present invention, features, and advantages can be more fully understood by referring give the preferred embodiments and accompanying figures, described in detail below.

附图说明 BRIEF DESCRIPTION

图1为一种传统薄膜晶体管结构的剖面示意图; Figure 1 is a schematic cross-sectional structure of a conventional thin film transistor;

图2A〜2E绘示依照本发明第一实施例的背沟道蚀刻(BCE)工艺的步骤; FIG 2A~2E shows steps in accordance with a back channel etch (BCE) a first embodiment of the present invention, the process embodiment;

图3为本发明第一实施例的背沟道蚀刻式薄膜晶体管(BCE Type TFT) Figure 3 is a back-channel-etched thin film transistor (BCE Type TFT) of the first embodiment of the present invention

的剖面示意图; The cross-sectional view;

图4显示以化学分析式电子光谱仪对依照本发明第一实施例所制得的间隔层进行表面分析的结果; Figure 4 shows the chemical analysis of electron spectroscopy for surface analysis results of the spacer layer in accordance with a first embodiment of prepared embodiment of the present invention;

图5A〜5D绘示依照本发明第二实施例的蚀刻停止式工艺的步骤; FIG 5A~5D depicts process steps in accordance with the formula stopping etching of the second embodiment of the present invention;

图6为本发明第二实施例的蚀刻停止式薄膜晶体管的剖面示意图; FIG 6 is etched a second embodiment of the present invention stops a schematic cross-sectional view of thin film transistor;

图7显示以化学分析式电子光谱仪对依照本发明笫二实施例所制得的间隔层进行表面分析的结果;及 Figure 7 shows the results of chemical analysis of electron spectroscopy surface analysis of the spacer layer in accordance with the second embodiment of the present invention, Zi prepared; and

图8为本发明的薄膜晶体管的电性特性曲线图。 FIG 8 is a graph showing the electrical characteristics of the thin film transistor of the invention.

图式标号说明 DESCRIPTION OF REFERENCE NUMERALS FIG formula

102、 202、 502:基板 102, 202, 502: substrate

104:栅极 104: gate

106:纟册极绝缘层 106: Volume Si gate insulating layer

108、 208、 508:非晶硅层(a-Si Layer) 110:奥姆接触层 108, 208, 508: amorphous silicon layer (a-Si Layer) 110: ohmic contact layer

112、 214:漏极 112, 214: drain

113、 216:源极 113, 216: a source

114、 218、 517:沟道区间116:保护层 114, 218, 517: the channel section 116: protective layer

204、 504:第一导电层206:第一绝缘层207、 507:绝缘表面210、 514: n+非晶硅层212、 516:第二导电层220、 512、 512a:氧化层224:笫二绝缘层505:氮氧化硅层(SiON》 506:氮化硅层(g-SiNJ 510:蚀刻停止层518:氮化珪层 204, 504: a first conductive layer 206: a first insulating layer 207, 507: insulating surface 210, 514: n + amorphous silicon layer 212, 516: second conductive layer 220, 512, 512a: oxide layer 224: second insulating Zi layer 505: a silicon oxynitride layer (SiON "506: silicon nitride layer (g-SiNJ 510: etch stop layer 518: nitride layer gui

具体实施方式 detailed description

本发明系在沟道内侧制作间隔层,以降低漏电流,增加组件的电于稳定性。 The present invention is made in the spacer layer inside the channel, to reduce leakage current and increase the stability of the electrical components. 以下系以背沟道蚀刻式薄膜晶体管的结构与工艺(Back-ChannelEtching (BCE) Type TFT Process),和蚀刻停止式薄膜晶体管结构与工艺(Etch Stop Type TFTProcess)为实施例作说明,然而这些实施例并不会对本发明所要保护的范围作限定。 The following lines to the back channel etch type thin film transistor structure and process (Back-ChannelEtching (BCE) Type TFT Process), and the etch stop thin film transistor structure and process (Etch Stop Type TFTProcess) as an example for illustrative embodiment, however, these embodiments Example does not have the scope of the claimed invention as defined.

第一实施例-背沟道蚀刻式薄膜晶体管的工艺与结构 First embodiment - a back channel etching process and the structure of the thin film transistor of formula

请参照图2A〜2E,其表示依照本发明第一实施例有背沟道蚀刻(BCE) 工艺的步骤。 Referring to FIG 2A~2E, which represents a first embodiment in accordance with the embodiment of the present invention have a back channel etch step (BCE) process. 首先,提供基板202,例如可透光的玻璃基板。 First, a substrate 202, such as a glass substrate may be transparent. 于基板202上形成图案化的第一导电层204,如第一金属层。 Forming a first conductive layer patterned on the substrate 202 to 204 as in the first metal layer. 接着,形成第一绝缘层206 于第一导电层204上方,以提供基板202的绝缘表面207,如图2A所示。 Next, formed over the first conductive layer 204 of the first insulating layer 206, the insulating substrate 202 to provide a surface 207, shown in Figure 2A. 该第一绝缘层206例如是可作为栅极绝缘层的氮化硅层(Silicon Nitride Layer),利用化学汽相沉积(Chemical Vapor Deposition, CVD)的方式沉积于第一导电层204上方。 The first insulating layer 206 may be, for example, a silicon nitride layer (Silicon Nitride Layer) of the gate insulating layer, by chemical vapor deposition (Chemical Vapor Deposition, CVD) is deposited above the first conductive layer 204.

然后,利用沉积、光刻、蚀刻等方式,于第一绝缘层206上方形成非晶珪层(Amorphous Silicon Layer,以下简称a-Si Layer)208和n+非晶珪层(1\+ a-SiLayer)210,如图2B所示。 Then, using deposition, photolithography, etching, etc., is formed over the first amorphous layer Gui insulating layer 206 (Amorphous Silicon Layer, hereinafter referred to as a-Si Layer) 208 and the n + amorphous Gui layer (1 \ + a-SiLayer ) 210, shown in Figure 2B. 其中,此非晶硅层由于未掺杂其它杂质,因此又称为本征非晶硅层(Intrinsic a-Si Layer)。 Wherein, the amorphous silicon layer due to other impurities are doped, also known as oriented amorphous silicon layer (Intrinsic a-Si Layer) sign.

接着,利用沉积、光刻、蚀刻等方式形成图案化的第二导电层(如第二金属层)212于本征非晶硅层208上方。 Next, deposition, photolithography, etching, etc. is formed a second patterned conductive layer (e.g., a second metal layer) 212 in the intrinsic amorphous silicon layer 208 above. 此第二导电层212可为铬、铝等金属,图案化后可分别形成薄膜晶体管中的漏极214与源极216,且两者之间以沟道区间(ChannelRegion)218隔开,如图2C所示。 This second conductive layer 212 may be a chromium, a metal such as aluminum, is patterned after the thin film transistor may be respectively formed in the drain 214 and source 216, and with the channel Qujian (ChannelRegion) spaced 218 therebetween, as shown in 2C. 其中,此沟道区间218 系形成暴露本征非晶硅层208的开口,使n+非晶硅层210断开而不致产生晶体管短路的现象。 Wherein, the channel section opening 218 is exposed is formed based intrinsic amorphous silicon layer 208 of the n + amorphous silicon layer 210 of the transistor turned off without creating a short circuit phenomenon. 而n+非晶硅层210和本征非晶硅层208之间则形成NI 接合区(NIJunction),如图中箭号所示。 And n + amorphous silicon layer is formed NI lands (NIJunction) between 210 and the intrinsic amorphous silicon layer 208, as shown in arrows in FIG.

接着,对沟道区间218进行处理以形成间隔层(Spacer Layer),例如是以含氧等离子体对沟道区间218进行处理,以形成氧化层(Oxide Layer)220(即作为前述的间隔层)于NI接合区的侧壁处,如图2D所示。 Next, the channel processing section 218 to form a spacer (Spacer Layer), for example, oxygen-containing plasma is processed on the channel section 218, to form an oxide layer (Oxide Layer) 220 (i.e., as the spacer layer) NI in the sidewall of the engagement area, shown in Figure 2D. 此含氧等离子体例如是灰化(Ashing)步骤中所使用的氧气等离子体(Oxygen Plasma),亦可使用臭氧等离子体(Ozone Plasma),及配合氟化碳(CF4)和氟化硫(SFe)等气体,亦或使用臭氧水(Ozone Water)或热氧化(Thermal Oxidation) 的方式形成。 This step, for example, oxygen-containing plasma ashing (ashing) using oxygen as a plasma (Oxygen Plasma), may also be used plasma ozone (Ozone Plasma), and with the carbon fluoride (CF4) and sulfur hexafluoride (SFe ) and other gases, or that the use of ozone water (ozone water) or a thermal oxide (thermal oxidation) are formed. 氧化层220的厚度约在10A〜500A范围之间,视实际操作条件(形成的方式、处理时间等)而定。 The thickness of oxide layer 220 is between about 10A~500A range, depending on the actual operating conditions (formed, the processing time, etc.) may be. 然后,再形成第二绝缘层224于第一绝缘层206的上方,以覆盖第二导电层212和填满沟道区间218,如图2E所示。 Then, a second insulating layer 224 is formed over the first insulating layer 206 to cover the second conductive layer 212 and fill channel segment 218, shown in Figure 2E. 其中,第二绝缘层224例如是氮化硅层(Silicon Nitride Layer, SiNx),利用化学汽相沉积(CVD)的方式沉积。 Wherein the second insulating layer 224, for example, a silicon nitride layer (Silicon Nitride Layer, SiNx), using a chemical vapor deposition (CVD) is deposited.

图3为本发明第一实施例的背沟道蚀刻式薄膜晶体管(BCE Type TFT) 的剖面示意图。 FIG 3 is a schematic cross-sectional view of the first embodiment, the back channel etched thin film transistor (BCE Type TFT) of the present invention. 基板202上方依序形成第一导电层204和第一绝缘层206, 其中,第一导电层204例如是金属铝,第一绝缘层206例如是氮化硅(SiHO。 之后于第一绝缘层206上方依序形成本征非晶硅层(a-Si Layer) 208、 n+非晶硅层(n+a-SiLayer)210、和图案化的第二导电层212。其中,n+非晶硅层210 和本征非晶硅层208之间形成NI接合区(NI Junction),如图中箭号所示。经过含氧等离子体处理后,于NI接合区的侧壁处形成氧化层(Oxide Layer)220 以作为间隔层。接着再以第二绝缘层(又称保护层)224,例如是氮化硅(SiNJ、 氧化硅(SiOJ、氮氧化硅(SiONJ或硅硅键为主的材料,覆盖第二导电层212 并填满沟道区间218。因此,依据此实施例,间隔层如氧化层220的存在系隔绝了含氮的第二绝缘层224与NI接合区的直接接触。 Sequentially over the substrate 202 and the first conductive layer 204 formed in the first insulating layer 206, wherein, for example, 204 is a first conductive layer of aluminum, a first insulating layer 206, for example, silicon nitride (SiHO. After the first insulating layer 206 sequentially forming a second conductive layer over the intrinsic amorphous silicon layer (a-Si layer) 208, n + amorphous silicon layer (n + a-SiLayer) 210, and the patterned 212. wherein, n + amorphous silicon layer 210 and the intrinsic amorphous silicon layer 208 is formed between the lands NI (NI Junction), as shown in the arrow. after an oxygen-containing plasma treatment, side walls joining the NI region forming an oxide layer (oxide layer) as the spacer layer 220 is then again with a second insulating layer (also called protective layer) 224, for example, silicon nitride (Sinj, silicon oxide (SiOJ, silicon oxynitride (SiONJ silicon bonds or silicon-based material, the first cover second conductive layer 212 and fills the channel section 218. Thus, according to this embodiment, the spacer layer is present as oxide-based layer 220 is cut off from direct contact with the bonding region of NI second insulating layer 224 containing nitrogen.

相关实验 Experiments

(A) 实验程序- (A) Experimental Procedures -

如图2A〜2E所示的步骤。 2A~2E step shown in FIG. 其中,第一绝缘层206和第二绝缘层224均为氮化硅。 Wherein the first insulating layer 206 and the second insulating layer 224 are silicon nitride. 在形成沟道区间218和暴露本征非晶硅层208的开口(使n+非晶硅层210断开)之后,进行含氧等离子体处理。 After forming the channel section opening 218 and the intrinsic amorphous silicon layer 208 is exposed (so that n + amorphous silicon layer 210 is disconnected), for oxygen-containing plasma process.

实验(l)系以含有氣气的等离子体对沟道区间218进行处理,处理时间约50秒。 Experiment (l) a plasma-based gas-containing gas in the channel processing section 218, the processing time is about 50 seconds.

实验(2)系以纯氧气等离子体(07)对沟道区间218进行处理,处理时间约20秒。 Experiment (2) in a pure oxygen-based plasma (07) of the channel processing section 218, the processing time is about 20 seconds.

(B) 实验结果- (B) Experimental Results -

显微镜镜检-根据透过式电子显微镜观察实验(1)和实验(2)的结果均显示,在NI接合区的侧壁处确有可区别的间隔层存在,厚度约为100-120A 之间。 Between the results of Experiment transmission electron microscopic observation (1) and test (2) are displayed in the sidewalls of the lands NI indeed exist distinguishable spacer layer, a thickness of approximately 100-120A - microscopic examination .

EDX定性分析-以能量分散光谱仪(Energy Dispersive X-raySpectrometry, EDX)对非晶硅层208、间隔层和氮化硅层224进行分析,其取样位置分别如图3中的A、 B、 C点所示。 EDX qualitative analysis - with an energy dispersive spectrometer (Energy Dispersive X-raySpectrometry, EDX) amorphous silicon layer 208, spacer layer 224 and the silicon nitride layer was analyzed, the 3 A, B, C are points which the sampling position in FIG. Fig. 表1列出实验(1)和实验(2)的EDX结果。 Table 1 Experiment (1) and experimental (2) of the EDX results.

表1 Table 1

A (逸自a-Si层208) B (选自层220) C (选自SiN层224) A (Yi from a-Si layer 208) B (selected layer 220) C (224 selected SiN layer)

实验(l) O/Cu:0.302 O/Cu:0.359 O/Cu:0.063 Experiment (l) O / Cu: 0.302 O / Cu: 0.359 O / Cu: 0.063

实验(2) O/Cu:0.159 O/Cu:0.217 O/Cu:0.014 Experiment (2) O / Cu: 0.159 O / Cu: 0.217 O / Cu: 0.014

EDX结果显示:实验(1)和实验(2)的B点,亦即间隔层220处,具有较高的氧含量(Oxide Rich),因此可证明此间隔层为氧化层220。 EDX results showed that: B Experiment point (1) and experimental (2), i.e., the spacer layer 220, has a high oxygen content (Oxide Rich), and therefore may prove to oxide spacer layer 220 here.

表面化学分析-取沉积有非晶硅层〖约1500 A)的基板,并以第一实施例的方式对非晶硅层的表面进行等离子体处理,处理后于非晶硅层上方形成薄层。 Surface chemical analysis - taking an amorphous silicon layer is deposited 〖about 1500 A) a substrate, and as to the first embodiment of the plasma treatment on the surface of the amorphous silicon layer, after processing the amorphous silicon layer is formed over the thin . 以化学分析式的电子光镨仪(Electron Spectroscopy for Chemical Analysis, ESCA)对此薄层表面进行分析。 Analysis of chemical formula of the electron beam instrument of praseodymium (Electron Spectroscopy for Chemical Analysis, ESCA) surface analysis of this thin layer. 其结果如图4所示。 The results are shown in Fig.

ESCA图错显示:此薄层所含的化合物具硅氧键结,且根据光电子束缚能信号峰和其位移,可判断此氧化态为二氧化硅(Si02)。 ESCA FIG error display: This compound has a thin layer of silicone contained in the bonded and optoelectronic binding energy peak and the displacement signals, can determine the oxidation states of silicon dioxide (Si02).

因此,根据上述相关实验及实验结果,可证明依照本发明第一实施例所制成的薄膜晶体管,其在NI接合区的侧壁处可形成含硅的氧化层(作为间隔层),而此氧化层可隔绝含氮的绝缘层(或保护层)与NI接合区的直接接触。 Thus, according to the relevant experiments and experimental results demonstrate thin film transistor may be made of a first embodiment according to the present invention, in which side walls NI engaging region can be formed of a silicon oxide layer (a spacer layer), and this can be isolated from the nitrogen-containing oxide insulating layer (or protective layer) is in direct contact with the NI engagement zone.

第二实施例-蚀刻停止式薄膜晶体管的工艺与结构 The etch stop thin film transistor structure and process - the second embodiment

请参照图5A〜5D,其绘示依照本发明第二实施例的蚀刻停止式(Etch Stop Type)工艺的步骤。 Referring to FIG step 5A~5D, which illustrates the process stops formula (Etch Stop Type) is etched in accordance with a second embodiment of the present invention. 首先,提供基板502,例如可透光的玻璃基板。 First, a substrate 502, such as a glass substrate may be transparent. 于基板502上形成图案化的第一导电层504,如由纯铝、或铝钕合金所形成的第一金属层。 Forming a first conductive layer patterned on the substrate 502504, as in the first metal layer is made of pure aluminum or an aluminum alloy formed by neodymium. 接着,形成绝缘层于第一导电层504上方,以提供基板502 的绝缘表面507。 Next, the insulating layer 507 is formed on the insulating surface above the first conductive layer 504, to provide a substrate 502. 其中,该绝缘层可包括:形成于第一导电层204上方的氮氧化硅层(SiON。505,和形成于氮氧化硅层505上方可作为栅极绝缘层的氮化硅层(Silicon Nitride Layer, g-SiNx)506,如图5A所示。可利用化学汽相沉积方式进行绝缘层的沉积。 Wherein, the insulating layer may include: forming a first conductive layer above the silicon oxynitride layer 204 (SiON.505, and is formed on a silicon oxynitride layer, silicon nitride layer 505 as before (Silicon Nitride Layer gate insulating layer 506, as shown in FIG, g-SiNx) 5A. insulating layer may be deposited using a chemical vapor deposition method.

然后,利用沉积、光刻、蚀刻等方式,于氮化硅层506上方形成非晶硅层(Amorphous Silicon Layer,以下简称a-Si Layer)508;接着,形成图案化的蚀刻停止层510,如图5B所示。 Then, using deposition, photolithography, etching, etc., to the silicon nitride layer 506 is formed over the amorphous silicon layer (Amorphous Silicon Layer, hereinafter referred to as a-Si Layer) 508; Next, a patterned etch stop 510, such as 5B. 其中,此非晶硅层508由于未掺杂其它杂质,因此又称为本征非晶硅层(Intrinsica-SiLayer)。 Wherein, the amorphous silicon layer 508 due to other impurities are doped, also known as oriented amorphous silicon layer (Intrinsica-SiLayer) sign. 而图案化的蚀刻停止层510例如是含氮的硅层(SiNxLayer)。 Patterned etch stop layer 510, for example, nitrogen-containing silicon layer (SiNxLayer).

接着形成间隔层,例如以臭氧等离子体(03Plasma)进行处理,使非晶硅层508的表面形成氧化层(OxideLayer)512(即为前述的间隔层),如图5C所示。 Spacer layer is then formed, for example, an ozone plasma (03Plasma) treated so that the surface of the amorphous silicon layer 508 forming an oxide layer (OxideLayer) 512 (that is, the spacer layer), shown in Figure 5C. 接着以氢气等离子体(H2Plasma)去除图5C中氧化层512对应于蚀刻停止层510上方的部分和非晶硅层508表面的部分,而剩下如图5D所示的蚀刻停止层510两侧的氧化层512a。 Followed by a hydrogen plasma (H2Plasma) removing the oxide layer 512 in FIG. 5C corresponding to the etch stop portion 510 and the upper portion 508 of the surface layer of the amorphous silicon layer, while the remaining etch stop 510 as shown in FIG. 5D both layers oxide layer 512a. 然后再沉积n+非晶硅层(n十a-Si Layer)514于蚀刻停止层510的上方并覆盖非晶硅层508的表面,如图5D 所示。 And then depositing a n + amorphous silicon layer (n ten a-Si Layer) 514 over the etch stop layer 510 and covers the surface of the amorphous silicon layer 508, shown in Figure 5D. 其中,利用氢气等离子体将蚀刻停止层510和非晶硅层表面的氧化层510去除可增进非晶硅层(a-SiLayer)508和11+非晶硅层(11+ a-Si Layer)514 之间的奥姆接触。 Wherein, with hydrogen plasma will etch stop layer 510 and the surface of the amorphous silicon oxide layer 510 can enhance the removal of the amorphous silicon layer (a-SiLayer) 508 and the amorphous silicon layer 11+ (11+ a-Si Layer) 514 between the ohmic contact.

另外,进行臭氧处理以形成间隔层之前,亦可4吏用氢氟酸(例如稀释后的氢氟酸、或是以氢氟酸与氟化铵所生成的緩冲溶液)进行前处理(Pre Clean),以清除硅晶圓表面自然生成的氧化层(Native Oxide)。 Further, before ozone treatment to form the spacer layer 4 may officials with hydrofluoric acid (e.g., diluted hydrofluoric acid, ammonium fluoride or hydrofluoric acid and the resulting buffer solution) pre-treated (Pre Clean), to remove the oxide layer (Native oxide) naturally occurring silicon wafer surface.

在n+非晶硅层514和非晶硅层508之间,是形成所谓的NI接合区(NI Junction)。 In the n + amorphous silicon layer 514 and the amorphous silicon layer 508 between, is a so-called lands NI (NI Junction). 由图5D中可知,经第二实施例所制成的TFT组件,其产生的间隔层(如氧化层512a)同样地可避免NI接合区和绝缘层(蚀刻停止层510)直接接触。 Seen from FIG. 5D, the TFT component is made of a second embodiment, the spacer layer (e.g. oxide layer 512a) can be avoided in the same manner generates NI junction region and an insulating layer (etch-stop layer 510) in direct contact.

在形成n+非晶硅层514后,可利用沉积、光刻、蚀刻等方式在上方形成图案化的第二导电层516,此第二导电层516例如是钼、铝等金属,图案化后可分别形成薄膜晶体管中的漏极与源极,且两者之间以沟道区间517 隔开。 After forming the n + amorphous silicon layer 514 may be utilized deposition, photolithography, etching, etc. The second conductive layer 516 is formed above the patterned, the second conductive layer 516, for example, after a metal pattern molybdenum, aluminum or the like may be are formed in the thin film transistor drain and source, and with a channel 517 spaced interval therebetween. 其中,此沟道区间517是使n+非晶硅层514断开,并形成暴露蚀刻停止层510的开口。 Wherein, the channel section 517 is to disconnect the n + amorphous silicon layer 514, and forming an opening exposing the etch stop layer 510. 然后,再形成绝缘层518,其材料如氮化硅(SiNx)、氧化硅(SiOx)、氮氧化硅(SiONJ或硅硅键为主的材料,以覆盖第二导电层516 和填满沟道区间517,如图6所示。 Then, an insulating layer 518, the material such as silicon nitride (an SiNx), silicon oxide (the SiOx), silicon oxynitride (SiONJ silicon bonds or silicon-based material to cover the second conductive layer 516 and fill channel section 517, as shown in FIG.

图6为本发明第二实施例的蚀刻停止式薄膜晶体管的剖面示意图。 FIG 6 is a schematic view of the etched cross section of a second embodiment of the thin film transistor of the invention is stopped. 基板502上方依序形成第一导电层504,和由氮氧化硅层(SiONx)505与氮化硅层506所组成的绝缘层。 502 are sequentially formed over the substrate a first conductive layer 504, and an insulating layer is formed of a silicon oxynitride layer (SiONx) 505 and the layer 506 consisting of silicon nitride. 之后于氮化硅层506上方依序形成本征非晶硅层(a-Si Layer)508和图案化的蚀刻停止层510。 After the silicon nitride layer 506 above the intrinsic amorphous silicon layer are sequentially formed (a-Si Layer) 508 and the patterned etch stop layer 510. 经过含氧等离子体和氢气等离子体处理后,于NI接合区的侧壁处形成氧化层512a以作为间隔层。 After oxygen-containing plasma and hydrogen plasma treatment, side walls in the bonding area of ​​the NI oxide layer is formed as the spacer layer 512a. 接着再形成图案化的n+非晶硅层514和第二导电层516,并以氮化硅层518覆盖第二导电层516并填满沟道区间517。 Followed by forming a patterned n + amorphous silicon layer 514 and the second conductive layer 516, and the silicon nitride layer 518 to cover the second conductive layer 516 and fills the channel section 517. 因此,依椐第二实施例,蚀刻停止式薄膜晶体管中,间隔层如氧化层512a的存在系隔绝了含氮的绝缘层(蚀刻停止层510)与NI接合区的直接接触。 Thus, according to the second embodiment As noted, the etch stop thin film transistor, the spacer layer, such as the presence of oxide-based layer 512a is cut off from the nitrogen-containing insulating layer (etch-stop layer 510) in direct contact with the NI engagement zone. 其中,氧化层512a的厚度约在10A〜500A范围之间,视实际操作条件(形成的方式、处理时间等)而定。 Wherein the thickness of the oxidized layer 512a is between about 10A~500A range, depending on the actual operating conditions (formed, the processing time, etc.) may be.

相关实验 Experiments

(A) 实验程序- (A) Experimental Procedures -

如图5A〜5D所示的步骤。 Step shown in FIG 5A~5D. 其中,在形成图案化的蚀刻停止层510后, 先以氢氟酸(浓度为0.14%~0.2%)与氟化铵(浓度为16.5%〜17.5%)所生成的緩沖溶液进行前处理,以清除非晶硅层508自然生成的氧化层,处理时间约27秒。 Wherein, after forming the patterned etch stop layer 510, first of hydrofluoric acid (concentration of 0.14% to 0.2%) and ammonium fluoride (16.5% ~17.5%) The resulting buffer solution is pretreated to Clear the amorphous silicon oxide layer 508 naturally occurring, the processing time of about 27 seconds. 再以臭氧水(OzoneWater)处理,处理时间约30秒(生成如图5C所示的氧化层512于非晶硅层508的表面),再经过氯气处理以形成间隔层于蚀刻停止层510的侧边(请对照图5D所示的氧化层512a)。 Ozone water again (OzoneWater) processing, the processing time is about 30 seconds (FIG. 5C generating an oxide layer 512 on the surface of the amorphous silicon layer 508), and then after chlorine treatment to form a side spacer layer 510 of the etch stop layer edge (see FIG oxidation control layer shown 5D 512a).

(B) 验结果- (B) Experimental results -

显微镜镜检-根据透过式电子显微镜观察结果显示,在NI接合区的侧壁处与蚀刻停止层510之间确有可区别的间隔层存在,厚度约为200A。 Microscopic examination - The transmission electron microscopy showed that, in the region of the side walls NI engagement with the etch stop layer can indeed exist differences between the spacer layer 510, a thickness of about 200A.

EDX定性分析-以能量分散光谱仪对n+非晶硅层514、间隔层、蚀刻停止层(氮化硅)510和非晶硅层508进行分析,其取样位置分别如图6中的D、 E、 F、 G点所示,其EDX结果如表2所示。 EDX qualitative analysis - with an energy dispersive spectrometer for the n + amorphous silicon layer 514, spacer layer, the etch stop layer (silicon nitride) 510 and the amorphous silicon layer 508 is analyzed in its sampling position 6 D are shown, E, F., as shown in point G, which EDX results shown in table 2.

表2 Table 2

<table>table see original document page 13</column></row> <table> <Table> table see original document page 13 </ column> </ row> <table>

EDX结果显示:取自间隔层中的E点,具有较高的氧舍量(Oxide Rich),因此可证明依照第二实施例所制成的组件,其间隔层确为氧化层512a。 EDX results showed: E point from the spacer layer, having a higher oxygen amount homes (Oxide Rich), and therefore may prove assembly made in accordance with the second embodiment, the oxide layer therebetween indeed compartment 512a.

表面化学分析-取沉积有非晶硅层f约3500 A)的基板,并以第二实施例的方式对非晶硅层的表面进行等离子体处理,处理后于非晶硅层上方形成薄层。 Surface chemical analysis - taking an amorphous silicon layer is deposited f about 3500 A) a substrate, and as to the second embodiment of the plasma treatment on the surface of the amorphous silicon layer, after processing the amorphous silicon layer is formed over the thin . 以化学分析式的电子光镨仪对此薄层表面进行分析。 Analysis of chemical analysis of this formula sheet surface of the electrophotographic light praseodymium instrument. 其结果如图7 所示。 The results are shown in Figure 7.

ESCA图镨显示:此薄膜所含的化合物具硅氧键结,且根据图7的光电子束縛能信号峰,可判断此氧化态为包括一氧化硅(SiO)、 二氧化硅(Si02) 和氮氧化硅(SION。。 ESCA FIG praseodymium show: This compound contained in the film having a silicon-oxygen bond, and the binding energy peak signal optoelectronic FIG. 7, this can be determined in oxidation state comprises a silicon oxide (of SiO), silicon dioxide (Si02) and nitrogen silicon oxide (SION ..

因此,根据上述相关实验及实验结果,可证明依照本发明第二实施例所制得的薄膜晶体管,其在NI接合区的侧壁处可形成氧化层以作为间隔层, 而此间隔层可隔绝含氮的绝缘层(蚀刻停止层)与NI接合区的直接接触。 Thus, according to the relevant experiments and experimental results, the thin film transistor can be demonstrated according to the second embodiment of the present invention is obtained, in which side walls joining region NI oxide layer may be formed as a spacer layer, the spacer can be isolated from here the nitrogen-containing insulating layer (etching stop layer) is in direct contact with the NI engagement zone.

组件电性分析- Electrical components analysis -

对依照本发明的第一实施例和第二实施例所形成的薄膜晶体管组件进行电性分析。 The thin film transistor according to the first assembly of the embodiment and the second embodiment of the present invention is formed of electrically analysis. 请参照图8,其为本发明的薄膜晶体管的电性特性曲线图。 Referring to FIG. 8, a graph showing the electrical characteristics of the thin film transistor according to present invention. 此电性曲线结果显示:具有间隔层(例如氧化层220、 512a)的存在,在结构上可隔绝含氮绝缘层(或保护层)与NI接合区的直接接触,在电性上亦可降低漏电流量。 This electrically profile results show: a spacer layer (e.g. oxide layer 220, 512a) is present, the structure can be isolated from direct contact with the nitrogen-containing insulating layer (or protective layer) and the bonding area of ​​the NI can also be reduced in electrically leakage flow. 其中,具有间隔层(以方块点所代表的曲线)比不具间隔层(以菱形点所代表的曲线)的组件其漏电流量约降低了10Q'5 。 Wherein a spacer layer (curve points represented by squares) than the component does not have the spacer layer (curve points represented by diamonds) which reduces the leakage flow rate of about 10Q'5.

综上所述,本发明的薄膜晶体管结构及其制造方法,形成间隔层(例如氧化层)以间隔含氮绝缘层与NI接合区,此间隔层的存在可降低漏电流量, 改善薄膜晶体管的组件电性。 In summary, a thin film transistor structure and method of the present invention, a spacer layer (e.g. oxide layer) at intervals of the nitrogen-containing insulating layer with NI bonding area, the presence here of the spacer can be reduced leakage flow, improve assembly of the thin film transistor electrical.

综上所述,虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明,对于本领域的技术人员来说,在不脱离本发明的精神和范围内, 当可作各种的更动与润饰,因此本发明的保护范围视所附的权利要求所限定的范围为准。 Although the present invention has been disclosed above by the preferred embodiments, they are not intended to limit the invention to those skilled in the art, without departing from the spirit and scope of the present invention, may be made when each modifications and variations thereof, thus depending on the scope of the invention defined by the claims appended scope of equivalents.

Claims (28)

  1. 1. 一种薄膜晶体管,包括:基板,其上形成绝缘表面;沟道区间,形成于该基板的该绝缘表面上方,且该沟道区间具有本征非晶硅半导体层;漏极与源极,位于该沟道区间的两侧,且该对漏极与源极和该本征非晶硅半导体层之间分别具有可导电的本征非晶硅半导体层;间隔层,形成于该可导电的本征非晶硅半导体层的侧壁处;和绝缘层,形成于该沟道区间内;其中,该间隔层隔绝了该绝缘层与该可导电的本征非晶硅半导体层的直接接触。 1. A thin film transistor comprising: a substrate on which is formed an insulating surface; a channel section formed on the upper surface of the insulating substrate and the channel section having an intrinsic amorphous silicon semiconductor layer; drain and source , located on both sides of the channel section, and between the drain and the source and the intrinsic amorphous silicon semiconductor layer each having an electrically conductive intrinsic amorphous silicon semiconductor layer; spacer layer, formed on the conductive the side walls of the intrinsic amorphous silicon semiconductor layer; and an insulating layer formed in the channel section; wherein the insulating spacer layer isolated from the conductive layer and the intrinsic amorphous silicon semiconductor layer is in direct contact .
  2. 2. 如权利要求1所述的薄膜晶体管,其中该间隔层的厚度在10A〜500A 范围之间。 The thickness of the thin film transistor as claimed in claim 1, wherein the spacer layer in a range between 10A~500A.
  3. 3. 如权利要求1所述的薄膜晶体管,其中该间隔层为氧化层,该绝缘层为氮化硅层。 The thin film transistor according to claim 1, wherein the spacer layer is an oxide layer, the insulating layer is a silicon nitride layer.
  4. 4. 如权利要求1所述的薄膜晶体管,其中,该可导电的本征非晶硅半导体层系为n+型的本征非晶硅半导体层,且与该沟道区间的该本征非晶硅半导体层系形成NI接合。 Is the intrinsic amorphous silicon n + -type semiconductor layer and the intrinsic amorphous section with the channel of the thin film transistor as claimed in claim 1, wherein the electrically conductive layer of intrinsic amorphous silicon-based semiconductor a silicon semiconductor layer is formed NI engagement.
  5. 5. 如权利要求1所述的薄膜晶体管,其中该基板上包括: 第一金属层,形成于该基板上;和氮化硅层,形成于该第一金属层上方并覆盖该第一金属层,以提供该基板的该绝缘表面。 The thin film transistor according to claim 1, wherein the upper substrate comprises: a first metal layer formed on the substrate; and a silicon nitride layer, is formed on the first metal layer over the first metal layer and covering the to provide the insulating surface of the substrate.
  6. 6. 如权利要求1所述的薄膜晶体管,其中该间隔层系延伸至该沟道区间的该本征非晶硅半导体层的上方,以隔绝该本征非晶硅半导体层与该绝缘层的直接接触。 6. The thin film transistor according to claim 1, wherein the spacer layer extends to the line above the intrinsic amorphous silicon semiconductor layer in the channel section, to isolate the intrinsic amorphous silicon semiconductor layer and the insulating layer direct contact.
  7. 7. 如权利要求1所述的薄膜晶体管,其中该绝缘层为钝化层,系形成于该沟道区间内并覆盖该漏极与该源极。 The thin film transistor according to claim 1, wherein the insulating layer is a passivation layer formed in the channel section and covering the source electrode and the drain electrode.
  8. 8. 如权利要求1所述的薄膜晶体管,其中该绝缘层为停止层,系形成于该沟道区间内。 The thin film transistor as claimed in claim 1, wherein the insulating layer is a stop layer formed in the channel section.
  9. 9. 如权利要求8所述的薄膜晶体管,进一步具有钝化层,系覆盖该停止层、该漏纟及与该源纟及。 9. The thin film transistor according to claim 8, further having a passivation layer covering the stop-based layer, the drain and the source of Si and Si.
  10. 10. 如权利要求9所述的薄膜晶体管,其还包括保护层,该保护层系以氮化硅、氧化硅、氮氧化硅或硅硅一睫为主作为材料。 10. The thin film transistor according to claim 9, further comprising a protective layer, the protective layer is silicon nitride-based, silicon oxide, silicon oxynitride, or silicon as the silicon-based material eyelashes.
  11. 11. 一种薄膜晶体管的制造方法,包括步骤: 提供基板,该基板上有绝缘表面;形成非晶硅半导体层于该绝缘表面上;形成导电层于该非晶硅半导体层上,其中该非晶硅半导体层与该导电层形成接合层;图案化该导电层以形成沟道区间,并断开该接合层使图案化的该导电层与该非晶硅半导体层之间形成对应的接合区; 形成间隔层于该接合区的侧壁;和形成绝缘层于该沟道区间内;其中,该间隔层系隔绝了该绝缘层与该接合区的直接接触。 11. A method for manufacturing a thin film transistor, comprising the steps of: providing a substrate with an insulating surface of the substrate; forming an amorphous silicon semiconductor layer on the insulating surface; forming a conductive layer on the amorphous silicon semiconductor layer, wherein the non- crystalline silicon semiconductor layer is formed of the bonding layer and the conductive layer; patterning the conductive layer to form a channel section, and disconnect the bonding layer is formed corresponding to the bonding area between the conductive layer and the amorphous silicon semiconductor layer is patterned ; forming a spacer layer on the sidewalls of the bonding region; and forming the insulating layer in the channel section; wherein the spacer layer is cut off line of the insulating layer and in direct contact with the bonding region.
  12. 12. 如权利要求11所述的制造方法,其中该间隔层的厚度在10A〜500A 范围之间。 12. The thickness of the manufacturing method of claim 11, wherein the spacer layer is in the range between 10A~500A.
  13. 13. 如权利要求11所述的制造方法,其中该间隔层为氧化层,该绝缘层为氮化硅层。 13. The manufacturing method of claim 11, wherein the spacer layer is an oxide layer, the insulating layer is a silicon nitride layer.
  14. 14. 如权利要求13所述的制造方法,其形成该氧化层的方法系选自等离子体处理、等离子体沉积、热氧化或使用臭氧的方式形成。 14. The manufacturing method according to claim 13, which is formed of the oxide layer is selected from plasma treatment, plasma deposition, forming a thermal oxidation or ozone manner.
  15. 15. 如权利要求11所述的制造方法,进一步包括步骤: 形成第一金属层于该基板上;和形成氮化硅层于该第一金属层上方并覆盖该第一金属层,以提供该基板的该绝缘表面。 The manufacturing method of claim 11, further comprising the step of: forming a first metal layer on the substrate; and forming a silicon nitride layer over the first metal layer and covering the first metal layer to provide the the insulating surface of the substrate.
  16. 16. —种薄膜晶体管的制造方法,至少包括步骤: 提供基板,该基板上有绝缘表面;形成本征非晶硅层于该绝缘表面上;形成导电层于该非晶硅层上,其中该非晶硅层与该导电层系形成n+非晶硅接合层;蚀刻该导电层以形成沟道区间,并断开该n+非晶硅接合层,其中图案化的该导电层与该非晶硅层之间形成NI接合区;对该沟道区间进行处理,以形成氧化层于该NI接合区的侧壁;和形成含氮的绝缘层于该沟道区间内;其中,该氧化层系隔绝了该含氮的绝缘层与该NI接合区的直接接触。 16. - Method for manufacturing thin-film transistor, comprising at least the steps of: providing a substrate with an insulating surface of the substrate; forming an intrinsic amorphous silicon layer on the insulating surface; forming a conductive layer on the amorphous silicon layer, wherein the forming an amorphous silicon layer and the conductive layer joining line n + amorphous silicon layer; etching the conductive layer to form a channel section, the n + amorphous silicon and disconnect the bonding layer, wherein the patterned conductive layer and the amorphous silicon NI bonding area between the layers is formed; processing the channel section, to form a side wall oxide layer on the bonding area of ​​the NI; nitrogen-containing insulating layer is formed within the channel interval; wherein, the oxide-based insulating layer direct contact with the nitrogen-containing region of the insulating layer and the NI engagement.
  17. 17. 如权利要求16所述的制造方法,进一步包括步骤: 形成第一金属层于该基板上;和形成氮化硅层于该第一金属层上方并覆盖该第一金属层,以提供该基^反的该绝纟彖表面。 17. The method according to claim 16, further comprising the step of: forming a first metal layer on the substrate; and forming a silicon nitride layer over the first metal layer and covering the first metal layer to provide the the absolute yl ^ Si Tuan opposite surface.
  18. 18. —种薄膜晶体管的制造方法,至少包括步骤: 提供基板,该基板上有栅极; 形成绝缘层于该基板上并覆盖该栅极; 形成本征非晶硅层于该绝缘层上;形成含氮停止层于该本征非晶硅层上,且对应于该栅极的上方; 对该含氮停止层进行处理,以形成氧化层覆盖该含氮停止层; 形成n+非晶硅层于该本征非晶硅层的上方,且该n+非晶硅层覆盖部分该含氮停止层的表面,并与该含氮停止层的侧壁以该氧化层阻隔;及形成导电层于该n+非晶硅层上方。 18. - Method for manufacturing thin-film transistor, comprising at least the steps of: providing a substrate, with a gate electrode on the substrate; forming an insulating layer on the substrate and covering the gate electrode; intrinsic amorphous silicon layer is formed on the insulating layer; stop forming a nitrogen-containing layer on the intrinsic amorphous silicon layer, and corresponds to the top of the gate; stop processing the nitrogen-containing layer to form the nitrogen-containing oxide layer overlying stop layer; forming an n + amorphous silicon layer above the intrinsic amorphous silicon layer and the n + amorphous silicon layer covers the surface portion of the nitrogen-stop layer, and the sidewall oxide layer to the barrier layer and the nitrogen-containing stopped; and forming a conductive layer on the n + amorphous silicon layer over.
  19. 19. 如权利要求18所述的制造方法,其中系以含氧等离子体、臭氧水、 或臭氧等离子体与含氟的液体的混合物对该含氮停止层进行处理,以形成该氧化层。 19. The method according to claim 18, wherein the system to oxygen-containing plasma, ozone water, ozone, or plasma mixture of liquid and the nitrogen-containing fluorine stop layer is treated to form the oxide layer.
  20. 20. —种薄膜晶体管,包括: 基板,该基板上有绝缘表面; 本征非晶硅层,形成于该绝缘表面上; n+非晶硅接合层,位于该本征非晶硅层上;漏极与源极,位于该n+非晶硅接合层上方,且以沟道区间相隔,且该沟道区间系使该n+非晶硅接合层形成缺口;氧化层,形成于该n+非晶硅接合层的侧壁; 绝^彖层,形成于该沟道区间内,其中,该氧化层系隔绝该绝缘层与该n+非晶硅接合层的直接接触。 20. - thin-film transistor comprising: a substrate having an insulation surface on the substrate; intrinsic amorphous silicon layer formed on the insulating surface; n + amorphous silicon bonded layer on the intrinsic amorphous silicon layer; drain and the source electrode, located above the n + amorphous silicon layer is bonded, and at intervals separated by a channel, and the channel section so that the n + amorphous silicon-based bonding layer formed notches; oxide layer is formed on the n + amorphous silicon bonded sidewall layer; ^ hog insulating layer formed in the channel section, wherein the oxide-based insulating layer is in direct contact with the insulating layer and the n + amorphous silicon layer is bonded.
  21. 21. 如权利要求20所述的薄膜晶体管,其中该基板上包括: 第一金属层,形成于该基板上;和氮化硅层,形成于该第一金属层上方并覆盖该第一金属层,以提供该基板的该绝缘表面。 21. The thin film transistor according to claim 20, wherein the upper substrate comprises: a first metal layer formed on the substrate; and a silicon nitride layer, is formed over the first metal layer and covering the first metal layer to provide the insulating surface of the substrate.
  22. 22. 如权利要求20所述的薄膜晶体管,其中该氧化层为二氧化硅层。 22. The thin film transistor according to claim 20, wherein the oxide layer is a silicon dioxide layer.
  23. 23. 如权利要求20所述的薄膜晶体管,其中该绝缘层系以氮化硅、氧化硅、氮氧化硅或硅硅键为主作为材料。 23. The thin film transistor according to claim 20, wherein the insulating layer is silicon nitride-based, silicon oxide, silicon oxynitride, or silicon as a main material silicon bonds.
  24. 24. —种薄膜晶体管,包括:基板,该基板上有栅极;绝缘层,形成于该基板上并覆盖该栅极; 本征非晶硅层,形成于该绝缘层上;含氮停止层,形成于该本征非晶硅层上,且对应于该栅极的上方;n+非晶硅层,形成于该本征非晶硅层的上方,且该n+非晶硅层覆盖该含氮停止层的部分表面;氧化层,形成于该含氮停止层与该n+非晶硅层之间,以隔绝该含氮停止层与n+非晶硅层和本征非晶硅层之间形成的NI接合区的直接接触;和导电层,形成于该n+非晶硅层的上方,使一部分该含氮停止层的表面棵露。 24. - thin-film transistor comprising: a substrate, with a gate on the substrate; an insulating layer formed on the substrate and covering the gate electrode; intrinsic amorphous silicon layer formed on the insulating layer; nitrogen-stop layer formed on the intrinsic amorphous silicon layer, and corresponds to the top of the gate; n + amorphous silicon layer is formed over the intrinsic amorphous silicon layer and the n + amorphous silicon layer overlying the nitrogen-containing portion of the surface of the stop layer; oxide layer formed on the nitrogen-containing stop layer between the n + amorphous silicon layer, to insulate the nitrogen-containing stop layer and the n + amorphous silicon layer and the intrinsic amorphous silicon layer is formed between the NI direct engaging contact region; and a conductive layer formed above the n + amorphous silicon layer, a portion of the exposed surface of the nitrogen-containing trees stop layer.
  25. 25. 如权利要求24所述的薄膜晶体管,其中该绝缘层包括: 氮氧硅层,形成于基板上;和氮化硅层,形成于该氮氧硅层之上。 And a silicon nitride layer formed over the silicon oxynitride layer; a silicon oxynitride layer, formed on the substrate: 25. The thin film transistor according to claim 24, wherein the insulating layer comprises a.
  26. 26. 如权利要求24所述的薄膜晶体管,进一步包括第二绝缘层,系形成于该导电层的上方,并覆盖该含氮停止层的该棵露表面与该导电层。 26. The thin film transistor according to claim 24, further comprising a second insulating layer formed above the conductive layer, and covering the exposed surface of the nitrogen-containing trees stop layer and the conductive layer.
  27. 27. 如权利要求26所述的薄膜晶体管,其中该第二绝缘层系以氮化硅、 氧化硅、氮氧化硅或硅硅键为主作为材料。 27. The thin film transistor according to claim 26, wherein the second insulating layer is silicon nitride-based, silicon oxide, silicon oxynitride, or silicon-silicon bonds as the main material.
  28. 28. 如权利要求24所述的薄膜晶体管,其中该氧化层系为由一氧化硅、 二氧化硅和氮氧化硅所组成的群组。 28. The thin film transistor according to claim 24, silicon dioxide and silicon oxynitride group consisting claim, wherein the oxide layer is a silicon oxide-based grounds.
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US5811325A (en) 1996-12-31 1998-09-22 Industrial Technology Research Institute Method of making a polysilicon carbon source/drain heterojunction thin-film transistor
CN1275813A (en) 1993-03-12 2000-12-06 株式会社半导体能源研究所 Transistor and making method thereof

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CN1275813A (en) 1993-03-12 2000-12-06 株式会社半导体能源研究所 Transistor and making method thereof
US5811325A (en) 1996-12-31 1998-09-22 Industrial Technology Research Institute Method of making a polysilicon carbon source/drain heterojunction thin-film transistor

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