CN100498730C - Computer redundant system - Google Patents

Computer redundant system Download PDF

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CN100498730C
CN100498730C CN 200710165942 CN200710165942A CN100498730C CN 100498730 C CN100498730 C CN 100498730C CN 200710165942 CN200710165942 CN 200710165942 CN 200710165942 A CN200710165942 A CN 200710165942A CN 100498730 C CN100498730 C CN 100498730C
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cpu
board
peripheral
central processing
bus transceiver
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CN101149695A (en
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 周
车惠军
臻 黄
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北京全路通信信号研究设计院
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Abstract

本发明公开了一种计算机冗余系统,涉及计算机技术领域,包括两个中央处理板、至少一个外设板,每个中央处理板上安装有两个CPU,每个外设板上安装有两个CPU,所述中央处理板的CPU、所述外设板的CPU均连接有各自的总线收发器;所述中央处理板的CPU与所述外设板相应的CPU通过各自的总线收发器一一连接,构成通信线路,所述不同中央处理板的CPU与所述外设板的同一CPU之间的两条通信线路构成冗余通信线路。 The present invention discloses a redundant computer system, relates to the field of computer technology, including two central processing board, at least one peripheral boards, each board is equipped with two central processing the CPU, each peripheral board mounted with two a CPU, the CPU of the central processing board, the peripheral board is connected with a respective CPU bus transceiver; said central processing corresponding CPU board CPU and said peripheral board via a respective bus transceiver a connection forming the communication line, the communication line between the two different CPU boards central processing CPU and said peripheral plate constituting the redundant communication path same. 当一个中央处理板出现故障时,外设板依然可以继续进行数据交互并实现其自身功能。 When a central processing board failure, peripheral boards can still continue to exchange data and achieve its own function.

Description

一种计算机冗余系统 A computer system redundancy

技术领域 FIELD

本发明涉及计算机冗余技术领域,特别是指一种计算机冗余系统。 The present invention relates to computer technology field redundancy, more particularly to a redundant computer system.

背景技术 Background technique

随着计算机技术的发展,在工业控制、生产、生活、轨道交通自动化控制等各个领域都有较大的应用,特别是在轨道交通自动化控制中,应用的更为广泛。 With the development of computer technology, have greater application in all areas of industrial control, production and living, rail automation and control, especially in rail traffic automation control, applied more widely.

在轨道交通自动化控制中,通常会采用高可靠或故障-安全计算的通用计算机,这种计算机普遍采用冗余的系统架构实现。 In rail traffic automation control, usually with high reliability or failure - general-purpose computer secure computing, which computers use a redundant system architecture implementation. 在中央处理板与外设板之间,需要设置高可靠或故障-安全的冗余总线,传统的并行总线使用引脚过多,进行冗余设计非常困难,且控制协议复杂。 Between the central processing board and peripheral boards necessary to provide highly reliable or fail - safe redundant bus, parallel bus excessive use conventional pins, redundant design very difficult and complicated control protocol.

另外,由于高可靠或故障-安全计算的通用计算机采用的不是点对点架构,在扩充外设板时会受到总线性能的限制。 Further, due to high reliability or failure - is not a point secure computing architecture general-purpose computer employed in the peripheral expansion board when bus performance is limited. 每增加一个外设板, 各个外设板的性能就会随之下降,且电磁兼容性差。 Each additional peripheral boards, each peripheral board performance will decline, and the electromagnetic compatibility is poor. 由于数据线为双向,难以实现电气隔离。 Since the data line is bidirectional, it is difficult to achieve electrical isolation.

传统的串行背板总线虽然也能实现冗余,但多偏向于性能较高的电信应用,而并不适合高可靠或故障-安全计算机的应用。 While conventional serial backplane bus can be redundant, but more biased in favor of high performance telecom applications, and is not suitable for high reliability or failure - computer security application.

由于上述串行背板总线具有实现的局限性;高可靠或故障-安全计算的通用计算机,其冗余设计复杂。 Due to the above limitations serial backplane bus implemented; highly reliable or fail - safe computing a general purpose computer, complex redundant design. 这两种计算机冗余技术均不适合轨道交通自动化所要求的设计筒单、易推广通用的技术要求。 Design single-cylinder two redundant computers are not suitable for rail transit automation technology requirements, easy to promote common technical requirements.

发明内容 SUMMARY

有鉴于此,本发明在于提供一种计算机冗余的系统,以解决现有的计算机冗余技术设计复杂、具有局限性的问题。 Accordingly, the present invention is to provide a redundant computer system, in order to solve complex computer redundancy conventional design limitations problems.

为解决上述问题,本发明提供一种计算机冗余系统,包括:两个 To solve the above problems, the present invention provides a redundant computer system, comprising: two

3中央处理板、至少一个外设板,每个中央处理板上安装有两个CPU, 3 the central processing board, at least one peripheral plate, each have two central processing board is mounted the CPU,

每个外设板上安装有两个CPU,所述中央处理板的CPU 、所述外i殳板的CPU均连接有各自的总线收发器;所述中央处理板的CPU与戶斤述外设板相应的CPU通过各自的总线收发器——连接,构成通信线^各,所述不同中央处理板的CPU与所述外设板的同一CPU之间的两条通信线路构成冗余通信线路。 Each peripheral board mounted with two CPU, the CPU of the central processing board, the outer plate Shu i are connected to a respective CPU bus transceiver; CPU and said central processing household kg of said peripheral plate corresponding CPU board via a respective bus transceiver - constituted by connecting two communication lines ^ each communication line between the CPU, the central processing board different CPU and said peripheral plate constituting the redundant communication path same.

优选的,所述总线收发器为单路总线收发器。 Preferably, the bus transceiver is a single bus transceiver.

优选的,所述中央处理板的每个CPU连接单路总线收发器的个数与所述外设板的个数相同;所述外设板的每个CPU连接两个单路总线收发器。 Preferably, the same number of the central processing board is connected to each single CPU bus transceiver and the number of said peripheral plate; each CPU board connecting said peripheral bus two-way transceiver.

优选的,所述中央处理板上总线收发器与所述外设板上的总线收发器一一连接。 Preferably, the central processing board bus transceiver and the bus transceiver connected to said peripheral board one by one.

优选的,所述总线收发器为多路总线收发器。 Preferably, said bus is a multiplexed bus transceiver transceiver.

优选的,所述中央处理板上的每个CPU连接唯——个多路总线收发器,所述外设板上的每个CPU连接唯——个多路总线收发器。 Preferably, each CPU board is connected to said central processing only - one multiplexed bus transceiver, the peripheral board connected to each CPU-only - of the multiplexed bus transceiver.

优选的,所述中央处理板上的多路总线收发器与各个外设板上多路总线收发器之间——连接。 Preferably, the central processing board transceiver multiplexed bus between the respective peripheral bus transceiver board multiplexer and - connection.

优选的,所述外设板的个数为偶数,且每对外设板之间互为冗余。 Preferably, the number of peripheral plates is even, and between each pair of mutually redundant peripheral board. 本发明实施例中的计算机冗余系统,两个中央处理板上的CPU与外设板上的同一CPU通过总线收发器连接,形成的双重的通信通道且互为冗余的。 A redundant computer system in the embodiment of the present invention, the same CPU CPU board and peripheral board of two central processing connected via a bus transceiver, a communication passage formed in the double and mutually redundant. 当一个中央处理板的CPU与外设^1的CPU之间数据交互出现故障时,另一个中央处理板的CPU与该外设板的CPU还可进行数 When the data exchange between the CPU and peripherals fails a central processing board of the CPU ^ 1, the central processing other CPU the CPU of the plate and also for the number of peripheral plates

据交互。 According to interact. 通过上述形成的冗余系统,系统的稳定性、可靠度有较大提高,如果一个中央处理板出现故障出现问题时,外设板依然可以继续进行数据交互并实现其自身功能。 By stability of a redundant system formed as described above, system reliability has improved greatly, if a central processing board failure problems, peripheral boards can still continue to exchange data and achieve its own function.

附图说明 BRIEF DESCRIPTION

图1是采用单路总线收发器实施例的系统结构图; 图2是采用多路总线收发器实施例的系统结构图。 FIG 1 is a single bus transceiver system configuration view of an embodiment; FIG. 2 is a multi-way bus transceiver system configuration diagram of the embodiment. 具体实施方式 Detailed ways

为清楚说明本发明的系统,下面给出优选实施例并结合附图详细说明。 To clearly illustrate the system according to the present invention, the following preferred embodiments are given and described in detail in conjunction with the accompanying drawings.

在该实施例中,每个中央处理板上具有两个CPU,每个CPU均 In this embodiment, each central processing board having two CPU, each CPU average

连接串行总线,并通过串行总线上的总线收发器与外设板上的总线收发器相连接。 Connecting the serial bus, and is connected to the bus via bus transceiver on-board transceiver serial peripheral bus. 从而实现中央处理板与外设板上的实时通信。 Enabling real-time communication CPU board and peripheral board. 中央处理板与外设板连接时,每个中央处理板上的总线收发器均与各个外设板上相对应的总线收发器连接,从而实现冗余控制。 The central processing board is connected to the peripheral boards, bus transceivers each central processing board are connected to the respective corresponding peripheral board bus transceiver, in order to achieve redundancy control.

参见图1,图1是本发明采用单路总线收发器实施例的系统结构 Referring to FIG. 1, FIG. 1 is a system configuration of the present invention employs an embodiment of the single bus transceiver

图,中央处理板A上具有CPUA1、 CPUA2两个处理器。 Fig having CPUA1, CPUA2 two processors on the central processing board A. 其中,CPUA1 与串行总线相连接,并与总线上的总线收发器All、总线收发器A12、 总线收发器A13相连接;CPUA2与串行总线相连接,并与总线上的总线收发器A21、总线收发器A22、总线收发器A23相连接。 Wherein, CPUA1 connected to the serial bus, and the bus transceiver All on the bus, a bus transceiver A12, A13 connected to the bus transceiver; CPUa2 is connected to the serial bus, and the bus transceiver on a bus A21, bus transceiver A22, A23 bus transceiver is connected.

中央处理板B上具有CPUB1、 CPUB2两个处理器。 Having CPUB1, CPUB2 two processors on the central processing board B. 其中,CPUB1 与串行总线相连接,并与总线上的总线收发器Bll、总线收发器B12、 总线收发器B13相连接;CPUB2与串行总线相连接,并与总线上的总线收发器B21、总线收发器B22、总线收发器B23相连接。 Wherein, the CPU B1 is connected to the serial bus, and the bus transceiver Bll on the bus, bus transceiver B12, B13 is connected to bus transceiver; CPUB2 is connected to the serial bus, and the bus transceiver on the bus B21, bus transceiver B22, B23 is connected to bus transceiver.

中央处理板A、中央处理板B分别连接外设板,外设板的数量可以是一个,也可以是多个,在该实施例中,连接三个外设板,分别为外设板C、外设板D、外设板E。 The central processing plates A, B are respectively connected to the central processing board peripheral boards, the number of peripheral plates may be one, or may be a plurality, in this embodiment, three peripheral plates connected, respectively, peripheral boards C, peripheral boards D, E. peripheral plate 在每个外设板上分别具有两个处理器、四个总线收发器。 It has two processors, four on each peripheral bus transceiver board.

以外设板C为例,具有CPUC1、 CPUC2,总线收发器Cll、总线收发器C12、总线收发器C21、总线收发器C22。 C, for example at Peripheral plate having CPUC1, CPUC2, Cll bus transceiver, a bus transceiver C12, C21 bus transceiver, a bus transceiver C22. CPUC1连接总线收发器Cll、总线收发器C21, CPUC2连接总线收发器C12、总线收发器C22。 CPUC1 connection bus transceiver Cll, bus transceiver C21, CPUC2 bus transceiver connected C12, bus transceiver C22.

外设板与中央处理板之间通过总线收发器连接,总线收发器All 连接总线收发器Cll,总线收发器A21连接总线收发器C12;总线收发器Bll连接总线收发器C21,总线收发器B21连接总线收发器C22。 Between the central processing board and the peripheral boards connected by a bus transceiver, a bus transceiver is connected All Cll bus transceiver, a bus transceiver is connected to bus transceiver a C12 A21; bus transceiver connected to bus transceiver C21 Bll, B21 connecting bus transceiver bus transceiver C22.

5通过上述的CPU与总线收发器之间的连接方式,CPUA1 、 CPUC1 之间形成一路通信,CPUB1、 CPUC1之间形成一路通信,这两路通信互为冗余;CPUA2、 CPUC2之间形成一路通信,CPUB2、 CPUC2之间形成一路通信,这两路通信互为冗余。 5 by the connection between the CPU and the bus transceiver, forming a communication between the way the way communication, CPUB1, CPUC1 between CPUA1, CPUC1, two mutually redundant communication path; way communication is formed between CPUA2, CPUC2 and all the way communication between, CPUB2, CPUC2, two mutually redundant communication path.

同理,CPUA1、 CPUD1之间形成一路通信,CPUB1、 CPUD1之间形成一路通信,这两路通信互为冗余;CPUA2、 CPUD2之间形成一路通信,CPUB2、 CPUD2之间形成一路通信,这两路通信互为冗余。 Similarly, formed between CPUA1, CPUD1 way communication, form one communication between CPUB1, CPUD1, two mutually redundant communication path; way communication is formed between CPUA2, CPUD2, form one communication between CPUB2, CPUD2, two Road communication mutually redundant. CPUA1、 CPUE1之间形成一路通信,CPUB1、 CPUE1之间形成一路通信,这两路通信互为冗余;CPUA2、 CPUE2之间形成一路通信, CPUB2、 CPUE2之间形成一路通信,这两路通信互为冗余。 CPUA1 formed between CPUE1 way communication, form one communication between CPUB1, CPUE1, two mutually redundant communication path; way communication is formed between CPUA2, CPUE2, form one communication between CPUB2, CPUE2, two way communication interoperability redundant.

通过上述的冗余设计,当系统在工作过程中,两个中央处理板的总线收发器与外设板上的总线收发器之间的通信线路形成冗佘。 By the above-described redundancy when the system is in operation, the communication line between the bus transceiver bus transceiver two central processing board is formed with a peripheral board the redundancy. 由于外设板上的每个总线收发器均与两个中央处理板上的总线收发器进行数据交互,当一个中央处理板出现故障,不能通过总线收发器与外设板上的总线收发器进行数据交互时,外设板上的总线收发器会与另外一个中央处理板上的总线收发器进行数据交互。 Since each bus transceiver boards are peripheral exchanging data with the CPU bus transceiver two boards, a CPU board when a fault occurs, not through the bus transceiver and the bus transceiver boards in peripheral when the data exchange, a peripheral bus transceiver board may further exchange data with a central processing board bus transceiver.

以外设板C为例,CPUA1、 CPUC1之间通过总线收发器All、 总线收发器Cll进行数据交互,当CPUA1或CPU Cl或总线收发器All或Cll出现故障不能继续进行通信时,CPUC1、 CPUB1之间可通过总线收发器C21、总线收发器Bll之间进行数据交互。 C, for example at Peripheral plate, between CPUA1, CPUC1 All through the bus transceiver, Cll bus transceiver to exchange data, or when the CPU Cl or CPUA1 bus transceiver Cll All or failure can not continue communication, CPUC1, CPUB1 of Room can exchange data between the bus transceiver through C21, bus transceiver Bll. 另外,CPUC1、 CPUC2之间也是互为冗余,CPUC1出现故障时,CPUC2还可以维持外设板C的正常功能。 Further, between CPUC1, CPUC2 are mutually redundant, when a failure occurs CPUC1, CPUC2 may also maintain the normal function of the peripheral plate C.

通过上述形成的冗余系统,系统的稳定性、可靠度有较大提高, 如果一个中央处理板上的一个CPU出现问题时,外设板依然可以继续 By stability of a redundant system formed as described above, system reliability has improved greatly, if a CPU of the central processing board is a problem, can still continue peripheral board

进行数据交互。 Data exchange.

上述的系统实施例中,总线收发器均是采用的单路总线收发器, 当然,还可采用多路总线收发器。 Single bus transceiver embodiment, bus transceivers are used in the above-described embodiment of the system, of course, also be employed multiplexed bus transceiver. 采用多路总线收发器的系统实施例 Using multiplexed bus transceiver system according to Example

可参见图2,图2是采用多路总线收发器实施例的系统结构图。 See FIG. 2, FIG. 2 is a multi-way bus transceiver system configuration diagram of the embodiment. 在该实施例中,所采用的总线收发器为多路总线收发器,下面结合图2详细说明该实施例。 In this embodiment, employed is a multi-way bus transceiver bus transceiver, described in detail below in conjunction with the FIG. 2 embodiment.

中央处理板A上具有总线收发器AZ1、总线收发器AZ2,中央处理板B上具有总线收发器BZ1、总线收发器BZ2。 Bus Transceivers having AZ1, bus transceiver on the central processing board A AZ2, the central processing board B having a bus transceiver BZ1, bus transceiver BZ2. 总线收发器AZ1、 总线收发器AZ2、总线收发器BZ1、总线收发器BZ2分别连接外设4反上各个不同的总线收发器。 Bus transceiver AZ1, bus transceiver AZ2, bus transceiver BZ1, BZ2 bus transceiver 4 are connected to various peripheral bus transceivers the reverse. 例如,总线收发器AZ1连接总线收发器CZ1、总线收发器DZ1、总线收发器EZ1;总线收发器AZ2连接总线收发器CZ2、总线收发器DZ2、总线收发器EZ2。 For example, a bus transceiver is connected to bus transceiver AZ1 CZ1, DZ1 is bus transceiver, a bus transceiver EZ1; AZ2 bus transceiver connected to bus transceiver CZ2, DZ2 is bus transceiver, a bus transceiver EZ2.

以外设板C为例,CPUA1、 CPUC1之间通过总线收发器AZ1、 总线收发器CZ1进行数据交互,CPUB1、 CPUC1之间通过总线收发器BZ1、总线收发器CZ1进行数据交互。 C, for example at Peripheral plate, between CPUA1, CPUC1 via bus transceiver AZ1, CZ1 bus transceiver exchange data bus transceiver to exchange data between the CZ1 CPUB1, CPUC1 via bus transceiver BZ1,. 这样,当CPUA1或总线收发器AZ1出现故障不能继续进行通信时,CPUC1、 CPUB1之间可通过总线收发器CZ1、总线收发器BZ1之间进行数据交互。 Thus, when the bus transceiver AZ1 CPUA1 or failure can not continue communication, can exchange data between the bus transceiver via CZ1, BZ1 between bus transceiver CPUC1, CPUB1.

上述形成的双重的通信通道均是互为冗余的,当一个中央处理拓、 的CPU与外设板的CPU之间数据交互出现故障时,另一个中央处理板的CPU与该外-i殳板的CPU还可进行数据交互,而系统可继续实现完整功能。 Dual communication channel formed as described above are mutually redundant data exchange when a failure occurs between a central processing extension CPU, CPU and peripheral board, the CPU board with the other central processing the outer -i Shu the CPU board also exchange data, and the system can continue to full functionality.

另外,外设板可以采用偶数个,每对外设板之间互为冗余,如外设板C、外设板D之间互为冗余。 Further, an even number of peripheral plates can be used, mutually redundant between each pair of peripheral boards, such as peripheral boards C, between the mutually redundant peripheral board D. 每对外设板中有不多于一个外设板故障时,系统可以继续全功能工作。 Each pair of peripheral plates when there is no more than a peripheral board failure, the system continues to be fully functional.

对于本发明各个实施例中所阐述的系统,凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。 Examples for the system set forth various embodiments of the present invention, any modifications within the spirit and principle of the present invention, the, equivalent substitutions, improvements should be included within the scope of the present invention.

7 7

Claims (7)

1、一种计算机冗余系统,其特征在于,包括:两个中央处理板、偶数个外设板,且每对外设板之间互为冗余,每个中央处理板上安装有两个CPU,每个外设板上安装有两个CPU,所述中央处理板的CPU、所述外设板的CPU均连接有各自的总线收发器;所述中央处理板的CPU与所述外设板相应的CPU通过各自的总线收发器一一连接,构成通信线路,所述不同中央处理板的CPU与所述外设板的同一CPU之间的两条通信线路构成冗余通信线路。 1, a computer redundant system comprising: a central processing two plates, an even number of peripheral boards, and between each pair of mutually redundant peripheral boards, each board are mounted two central processing CPU , each peripheral board mounted with two CPU, the CPU of the central processing board, the peripheral board is connected with a respective CPU bus transceiver; the central processing board CPU and said peripheral plate corresponding CPU eleven connected by a respective bus transceiver, constituting a communication line, a communication line between the same two CPU boards of the different central processing CPU and said peripheral plate constituting a redundant communication line.
2、 根据权利要求1所述的计算机冗余系统,其特征在于,所述总线收发器为单路总线收发器。 2, a redundant computer system according to claim 1, wherein said bus is a single-channel transceiver bus transceiver.
3、 根据权利要求2所述的计算机冗余系统,其特征在于,所述中央处理板的每个CPU连接单路总线收发器的个数与所述外设板的个数相同;所述外设板的每个CPU连接两个单路总线收发器。 3, a redundant computer system according to claim 2, wherein each of said central processing CPU connected to the same number plate number of single bus transceiver with said peripheral plate; the outer each CPU is connected to two plates provided single bus transceiver.
4、 根据权利要求3所述的计算机冗余系统,其特征在于,所述中央处理板上总线收发器与所述外设板上的总线收发器——连接。 4. The computer redundant system according to claim 3, wherein said central processing board bus transceiver and said peripheral bus transceiver board - connector.
5、 根据权利要求1所述的计算机冗余系统,其特征在于,所述总线收发器为多路总线收发器。 5. The computer redundant system according to claim 1, wherein said bus is a multiplexed bus transceiver transceiver.
6、 根据权利要求5所述的计算机冗余系统,其特征在于,所述中央处理板上的每个CPU连接唯——个多路总线收发器,所述外设板上的每个CPU连接唯——个多路总线收发器。 6, the redundant computer system of claim 5, wherein each of said central processing CPU board is connected only - one multiplexed bus transceivers, each CPU is connected to said peripheral board only - one multiplexed bus transceivers.
7、 根据权利要求6所述的计算机冗余系统,其特征在于,所述中央处理板上的多路总线收发器与各个外设板上多路总线收发器之间——连接。 7, a redundant computer system according to claim 6, wherein said central processing board transceiver multiplexed bus between the respective peripheral bus transceiver board multiplexer and - connection.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1136250A (en) 1995-03-16 1996-11-20 Abb.专利有限公司 Method for fault-tolerant communication under strictly real-time conditions
US6550018B1 (en) 2000-02-18 2003-04-15 The University Of Akron Hybrid multiple redundant computer system
CN1952821A (en) 2006-11-06 2007-04-25 中国科学院电工研究所 Embedded real-time control system of industrial ethernet

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1136250A (en) 1995-03-16 1996-11-20 Abb.专利有限公司 Method for fault-tolerant communication under strictly real-time conditions
US6550018B1 (en) 2000-02-18 2003-04-15 The University Of Akron Hybrid multiple redundant computer system
CN1952821A (en) 2006-11-06 2007-04-25 中国科学院电工研究所 Embedded real-time control system of industrial ethernet

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
一种双冗余总线多处理机容错系统的探讨. 原民辉.航天控制,第4期. 1990

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