CN100493175C - Apparatus for implementing video frequency sequential to interlaced conversion and converting method - Google Patents

Apparatus for implementing video frequency sequential to interlaced conversion and converting method Download PDF

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CN100493175C
CN100493175C CNB2005100877654A CN200510087765A CN100493175C CN 100493175 C CN100493175 C CN 100493175C CN B2005100877654 A CNB2005100877654 A CN B2005100877654A CN 200510087765 A CN200510087765 A CN 200510087765A CN 100493175 C CN100493175 C CN 100493175C
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frame
frame memory
data
write
read
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CN1719889A (en
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刘健
居晓波
杨柱
高晓宇
赵晓海
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Vimicro Corp
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Vimicro Corp
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Abstract

This invention discloses a device realizing conversion of video from line by line to interleaving used in converting video forms between the image sensor and the TV encoder including: a first frame storage, a second frame storage and a frame storage controller, among which, said controller receives images from the image sensor and writes the image data in a first frame storage and a second frame storage in the form of frames to be read out in the way of fields and transmitted to the TV decoder. This invention also discloses a conversion method for video from line by line to interleaving.

Description

Realize the device and the conversion method of video frequency sequential to interlaced conversion
Technical field
The present invention relates to video processing technique, relate in particular to a kind of device and conversion method that realizes the video frequency sequential to interlaced conversion.
Background technology
It is traditional that what simulate that TV signal adopts all is that the method for a kind of Interlace Scan by name (interlacing scan) is reappeared the image information that is transmitted by holding wire, because of technical limitations at that time, data processing speed does not catch up with, and traditional TV information transmitting medium can't satisfy the requirement of transmitting the mass data bag, its data of extracting odd-numbered line earlier form image outline, replenish with the even number of lines certificate again, 60Hz with NTSC is an example, per second basically can be by the picture of 60 width of cloth on TV, and the first frame picture in this 60 width of cloth all adopts interleaved mode to draw, and interlacing scan means on display end, can only be at the picture of same screen displayed odd-numbered line or the picture of even number line, such as TV the reduction 1 second 1/60 picture the time, scanning be 1,3,5,7,9 such odd-numbered lines, and to just transferring the scanning reductase 12 when reducing the 2/60th picture to, 4,6,8,10 even number line information; The working method of lining by line scan is different fully with interlacing scan, its scanning sequence be every scanning reduce the 1st the row information, next be the 2nd the row, the 3rd the row analogize in proper order.
Along with making rapid progress of electronic technology development, development of television has also developed into Digital Television by simulated television gradually.The processing procedure of traditional simulated television system may be summarized to be from the camera tube sampling, coding, and transmission, decoding are arrived picture tube again and are shown.Because technology is limit, this process is from shooting, and being transferred to demonstration all is that unit handles with the field; And for digital television system, because the development of CCD and cmos image sensor technology, the video sampling process has had revolutionary variation, based on CCD, the image that cmos image sensor obtains generally all is unit with the frame, one frame equals two, all is interlacing but the problem of bringing is exactly present most TV, can only show with the field to be the vision signal of unit.
In addition, because CCD, the speed of the output image of cmos image sensor mainly is subjected to the restriction of exposure sensor time, and under the different situation of illumination condition, the output image frame per second is also different.Under the darker situation of illumination condition, in order to reach the better image quality, needing increases the time for exposure, thereby causes the reduction of output frame rate.And for TV showed, the speed of its display image was fixed, and for example common Phase Alternation Line system is 50 times/second, and TSC-system is 60 times/second, even support the conversion of progressive-to-interlace like this, also can cross slowly and can't be by television reception owing to frame per second.
At last, for general CCD, cmos image sensor, its output image size is fixed, and television system then has a variety of, and modal have TSC-system and a Phase Alternation Line system.Its image size of different television systems is also different, want both to support TSC-system, also support Phase Alternation Line system, just need under the prerequisite that does not influence display quality, can support the change of picture size size, make and to export the pal television signal, also can export the TSC-system TV signal.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of device of realizing the video frequency sequential to interlaced conversion, can change a frame image data into two field data, thereby supports that the progressive image that cmos image sensor obtains is presented on the interlacing TV with CCD.
Another purpose of the present invention is to provide a kind of conversion method that realizes the video frequency sequential to interlaced conversion, support is with CCD, the progressive image that cmos image sensor obtains is presented on the interlacing TV, and guarantees that the speed of display image under the situation that transducer output image frame per second changes fixes.
A further object of the present invention is to provide a kind of device of realizing the video frequency sequential to interlaced conversion, makes and can support different television systems when finishing above-mentioned translation function.
For achieving the above object, technical scheme of the present invention specifically is achieved in that
A kind of device of realizing the video frequency sequential to interlaced conversion is used for carrying out video format conversion between imageing sensor and television encoder, it is characterized in that, comprising:
First frame memory,
Second frame memory and
Frame store controller, wherein
Frame store controller receives the picture frame from imageing sensor, and view data is write first frame memory and second frame memory with the form of frame, and read with the form of field and send television decoder to,
Wherein frame store controller is controlled first frame memory and second frame memory with the work of table tennis form, receive picture frame in turn from imageing sensor, when writing first frame memory, read second frame memory, read first frame memory when writing second frame memory, when needs carry out the read and write operation simultaneously to same frame memory, the data that needs are write write according to the order of sense data, and be capped to avoid the previous frame data by the order that the frame store controller control data writes, the current frame that writes also will be controlled the order of reading and guarantee to read correct data when reading simultaneously.
Further, said apparatus also comprises an image size conversion module, and the view data that is used for described frame store controller is spread out of is carried out size conversion, and the data after will changing are passed to the television encoder output of encoding.
Further, the writing speed of described said apparatus picture frame is supported n frame/second, and reading speed is supported m frame/second, wherein 2n≤m.
Further, described image size conversion module utilizes the method for bilinear interpolation to change picture frame picture size.
The basic calculating formula of above-mentioned bilinear interpolation is as follows:
p=(1-x)*p(n)+x*p(n+1);
Wherein, p represents calculative pixel, the previous pixel of the calculative pixel of p (n) representative, and a back pixel of the calculative pixel of p (n+1) representative, x represents the distance of calculative pixel to p (n).
In said method, need not calculate all insertion pixels, only calculate the insertion pixel corresponding with actual pixels behind the convergent-divergent.
Further, imageing sensor described in the described device is CCD or cmos image sensor.
For achieving the above object, the present invention also provides a kind of conversion method that realizes the video frequency sequential to interlaced conversion, the device that is used for the video frequency sequential to interlaced conversion, described device is used for carrying out video format conversion between imageing sensor and television encoder, described device comprises first frame memory, second frame memory and frame store controller, said method comprising the steps of:
Write the frame memory step:
Step 1 begins to write fashionable when frame store controller receives imageing sensor one frame data, checks that at first two frame memories are whether empty, and order is to check earlier to reexamine second frame memory by first frame memory;
Step 2 is as long as there is a frame memory to be the empty frame memory that just data is write sky;
With, read the frame memory step:
Step 1, when needs when frame memory is read frame data, check that at first the data that previous frame is read come from first frame memory or second frame memory;
Step 2 checks earlier whether another frame memory data have been write, if write, then read the data of this frame memory, if do not have, then repeat to read the data of a frame memory;
Its characteristics are,
Write in the frame memory step, treatment step for the moment, if two frame memories are not empty, then check currently reading which frame memory,, then can write that frame memory of reading if first pass runs through, if do not run through, then simultaneously this frame memory is carried out the read and write operation, the order that writes by the frame store controller control data is capped to avoid the previous frame data, and this frame also will be controlled the order of reading and guarantee to read correct data when reading simultaneously.
Further, said method also comprises following characteristics:
Above-mentioned frame memory is carried out read and write when operation simultaneously, the data that needs are write write according to the order of sense data.
Further, imageing sensor described in the said method can be CCD or CMOS.
As seen from the above technical solution, the control of passing through reading of data of the present invention makes final system can support to become line by line the function of interlacing, also can accomplish not frame-skipping under the situation that the sensor image output frame rate changes, and guarantees the continuity of image.
In addition,, can also reach the effect of supporting multiple television system, in the process of interpolation calculation, only calculate a spot of pixel, also can reduce amount of calculation by image is carried out size conversion.
Description of drawings
Fig. 1 is the structure diagram of the device of realization video frequency sequential to interlaced conversion of the present invention;
Fig. 2 is the structure diagram of preferred embodiment of the device of realization video frequency sequential to interlaced of the present invention conversion;
Fig. 3 is for writing the frame memory flow chart;
Fig. 4 is for reading the frame memory flow chart;
Fig. 5 is the basic calculating mode schematic diagram of bilinear interpolation of the present invention;
Fig. 6 is an one dimension bilinear interpolation schematic diagram of the present invention.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
As shown in Figure 1, structure diagram for the device of realization video frequency sequential to interlaced of the present invention conversion, the picture frame that frame store controller 23 receives from imageing sensor 1, and view data write first frame memory 21 and second frame memory 22 with the form of frame, read with the form of field and send television decoder 4 to.
Frame store controller 23 control first frame memories 21 and second frame memory 22 are worked with the table tennis form, receive picture frame in turn from imageing sensor 1, when writing first frame memory 21, read second frame memory 22, read first frame memory 21 when writing second frame memory 22.
As shown in Figure 2, the structure diagram for the preferred embodiment of the device of realization video frequency sequential to interlaced of the present invention conversion has increased an image size conversion module 3 in the present embodiment.
At two frame memories all is that data at first are stored in first frame memory 21 under the situation of sky, and after the storage of first frame data finished, it was in second frame memory 22 that second frame data will be stored in another frame memory.Simultaneously, first frame data can be read, and deliver to image size conversion module 3, through giving television encoder 4 output of encoding after the image size conversion.Then, television encoder 4 reads second frame data in second frame memory 22, and simultaneously, the next frame image is written into first frame memory 21; These two frame memories are used for receiving in turn the picture frame from imageing sensor, and are read successively.
Every frame data are that unit writes with the frame when writing, and are that unit is read with the field when reading, and every frame need be read two.The field is interlacing and relation line by line with the relation of frame, that is to say, writes frame memory with 1,2,3,4 ..., 479, the order of 480 (with behavior unit) writes, and when reading according to 1,3,5,7 ..., 479 (first), 2,4,6,8 ..., 478,480 (second) call over.
From here as can be seen, because each frame need be exported two, and, that is to say because the needs of image size conversion module 3 are actually frame memory and need export two frames, after writing, every frame needs to read the output of finishing two field data for twice.
At first, for frame memory, for simplified design, the bandwidth of distributing to read and write usually equates, and, that is to say that the speed of reading is not less than the speed of writing because the frame per second (30 frames or 25 frames) of read data generally all is the maximum frame per second of imageing sensor output.
Generally speaking, the maximum frame per second of imageing sensor output can reach for 30 frame/seconds, if but the illumination condition of environment is darker, in order to guarantee certain picture quality, need the lengthening time for exposure, then the frame per second of imageing sensor output just will be lower than for 30 frame/seconds, environment is dark more, and frame per second is low more.
So just brought a problem, because the frequency that TV refreshes is fixed, Phase Alternation Line system is 50 times/second, and TSC-system is 60 times/second, and the speed of reading data from frame memory also must be fixed like this, for Phase Alternation Line system is 50 times/second, for TSC-system is 60 times/second, thereby has just caused the writing speed of frame memory and the reading speed might be unequal, that is to say, after frame data run through, might the next frame data also not write.
As mentioned above, reading speed is not less than writing speed on average angle, if therefore at this moment go the next frame data reading also not write, because it is slower to write the frame per second of data, probably read to catch up with and write, cause the destruction of data, this is unacceptable.
When for example being operated in TSC-system, the output frame rate of supposing imageing sensor was 20 frame/seconds, because reading speed is 60 times/second, like this after first frame data run through, second frame data have not also been write, and have only write 2/3 frame, if at this moment remove to read second frame memory, then read to catch up with and write, thus the destruction of causing view data.In order to address this problem, the present invention determines a rule: allow to begin to read just have only after a certain frame data write in the frame memory fully.Current frame data has not also been write if the former frame data run through, and just repeats to read the former frame data.Though the continuity of image has been subjected to influence like this, this is because the illumination condition of this moment is too poor, need extend the time for exposure in order to reach the better image quality, thereby cause the frame per second reduction to cause, and it is generally acknowledged that this result also still is an acceptable.
Equally, because first frame data have been carried out repeating to read, second frame data just might occur and write, the 3rd frame data begin to arrive, and the situation that first frame data also do not run through under the situation that repeats to read.As previously mentioned, every frame data are that unit writes with the frame when writing, and are that unit is read with the field when reading, and every frame need be read two.The field is interlacing and relation line by line with the relation of frame, that is to say, writes frame memory with 1,2,3,4 ..., 479, the order of 480 (with behavior unit) writes, and when reading according to 1,3,5,7 ..., 479 (first), 2,4,6,8 ..., 478,480 (second) call over.
Therefore two kinds of situations are arranged this moment:
A kind of is that first frame data have run through first; Another kind is that first frame data are being read first.
For first kind of situation, according to the introduction of front, because reading speed is faster than writing speed, and to read for the field be according to calling over of slipping a line, even begin to write the 3rd frame data this moment, also can not catch up with and read, cause first frame data to destroy, therefore the 3rd frame data can write;
For second kind of situation, because first frame data also need to read second, if the 3rd frame data are write according to normal order, promptly 1,2,3 ..., 479,480 order will cover first frame data, causes mistake occurring when reading second field data.
Common situation is that the 3rd frame is skipped, and promptly abandons, and waits for the data of the 4th frame, as shown in Figure 3.Owing to frame-skipping causes the discontinuous of image, can have influence on the display effect of image in this case.
For fear of frame-skipping, analyze the process that reads and writes data below.
As previously mentioned, write data is to write with the order of frame, according to 1,2,3,4 ..., 479,480 capable orders write, and read data is to read with the order of field, according to 1,3,5,7 ..., 477,479,2,4,6 ..., 478,480 capable calling over.The data volume of write and read is the same, but the order difference of write and read.
Because the speed of reading is not less than the speed of writing,, just can guarantee that data originally can not be capped, and so just can guarantee not frame-skipping when a frame memory is carried out read-write operation simultaneously if therefore suitably adjust the order of read and write.
Concrete design process is such, and when some frame memories during also in the data of reading first, the order of its read data is 1,3,5,7 ..., 477,479 row, i.e. the odd-numbered line of a frame is if at this moment another frame data write, the order that writes is 1,2,3,4 ..., 479,480 row, the data of even number line will be capped like this, will make a mistake when reading second.If with 1,2,3,4 of second frame data, ..., 479,480 row are according to 1,3,5,7 ..., 477,479,2,4,6,8 ..., the order of 478,480 row, because it is identical with the order of sense data to write the order of data, and the speed of sense data is not less than the speed that writes data, so the data of previous frame are destroyed never, avoided frame-skipping.When reading a current frame that writes because the order that writes is 1,3,5,7 ..., 477,479,2,4,6,8 ..., 478,480 row need also adjust accordingly the order of sense data, with 1,5,9 ... call over data.The rest may be inferred, as long as the speed of sense data is not less than the speed that writes data, need never just can guarantee frame-skipping.
For simplicity, see the treatment of picture of a width of cloth being had only 8 row first.
First frame, write sequence: 1,2,3,4,5,6,7,8
Read order: 1,3,5,7,2,4,6,8
When taking place first when not running through the situation that second frame just arrives, according to the introduction of front, the order that writes data becomes the order of reading of first frame, and the read-write that obtains second frame like this is in proper order:
Second frame, write sequence: 1,3,5,7,2,4,6,8
Read order: 1,5,2,6,3,7,4,8
When the 3rd frame arrived, no matter whether first of second frame ran through, and all the order of reading according to second frame writes, and the read-write order of such the 3rd frame is as follows:
The 3rd frame, write sequence: 1,5,2,6,3,7,4,8
Read order: 1,2,3,4,5,6,7,8
When the 4th frame arrives, write according to reading in proper order of the 3rd frame, its read-write order is as follows:
The 4th frame, write sequence: 1,2,3,4,5,6,7,8
Read order: 1,3,5,7,2,4,6,8
Through after four frames, got back to starting point again like this, still the frame that can need store according to the disposal methods back of front.
As can be seen from the above, the order of reading of each frame equals the write sequence of next frame, and therefore for the images of 8 row, the write sequence of consecutive image is:
First frame: 1,2,3,4,5,6,7,8
Second frame: 1,3,5,7,2,4,6,8
The 3rd frame: 1,5,2,6,3,7,4,8
The 4th frame: 1,2,3,4,5,6,7,8
The 5th frame: 1,3,5,7,2,4,6,8
。。。
If variable delta and j expand to n with 8, can obtain following conclusion:
First frame: delta=1, j=0, write sequence is: a (0), a (1), a (2), a (3) ..., a (n-1),
Wherein, a (0)=1, a (i+1)=a (i)+delta,
Second frame: delta=2, j=1, write sequence is: a (0), a (1), a (2), a (3) ..., a (n-1), wherein, a (0)=1, a ( i + 1 ) = a ( i ) + delta , ( a ( i ) + delta ) ≤ n a ( i ) + delta - n + 1 , ( a ( i ) + delta ) > n
The 3rd frame: delta=4, j=2, write sequence is: a (0), a (1), a (2), a (3) ..., a (n-1), wherein, a0=1, a ( i + 1 ) = a ( i ) + delta , ( a ( i ) + delta ) ≤ n a ( i ) + delta - n + 1 , ( a ( i ) + delta ) > n
M frame: delta=2 ', j = j = j + 1 , j ( m - 1 ) ! = n / 2 0 , j ( m - 1 ) = n / 2
Write sequence is: a (0), and a (1), a (2), a (3) ..., a (n-1),
Wherein, a (0)=1, a ( i + 1 ) = a ( i ) + delta , ( a ( i ) + delta ) ≤ n a ( i ) + delta - n + 1 , ( a ( i ) + delta ) > n
The rest may be inferred.
As shown in Figure 4, for reading the frame memory flow chart, when needs are exported frame data, check that at first the data that previous frame is read come from first frame memory 21 or second frame memory 22, check that then whether another frame memory data have been write, if write, then read the data of another frame memory, if no, then repeat to read the data of a frame memory.
For imageing sensor 1, its image resolution ratio generally can be supported 1280 X 960, VGA (640 X 480), QVGA (320 X 240), CIF (352 X 288) etc., but can only support the output frame rate of 15 frame/seconds for the image of 1280 X 960, because the output frame rate maximum of the image of present imageing sensor VGA size can support for 30 frame/seconds, and the display frame rate of TSC-system also was 30 frame/seconds, the display frame rate of Phase Alternation Line system was 25 frame/seconds, in order to guarantee the final picture quality and the continuity of image, the embodiment of the invention is selected and is had the immediate VGA pattern of TV resolution now, is converted into PAL or the required image resolution ratio of NTSC by image size conversion module.
Because image size conversion module 3 adopts bilinear interpolation method to realize the conversion of image size, this method needs adjacent lines and adjacent column data when calculating current data.Therefore, though the data of image size conversion module 3 outputs are interlacing, in order to finish the image size conversion, the data of reading from above-mentioned frame memory still are line by line.
The image resolution ratio difference that different television systems are supported, in order to support different television systems, need can control chart as the function of size conversion.Among the various algorithms of control image zoom, bilinear interpolation method realizes simple with it, characteristics such as output effect is better and being widely adopted have also used bilinear interpolation method to change size of images in image size conversion module 3 of the present invention.
Image size conversion module 3 is the needed image size of TSC-system or Phase Alternation Line system with the image transitions of VGA size; For TSC-system, its image resolution ratio is 720 X 480, and every is 720 X 240; For Phase Alternation Line system, its resolution is 720 X 576, and every is 720 X 288.And input picture is VGA, just 640 X 480.Therefore, the function that image size conversion module 3 of the present invention is finished is such, for TSC-system, only do the size conversion of horizontal direction, conversion proportion is 640-" 720, vertical direction is not done size conversion, according to the difference of strange field or idol field, will very go or even line output; For Phase Alternation Line system, the size conversion of horizontal direction is identical with NTSC, and conversion proportion is 640-" 720, the vertical direction conversion proportion is 480-" 576, according to the difference of strange field or idol field, only export very row or even row.
The basic calculating formula of bilinear interpolation of the present invention is as follows:
p=(1-x)*p(n)+x*p(n+1);
As shown in Figure 5, p represents calculative pixel, the previous pixel of the calculative pixel of p (n) representative, and a back pixel of the calculative pixel of p (n+1) representative, x represents the distance of calculative pixel to p (n).
According to above-mentioned formula, can carry out the one dimension convergent-divergent to the image of giving sizing: the size of establishing input picture is b, the size of output image is a, a and b are relatively prime, through needing to reach the scaled results of a/b after the image size conversion,, at first input picture is amplified a doubly then according to above-described bilinear interpolation method, just insert (a-1) individual pixel between neighbor, the value of inserting pixel can calculate according to the formula of bilinear interpolation; Image after will amplifying then dwindles b doubly again, and method is pixel of every b pixel decimation, has so just reached the zooming effect of a/b.
For the present invention, according to the introduction of front, input picture is 640 X 480, and output image is 720 X 480 or 720 X 576.Therefore horizontal direction need reach the zooming effect of 640/720=8/9, and vertical direction need reach the zooming effect of 480/576=5/6.For horizontal direction, according to the introduction of front, a equals 9, and b equals 8.
The interpolation calculation process as shown in Figure 6, the pixel of solid pixel representing input images among the figure, the value that obtains through bilinear interpolation between the hollow pixel representing input images neighbor, the pixel of black grid is represented the pixel of output image.Can see that input picture at first is exaggerated 9 times according to the bilinear interpolation formula, and then reduced 8 times, thereby obtain comparing with input picture, amplify 9/8 times image.
Can see that according to Fig. 6 hollow pixel need not all to be calculated, only need to calculate hollow pixel and get final product with those pixels that black grid pixel overlaps.Describe the process of carrying out the one dimension convergent-divergent for input picture above, in like manner, it can be generalized to the realization of two dimension.Like this, for given input picture, can obtain the output image of process convergent-divergent according to the algorithm of foregoing description.
By the above embodiments as seen; except that the video conversion that is used for common TV; apparatus and method of the present invention can be used to fully such as in supervisory control system that has camera and common TV display unit etc.; the above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvement and variation, these improvement and variation also should be considered as protection scope of the present invention.

Claims (9)

1, a kind of device of realizing the video frequency sequential to interlaced conversion is used for carrying out video format conversion between imageing sensor and television encoder, it is characterized in that, comprising:
First frame memory,
Second frame memory and
Frame store controller, wherein
Frame store controller receives the picture frame from imageing sensor, and view data is write first frame memory and second frame memory with the form of frame, and read with the form of field and send television encoder to,
Wherein, frame store controller is controlled first frame memory and second frame memory with the work of table tennis form, receive picture frame in turn from imageing sensor, when writing first frame memory, read second frame memory, read first frame memory when writing second frame memory, when needs carry out the read and write operation simultaneously to same frame memory, the data that needs are write write according to the order of sense data, and be capped to avoid the previous frame data by the order that the frame store controller control data writes, the current frame that writes also will be controlled the order of reading and guarantee to read correct data when reading simultaneously.
2, device according to claim 1, it is characterized in that, described device also comprises an image size conversion module, and the view data that is used for described frame store controller is spread out of is carried out size conversion, and the data after will changing are passed to the television encoder output of encoding.
3, device according to claim 1 is characterized in that, imageing sensor described in the described device is CCD or cmos image sensor.
4, device according to claim 1 is characterized in that, the writing speed of the picture frame in the described device is supported n frame/second, and reading speed is supported m frame/second, wherein 2n≤m.
5, device according to claim 2 is characterized in that, described image size conversion module utilizes the method for bilinear interpolation to change picture frame picture size.
6, device according to claim 5 is characterized in that, the basic calculating formula of above-mentioned bilinear interpolation is as follows:
p=(1-x)*p(n)+x*p(n+1);
Wherein, p represents calculative pixel, the previous pixel of the calculative pixel of p (n) representative, and a back pixel of the calculative pixel of p (n+1) representative, x represents the distance of calculative pixel to p (n).
7, device according to claim 6 is characterized in that, in the method for described bilinear interpolation, need not calculate all insertion pixels, only calculates the insertion pixel corresponding with actual pixels behind the convergent-divergent.
8, a kind of conversion method that realizes the video frequency sequential to interlaced conversion, the device that is used for the video frequency sequential to interlaced conversion, described device is used for carrying out video format conversion between imageing sensor and television encoder, described device comprises first frame memory, second frame memory and frame store controller, said method comprising the steps of:
Write the frame memory step:
Step 1 begins to write fashionable when frame store controller receives imageing sensor one frame data, checks that at first two frame memories are whether empty, and order is to check earlier to reexamine second frame memory by first frame memory;
Step 2 is as long as there is a frame memory to be the empty frame memory that just data is write sky;
With, read the frame memory step:
Step 1, when needs when frame memory is read frame data, check that at first the data that previous frame is read come from first frame memory or second frame memory;
Step 2 checks earlier whether another frame memory data have been write, if write, then read the data of this another frame memory, if do not have, then repeat to read the data of a frame memory;
It is characterized in that,
Write in the frame memory step, treatment step for the moment, if two frame memories are not empty, then check current which frame memory of reading, if first runs through, then write that frame memory of reading, if do not run through, then simultaneously this that frame memory of reading is carried out the read and write operation, the order that writes by the frame store controller control data is capped to avoid the previous frame data, simultaneously the current frame that writes also will be controlled the order of reading and guarantee to read correct data when reading, and frame store controller writes first frame memory and second frame memory with view data with the form of frame, reads with the form of field.
9, method according to claim 8 is characterized in that, above-mentioned frame memory is carried out read and write when operation simultaneously, and the data that needs are write write according to the order of sense data.
CNB2005100877654A 2005-08-08 2005-08-08 Apparatus for implementing video frequency sequential to interlaced conversion and converting method Expired - Fee Related CN100493175C (en)

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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104270585A (en) * 2014-10-17 2015-01-07 中国电子科技集团公司第四十四研究所 CMOS image sensor data read-write control method
CN107870865A (en) * 2016-09-27 2018-04-03 晨星半导体股份有限公司 Time release of an interleave circuit and the method for run time release of an interleave processing
CN108632624B (en) * 2017-12-18 2020-10-30 百富计算机技术(深圳)有限公司 Image data processing method and device, terminal equipment and readable storage medium
CN110073653B (en) * 2018-09-07 2021-01-12 深圳鲲云信息科技有限公司 Video image data transmission method, system and storage medium
CN110832870A (en) * 2018-10-30 2020-02-21 深圳市大疆创新科技有限公司 Data processing method and equipment and pass-through glasses
CN112188137B (en) * 2019-07-01 2022-07-08 北京华航无线电测量研究所 Method for converting high frame frequency progressive image to standard definition PAL interlaced image based on FPGA
CN112511861B (en) * 2020-12-03 2022-05-03 威创集团股份有限公司 Low-delay video transmission method and system and storage medium thereof
CN114153416B (en) * 2021-11-27 2024-02-23 深圳曦华科技有限公司 Display control method and related device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
基于PCI的视频信号发生器的实现方法. 王信.电子科技,第3期. 2005
基于PCI的视频信号发生器的实现方法. 王信.电子科技,第3期. 2005 *

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