CN100485942C - Three-dimensional electric programming read-only memory - Google Patents

Three-dimensional electric programming read-only memory Download PDF


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CN100485942C CN 200610159412 CN200610159412A CN100485942C CN 100485942 C CN100485942 C CN 100485942C CN 200610159412 CN200610159412 CN 200610159412 CN 200610159412 A CN200610159412 A CN 200610159412A CN 100485942 C CN100485942 C CN 100485942C
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本发明提出一种三维电编程只读存储器(3D-EPROM),它含有一编程电压接线垫,该编程电压接线垫为该3D-EPROM引入编程电压(V<sub>pp</sub>)。 The present invention provides a three-dimensional electrically programmable read only memory (3D-EPROM), comprising a program voltage terminal pad, 3D-EPROM introduced programming voltage (V <sub> pp </ sub>) for the programming voltage terminal pad. 因此,3D-EPROM不需含有V<sub>pp</sub>产生电路。 Thus, 3D-EPROM without containing V <sub> pp </ sub> generating circuit. 这能简化3D-EPROM设计,并降低其成本。 This 3D-EPROM can simplify the design and reduce the cost. 本发明还提出一种能对至少两个存储元同时进行编程的3D-EPROM。 The present invention also provides a program capable of 3D-EPROM memory cells while at least two.


三维电编程只读存储器 Electrically programmable read-only memory D

本发明是申请号为02150190.4、申请日为2002年11月17日、发明名称为"三维存储器的设计"的发明专利申请的分案申请。 The present invention Application No. 02150190.4, filed a divisional application November 17, 2002, entitled "Memory of the three-dimensional design" invention patent application.

技术领域 FIELD

本发明涉及集成电路领域,更确切地说,涉及三維只读存储器的设计。 The present invention relates to the field of integrated circuits, and more particularly, relates to the design of a three-dimensional read only memory.

背景技术 Background technique

三维集成电路(简称为3D-IC )将一个或多个三維集成电路层(简称为3D-IC层)在垂直于衬底的方向上相互叠置在衬底上。 Three dimensional integrated circuit (3D-IC for short) one or more three-dimensional integrated circuit layer (referred to as 3D-IC layer) in a direction perpendicular to the substrate mutual superposition on the substrate. 3D-IC可以具有多种功能,如模拟功能、数字功能、 存储器功能等。 3D-IC may have a variety of functions, such as analog functions and digital functions, memory functions. 由于存储器具有纠错能力,它能容忍较大的缺陷密度;且其功耗低,不存在散热问题,故存储器尤其适合于三维集成。 Since the memory with error correction capabilities, it can tolerate a larger defect density; and its low power consumption, heat dissipation is not a problem, it is particularly suitable for three-dimensional integration of the memory.

三维存储器(3-dimensional memory,简称为3D-M )将一个或多个存储层在垂直于衬底的方向上相互叠置在衬底电路上。 Three dimensional memory (3-dimensional memory, referred to as 3D-M) one or more storage layers in a direction perpendicular to the substrate circuit substrate stacked on each other. 如图1A所示,3D-M含有至少一个叠置于半导体衬底0s 上的三维存储层100,每个三维存储层(如100)上有多条地址选择线(包括字线20a和位线30a)和多个三维存储元,即3D-M元(laa…)。 As shown in FIG. 1A, 3D-M contains at least one three-dimensional stacked memory layer disposed on the semiconductor substrate 0s 100, a plurality of address selection lines (including word lines and bit lines 20a on each of the three storage layers (e.g., 100) 30a) and a plurality of three-dimensional memory element, i.e., 3D-M element (laa ...). 衬底0s上有多个晶体管。 A plurality of transistors on a substrate 0s. 接触通道口(20av、 30av…)为地址选择线(20a、 30a…)和村底电路提供电连接。 Opening contact channel (20av, 30av ...) village circuit substrate electrically connected to provide address select lines (20a, 30a ...). 3D-M可以分为三维随机存取存储器(3D-RAM)和三维只读存储器(3D-ROM)。 3D-M random access memory can be divided into three-dimensional (3D-RAM) and read only memory dimensional (3D-ROM). 3D-RAM元的电路与常规RAM元类似,只是它一般由薄膜晶体管lt构成(图1B) 。 3D-RAM element similar to a conventional RAM circuit element, but it is generally a thin film transistor lt configuration (FIG. 1B). 3D-ROM可以是掩膜编程(3D-MPROM)、至少一次编程(3D-EPROM)、或多次编程(包括3D-flash、 3D-MRAM、 3D-FRAM、 3D-OUM等)。 3D-ROM may be mask-programmed (3D-MPROM), at least one program (3D-EPROM), or multiple program (including 3D-flash, 3D-MRAM, 3D-FRAM, 3D-OUM, etc.). 其基本结构可见美国专利5,835,396等公开文件。 Its basic structure found in U.S. Patent 5,835,396 and other publications. 它可以使用如薄膜晶体管(TFT) lt的有源元件(图1CA、图1CB )和/或如二极管ld的无源元件(图IDA -图1E )。 It may be used as an active element a thin film transistor (TFT) lt (FIG 1CA, 1CB FIG) and / or passive elements such as diodes ld (FIG IDA - FIG. 1E). 对于使用TFT的3D-ROM元来说,它们可以含有悬浮栅30fg (图1CA)或具有垂直沟道25c (图1CB )。 For the 3D-ROM using a TFT element, they may contain floating-gate 30fg (FIG 1CA) or with a vertical channel 25c (FIG 1CB). 对于使用二极管的3D-MPROM元来说,它含有具有非线性电阻特性的3D-ROM膜22 (包括准导通膜),并以信息开口24 (即通道孔)的存在(即设置介质26的不存在)来表示逻辑"1"(图IDA ),信息开口24的不存在(即设置介质26的存在)来表示逻辑"0"(图1DB )。 For 3D-MPROM diode element, it contains 3D-ROM film 22 having a non-linear resistance characteristics (including quasi-conductive film), the presence of opening 24 and the information (i.e., channel hole) (i.e., the medium 26 is provided absent) to represent a logic "1" (FIG IDA), the information does not exist the opening 24 (i.e., provided the presence of medium 26) to represent the logic "0" (FIG 1DB). 这里,设置介质26是指介于地址选择线20a、 30a之间的介质,其存在与否决定该3D-ROM 元的设置值。 Here, the medium 26 is disposed between the address select line means 20a, between the medium 30a, which determines the presence or absence of settings 3D-ROM element. 对于使用二极管的3D-EPROM来说,可以通过反熔丝22af的完整性来表示逻辑信息(图1E )。 For 3D-EPROM diode, it can be used to represent logical information (FIG. 1E) the integrity of the antifuse 22af.

3D-M具有低成本、高密度等优点,但由于其存储元一般由非单晶半导体材料构成,故其性能尚难于与常规的、基于单晶半导体的固态存储器相比。 3D-M low cost, high density, etc., but because of its non-memory element typically formed of monocrystalline semiconductor material, it is hard on the performance of conventional, solid state memory based on comparison with a single crystal semiconductor. 这需要对3D-M的周边电路作进一步改进,并充分利用其与村底电路的可集成性,来提高3D-M的的速度、成品率和可编程性。 This requires 3D-M of the peripheral circuit further improvement, and make full use of its bottom and village integration circuit may be to increase the speed of the 3D-M, the yield and programmability. 本发明在这些方面对3D-M做了进一步完善。 In these aspects of the present invention is 3D-M were further improved.

发明目的本发明的主要目的是进一歩提高三维电编程只读存储器(313-EPROM)的写速度。 OBJECT OF THE INVENTION The main object of the present invention is to improve the feed-dimensional electrically programmable read only memory (313-EPROM) a ho writing speed. 本发明的另一目的是降低3D-EPROM的成本。 Another object of the present invention is to reduce the cost of 3D-EPROM.

根据这些以及别的目的,本发明提供了多种三维电编程只读存储器(3D-EPROM)。 According to these and other objects, the present invention provides a variety of three-dimensional electrically programmable read only memory (3D-EPROM).


与常规的、基于单晶半导体的固态存储器相比,3D-M元的读写速度较慢,这可以从电路设计和系统设计的角度来解决。 Conventional, as compared to the single crystal semiconductor based solid state memory, 3D-M-membered slower read and write, which can be resolved from the perspective of system design and circuit design. 从电路设计的角度,可以利用读出放大器(S/A)、全读模式和自定时来提高其读速度。 From the viewpoint of circuit design, the sense amplifier may be utilized (S / A), a full read mode and to increase its self-timing the reading speed. 由于使用S/A,产生逻辑输出所需的位线电压摆幅很小(〜0.1V), 所以对位线充电只需较短时间,这能极大地缩短首访时间;全读模式在一次读操作时将一条字线上的所有存储元中的数据同时读出,这能提高带宽,并能提高3D-M单位阵列的容量; 自定时能提高读的可信度并降低能耗。 The use of S / A, to produce the desired logic output voltage swing of the bit line is small (~0.1V), only a short time the charging of the bit lines, which can greatly shorten the time of first visit; read all at once mode when all the data read element stored in one word line are simultaneously read out, which can improve the bandwidth, and can increase the capacity of the 3D-M unit arrays; self-timed read can improve the reliability and reduce power consumption. 电编程3D-M可以采用平行编程来提高写速度。 Electrically programmed 3D-M may be employed to increase the write speed parallel programming.

从系统设计的角度,可使用三维集成存储器(3-diinensionalintegrated memory,简称为3DiM,参见由同一发明人于2002年9月30日递交的、申请号为02131089.0的专利申请"三维集成存储器")来隐藏3D-M的首访时间。 From the perspective of system design using a three-dimensional integrated memory (3-diinensionalintegrated memory, referred to as 3DiM, see, by the same inventor on September 30, 2002 filed application No. 02131089.0 patent application "Three-dimensional integrated memory") to Hide the first time to visit the 3D-M. 3DiM中的嵌入式RAM (embedded RAM,简称为eRAM)可用作3D-M的读写緩冲器(cache)。 3DiM embedded RAM (embedded RAM, referred to as the eRAM) 3D-M may be used as a write buffer (cache). 在读操作之后,锁存在S/A上的3D-M数据被分段传送到eRAM。 After the read operation, the latched S / 3D-M segmented data are transmitted to the A eRAM. 相应地,eRAM中保留了3D-M数据的一个备份。 Accordingly, eRAM retained in a 3D-M data backup. 当系统从3DiM 中寻找数据时,它先从eRAM寻找,如"命中",则直接从eRAM中读;如"未命中", 则再从3D-M中读。 When the system is looking for data from 3DiM, which eRAM start looking, such as "hit", it is read directly from the eRAM; as "miss", then it is read in from the 3D-M. 注意到,虽然单个3D-M元的性能尚难于与常规存储元相比,通过系统集成,其集体性能能与常规存储器相比,甚至更好。 It noted that, although a single 3D-M-membered performance is hard in comparison with the conventional memory element, through system integration, their collective performance compared to the conventional memory can be even better.

大容量3D-M单位阵列有助于提高3D-M的可集成性。 3D-M mass unit arrays can help to improve the integration of 3D-M. 可以从几个方面来提高3D-M单位阵列的容量。 You can improve the capacity of 3D-M unit arrays from several aspects. 首先,在全读模式下,由于单位阵列的位线数目没有任何限制,故3D-M阵列可以被设计成一矩形,其位线数目大于字线数目。 First, in the full read mode, since the number of the bit lines of the array units without any limitation, it is 3D-M array may be designed as a rectangular shape, which number of bit lines is greater than the number of word lines. 其次,由于单位阵列的字线数目受限于读操作时3D-ROM元的正反电流比,故可以通过提高正反电流比来提高字线数目。 Second, since the number of word lines of the array units is limited to a read operation reverse current ratio 3D-ROM element, so that the word lines can be increased by increasing the number of positive and negative current ratio. 一个提高正反电流比的方法是使用大读电压VR。 Forward and a current ratio is large to improve the read voltage VR. 由于本发明使用了S/A和全读模式等设计,正反电流比中的反向偏压和正向偏压分离:最大反向偏压在S/A的阈值电压Vt(^0.1V)附近;正向偏压由Vr决定。 Since the present invention is the use of S / A and read all design mode, positive and negative current and reverse bias than in forward bias isolated: the maximum reverse bias Vt of the threshold voltage in the vicinity of S / A of (^ 0.1V) ; forward bias is determined by Vr. 一般说来,正向偏压(如〜3V)远比反向偏压(如4.2V)大。 Generally, forward bias (e.g. ~3V) than the reverse bias voltage (e.g., 4.2V) large. 通过提高VR 可极大地提高正反电流比。 By increasing VR can greatly improve the ratio of positive and negative current. 另一个提高正反电流比的方法是使用二极化3D-ROM元:二极化3D-ROM元的上下半膜含有不同的基材料,或其与上下电极有不同界面。 Another method is to increase the reverse current ratio 3D-ROM using two polarization element: Element two polarized 3D-ROM containing different upper and lower halves of a film-based material, and the upper and lower electrodes or a different interface.

为了提高3D-M的成品率,可以通过一无缝3D-ROM元直接减少3D-ROM阵列中的缺陷数目。 In order to improve the yield of 3D-M can be produced by a seamless 3D-ROM membered directly reduce the number of defects in the 3D-ROM array. 无缝3D-ROM元中的缺陷敏感膜(包括3D-ROM膜以及与之相邻的底电极和顶电极)是以一种"无缝"形式来形成的,即在这些膜的形成过程中无图形转换步骤。 The seamless 3D-ROM membered defects sensitive membrane (membrane comprising 3D-ROM and a bottom electrode and the top electrode adjacent thereto) is a 'seamless' form is formed, i.e., the formation of these films in no graphics conversion step. 另一种提高成品率的方法使用如纠错码(ECC)和/或冗余电路等的纠错方案。 Another method to improve the yield of the error correction scheme such as an error correction code (ECC) and / or redundant circuit and the like. 它们可以纠正3D-M阵列中已有缺陷导致的错误。 They can correct errors in the 3D-M array existing defects. 使用ECC方案的3D-M阵列可使用列冗余码(如Hamming码)。 ECC scheme using 3D-M column redundancy array may be used (e.g., Hamming codes). 在冗余电路中,3DiM中的eROM可以用来存储缺陷位的地址及相应的纠错数据。 In the redundancy circuit, the 3DiM eROM and can be used to address the data storage defect corresponding error bits. 冗余电路可以对个别位错误、位线错误、字线错误进行纠错。 Redundancy circuit may be individual bit error correction, the error bit line, word line error. 该纠错过程可以在完成列译码后、并在数据送到eRAM前进行(即"读时,,修复),也可以在保留3D-M数据备份的eRAM中进行(即"读后"修复)。冗余电路其实是利用3DiM来提高3D-M成品率的一个例子。 The error correction process can be, and (i.e., prior to the data after completion of the column decoder eRAM ",, read repair), may be retained in the 3D-M eRAM data backup is performed (i.e.," reading "Repair ). in fact, the use of redundancy circuit 3DiM example to improve a yield 3D-M.

3DiM除了可以用来提高3D-M的成品率外,还可以对3D-M所栽的软件码提供升级能力,如可使用上述的字线冗余电路来存储软件升级码。 3DiM addition may be used to improve the yield of the 3D-M, can also provide the ability to upgrade the software code 3D-M planting of the above may be used as a word line redundancy circuit for storing software upgrade code. 软件升级还可以使用地址转换法。 Software upgrades can also use the address translation method. 在地址转换法中,3D-M和与之集成的嵌入式ROM (embedded ROM,简称为eROM)形成一单独存储空间:3D-M中所栽的是原始码,eROM中所载的是升级码。 In the address translation process, 3D-M and integrated with an embedded ROM (embedded ROM, EROM for short) form a single storage space: 3D-M is in the planting of the source code contained in the code upgrade is EROM . 同时,衬底集成电路还含有一地址转换块,它将输入地址视为虚拟地址,并将其转换成上述单独存储空间的物理地址。 Meanwhile, an integrated circuit substrate further comprises a block address translation, it will enter the address as a virtual address and converts it into a physical address above the individual storage space. 如果执行码使用原始码,那么,该物理地址指向3D-M;如果执行码使用升级码, 那么,该物理地址指向eROM。 If the use of source code is performed, then the physical address points to 3D-M; upgrade code if the execution code use, then the physical address points eROM. 附困说明 Description attached trapped

困1A是一种3D"M的透視困;困lB-田1CB表示多种基于薄膜晶体管的3D-M元;困1DA、田1DB分JW表示一逻辑"1"和"0"3D-MPROM元;困1E表示一种3D^EPROM元. 1A is trapped "trapped perspective of M; 1CB trapped lB- field indicates more based 3D-M thin-film transistor element; trapped 1DA, JW field represents a logical division 1DB" an 3D 1 "and" 0 "3D-MPROM element ; trapped 1E shows a 3D ^ EPROM element.

困2A-困2C表示一种3D-M核的电路符号、JMMt困和详细框困. 2A- 2C trapped trapped symbol represents one kind of 3D-M circuit core, JMMt sleepy and tired detailed block.

田3A -田3G描迷多种3IWVf核使用的电路块. Tin 3A - 3G field the circuit blocks described more fans 3IWVf nuclear use.

田4AA-困4AD解释首访时问的来源;困4BA-田4CC提供多种参考位线的设计;困4D为3D>ROM阵列中数据位线、嚷位线和定时位线的一种实现方法. Field 4AA- trapped 4AD when asked to explain the source of first visit; 4CC trapped 4BA- field design a variety of reference bit lines; 4D is trapped 3D> type of ROM data array bit line, bit line and shouting timing of the bit lines to achieve method.

困S表示一种3D-ROM核中各种信号的时序困, S represents one kind of timing difficulties 3D-ROM core trapped various signals,

曲6A-田6H表示多种3DcM (cached 3&M)及其读^. 6A- 6H Tian Qu represents more 3DcM (cached 3 & M) and read ^.

困7A -田7B表示一种采用平行编程的3D^EPROM;困7C表示一种具有外接编程电源的3D~EPROM. Trapped 7A - 7B shows a field of parallel programming using the 3D ^ EPROM; trapped 7C shows a power supply having an external programming 3D ~ EPROM.

田8AA-田8G描迷多种提离单位阵列容量的方法. Method arrays away from the unit capacity field 8AA- field 8G described more fans mentioned.

困9AA-困9CB描述多种3D^M缺陷. 9AA- trapped trapped 9CB describe various 3D ^ M defect.

困10A -田WB表示两种无缝3D4lOM元. Sleepy 10A - Tian WB represent two seamless 3D4lOM yuan.

困UAA-困11E,表示多种无缝3D-ROM元的工艺iW. UAA- trapped trapped 11E, represents more seamless 3D-ROM membered process iW.

图12A -田12B是两种准无缝3D-ROM元. FIGS 12A - 12B are two field quasi seamless 3D-ROM element.

困13表示一种3D^M纠错(ECC)电路. 13 shows a trapped 3D ^ M error correction (ECC) circuit.

困14A -田14DC表示多种3IKM冗余电路. Trapped 14A - 14DC field indicates more 3IKM redundancy circuit.

田ISA -田15C表示多种具有软件升級功能的 Tian ISA - Tian 15C show a variety of functions with a software upgrade

为痛便计,在本说明书中,如果一个困号缺应有的后緩,則表示它代表所有具有该后綴的困.如困9槺困9AA-困9CB;困9C指田9CA-困9CB. Pain meter is then, in the present specification, if after a number of difficulties due to lack of buffer, it indicates that it represents all of the difficulties with such difficulties suffix 9 Kang trapped 9AA- trapped 9CB;. 9C refers field 9CA- trapped trapped 9CB.

具体实施方式 Detailed ways

1.读写iUL 1. read iUL

本节以3D-ROM为例,以提离读写逸St为目的,对3IWVI晶体管层次的电路设计,尤其是对3D"M核、3DcM(c狄lied3D-M)以及编租电路的设计,做了进一步的完善.这里,3D>M 核是指3D"M辟列以及能将3D^M数振读出的:U本的周边电路.为了提高读速度,从电路的角度,最好能^U9读出放大器和4^棋式,并4Upt自定时;从系统的角度,最好能利用3DcM 中的eRAM来睡義31VM的首访时间.相应地,虽然羊个3D-M元的性能尚难于与常规存储元相比,然而,通过系统集成,其集体性能可以与常规存储器相比,甚至更好.为了提高写最好使用平行编程. This section 3D-ROM, for example, to write Yi St liftoff for the purpose of 3IWVI transistor level circuit design, especially design 3D "M nucleus, 3DcM (c Di lied3D-M) and encoding rent circuit, made further improvement here, 3D> M core refers 3D "M columns and the provision of 3D ^ M can read the number of vibration:.. U present in the peripheral circuit in order to improve the reading speed, from the perspective of the circuit, preferably sense amplifiers U9 and ^ 4 ^ chess problems, and self-timed 4Upt; from a system perspective, it is best to use the first visit 3DcM eRAM sleep time to sense 31VM accordingly, although a 3D-M sheep-membered performance. is hard in comparison with the conventional memory element, however, by a system integrator, which performance can be compared with a conventional collective memory, even better. in order to improve the write parallel programming is preferably used.

A. 3D^M核 A. 3D ^ M nuclear

困2A表示3D«M核0的读I/O端口. 3IKM核包舍3D"M阵列及其最基本的周边电路. 其输入偉号包括行地址AS 2以及读启动信号RD 4,输出信号包括输出数据DO8以及数据就缭信号RY6.这里未函出写I/0端口. 2A represents trapped 3D «M core 0 reads the I / O port. 3IKM core packet round 3D" M basic array and peripheral circuit. Wei input number comprising a row address AS 2, and 4, the output signal comprises a read enable signal RD DO8 output data signal and the data on the wind RY6. Functional not shown here, a write I / 0 ports.

闺2B是一种3D4lOM核0的基絲爾,它含有一个3D>ROM阵列0A、读出放大器(S/A) 块W、翻转电压(VM)产生电路块M、衧译码器12、位线使无效电路块18,、偏置电路块16 和地址寄存器121.其中,3D-ROM单位阵列0A含有iVwL条字线(20c…)和Wbl奈位栽(30c…).在字线和位线交叉处有二极管則表*逻辑"i",无二板管则表示逻辑"0"。 2B is a nuclear 3D4lOM Gui 0 Ji Sier, comprising a 3D> ROM 0A array, a sense amplifier (S / A) block W, inversion voltage (VM) generation circuit block M, Yu decoder 12, a bit invalid line enable circuit block 18 ,, a bias circuit 16, and address register block 121. wherein, 3D-ROM unit arrays comprising iVwL 0A word lines (20c ...) and bit planted Wbl Chennai (30c ...). in the word line and bit at the intersection of the line with a diode logic table * "i", said tube plate goes logic "0." 为了与以后将引入的参考位线(包括定时位线和哑位线等)区分,这里将存放有效数据的位线30a-30d称为数据位线。 For future reference bit lines and the introduced (including the timing of the bit line and dummy bit-line, etc.) to distinguish where the store valid data bit lines 30a-30d of bit lines referred to as data. S/A块18将位线上的小模拟信号放大成一逻辑信号8,它由S/A使能信号SE 5 控制并只在SE5高时才工作。 S / A small block 18 is amplified analog signal into a bit line logic signal 8, which allows the S / A and the control signal SE 5 only works when the high SE5. VM产生电路块14产生一翻转电压VM。 VM block generating circuit 14 generates a voltage VM inversion. 当S/A的偏置电压为Vw时,S/A对输入变化很敏感。 When the bias voltage S / A is Vw, S / A is sensitive to input changes. 行译码器12基于输入地址21选择一条字线。 21 selects the row decoder 12 based on the input address of a word line. 当RY6高时, 行译码器12和位线使无效电路块18,均失效,即所有的字线和位线都预充/放电至VM。 When high RY6, the row decoder 12 and the bit line invalidating circuit block 18, are invalid, i.e., all the word lines and bit lines are pre-charging / discharging to VM. 偏置电路块16通过一定时信号TS8T产生SE5。 The bias circuit block 16 TS8T SE5 generated by a timing signal. 在读开始时,SE5为低,所有数据S/A不工作。 When reading starts, SE5 low, all the data is S / A does not work. 当TS8T变高后,SE5被置高,所有数据S/A进行取样。 When TS8T becomes high, SE5 are set high, all the data of S / A is sampled. 该取样过程直到所有输出8均变为有效输出为止。 The sampling process until all 8 are output until the output becomes valid. 然后RY6被送出,完成一个读周期。 RY6 is then sent out to complete a read cycle. 3D-ROM的读时序关系由图5描迷。 3D-ROM read timing relationship of FIG. 5 described by the fans.

在大部分读周期中,位线上的电压升幅不足以触发其S/A。 Most read cycle, the bit line voltage increases enough to trigger its S / A. 如果这时所有的S/A都处于工作状态,则它们会消耗掉大量电能,但它们的输出却是无效的。 If at this time all of the S / A are in working condition, they consume a lot of power, but their output is invalid. 最好这时只留下少量S/A 处于工作状态,它们检测其位线上的电压变化。 Leaving only a small amount of time is preferably S / A is in operation, which detects a voltage variation of its bit lines. 只有当它们发现该电压变化足够大时,别的S/A才被打开并取样。 They found that only when the voltage change is large enough, the other S / A was only open and sampled. 相应地,大部分S/A只在读周期的一小部分时间内工作,这可以降^f氐能耗。 Accordingly, most of the S / A work only during a fraction of the time of the read cycle, which can reduce energy consumption Di ^ f. 这就是自定时的一个目的。 It is an object of self-timed.

图2C表示一种自定时的实现方法。 FIG 2C shows a self-timing method implemented. 在3D-M阵列0A中增加一第一定时位线30T。 Adding a first timing bit lines 30T in the 3D-M in array 0A. 它最好为最远离任何地址解码器12的位线,同时它和每条与之相交的字线(20a…)之间有一二极管连接(laT...)。 It is most preferably away from any bit line address decoder 12 while a diode connection (LAT ...) between it and the word lines (20a ...) of each intersect. 在读过程中,其上的电压变化速度最好比最慢的数据"1"位线还要慢。 In the read process, the voltage change of the speed ratio of which is preferably in the slowest data "1" bit line slower. 这样,当第一定时位线30T上的电压能触发其S/A17T时,所有数据'T'位线上的电压都应已大到足以能够触发其S/A 17a-17d的程度。 Thus, when the voltage on the first bit line 30T trigger timing of its S / A17T, all data 'T' should be the bit line voltage is large enough to be able to trigger the extent of its S / A 17a-17d of. 这时才打开数据S/A 17a-17d进行取样。 In this case only the Open Data S / A 17a-17d is sampled.

图2C还描述了S/A块18、偏置电路块16、行译码器12和位线使无效电路块18,。 2C also described S / A block 18, a bias circuit block 16, a row decoder 12 and the bit line invalidating circuit block 18 ,.

S/A块18含有多个数据S/A 17a-17d和第一定时S/A 17T,它们分别将数据位线和第一定时位线上的信号放大。 S / A data block 18 contains a plurality of S / A 17a-17d and the first timing S / A 17T, respectively, the signal timing of the data bit lines and the bit lines of the first amplification. S/A(17a…)在与之相连的位线上的电压变化超过其阈值电压Vr时, 输出翻转。 When S / A (17a ...) the voltage variation on the bit line connected thereto exceeds its threshold voltages Vr, the output inverted. 这里,数据S/A17a-17d由SE5控制,它们只在SE5高时取样,这样可以降低能耗。 Here, the data S / A17a-17d by the control SE5, they are only sampled at high SE5, lower power consumption. 第一定时S/A17T在读时一直对其位线30T上的电压进行监控,故其偏置信号5T在读过程中恒定。 First timing S / A17T been monitor its voltage on the bit line when reading 30T, so the bias signal is set at read Cheng Zhongheng 5T.

偏置电路块16根据第一定时S/A17T的输出8T决定SE5的大小。 Block 16 determines the size of the bias circuit SE5 8T first timing based on an output S / A17T in. 它含有一定时电路15T和一偏置产生电路15B。 A timing circuit comprising a bias generating circuit 15T and 15B. 定时电路15T控制时序信号5d,偏置产生电路15B产生相应的偏置信号SE5和5T。 A timing control circuit 15T timing signal 5d, the bias generation circuit 15B generates a corresponding bias signal SE5 and 5T. 当5d置低时,SE5置高。 5d is set when the low and high set SE5.

行译码器12含有一个标准行译码器11C和多个行译码器使无效电路块lla-lld。 The row decoder 12 comprises a row decoder 11C standard and a plurality of row decoder enabling circuit block is invalid lla-lld. 当RY 6 为高时,译码器12失效,所有的字线都与Vm7短接。 When RY 6 is high, decoder 12 fails, all the word lines are shorted and Vm7. 当RY6为低且20a,为高时,字线与Vk相接,即进入读状态。 When RY6 is low and 20a, it is high, and the word line Vk phase, i.e. into the reading state.

位线使无效电路块18,通过开关(即晶体管17a,-17d,)将所有位线与VM7短接,这些开关17a,-17d,的控制端均与同一信号RY6相连。 Invalid bit line enable circuit block 18 by the switch (i.e., transistors 17a, -17d,) and all the bit lines VM7 short, these switches 17a, -17d, the control terminal are connected to the same signal RY6. 当RY6为高时,所有的位线都与Vm7短接。 When RY6 is high, and all the bit lines are shorted Vm7. 位线使无效电路块18,使全读模式得以实现。 Invalid bit line enable circuit block 18, so that the entire read mode can be achieved.

以下描述图2B和图2C中3D-M核0的一种读出流程,其时序图见图5。 2B and 2C one kind of 3D-M core 0 reads out the process is described as follows, which is a timing chart of Figure 5. 读时最好使用全读模式,即在一次读时将一条字线上的所有存储元中的数据同时读出。 Preferably used the full read read mode, i.e., when a read data element all stored in one word line are simultaneously read out. 3D-M核0最初处于默认状态,即所有的字线和位线都偏置于VM,且所有的数据S/A均不取样。 3D-M core initially 0 in the default state, i.e., all the word lines and bit lines are biased to the VM, and all the data of S / A are not sampled. 在RD 4的上升沿,寄存器121捕获到AS 2 (如"00")并将其送到行译码器12,然后与该地址相对应的字线20a上的电压升到读电压VR并对每一条与它有二极管连结的位线(30a…)进行充电。 RD 4 at the rising edge of the capture register 121 to the AS 2 (such as "00") and to the row decoder 12, then the voltage on the word line address corresponding to the read voltage VR 20a rises and each with its bit lines (30a ...) connected to the charging diode. 此时,所有的数据S/A17a-17d均不取样,但第一定时S/A 17T—直在监测其位线30T上的电压。 At this time, all data is S / A17a-17d are not sampled, but the timing of the first S / A 17T- directly monitoring the voltage on its bitline 30T. 当该电压变化超过VT时,输出8T变高。 When the change in voltage exceeds VT, the output becomes high 8T. 相应地,SE5被置高,所有的数据S/A17a-17d 开始对它们各自相连的位线电压进行取样。 Accordingly, SE5 is set high, all the data S / A17a-17d start their respective bit line voltage is connected to sampling. 在产生输出DO 8后,SE 5置低,数据S/A l"7a-l"7d 被断开;同时字线20a也没有必要再保持在VR。 After generating the output DO 8, SE 5 is set low, the data S / A l "7a-l" 7d is turned off; the same word line 20a is also no need to remain in VR. 相应地,RY6置高,3D-ROM核0回到默认状态。 Accordingly, RY6 is set high, 3D-ROM core back to the default state 0. 这样完成一个读周期T。 This completes a read cycle T. 图3A -图3G描迷多种3D-M核使用的各种电路。 FIG 3A - FIG. 3G various circuits described more fans 3D-M nuclear use. 困3A -图JCCJ描述多种差分S/A。 Trapped 3A - FIG JCCJ differential describe various S / A. 图3DA -图3DD描述第二定时位线及其一种定时电路15T。 FIG 3DA - FIG 3DD bit line and the second timing described in a timed circuit 15T. 图3E -图3G描述一种偏置产生电路15B、行译码使无效电路lla和Vw产生电路14。 FIG 3E - 3G FIG describes a bias generating circuit 15B, the row decoder circuit lla invalidate generating circuit 14, and Vw.

由于S/A要求具有极强的抗干扰性,最好能使用差分S/A。 Since the S / A is required to have a strong anti-interference, it is best to use a differential S / A. 差分S/A除一个输入为被读位线的电压,它还需要一参考电压。 Differential S / A to be input in addition to a bit line read voltage, it requires a reference voltage. 该参者电压可以通过一哑位线来提供。 The reference voltage may be provided by via a dummy bit line. 图3A表示两条被读位线(30a、 30z>、 一哑位线30D以及它们与差分S/A(17a、 17z)之间的连接。哑位线30D 可以被多个S/A共享,在与其相交的每条字线处都有一二极管laD。在读操作中,吸位线30D 上的电压最好介于数据"1"位线电压和数据"0"位线电压之间。 3A shows the connection between the two read bit lines (30a, 30z>, 30D and a dummy bit line differential thereof with S / A (17a, 17z). 30D dummy bit line may be a plurality of S / A share, at the word line intersecting each diode has a LAD. in the read operation, the voltage on the bit line 30D is preferably interposed suction data between "1" and the bit line voltage data "0" bit line voltage.

图3BA是第一差分S/A核17C的电路图。 FIG 3BA is a circuit diagram of the first differential S / A of the core 17C. 它使用NMOS对51a、 51b作为输入晶体管, 以及镜像对称的PMOS对51d、 51e作为负载。 It uses NMOS PMOS pair 51a, 51b as the input transistors, and mirror-symmetrical to 51d, 51e as a load. 其电源电压为Vs/A和GND。 Which power supply voltage is Vs / A and GND. 注意到,Vs/A 可能不同于芯片电源电压。 Notes, Vs / A may differ from the chip supply voltage. 偏置信号B通过NMOS 51c来控制尾电流。 Bias signal B to control the tail current through the NMOS 51c. 图3BB表示一使用第一差分S/A核17C的数据S/A。 FIG 3BB using a first differential represents a S / A 17C nucleus data S / A. 它还含有一由NMOS51g和反相器51h构成的锁存器17L。 It also contains a latch composed of inverters and NMOS51g 51h 17L. 在锁存信号5,的控制下,NMOS51g在SE5变高时关闭,但先于SE5变低时打开。 In the latch signal 5, the control, NMOS51g SE5 becomes high when closed, but is opened at the time of the first low SE5. 这样, 即使S/A核17C不取样,输出8a仍保持不变。 Thus, even when the S / A 17C nucleus is not sampled output 8a remains unchanged. 图3BC表示一使用第一差分S/A核17C的第一定时S/A。 FIG. 3BC using a first differential represents a S / A 17C nucleus first timing S / A. 该定时S/A始终取样。 The timing of S / A is always sampled. 反相器51i、 51j组成一锁存器17TL, 511、 51m对波形进行调整。 An inverter 51i, 51j form a latch 17TL, 511, 51m of the waveform is adjusted. 在每次读周期开始时,NMOS51k在RD4控制下,将锁存器17TL清零(平衡化)。 At each read cycle begins, NMOS51k RD4 under control, the latch is cleared 17TL (equilibration).

图3CA是第二差分S/A核17C,的电路图。 FIG 3CA second differential S / A core 17C, a circuit diagram. 与图3BA相比,它使用交叉耦合的PMOS 对52d、 52e作为负载。 Compared with FIG. 3BA, it uses a cross-coupled PMOS pair 52d, 52e as a load. 偏置信号B通过NMOS 52c来控制尾电流。 Bias signal B to control the tail current through the NMOS 52c. 当B《氐的时候,S/A核的输出o+,o-保持其在B变低前的水平,故该S/A核是一锁存器。 When B "when Di, S / A nuclear output o +, o- maintain its low levels prior to B, so that the S / A is a latch core. 图3CB表示另一使用第二差分S/A核17C,的数据S/A。 FIG 3CB shows another use of a second differential S / A core 17C, the data of S / A. 反相器52f用来调整波形。 The inverter 52f is used to adjust the waveform. 图3CC表示另一使用第二差分S/A 核17C,的第一定时S/A。 FIG 3CC shows another use of a second differential S / A core 17C, the timing of the first S / A. 该定时S/A始终取样。 The timing of S / A is always sampled. 在每次读周期开始时,NMOS52g在RD4 控制下,将差分S/A核17C,清零(平衡化)。 At each read cycle begins, NMOS52g RD4 under control, the differential S / A 17C nucleus, is cleared (equilibration).

图3DA-图3DD表示多种定时电路15T的设计。 FIG 3DA- FIG 3DD 15T showing various timing circuit design. 定时电路15T与偏置产生电路15B结合,可以控制数据S/A的偏置电压SE5。 A timing circuit 15B and the bias generating circuit 15T binding, may control the data S / SE5 A of the bias voltage. 当8T变高后,它抬高SE5并让所有的数据S/A开始取样;经过一段延迟,即所有数据S/A均已得到有效输出后,它切断SE5,进而结束数据S/A的取样。 When 8T becomes high, and it is raised so that all data SE5 S / A sampling starts; after a delay, i.e., all the data after S / A output have been effective, it cuts off SE5, and thus the end of the sample data S / A of . 为了实现该延迟,图3DA的实施例在3D-M阵列中增加了一第二定时位线30T,, 其S/A17T,控制延迟的大小。 In order to achieve this delay, the embodiment of FIG 3DA 3D-M increased in a second array of bit line 30T ,, the timing of its S / A17T, controls magnitude of the delay. 这里,第二定时位线30T,在所有与它相交的字线处均有一二极管laT,,但其S/A 17T,较一般的数据S/A慢。 Here, the timing of the second bit lines 30T, have a diode laT in all the word lines intersecting at its ,, but the S / A 17T, more general data S / A slower. 当其输出8T,翻转时,所有的数据S/A的输出应已就绪,故可以结束数据S/A的取样。 When the output 8T, when inverted, all the data outputting S / A to be ready, it is possible to end the sample data S / A's. 很明显,这也能降低能耗。 Obviously, this can also reduce energy consumption. 注意到,第一定时位线30T控制数据S/A取样的开始,第二定时位线30T,控制数据S/A取样的结束。 Began to notice, the first timing control data bit lines 30T S / A sampling, the timing of the second bit line 30T, the end of the control data S / A sampling. 图3DB表示一种第二定时位线30T,使用的S/A 17T,的电路图。 FIG 3DB shows a timing of a second bit lines 30T, S used / A 17T, a circuit diagram. 与一般数据S/A (图3BA)相比,其输出端o可以有一多余负栽电容51C,也可以是其输入或负栽晶体管51a,、 51b,、 51d,、 51e,的沟道较长,等等。 Compared with the general data of S / A (FIG. 3BA), the output terminal o plant may have a surplus of negative capacitor 51C, which may be a plant or negative input transistor 51a ,, 51b ,, 51d ,, 51e, the longer channel ,and many more. 这样,该S/A 17T,较一般的数据S/A慢。 Thus, the S / A 17T, more general data S / A slower.

图3DC是一种定时电路15T的电路图。 FIG 3DC is a circuit diagram of a timed circuit 15T. 第二定时位线30T,的输出8T,可直接用作RY 6, 它与第一定时位线30T的输出8T结合,产生偏置控制信号5d,然后5d通过偏置产生电路15B控制SE5 (参见图3E)。 Second timing bit lines 30T, 8T output, can be used directly as RY 6, it is combined with the bit line 30T 8T outputs a first timing control signal to generate a bias 5d, and 5d generating circuit 15B controls SE5 (see, by the bias Figure 3E). 图3DD是另一种定时电路15T的电路图。 FIG 3DD is a circuit diagram of another timing circuit 15T. 与图3DC相比较, 它有一为外界电路(如在3DiM中但在3D-M外的电路)提供的状态控制信号6E。 Compared with FIG 3DC, it is an external circuit (e.g., but in the circuit outside the 3DiM 3D-M) of the state control signals provided 6E. 当6E为高时,3D-M进入默认状态(所有字线和位线接VM),不能进行任何操作,这时,3D-M处于"软断电"状态。 When 6E is high, 3D-M default states (all word lines and bit lines connected to the VM), can not carry out any operation, this time, 3D-M in the "soft off" state. 在"软断电"时,3D-M不消耗电能;但一旦6E被置低后,3D-M能快速进入工作状态。 When "soft power off", 3D-M do not consume energy; but once 6E is set low, 3D-M into operation quickly. 与"硬断电,,(即所有字线和位线接地)相比,3D-M能更快地"苏醒", 即恢复工作的速度更快。该设计可以用在多种应用中,如字线冗余电路和机动码电路(在该3D-M被读字线为缺陷位线或需要被升级替换时),或基于三维存储器的集成电路测试(在被测试电路正常工作时)。 And "hard off ,, (i.e., all the word lines and the bit line is grounded) compared, 3D-M faster to" wake up ", i.e., return to work faster. This design may be used in a variety of applications, such as word line redundancy circuit and motor code circuit (a word line is read for the defective bit line needs to be replaced or upgraded in the 3D-M), or based on a three-dimensional integrated circuit memory test (normal working hours in the circuit under test).

7图3E是--偏置产生电路i5B。 FIG 7 3E is - bias generating circuit i5B. 电流源53a可以是片内电流源或片外电流源。 The current source 53a may be an on- chip current source or a current source. 偏置电乂五5T由一采取二极管连接的NMOS53b产生。 Qe five bias 5T taken by a diode-connected NMOS53b generated. 当5d为低时,5T被传送至SE5。 When 5d is low, 5T transferred to SE5. 当5d为高时, SE 5接地。 When 5d is high, SE 5 is grounded.

图3F是一行译码器使无效电路lla。 FIG 3F is a valid row decoder enabling circuit lla. 当RY 6高时,NMOS 54b被接通,字线20a与VM 7短接。 When RY 6 high, NMOS 54b is turned on, the word lines 20a and VM 7 short. 当20a'高且RY6为低时,PMOS54c被接通,字线20a与读电压Vr短接。 When 20a 'when the high and low RY6, PMOS54c is turned on, the read word line 20a and the shorting voltage Vr. 注意到, VR可能不同于芯片的电源电压Vdd (参见图8CA)。 Notes, VR may be different from the chip supply voltage Vdd (see FIG 8CA).

图3G是一VM产生电路14。 FIG 3G is a VM generating circuit 14. 它使用与S/A相同的S/A核55a,并含有一稳压器(含运放器55b和驱动NMOS 55c ) 。 It uses the same S / A to S / A core 55a, and containing a regulator (including an operational amplifier 55b and a drive NMOS 55c). S/A核的所有输入输出被短接,从而产生翻转电压VM 7'。 S / A nuclear all input and output are shorted, thereby generating inverted voltage VM 7 '. 一般说来,VM~Vs/A/2。 Generally, VM ~ Vs / A / 2. 稳压器使Vw产生电路14的输出保持在VM,并提供足够大的电流,故Vw7是一稳压直流电源。 Vw output voltage regulator enable generating circuit 14 is maintained in the VM, and to provide a sufficiently large current, it is a regulated DC power supply Vw7.

图4AA-图4AD描述位线电压的时序特性。 FIG 4AA- FIG 4AD described bit line voltage timing characteristics. 如图4AA所述,当字线20y上的电压被升至Vr后,字线20y开始通过二级管lyj对位线30j充电„位线30j上的电压从其初始值(Vw) 升高,其升高的速度由二极管电流对位线30j的寄生电容充电的速率来决定。 一般说来,位线寄生电容ljC包括:字线20x和位线30j的耦合电容lj0 (对应于"0"存储元)、反向偏置的二极管lzj的结电容lj2 (对应于"1"存储元)、与相邻位线30i和30k之间的耦合电容lj3和lj4、与别的互连线层之间的耦合电容ljl。位线30j上的电压在读过程中高于VM, 而除被读字线20y外的别的字线20x、 20z均处于VM,故有漏电流通过二极管lzj从位线30j 流到别的字线20z上。该漏电流对位线30j产生的放电效果与字线20y产生的充电效果相反。 FIG said 4AA, when the voltage on the word line 20y is raised Vr, the word line is started by diode 20y lyj charging the bit line 30j "the voltage on the bit line 30j rises from its initial value (Vw), which is determined by the rate of rise of the diode current charge the parasitic capacitance of the bit line 30j rate general, the bit line parasitic capacitance ljC comprising: a word line and a bit line coupling capacitance 20x lj0 30j (corresponding to a "0" is stored between the element), a reverse-biased diode junction capacitance lzj LJ2 (corresponding to the coupling capacitance between lj4 lj3 and "1" memory elements), and the adjacent bit lines 30i and 30k, and other interconnect layers coupling capacitance ljl. 30j voltage on the bit line during a read is higher than VM, the read word line in addition to the other word lines 20y 20x, 20z are in the VM, so that leakage from the bit line current flows through the diode 30j lzj opposite the other word line 20Z. the leakage current is generated in the bit line 30j discharge effect produced by the word line 20y charging effect.

图4AB是一用来模拟位线电压时序特性的等效电路。 FIG 4AB is an equivalent circuit used to simulate the bit line voltage timing characteristics. 字线30j上的电压变化AVb由三个因素决定:二极管lyj、寄生电容ljC和等效二极管ljD。 AVb voltage variation on the word line 30j is determined by three factors: a diode lyj, and an equivalent parasitic capacitance diode ljC ljD. 等效二极管ljD是由ai个二极管并联组成。 Ai is equivalent diode ljD diodes connected in parallel. 这里,"是所有与位线30j相连、并处于反向偏置的二极管的数目。在最坏的读模式下,/J等于yVwL-l。当二极管lyj的正向电流等于等效二极管ljD的反向电流时,AVb Here, "all connected to the bit line 30j, and the number of diodes in the reverse biased. In the worst read mode, / J is equal yVwL-l. Lyj when the diode forward current is equal to the equivalent diode ljD when the reverse current, AVb

达到静态平衡电压AVbe。 Reach static equilibrium voltage AVbe.

图4AC表示二极管lyj的电流电压(IV)特性。 FIG 4AC represents lyj diode current-voltage (IV) characteristics. 其正向电流/y(V) If大于其反向电流/,(V) lr。 The forward current / y (V) If greater than the reverse current /, (V) lr. 可以用图像法来找到最坏读模式下的静态平衡电压AVbe。 Image method can be used to find the static equilibrium voltage AVbe worst reading mode. 首先将反向IV曲线乘以然后将它向右移VR-VM。 First, reverse IV curves it to the right and then multiplying the VR-VM. 这样得到的曲线lrs与If的交点即为最坏读模式下的静态平衡电势AVbe。 If the intersection curve lrs thus obtained is the worst static equilibrium potential read mode AVbe. 写成方程的形式, Written in the form of equations,

/KVR-VM-AVbe) = (iVWL-l)x/r(AVbe) «7VWLx/r(AVbe) eq. (1) / KVR-VM-AVbe) = (iVWL-l) x / r (AVbe) «7VWLx / r (AVbe) eq. (1)

图4AD是该位线电势的时序图。 FIG 4AD is a timing diagram of the bit line potential. 位线电势升值AVb最终达到其静态平衡电压AVbe。 The bit line potential appreciation AVb eventually reach its static equilibrium voltage AVbe. 在时刻t, AVb超过VT, S/A的输出成为有效输出,故T为首访时间。 At time t, AVb than the VT, the output of S / A output becomes valid, so the access time T headed. 对位30j来说, Para 30j, the

T30j ~ VTxC30j//f eq. (2) T30j ~ VTxC30j // f eq. (2)

才艮据图2C和图3A,第一定时位线和哑位线的时序特性与数据位线不同。 It was Gen 2C and 3A, the timing of the timing characteristics of the first bit line and the dummy bit lines and data bit lines are different. 相应地,它们的设计最好与数据位线不同。 Accordingly, they are preferably designed with different data bit lines. 图4BA -图4CC解释并提供了几种设计。 Figure 4BA - Figure 4CC explain and provides several design. 图4BA表示一数据位线30a和一参考位线30r。 FIG 4BA 30a represents a data bit lines and a reference bit line 30r. 参考位线30r可以是一第一定时位线或哑位线。 30r reference bit line may be a first timing of the dummy bit line or bit lines. 在读过程中, 参考位线30r上的电压变化AV術最好应慢于数据"I"位线30a上的电压变化AV30a。 In the read process, the voltage variation AV operation on the reference bit line 30r should preferably be slower than the data "I" AV30a voltage variation on the bit line 30a. 对于哑位线来说,最好AV3o广AV;soa/2 (图4BB )。 For the dummy bit-line, it is best AV3o wide AV; soa / 2 (FIG. 4BB). 根据eq. (2),可以通过增加参考位线30r上的寄生电容lrC来达到该目的。 According to eq. (2), this object can be achieved by increasing the parasitic capacitance lrC on the reference bit line 30r. 图4CA -图4CC表示了几种实现方法。 FIG 4CA - FIG 4CC shows several implementations.

图4CA表示第一参考位线30r。 FIG 4CA represents a first reference bit line 30r. 它比数据位线30a要宽,因此它有较大的寄生电容。 30a which is wider than the data bit lines, so it has a large parasitic capacitance. 图4CB表示第二参考位线30r。 FIG 4CB shows a second reference bit line 30r. 它包括两条相连的次位线30rl和30r2。 It includes two sub bit lines connected 30rl and 30r2. 它们和一般的数据位线30a有相同宽度。 And their general data bit lines 30a have the same width. 次位线30rl与每条和它相交的字线有二极管连接,而次位线30r2没有和任何字线有二极管连接。 30rl times the bit lines coupled to each diode and its intersecting word lines and bit lines 30r2 times without any word line and a diode connected. 相应地,参考位线30r上的寄生电容较大,电压上升速率较慢。 Accordingly, the parasitic capacitance of the reference bit line 30r is large, the voltage rises at a slower rate. 注意到,次位线30r2的长度可以通过版图设计来调节。 It noted, the length of the bit lines 30r2 times can be adjusted by the layout. 图4CC表示第三参考位线30r,它与一物理电容lrO相连。 FIG 4CC a third reference bit lines 30r, which is connected to a physical capacitor lrO. 物理电容lrO可以是MOS电容(包括S/A的输入电容)、金属电容或别的常规电容。 MOS capacitor may be physically lrO capacitance (input capacitance comprises S / A's), or other conventional metal capacitor capacitance. 这些电容也能延迟首访时间T。 These capacitors can also delay the first visit time T.

图4D表示在一3D-M阵列中数据位线、哑位线和定时位线的设计。 4D shows a design of the 3D-M array of data bit lines, the dummy bit line and the timing of the bit line. 在该实施例中有两个位线组D1、 D2,每个位线组中的所有数据位线共用一条哑位线30D。 There are two bit lines D1 In this embodiment, D2, all the data bit lines in each bit line group share a dummy bit-line 30D. 该哑位线30D含有两条次^立线30D1, 30D2。 The dummy bit line 30D containing two secondary lines Li ^ 30D1, 30D2. 在3B-M阵列中还有第一定S.]^位线30T和作为它参考位线的哑定时位线30TD。 3B-M in the first array as well as some S.] ^ Bitline 30T as its reference bit line and dummy bit-line timing of 30TD. 第一定时位线30T含有两条次位线30T1、 30T2,哑定时位线30TD含有4条次位线30TD1-30TD 4。 First timing bitline 30T order bit lines comprising two 30T1, 30T2, the timing of the dummy bit line 30TD containing four times the bit lines 30TD1-30TD 4. 该实施例还含有第二定时位线30T,,它只含一条次位线,但其S/A 17T, 较慢。 The second embodiment further comprises a timing bit line only contains one 30T ,, order bit lines, but the S / A 17T, slower. 很明显,哑位线30D和第一定时位线30T上的电压变化慢于数据位线30a,哑定时位线30TD上的电压变化更慢。 Obviously, the voltage variation on the bit line 30D and the dummy bit line 30T a first timing slower than the data bit line 30a, the voltage variation on the timing of the dummy bit line 30TD slower.

实际上,哑位线30D和第一定时位线30T可以采用一些简单设计。 In fact, the dummy bit lines 30D and the timing of the first bit line 30T simple designs can be used. 因为哑位线30D需要带动大量的数据S/A,这些数据S/A的输入电容使哑位线上的电压变化变慢很多,故哑位线30D可只使用一条次位线。 Since the dummy bit line 30D amount of data required to drive S / A, the data S / A so that the input capacitance of the dummy bit line voltage changes much slower, so that the dummy bit line 30D can be used only once a bit line. 另一方面,第一定时位线30T也可只含有一条次位线。 On the other hand, the timing of the first bit line 30T may contain only a sub bit line. 这时,其S/A最好较慢,但应快于第二定时位线30T,的S/A。 In this case, its S / A is preferably lower, but should be faster than the timing of the second bit lines 30T, the S / A.

图5是一3D-M核0中各种信号的时序图„在时刻T30a,数据位线30a上的电压已超过其S/A 17a的VT。但因为这时S/A未打开,故并无有效数据输出。在时刻tl,第一定时位线30T 触发其S/A17T,这表示所有的数据S/A可开始取样。这时,SE5被送出,所有的数据S/A 开始工作。在时刻T,第二定时位线30T,触发其S/A17T,时,这表示所有的数据S/A均完成取样。所有的数据S/A被断开。这样完成一个读周期。 FIG 5 is a 3D-M core 0 in a timing chart of various signals "at time T30a, the data voltage on the bit line 30a has exceeded its S / A 17a of VT., But because when S / A is not open, and therefore no valid data output. at time tl, a first timer which bitline 30T trigger S / A17T, which means that all data S / a sampling may start. in this case, SE5 is sent, all the data of S / a to work in time T, the timing of the second bit lines 30T, which trigger S / A17T, time, which means that all data S / a samples are completed. All S / a is turned off. this completes a read cycle.

Eq. (2)和图4AA为3D-M提供了一种设计方针。 Eq. (2) and provides a design guideline 4AA is 3D-M. 为了缩短首访时间,最好能减少位线的寄生电容ljC。 In order to shorten the time of the first visit, it is best to reduce the parasitic capacitance ljC bit lines. 由于位线寄生电容的很大一部分来自于位线边壁之间的耦合电容lj3、 lj4, 3D-R0M最好能使用较薄的位线。 Since a large part of the bit line parasitic capacitance from the coupling capacitance between the bit lines lj3 side walls, lj4, 3D-R0M best to use a thin bit line. 虽然较薄的位线会有较大的串联电阻,但由于决定首访时间的主要电阻来自3D-ROM膜,故使用较薄位线引起的电阻增加并不会对首访时间有太多影响。 Although there is not much of an impact will be greater the thinner the bit line series resistance, since the primary resistance determined from the first time visit film 3D-ROM, it is a resistance increase due to the bit lines have a thinner first visit time . 另外,在全读模式时,字线要为所有位线提供读电流,其电流一般较大。 Further, when the full read mode, the read word line current to be supplied to all the bit lines, the current is generally large. 为了减少寄生电压降和克服电迁移(e,ectro-migration)等问题,3D-M最好能使用较厚的字线。 In order to reduce the parasitic voltage drops and overcoming electromigration (e, ectro-migration) and so on, 3D-M best word lines thicker. 图2A表示一种使用较厚字线和较薄位线的3D-ROM结构。 FIG 2A shows a configuration using the 3D-ROM word lines and thicker thin bit line.

B. 带数据緩冲区的3D-M(3DcM) B. data buffer with 3D-M (3DcM)

单个3D-M元的性能尚难于与常规存储元相比。 3D-M-membered single performance is hard in comparison with the conventional memory element. 通过系统集成,3D-M的潜能才能被完全开发出来。 Through systems integration, 3D-M's potential to be fully developed. 从集体性能来说,3D-M可以与常规存储器相比,甚至更好。 , 3D-M from the collective performance is comparable to the conventional memory, or even better. Cached 3D-M(简称为3DcM )是3DiM的一个典型例子。 Cached 3D-M (referred to as 3DCM) is a typical example of 3DiM. 它含有一3D-M和一与之集成的嵌入式RAM( eRAM ), 并通过隐藏3D-M的首访时间来提高其读取速度。 It contains a 3D-M and integrated with an embedded RAM (eRAM), and to improve their reading speed 3D-M by hiding the first time visit. 对外部电路来说,3DcM可被视为一单独存储器:eRAM形成在衬底里,3D-M堆叠在eRAM之上,且eRAM中保留了3D-M数据的一个备份。 For the external circuit, 3DcM can be considered as a separate memory: in eRAM formed in the substrate, 3D-M are stacked on top eRAM, and retained in a backup eRAM 3D-M data. 当系统从3DcM中寻找数据时,它先从eRAM中寻找,如"命中",则直接从eRAM中读;如"未命中",则要从3D-M中读数据,且将一个备份存放在eRAM中。 When the system is looking for data from 3DcM, start eRAM find it, such as "hit", it is read directly from the eRAM; as "miss", the 3D-M to read data from, and stored in a backup eRAM in. 相应地,eRAM是3D-M的cache。 Accordingly, eRAM of a cache 3D-M. 如"命中",3DcM的首访时间就是eRAM的首访时间,夕卜界无法察觉3D-M的首访时间;如"未命中",3DcM的首访时间与3D-M相近。 Such as "hit", the first time to visit is the first visit 3DcM time eRAM, the eve of his first visit to BU community can not detect 3D-M of time; as a "miss", the first visit time 3DcM similar to the 3D-M. 如果eRAM 容量足够大,命中的几率较大,这样可以减少平均首访时间。 If eRAM capacity is large enough, it hits the greater risk, thus reducing the average time of the first visit. 3DcM的带宽一般由eRAM控制。 3DcM bandwidth is generally controlled by eRAM.

3DcM的读操作与计算机中高速緩冲存储器的操作类似。 Similar operation 3DcM cache read operation in the computer. 图6A -图6G对3DcM的细节, 尤其是其内部数据流,做了更详细的描述。 FIG 6A - 6G FIG 3DcM details, particularly its internal data stream, a more detailed description made. 图6A表示一种3DcM OC的I/O端口,它包括输入地址AS73、 3DcM读启动信号cRD75、 3DcM数据就绪信号cRY 77、时钟信号CK 71 和数据输出DO 79。 FIG 6A shows a 3DcM OC of I / O ports, including an input address AS73, 3DcM read enable signal cRD75, 3DcM data ready signal cRY 77, the clock signal CK 71 and a data output DO 79.

图6B是一种3DcM0C的框图。 6B is a block diagram of a 3DcM0C. 它含有3D-M核0、列译码器70、 eRAM72、控制电路块74和读出选择块76。 It contains 3D-M core 0, a column decoder 70, eRAM72, control circuit block 74 and the readout selection block 76. 在此特例中,3D-M核0的大小是1024x1024。 In this particular case, the size of the 3D-M core 0 is 1024x1024. 在读操作时,根据行地址2 ( AS 73的前10位【13:4】)从3D-M阵列中选择一页数据(1024位)并将它送到输出8。 In the read operation, according to a row address 2: Select a data (1024) and outputs it to the 3D-M 8 from the array (top 10 [134] of the AS 73). 这里, 一页3D-M数据是指3D-M阵列中一条字线上的所有数据。 Here, a 3D-M data refers to all data in a 3D-M word lines of the array. 列译码器70再根据列地址2c ( AS73的末4位【3:0j)从该输出页(1024位)中选中一个字(64位)。 Column decoder 70 then (AS73 the last 4 [3: 0j) 2c select a column address word (64) from the output page (1024 bits). 选中的字和与之对应的地址被复制到eRAM 72中。 The selected word and the corresponding address is copied into eRAM 72. 控制电路块74控制3D-M核0到eRAM 72之间的数据流动。 The control circuit 74 controls the block 3D-M core flow of data between 0 to 72 eRAM. 熟悉本技术的人士可以很容易地根椐图6D的数据流程设计出控制电路块74。 Those skilled in the art can readily noted in FIG. 6D design a data flow control circuit block 74. 读出选择块76决定输出数据79是来自列译码器70或来自eRAM 72。 Selection block 76 determines the readout data output from the column decoder 79 or 70 from eRAM 72.

9图6C表示一种eRAM 72。 FIG 6C shows a 9 eRAM 72. 它-念-有一-漆写使能端RAV' 74r和命屮/未命中输出端H/M 72h。 It - read - a - lacquer write enable terminal RAV '74r and life Che / miss output H / M 72h terminal. 它还含有eRAM数据块72D和一eRAM标签块72T。 It also contains a eRAM block 72D and block eRAM label 72T. eRAM数据块72D储存3D-M数据, eRAM标签块72T的每行存储与它对应的eRAM数据行中数据的地址标签。 eRAM block 72D 3D-M data store, each row of memory address tag block eRAM tag 72T with its corresponding data in the row eRAM data. 在该实施例中, eRAM数据块72D的大小是64x64, eRAM标签块72T的大小是8x64。 In this embodiment, the size of the data block eRAM 72D is 64x64, the size of the label block eRAM 72T is 8x64. AS 73【13:6j的前8 位2a存储在eRAM标签块72T中,AS 73【5:0j的后6位被用作eRAM 72的列地址2b。 AS 73 [13: 8 2a before 6j stored in the label block 72T in eRAM, AS 73 [5: 0j 6 bits are used as the column address 72 eRAM 2b. 该eRAM 72还有一比较器72C。 The eRAM 72 there is a comparator 72C. 在读操作时,它将eRAM标签块72T中的地址标签72to与地址2a比较。 In the read operation, the address tag 72to the address tag block 72T will eRAM in Comparative 2a. 如果它们相同,即命中,则输出72h为高;否则,72h为低。 If they are identical, i.e. a hit, then the output is high 72h; otherwise, low 72h.

图6D描述3DcM的一种读操作。 FIG. 6D describes a reading operation of 3DcM. 首先,在接受到cRD 75后,AS 73被送到eRAM 72, eRAM 72进入读模式(步骤91 )。 First, after receiving cRD 75, AS 73 is supplied eRAM 72, eRAM 72 enters read mode (step 91). 然后,根据H/M信号72h进行不同操作(步骤92 ):如命中,则直接将从eRAM 72中读出的数据79a送到输出79 (步骤97 ),并送出cRY 79 (步骤98);如未命中,则需要从3D-M核0中读数据。 Then, according to the H / M signal 72h different operations (step 92): If the hit, the data 72 directly from eRAM 79a read out to the output 79 (step 97) and sends CRY 79 (step 98); if miss, it is necessary to read data from the 3D-M core 0. 这包含如下步骤:首先,送出RD44言号(步骤93);然后从3D-M中读出一页数据,并送出RY 6 (步骤94 );这时,eRAM 72 进入写模式,列译码器70选中的一个字79a及其地址2b被存入eRAM 72 (步骤95 );最后,将数据79a或79b送到输出79 (步骤96 ),再送出cRY 79 (步骤98 )。 It comprises the following steps: First, the number of feeding RD44 made (step 93); and a data read out from the 3D-M, and sends RY 6 (step 94); in this case, eRAM 72 into the write mode, column decoder 70 a selected address word 79a and 2b are stored eRAM 72 (step 95); and finally, the data 79a or 79b to the output 79 (step 96), then sends CRY 79 (step 98).

在步骤96时,数据可以在3D-M数据被传送到eRAM 72时直接在列译码器处读出。 In step 96, the data may be directly transferred to the readout column decoder at the time of the 3D-M 72 eRAM data. 这种方法的首访时间要短一些。 First time visit to this method is shorter. 图6EA表示一种相应的数据选择器76。 FIG 6EA shows a corresponding data selector 76. 它使用一多路选择器76M。 It uses a multiplexer 76M. 根据其控制信号79s的大小( 一般由H/M信号72h决定),多路选择器76M决定输出79采用来自列译码器70的数据79a (未命中情形)或来自eRAM 72的数据79b (命中情形)。 The size of controls (72h typically determined by the H / M signal) 79s, the multiplexer 79 determines an output 76M using data from the column decoder 70 of 79a (miss case) or data from the eRAM 72 79B (hit situation).

另外,即使是未命中,也可以在3D-M数据复制到eRAM后从eRAM72中读出数据。 Further, even if not hit, can be copied to eRAM72 eRAM read from the data in the 3D-M. 这种方法较易满足冗余电路和软件升级的要求。 This method is easier to meet the redundancy circuitry and software upgrade request. 图6EB表示一种读流程,该读流程是图6D 中步骤96的一部分。 FIG 6EB shows a reading process, the read process is part of step 96 in FIG. 6D. 在3D-M数据被下栽到eRAM 72后,重复eRAM的读操作(包括图6D的步骤91、 92、 97等)。 In 3D-M data is tilted downward and crashed after eRAM 72, eRAM repeated read operations (including the step 91 in FIG. 6D, 92, 97, etc.). 具体说来,在步骤95完成后,AS 73被再次送至eRAM 72, 并读数(步骤96a)。 Specifically, after the completion of step 95, AS 73 eRAM 72 is supplied again, and read (step 96a). 因为这次肯定会"命中",即H/M信号72h肯定为高(步骤96b ), eRAM的读出数据79b被直接送至输出79 (步骤%c )。 Because this will certainly be "hit", i.e., H / M 72h affirmative signal is high (step 96b), eRAM 79b read data directly to the output 79 (step% c). 图6EC表示该方法使用的一种数据选择器76。 FIG 6EC indicates that the method using a data selector 76. 因所有的输出数据均来自eRAM72,该数据选择器只是一简单的传输门76T,它决定是否将eRAM 72数据79b输出。 Since all the data is output from eRAM72, the data selector is just a simple transfer gate 76T, which determines whether eRAM 72 data output 79b.

图6B-图6EC的实施例基于"字复制",即输出页U024位)中可能只有一个字(64 位)被复制至eRAM72中(别的字可能都被浪费了)。 FIG 6B- embodiment of FIG 6EC may be one word (64) based on the "word copy", i.e., U024 bit output page) is copied to the eRAM72 (other word may have been wasted). 为了充分利用每次读出的数据,最好使用"页复制",即输出页上的所有字被全部复制至eRAM72中。 In order to take full advantage of each read data, it is preferable to use "page replication", i.e., the output of all the words on the page are copied to all the eRAM72. "页复制"能提高读效率。 "Page copy" can improve reading efficiency. 图6F表示一种使用"页复制"的3DcM。 Figure 6F shows a use "page copy" 3DcM. 与图6B不同的是,其列地址2c,不是AS 73 的末4位,而是由控制电路块74,内部产生的。 FIG 6B is different from that column address 2C, the end 4 than AS 73, but by the control circuit block 74, internally generated. 对于熟悉本专业的人士,可以很容易地根据图6D和图6G的读流程设计出控制电路块74,。 For those skilled professional, it can easily be designed in accordance with the control circuit block 74 in FIG. 6D and FIG. 6G reading process ,. 图6G表示一种列地址产生流程,它是图6D 中步骤95的一部分。 FIG. 6G shows a column address generating process, which is part of step 95 in FIG. 6D. 在步骤94后,在74,的控制下,依次产生输出页上的所有字的地址(步骤95a),然后,被选中的字及其地址被复制至eRAM72 (步骤95b)。 After the step 94, under the control of 74, sequentially generates addresses (step 95a) of all words on the output page, and then, the selected word and its address are copied to eRAM72 (step 95b). 重复步骤95a、 95b 直到2c,达到其预设最大值(步骤95c)。 Repeat steps 95a, 95b until 2c, reaches its preset maximum value (step 95c). 这样,输出页被全部复制至eRAM72中。 Thus, the output pages are copied to eRAM72 in all. 图6H 表示一种"页复制"中使用的eRAM 72。 FIG 6H shows a "page replication" used in the eRAM 72. 在该实施例中,eRAM数据块72D的大小仍为64x64, 但它被分为4个eRAM扇区。 In this embodiment, the size is still eRAM 64x64 block 72D, but it is divided into four sectors eRAM. 每个eRAM扇区的大小为64x16,并存储一个输出页中的所有数据(1024位)。 ERAM size of each sector is 64x16, and all data stored in an output (1024) page. 每个扇区《吏用一地址标签行。 Each sector "officials by a row address labels. 相应地,eRAM标签块72T的大小可以为8x4。 Accordingly, the size of the label block eRAM 72T may be 8x4.

C. 编程速度 C. Programming speed

3D-EPROM的用户可以编程。 3D-EPROM can be programmed user. 为了缩短芯片编程时间,最好多个存储元能被同时编程。 In order to shorten the programming time chip, preferably a plurality of memory elements can be programmed simultaneously. 这即是平行编程的概念。 This is a concept that is parallel programming. 图7A表示平行编程的一种实施方法。 7A shows an embodiment of a method of parallel programming. 在此特例中,3D-EPROM元lcb和lcc同时被编程。 In this particular case, 3D-EPROM element and lcb lcc simultaneously programmed. 在编程时,字线20c上的电压升至Vpp,位线30b、 30c上的电压降为0,而所有别的地址选择线的电压均为Vpp/2。 When programming, the voltage on the word line 20c raised to Vpp, bit line 30b, 30c on the voltage drops to 0, while all other addresses selected line voltage are Vpp / 2. 因此,加在存储元lcb、 lcc上的电压是Vpp,故它们被同时编程.为了將至少两条位线上的电压降为0,列译码器最好是平行列译码(图7B)。 Thus, the storage element applied to the lcb, lcc the voltage Vpp, so that they are simultaneously programmed to the voltage drop of the at least two bit lines 0, the column decoder row decoder is preferably flat (FIG. 7B) . 它使用了两个亚译码器70a、 70b。 It uses two sub-decoders 70a, 70b. 这些亚译码器70a、 70b具有相同的列地址2C。 These sub-decoders 70a, 70b have the same column address 2C. 它们可以是相邻的,也可以是相互交叉的。 They may be adjacent, it may be interdigitated. 在此实施例中,它们是镜像对称的。 In this embodiment, which are mirror-symmetrical. 列地址2C(如"1")被同时送到该亚译码器70a、 70b中,这将位线30b、 30c上的电压降为0,从而能满足图7A的电压要求。 2C column address (eg "1") are simultaneously supplied to the sub decoder 70a, 70b in which the bit line 30b, 30c on the voltage drops to zero, so that it can meet the voltage requirements of FIG. 7A.

为了减少封装脚的数目,美国专利6,385,074建议使用一片内Vpp产生器。 To reduce the number of package pins, U.S. Patent No. 6,385,074 recommends the use of a Vpp generator. 该片内V叩产生器利用芯片电源电压Vdd产生Vpp。 The sheet utilizing V knock generator chip supply voltage Vdd generated Vpp. 这种设计对于经常需要编程的3D-M来说是必要的。 This design is often required for programming 3D-M is necessary. 但对于"一次性"编程的3D-M来说,它们不需要经常编程;尤其对于作为资料栽体的3D-EPROM (如图3中的PonC)来说,它们一般在工厂里面编程(如由资料发行商)。 But for the "disposable" programmed 3D-M, they do not need regular programming; in particular, as a material for the 3D-EPROM plant body (in FIG. 3 PonC), they generally inside the factory programmed (e.g., by the data publisher). 在使用时,用户只读,而不编程。 In use, a read only user, without programming. 对这些应用来说,Vpp产生器没有必要,其节省的芯片面积可以用来设计别的功能。 For these applications, Vpp generator is not necessary, which saves chip area can be used to design other function. 图7C描述一种具有Vpp接线垫12P、 70P的3D-M。 Figure 7C describes a pad having a Vpp terminal 12P, 70P of 3D-M. 这些接线垫提供外界编程电压。 These pads provide external programming voltage wiring. 对于工厂编程、作为资料载体的3D-EPROM来说,其编程一般是芯片层次编程,故这些接线垫不需要和封装引线相连。 For factory-programmed data carriers as 3D-EPROM, it is generally programmed chip-level programming, and it does not require the connection pads connected to package leads. 这能减少封装脚的数目。 This can reduce the number of package pins.

工厂编程的3D-EPROM可采用因特网的商业模式,即利用因特网来传输用户所希望写入芯片的数据。 Factory programmed 3D-EPROM may be employed the Internet business model, i.e., use the Internet to transmit the data desired by the user to write chip. 同时,工厂(如资料发行商)还可以拥有多个数据库,这些数据库存有多个文件。 At the same time, the plant (such as data distributors) may also have multiple databases, these database contains multiple files. 用户只需在工厂网页上点击所需文件的指针(pointer),工厂就能将所需文件从数据库中提出,并写入3D-EPROM中(参见由同一发明人提交的PCT申请"低成本光刻技术"的图8AA和图39A,为简便计,本说明书中未画出这些图,只需将这些图中的光刻编程系统换成电编程系统即可)。 The user simply clicks on the page factory desired file pointer (pointer), the plant will be able to raise the required files from the database, and 3D-EPROM write (see PCT Application, "filed by the same inventor low-cost optical lithography "FIG. 39A and FIG 8AA, the count for simplicity, not shown in the present specification, the figures, these figures simply lithographic programming system into an electrical system can be programmed).

2. 单位阵列的容量 2. The capacity of unit arrays

如图8AA-图8AB所示,单位阵列的容量对3D-M的可集成性有极大影响。 As shown in FIG 8AA- FIG 8AB, the capacity of the unit array can have a dramatic effect on the integration of 3D-M. 对于大的单位阵列,3D-M芯片可以只含有少量的单位阵列0A (图8AA);对于小的阜位阵列,3D-M 芯片需含有较大数量的单位阵列0Aa-0Ai (图8ABK因为单位阵列的周边电路位于衬底里, 较大数量的单位阵列意味着衬底被严重地支离了。这种支离的衬底会使衬底集成电路的版图设计受到极大限制。此外,较大数目的单位阵列会使阵列效率变低。为了提高3D-M的可集成性,最好能使用具有大容量的单位阵列。 For large arrays units, 3D-M chip may contain only small amounts of unit arrays 0A (FIG 8AA); Fu for small bit array, 3D-M chip for an array comprising a large number of unit 0Aa-0Ai (because the unit of FIG 8ABK circuit array located outside the substrate, the greater number of units of the array substrate is meant a severely fragmented. this causes fragmentation of the substrate of an integrated circuit layout design of the substrate is greatly limited. in addition, a large number of an array of unit arrays will efficiency becomes low. in order to improve the integration of 3D-M, it is best to use an array having a large capacity units.

3D-M单位阵列的容量C"a等于其字线数目A^l与位线数目7V礼之乘积(图2B、图8B), 因此可以通过分别提高Wwl和7Vbl来提高CA。从设计的角度来说,A^l—般无限制,因此可以采用矩形的单位阵列。另一方面,根据eq. (1)并令AVb^rtVT (—般说来,rt~2, VT~0.1V), ASvl可以表示如下, 3D-M unit arrays capacity C "a number of word lines which is equal to the product of A ^ l and the bit line number Li of 7V (FIG. 2B, FIG. 8B), so the angle can be improved by improving the design CA. Wwl respectively and 7Vbl for, a ^ l- as unlimited, so the rectangular array of units may be employed other hand, according to eq (1) and to make AVb ^ rtVT.. (- generally speaking, rt ~ 2, VT ~ 0.1V), ASvl can be expressed as follows,

A\vl= /f( ,/r(Vr)=/f( 〜-"W/"" W eq. (3) A \ vl = / f (, / r (Vr) = / f (~- "W /" "W eq. (3)

MvL受限于读时存储元的正反电流比Y。 MvL reverse current is limited by the ratio of the read memory element Y. 这里,"/的定义与常规定义不同:其正向偏置电压Vf (如〜3V)可远大于反向偏置电压Vr (如4.3V)。这得力于S/A和全读模式等的应用。Eq. (3)对3D-ROM的设计极有价值。很明显,可以通过增加Vr来提高7Vwl。另一方面,可以通过使用二极化元来提高7VwL。所谓二极化元,是指流过它一个方向上的电流和相反方向上的电流所遇到的阻抗极不相同。 Here, different "/ definition and conventional definition: the forward bias voltage Vf (as ~3V) may be much greater than the reverse bias voltage Vr (such as of 4.3 V) which thanks to S / A and read all of the mode. application .Eq. (3) design of the 3D-ROM extremely valuable. obviously, it can be improved by increasing the Vr of 7Vwl. on the other hand, by using two polarizing element to improve 7VwL. the so-called two polarization element, is refers to the current and the current flowing through it in the opposite direction in the direction encountered a very different impedances.

图8B表示一种矩形3D-M阵列。 FIG 8B shows a rectangular array of 3D-M. 在此实施例中,Wbl>Mvl。 Embodiment, Wbl> Mvl in this embodiment. 在该芯片中可沿j方向放置数个这种3D-M阵列。 Arranging multiple arrays of such 3D-M j in the direction of the chip. 这样,芯片的最后形状可以大致保持正方形。 Thus, the final shape of the chip may be maintained substantially square.

图8CA描述一种利用大VR来提高7VwL的方法。 FIG 8CA describes a method for improving the use of large 7VwL of VR. 这里,K大于电源电压Vdd。 Here, K is greater than the power supply voltage Vdd. 由于3D-ROM膜的IV特性一般是指数型的,故其读电流I, (VR时)远远大于Vdd时的电流12。 Because the IV characteristic of 3D-ROM film is generally exponential, so the read current the I, (when VR) Vdd is much larger than the current 12. 因此,Mvl以及Ca可以増加很多。 Therefore, Mvl and Ca can to increase in number. 图8CB、图8CC表示一种VR的产生方法。 FIG 8CB, FIG 8CC showing a method of generating the VR. 图8CB是其电路框图。 FIG 8CB is a circuit block diagram thereof. VR产生器12R为行译码器12产生读电压Fr。 VR generator 12R for the read voltage generating row decoder 12 Fr. 它一般采用电荷泵(charge-pump)等设计。 It generally uses a charge pump (charge-pump) and other design. 图8CC是一种含有VR产生器12R的衬底版图设计。 FIG 8CC is a substrate layout generator VR contains 12R. 这里,三维集成使VR产生器12R 可以位于衬底0s中,尤其是能位于3D-M阵列0A下方。 Here, three-dimensional integration enables VR generator 12R 0s may be located in the substrate, especially an array of 3D-M located below 0A. 除了使用大Vr外,还可以使用二极化元来提高CA。 In addition to large Vr, the two polarization element can also be used to improve the CA. 二极化元可以含有一极化膜和/或二极化结构。 Two polarizing element may contain a polarizing film and / or di-poled structure. 二极化膜是通过材料的不同来产生二极化效应(图8D -图8EC) ; 二极化结构通过界面的不同来产生二极化效应(图8F-图8GC)。 Two polarizing film is to produce two polarization effect (FIG. 8D - FIG. 8EC) by a different material; two polarization structure to produce two polarization effect (FIG 8F- FIG 8Gc) through different interfaces.

图8D解释二极化膜的概念。 FIG. 8D explain the concept of two membrane depolarization. 二极化膜38含有至少二层次膜38a、 38b。 Two polarizing film 38 comprising at least two levels of membrane 38a, 38b. 它们的材料最好有较大的差别。 Their material is preferably greater difference. 当电流沿着方向37a流过二极化膜38 (即从端口39a到端口39b ),它首先遇到次膜38a,然后遇到次膜38b;另一方面,当它沿方向37b (即从端口39b到端口39a ) 流动时,它先遇到次膜38b,然后再遇到次膜38a。 When the direction of current flow through the two polarizing films 37a 38 (i.e. from the port 39a to port 39b), it first encounters secondary film 38a, then encounters the secondary film 38b; on the other hand, when it is in the direction 37b (i.e., from port 39b to the port 39a) flows, it first encounters secondary film 38b, and then the film face views 38a. 这种遇到次膜38a、 38b的顺序能够极大地影响到电流的大小。 This film met views 38a, 38b sequence can greatly affect the magnitude of the current. 一个很熟悉的例子即pn结二极管,它通过使用不同的掺杂类型来导致二极管现象的发生。 I.e., a familiar example of a pn junction diode, which lead to the phenomenon of the diode by using different types of doping. 二极化膜38比二极管走得更远:除了掺杂类型外,它们的基材料还可以不同。 Two polarizing film 38 to go further than the diode: In addition to the type of doping, the base material thereof may also be different. 这里, 一层膜的基材料是构成这层膜的主要材料。 Here, a film-based material is a material constituting the main layer of this film. 图8EA-图8EC表示了几种二极化膜的实施例。 FIG 8EA- FIG 8EC shows several embodiments of two membrane depolarization.

图SEA表示第一种二极化3D-ROM膜。 FIG two SEA represents a first polarization film 3D-ROM. 它含有两层次膜32a、 32b,它们分别使用不同的基材料,如次膜32a的基材料是硅,次膜32b的基材料是碳硅合金(Siy C,.v, 0<y<l)。 It contains two levels of membrane 32a, 32b, respectively, using different base materials, the film 32a is summarized as follows based material is silicon, the base material film 32b views a carbon-silicon alloy (Siy C, .v, 0 <y <l) . 其它半导体材料,如锗、锗硅合金(SizGe,a, 0<z<l)、金钢石也可用作基材料。 Other semiconductor materials, such as germanium, silicon germanium alloys (SizGe, a, 0 <z <l), diamond-based materials may also be used. 这里,碳硅合金、金钢石等高带隙半导体材料(指带隙大于硅的半导体材料)有一定优势,因为它们具有较好的高温特性。 Here, silicon carbon alloys, diamond high band gap semiconductor material (of a semiconductor material of larger bandgap than silicon) has certain advantages because of their good high temperature properties. 除了半导体材料外,二极化膜38可以包括:半导体材料和介质材料的复合膜(譬如说,次膜32a含一半导体材料,次膜32b含一介质材料);不同的介质材料(譬如说,次膜32a含非晶硅,而次膜32b含氮化硅);不同结构的基材料(譬如说,次膜32a 具有非晶结构,次膜32b具有多晶或微晶结构,这在图8EB中也有表示);不同的电极材料(譬如说,使用具有不同功函数的金属;或与3D-ROM膜有不同界面特性的金属;或一个电极使用金属,另一电极使用掺杂的半导体材料)。 In addition to semiconductor materials, two polarizing film 38 may include: a semiconductor film dielectric material and a composite material (say, once a film containing a semiconductor material 32a, 32b comprising a secondary film of dielectric material); different dielectric material (say, Ci-containing amorphous silicon film 32a, while the second silicon nitride-containing film 32b); based materials of different structures (say, once the film has an amorphous structure 32a, 32b having a secondary film polycrystalline or microcrystalline structure, in which FIG 8EB there are also shown); different electrode materials (say, a metal having a work function different; the 3D-ROM, or a metal film having different interface characteristics; electrode using a metal or a semiconductor material doped to the other electrode) . 这些方法可以提高3D-ROM元的正反电流比。 These methods can improve the 3D-ROM membered reverse current ratio.

图8EB表示第二种二极化的3D-ROM膜。 FIG 8EB shows a second two polarized 3D-ROM film. 在此特例中,在电极31和3D-ROM膜32a 之间有一层微晶材料32au。 In this particular case, between the electrode 31 and the 3D-ROM film 32a with a layer of microcrystalline material 32au. 如果只在一个电极界面(如电极31和3D-ROM膜32的界面) 有微晶膜,则3D-ROM膜的二极化被强化,这样能得到一个较大的正反电流比;另一方面, 微晶材料可以降低金属_半导体的接触电阻,在至少一个电极界面(如电极31和3D-ROM 膜32的界面;和/或电极33和3D-ROM膜32的界面)增加微晶材料可以加强导通电流,缩短3D-ROM的首访时间。 If only one electrode interface (electrode 31 and the 3D-ROM interface membrane 32) with a microcrystalline film, the two polarization 3D-ROM film is reinforced, can be obtained such a large reverse current ratio; further aspect, microcrystalline material can reduce the contact resistance of the semiconductor _ a metal, at least one electrode interface (e.g., interface between the electrode 31 and the membrane 32 of the 3D-ROM; and / or the interface 33 and the electrode film 32 of the 3D-ROM) microcrystalline material increases It can enhance the on-current, shortening the first visit time 3D-ROM's.

图8EC表示第三种二极化的3D-ROM膜。 FIG 8EC showing a third two polarized 3D-ROM film. 在此实施例中,3D-ROM膜32含有一p+膜32p、 v膜32x和n+膜32n。 In this embodiment, 3D-ROM 32 containing a p + membrane film 32p, v films 32x and the n + film 32n. v膜32x是n低掺杂或不掺杂的,且这些膜基于非晶硅。 v film 32x is low n-doped or undoped, and these films of amorphous silicon. 这些膜的淀积顺序为32n、 32x、 32p。 The order of these films are deposited 32n, 32x, 32p. 这种结构可以得到〉10A/cm2的正向电流和<6 xl(T5A/cm2的反向电流。 This structure can be obtained> forward current of 10A / cm2 and <6 xl (reverse current T5A / cm2 of.

图8F解释二极化结构的概念。 FIG 8F explain the concept of two polarization structure. 3D-ROM膜32与顶电极31之间的界面为顶界面32仏与底电极33之间的界面为低界面32bi。 32 and the interface between the top electrode 31 3D-ROM interface between the film and the bottom electrode 33 Fo interface 32 is a low interfacial 32bi. 在一种二极化结构中,这些界面的形状不同:最好一个界面具有一强化场的尖端33t,而另一界面较平滑。 In one arrangement two polarization, different shapes of these interfaces: an interface having a tip 33t is preferably a strengthening field, and another relatively smooth interface. 相应地,电子发射在一个方向得到加强,从而提高正反比。 Accordingly, the electron emission enhanced in one direction, thereby increasing the ratio of positive and negative.

图8G为一种二极化结构的实施例。 FIG. 8G is a embodiment of a two-poled structure. 在此实施例中,底电极33具有多晶结构,其表面32bi 比较粗糙;当3D-ROM膜32淀积在底电极33上之后,其中的非晶材料使它和顶电极31之间的界面32ti变得较为平滑。 In this embodiment, the bottom electrode 33 has a polycrystalline structure, which rough surface 32bi; 3D-ROM when the film 32 is deposited on the bottom electrode 33, 31 wherein the interface between the top electrode and the amorphous material makes it 32ti becomes smoother. 因此,从底电极33到顶电极31的电子发射得到增强,即从顶电极31流到底电极33的电流变得较相反方向上的电流大。 Thus, the bottom electrode 33 to the top electrode 31 from the electron emission is enhanced, i.e., becomes relatively large current in the opposite direction of the current flowing in the end the top electrode 31 from the electrode 33. 因此,可以将顶电极31用作字线, 将底电极33用作位线。 Accordingly, the top electrode 31 serves as a word line, the bit line 33 serves as the bottom electrode.

3. 成品率的提高 3. improve yield

缺陷会导致各种形式的读错误并降低成品率。 Defects cause various forms of read errors and reduce yield. 如图9AA-图9CB所示,3D-M阵列有六种缺陷,包括:1.字线断路200 (图9AA) 、 2.字线短路20s (图9AB ) 、 3.位线断路30t) As shown in FIG. 9CB 9AA- shown, 3D-M array has six defects, comprising: a word line circuit 200 (FIG. 9AA), 2. short-circuited word lines 20S (FIG 9AB), 3. the bit line circuit 30T)

12(图9BA ) 、 4.位线短路30s (图9BB ) 、 S.过小的3D-ROM元正向电流(图9CA ) 、 6.过大的3D-ROM元反向电流(图9CB )。 12 (FIG. 9BA), 4. the bit line short 30s (FIG 9BB), S. too small 3D-ROM membered forward current (FIG 9CA), 6. 3D-ROM excessive reverse current element (Fig 9CB) .

对字线缺陷1和2,整条字线不能读出正确数据,这导致字线错误。 1 and 2 of the whole word lines correct data can not be read word line defect, which results in an error word line. 对位线缺陷3和4, 整条位线不能读出正确数据,这导致位线错误。 The bit line defect 3 and 4, the entire bit line is not read data correctly, the error which results in the bit lines. 3D-ROM缺陷元5的正向电流lf'太小,导致AVbe过低,使S/A不能够被触发,从而一个逻辑"1"元被误读成逻辑"0"(图9CA)。 3D-ROM defect membered forward current lf '5 is too small, resulting in low AVbe the S / A can not be triggered, so that a logic "1" cell is misread as a logic "0" (FIG 9CA). 所幸的是,该缺陷只会导致个别位错误。 Fortunately, the defect will only lead to individual bit errors. 3D-ROM缺陷元6的反向漏电流太大,当读取与该缺陷元处于同一条位线上的其它存储元时,它会限制AVbe,使S/A不能被触发,从而不能读出有效数据(图9CB)。 3D-ROM defect 6 membered reverse leakage current is too large, the defect when reading other storage element in the same element of one bit line, which limits the AVbe, so that S / A can not be triggered, so as not to be read valid data (Fig 9CB). 这种缺陷会导致位线错误。 This deficiency can lead to a bit line errors. 缺陷5和6,尤其是6,对3D-M阵列的本征成品率影响很大。 5 and 6 the defect, especially 6, a great influence on the yield of the intrinsic 3D-M array.

为提高成品率,可使用无缝3D-ROM元,它直接减少3D-ROM阵列中的缺陷数目(图10A-图12B)。 To improve the yield, using the seamless 3D-ROM element, which directly reduce the number of defects 3D-ROM array (FIG. 10A- 12B). 另夕卜,也可以使用多种3D-M纠错方案,如纠错码(ECC)、冗余电路等,纠错方案纠正3D-M阵列中已有缺陷导致的错误(图13 -图15C )。 Another Bu Xi, may be used a variety of 3D-M error correction scheme, such as an error correction code (the ECC), the redundancy circuit, etc., 3D-M error correction scheme to correct defects in the array has an error (FIG. 13 due to - 15C in FIG. ).

A. 无缝3D-ROM元 Seamless 3D-ROM element A.

3D-ROM阵列中的缺陷可能在工艺流程的几个阶段引入,即在3D-ROM膜形成之前(如对底电极顶部),在3D-ROM膜形成中(对3D-ROM膜),在3D-ROM膜形成之后(如对3D-ROM膜顶部)。 3D-ROM array defects may be introduced at several stages of the process, i.e. before the film-forming 3D-ROM (such as the top of the bottom electrode), in the film forming the 3D-ROM (for 3D-ROM film) in 3D -ROM after film formation (e.g., a top membrane of the 3D-ROM). 这些膜(即3D-ROM膜以及至少与之相邻的部分底电极和部分顶电极) 的清洁度对3D-ROM的成品率影响极大,故它们被称为缺陷敏感膜。 These films (i.e. films 3D-ROM and at least a portion adjacent the bottom electrode and the top electrode portion) cleanliness great impact on the yield of the 3D-ROM, so they are referred to as the sensitive film defects. 一个常见的、易于引入缺陷的工艺步骤是图形转换。 A common, easily introduce defects graphics conversion process steps. 在图形转换过程中,硅片要经过光刻和蚀刻(或平面化)等步骤。 In the pattern conversion process, the wafer through photolithography and etching to (or planarization) and other steps. 所有这些步骤会引入外界有害杂质或损伤3D-ROM膜。 All of these steps may introduce impurities or harmful external 3D-ROM membrane damage. 因此,在缺陷敏感膜的形成过程中应避免图形转换步骤。 Thus, during the formation of a defect-sensitive film pattern converting step should be avoided.

为了提高3D-M的本征成品率,本发明提出一无缝3D-ROM元。 In order to increase intrinsic yield 3D-M, the present invention provides a seamless 3D-ROM element. 图10A表示一种无缝3D-ROM元,它含有底电极64、 3D-ROM膜62、顶緩冲膜60以及顶电极66。 10A shows a seamless 3D-ROM element, comprising a bottom electrode 64, 3D-ROM film 62, a top 60 and a top electrode buffer film 66. 顶电极66含有顶緩冲膜60和顶导体65,它们通过通道孔(开口) 67相连。 The top electrode 66 comprises a top buffer film 60 and the top conductor 65, which through the passage hole (opening) 67 is connected. 顶緩冲膜60和3D-ROM膜62之间的界面为顶界面62ti, 3D-ROM膜62和底电极64之间的界面为底界面62bi。 The interface between the top film 60 and buffer film 3D-ROM interface 62 is a top 62ti, 3D-ROM film 62 and the bottom electrode 64 between the bottom boundary interface 62bi. 在无缝3D-ROM中,至少一部分顶緩冲膜60与至少一部分3D-ROM膜62具有相同的截面。 Seamless 3D-ROM, at least a portion of the top of at least part of the buffer film 60 3D-ROM film 62 having the same cross section. 在其工艺流程(图11AA-图IIE,)中,3D-ROM膜以及至少与之相邻的部分底电极和部分顶电极是以一种无缝的形式形成的:在这些工艺步骤之间没有图形转换,故不会对顶界面62ti和底界面62bi引入杂质。 In, 3D-ROM portion of the bottom electrode film, and at least a portion adjacent thereto and the top electrode is formed in the form of a seamless process thereon (FIG 11AA- FIG IIE,): between these process steps do not graphics conversion, it will not introduce impurities to the top interface and a bottom interface 62ti 62bi. 该工艺流程最好能在一集束设备(clustertool)中进行。 The process is preferably carried out in a cluster tool can (clustertool) in. 图10B表示另一种无缝3D-ROM元。 FIG 10B shows another element seamless 3D-ROM. 其开口67在形成过程中使用了nF开口掩模版,故其大小比顶緩冲膜60的边长长。 67 in which an opening is formed in the opening process uses a reticle nF, so the buffer size is larger than the top edge of the long film 60.

图11AA-图11E,表示无缝3D-ROM元采用的多种工艺流程。 FIG 11AA- FIG. 11E, showing more seamless 3D-ROM membered process employed. 在图11AA中,所有缺陷敏感膜,包括底电极64、 3D-ROM膜62以及一部分顶电极(即顶緩冲膜60)是以一种无缝的形式形成的。 In FIG. 11AA, all defects sensitive membrane comprising a bottom electrode 64, 3D-ROM and a portion of the top electrode film 62 (i.e., the top buffer film 60) is formed in a seamless form. 因此,顶界面62ti和底界面62bi的缺陷很少。 Thus, defective top interface and a bottom interface 62bi 62ti few. 另外,在3D-ROM膜62和顶緩冲膜60之间还可以有一层抗蚀膜(etchstop layer) 60b (图11AB ),其功能在图11BC中描述。 Further, the film 62 between the 3D-ROM and the buffer film 60 may be a top layer of the resist film (etchstop layer) 60b (FIG. 11AB), whose function is described in FIG. 11BC. 所有这些膜(64、 62、 60b、 60)都可以用无缝的形式形成。 All these films (64, 62, 60b, 60) may be formed by a seamless form.

然后,对顶緩冲膜60进行图形转换。 Then, on top of the buffer film 60 is patterned conversion. 图11BA-图11BC表示几个在该步骤后的3D-ROM 结构。 FIG 11BA- FIG 11BC showing several 3D-ROM structure after this step. 在图11BA中, 一部分底电极64被暴露。 In FIG 11BA, a portion of the bottom electrode 64 is exposed. 在图11BB中, 一部分3D-ROM膜62被暴露。 In FIG 11BB, a portion of 3D-ROM film 62 is exposed. 图IIBC是图11AB中的结构在该步骤后的截面图。 FIG IIBC 11AB is a sectional view of the structure after this step. 抗蚀膜60b处可以保护3D-ROM膜62,并使之在该步骤时不被刻蚀。 60b of the resist film can protect the film 62 3D-ROM, and it is not etched during this step.

在顶緩冲膜60成形之后,最好还要一个修复3D-ROM膜62边缘的步骤(图IICA-图11CC)。 After the step of forming the top of the buffer film 60, film 62 preferably also fixes the edge of a 3D-ROM (FIG IICA- FIG 11CC). 该步骤类似于常规MOS工艺的栅后氧化步骤(post-gate-oxidation)。 After gate oxidation step (post-gate-oxidation) This step is similar to a conventional MOS process. 图11CA是图11BA中的结构在该步骤后的截面图, 一部分底电极64通过氧化等方法转换成介质68d。 11BA is a configuration diagram of FIG 11CA in the cross-sectional view of the step, a portion of the bottom electrode 64 is converted into medium 68d by oxidation or the like. 图11CB是图11BB中的结构在该步骤后的截面图,至少一部分3D-ROM膜62通过氧化等方法转换成介质68d。 FIG 11CB 11BB is a sectional view of the structure after this step, at least a portion of the 3D-ROM medium 68d is converted into film 62 by oxidation or the like. 图IICC是图11BC中的结构在该步骤后的截面图,至少一部分抗蚀膜60b 通过氧化等方法转换成介质68d。 FIG 11BC IICC is a sectional view of the structure after this step, converting at least a portion of the resist film 60b to 68d medium by oxidation or the like. 接着,对底电极64进行图形转换,形成3D-KOM堆69 (闺11D )。 Next, the bottom electrode 64 is patterned conversion, 3D-KOM stack 69 (Gui 11D) are formed. 然后淀积低层间介质68,打开通道孔(开口) 67,并形成顶导体65 (图11E )。 Then the lower layer is deposited between the medium 68, to open the passage hole (opening) 67, and a top conductor 65 (FIG. 11E) is formed.

图11D,、图IIE,表示为形成图10B中无缝3D-ROM元所需的额外步骤。 FIG. 11D ,, FIG IIE, represents an additional step to form a seamless FIG. 3D-ROM desired element 10B. 在形成3D-ROM 堆69后,淀积低层介质68并对其作平面化。 After heap 69 is formed 3D-ROM, deposited medium 68 and subjected to a low-level planarized. 之后,在该结构上形成设置介质23 (图IID,)。 Thereafter, the medium 23 is formed is provided (FIG. The IID,) on the structure. 低层介质68和设置介质23最好舍不同介质,如低层介质68为氧化硅,设置介质23为氮ib 硅。 Lower medium 68 and the medium 23 is preferably provided homes different media, such as the lower layer is a silicon oxide dielectric 68, dielectric 23 is provided to a silicon nitrogen ib. 接着,对nF开口掩模版曝光。 Next, the reticle exposure opening nF. 然后通过一刻蚀步骤在设置介质23内形成开口67。 Then a step of etching an opening 67 is provided within the medium 23 is formed. 刻蚀时,可以选择其处方使它在低层介质68上停止。 When etching, you can choose their prescriptions to make it stop on the lower medium 68. 最后,填充导体材料以形成顶导体65 (图IIE,)。 Finally, filling a conductive material to form the top conductor 65 (FIG IIE,).

图12A和图12B描述两种准无缝3D-EPROM元。 12A and 12B describe two quasi seamless 3D-EPROM element. 这些准无缝3D-EPROM元中的一部分膜(如准导通膜62a)是以无缝形式形成的;而另一部分膜(如反熔丝膜62b )则是以常规方式形成。 These quasi-seamless part of the film (e.g., quasi-conductive film 62a) in 3D-EPROM element is formed in the form of seamless; while another part of the membrane (e.g. antifuse film 62b) is formed in the conventional manner. 在图12A中,准导通膜62a位于顶緩冲膜60和底电极64之间,它是以一种无缝形式形成的;而反熔丝膜62b介于通道孔塞63和顶电极65之间,它是以常规方法形成的。 In FIG. 12A, the quasi-conductive film 62a on the top and bottom buffer film 60 between the electrode 64, which is formed in a seamless form; and antifuse film passage hole 62b between the plug 63 and the top electrode 65 between, which is formed by a conventional method. 在图12B中,准导通膜62a是以一种无缝形式形成的;反熔丝膜62b介于顶緩冲膜60和顶电极65之间,它是以常规方法形成的。 In FIG. 12B, the quasi-conductive film 62a is formed in a seamless form; antifuse film 62b interposed between the top buffer film 60 and the top electrode 65, which is formed by a conventional method. 在这两个特例中,准导通膜的缺陷极少。 In these special cases, the quasi conductive film with very few defects. 注意到,准导通膜和反熔丝膜的位置可以互换。 It noted, the quasi-conductive film and a film of the antifuse locations may be interchanged.

B.纠错方案 B. error correction scheme

为提高3D-M的成品率,还可以使用纠错方案,包括纠错码(ECC)和/或冗余电路等。 To improve the yield of the 3D-M, error correction schemes can also be used, including error correction code (ECC) and / or redundancy circuit. 图13表示一带ECC的3D-M。 13 shows an ECC area 3D-M. 该3D-M包括一具有ECC码的3D-M核0、列译码器70和ECC 电路IIO。 The 3D-M comprises a core having a 3D-M ECC code 0, a column decoder 70 and ECC circuit IIO. 在3D-M核0中,每条字线上有1024位有效数据,它们被分成16'个64位的字。 In 3D-M core 0 in each word line 1024 with a valid data, they are divided into 16 '64-bit word. 对于Hamming码来说,每个字需要7个校对位,故每条字线上的数据位有16x(64+7) = 1136。 For the Hamming code, each character requires 7 bits proof, so the data bits of each word line are 16x (64 + 7) = 1136. 在读时,这1136位数据8通过列译码器70后输出71位数据79a,。 In reading, the output data 79a 71 70 1136 This data by the column decoder 8 ,. ECC电路110将这71 位数据79a,转换成64位有效数据79a。 ECC circuit 110 these 71 data 79a, converted into a 64-bit valid data 79a.

另一方面,冗余电路可以纠正个别位错误,字线错误和位线错误。 On the other hand, redundancy circuit can correct individual bit errors, the error word lines and bit lines errors. 图14A表示第一种具有冗余电路的3D-M。 14A shows a first 3D-M having a redundant circuit. 它含有3D-M核0、列译码器70、三组64位的二选一多路选择器(imix) 116S、 116B、 116W和三个冗余电路块。 It contains 3D-M core 0, a column decoder 70, three 64-bit second election multiplexer (imix) 116S, 116B, 116W and three redundant circuit blocks. 冗余电路块包括个别位冗余电路块118S、位线冗余电路块118B和字线冗余电路块118W,它们分别纠正个别位错误、位线错误、字线错误。 Redundancy circuit block comprises a block redundancy circuit 118S individual bit, bit line redundancy circuit block 118B and 118W word line redundancy circuit blocks, respectively, to correct individual bit errors, the error bit line, word line error. 每个冗余电路块存储缺陷(如缺陷元、缺陷位线、缺陷字线)的地址和纠错数据。 Each block storing defect redundancy circuit (defect such element, defective bit lines, the defective word line) of the address data and error correction. 当输入地址与一个缺陷地址相符时,与该缺陷地址对应的纠错数据被送到多路选择器(即mux) (116S、 116B、 U6W)的一个输入端(117S、 117B、 117W)。 When the input address matches the address when a defect, the error correction data corresponding to the defect address is sent to multiplexer (i.e. mux) (116S, 116B, U6W) an input terminal (117S, 117B, 117W). 在mux选中端(115S、 115B、 115W)的控制下,纠错数据将对应的3D-M输出79a",替换。个别位冗余电路块118S、位线冗余电路块118B在图14B-图14DC中描述;字线冗余电路块118W可用在软件升级中,它们又被称为机动码块,其细节在图15B -图15C中描述。 The mux select terminal (115S, 115B, 115W) under the control of correction data corresponding to the 3D-M output 79a ", replace. 118S individual bits of the redundant circuit block, bit line redundancy circuit block 118B in FIG. 14B- FIG. described in 14DC; word line redundancy circuit block 118W software upgrade is available, which is also known as a motor code block, the details of which FIG. 15B - 15C described in FIG.

图14B表示一种个别位冗余电路块118S。 FIG 14B shows a block individual bit redundancy circuit 118S. 该实施例含有两个纠错组,它们可以纠正两处缺陷元。 This embodiment comprises two correction groups, which can correct two defective element. 很明显,USS可以舍冇更多的纠错组。 Obviously, USS more error correction can Nuisance group homes. 每.个糾错纽含有多个寄存器,它们分別存储有效位vsl (1位)以及缺陷元的列地址前4位bsl 、行地址wsl (10位)、列地址后6位bsl, 和纠错位dsl (l位)。 Each. New comprising a plurality of error correction registers, which store valid bit vsl (1 bit) and a front defective element BSL four column address, row address wsl (10 bits), the column address BSL 6, and error correction bit dsl (l bit). 每个存储器的选中端由">"表示。 Select the end by each memory by ">". 有效位表示该纠错组的有效性, 只有在它高时,纠错组存储的地址和纠错数据才有效。 Effective error correction bit indicates the validity of the group, only when it is high, address correction and error correction data set storage to be effective. vsl寄存器的选中端122s可与Vdd连接,也可和别的时序信号(如74r)连接。 End 122s vsl selected register may be connected to Vdd, and other timing signals may be (e.g., 74R) is connected. 在读时,比较器121a、 121c将输入列地址2c、 AS2分别与bsl、 wsl比较,如相符,则读bsl'、 dsl。 In reading, the comparator 121a, 121c of the input column address 2c, AS2 respectively bsl, wsl comparison, such as match, the read bsl ', dsl. 译码器121D根据bsl, (6位)将一根muxll6S的控制端115S置高。 The decoder 121D bsl, (6 bits) opposite a control terminal 115S muxll6S high. 同时,dsl被传送至mux 116S的一个输入端117S,在115S 的控制下替换相应的输出数据79a"。这里,当vsl为低或输入地址与缺陷地址不符时,信号122D置低且使译码器121D失效,所有的115S均为低,则mux 116S不进行任何数据替换。 Meanwhile, DSL conveyed to an input terminal 117S mux 116S, the replacement data corresponding output 79a under the control of the 115S. "Here, when discrepancies vsl low defect address or address input, and a low signal is set so that the decoder 122D failure device 121D, 115S are all low, the mux 116S without any replacement data.

图14C表示一种位线冗余电路块118B。 FIG 14C shows a bit line redundancy circuit block 118B. 该实施例含有两个纠错组,它们可以纠正两处缺陷位线。 This embodiment comprises two correction groups, which can correct two bit line defects. 4个纠错组存储有效位vbl (l位)以及缺陷位线的列地址前4位bbl、列地址后6位bbl,和纠错列dbl U024位)。 4 stores valid bits sets correction VBL (L bits) and a front column address of the defective bit line 4 bbl, after the column address 6 bbl, and an error correction bit column dbl U024). 纠错列含有缺陷位线上所有数据的纠错数据。 Correction data of the defective column contains correction data for all bit lines. 在读时,列地ii 2c与bbi比丰i, diu4目符,则读bbl,、 dbi。 In reading, the column and ii 2c bbi abundance ratio i, diu4 head character, the read bbl ,, dbi. 译^马器12Ji)才艮据bbl,将一丰艮mux 116B 的控制端115B置高。 Translation ^ horse is 12Ji) It was Gen bbl, the abundance of Burgundy a control terminal mux 116B 115B set high. 同时,根据AS2从dbl中选择出对应的纠错位并送至muxll6B的一个输入端117B,在115B的控制下替换相应的输出数据79a,。 Meanwhile, according to the selection dbl AS2 in the corresponding error check bits and fed to one input terminal 117B muxll6B, the replacement data corresponding output 79a under the control of 115B ,.

图14B-图14C中的冗余电路块基于"读时纠错"。 14B- redundancy circuit block diagram of FIG. 14C is based on the "correction read." 另外,可以利用3DiM中的eRAM 存储3D-M数据的一个备份的特点,实现"读后纠错",即3D-M中的数据(包括正确数据和错误数据)先被下载到eRAM,然后在eRAM中进行纠正。 Further, the characteristics may be utilized in a backup storage 3DiM eRAM 3D-M data, and "reading correction", i.e. the data in the 3D-M (including the correct data and error data) is downloaded to the eRAM first, then eRAM in correct. 图14DA描述了一种基于"读后纠错"的冗余电路块118SB,它先纠正个别位错误,再纠正位线错误。 FIG 14DA is described based on "reading correction" redundancy circuit block 118SB, it first correct individual bit errors, then the error correction bit lines. 它含有个别位纠错块120S和位线纠错块120B,它们分别纠正个别位错误、位线错误。 It contains individual bits of an error correction block and the bit line 120S error correction block 120B, respectively, to correct individual bit errors, bit error lines.

个别位纠错块120S含有第一纠错存储块126S。 120S individual bits of error correction block comprising a first memory block error correction 126S. 该纠错存储块126S含有多个纠错组,每个纠错组存储有效位126d ( 1位)以及缺陷元的列地址bs (10位)、行地址ws (10位)和纠错位ds(l位)。 The error correction block stores a plurality of error correction 126S containing groups, each correction set bs column address valid bit memory 126d (1 bit) and a defect element (10), the row address WS (10) and error correction bits ds (L bits). 在该实施例中,有效纠错组依次从126S的底部存起。 In this embodiment, the effective error correcting group sequentially from the bottom of the deposit from 126S. 当信号cRY79置高后(即eRAM数据就绪),126S在定时电路126a的控制下逐行读纠错组。 When the high signal cRY79 set (i.e. eRAM data ready), 126S progressive read error correction circuit group 126a under the control of the timing. 图14DB表示定时电路126a的一种电路设计,其功能是:只要有效位125d为高,它会一直送出计数器时钟信号125a; —旦125d变低,则送出计数器清零信号125b和个别位纠错完毕信号79,。 FIG 14DB timing circuit 126a represents a circuit design, which is: as long as the valid bit 125d is high, it would have been sent counter clock signal 125a; - once 125d becomes low, the counter clear signal sent 125b and individual bit error correction completion signal 79 ,. 故只要还有有效纠错组被读出(125d为高),计数器126b的输出125c —直增加,125c被用作纠错存储块的地址125c。 So long as there is a valid set of error correction is read out (125D is high), the output of counter 126b 125c - linear increase, 125c is used as the address of the memory block error correction 125c. 地址译码器126c根据125c读出一纠错组。 The address decoder 126c 125c reads out a set of error correction. 比较器126e比较ws 125e 与AS 2,如相符,则bs 125f被送至eRAM 72的地址端A[9:0j, ds 125g被送至eRAM 72的数据端D,并将eRAM 72中对应于个别位错误的数据进行替换。 A comparator comparing ws 125e and 126e AS 2, such as a match, then bs 125f is supplied to the address terminal 72 eRAM A [9: 0j, ds 125g is sent to the data terminal eRAM D 72, and 72 correspond to the individual eRAM bit error data to be replaced.

位线纠错块120B含有第二纠错存储块126B。 The error correction block comprising a bit line 120B of the second memory block error correction 126B. 该纠错存储块126B也含有多个纠错组。 The error correction block stores a plurality of error correction 126B also contain groups. 每个纠错组存储有效位128d (1位)以及缺陷位线的列地址bb (10位)和纠错列db (1024 位)。 Storing each set of active bit error correction 128d (1 bit) and a column address of the defective bit line bb (10 bits) and column error correction db (1024 bits). 当收到个别位纠错完毕信号79,后,128B开始读纠错组。 When receiving the individual bits of the error correction completion signal 79, after the, group 128B is started to read the error correction. 128a使用与126a相同的定时电路。 128a and 126a using the same timing circuit. 类似地,当有效位127d为高时,计数器128b会一直增加128B的地址127c。 Similarly, when the valid bit 127d is high, the counter 128b will always increase the address 127c 128B. 地址译码器128c根据127c读出bb 127f,并将其送至eRAM 72的地址端A【9:0】。 Read address decoder 128c bb 127f according to 127c, and sends it to the address terminal A eRAM 72 [9: 0]. 128B再根据AS2从db中选出所需的纠错位127g (l位),并将其送至eRAM 72的数据端D,从而替换对应于位线错误的数据。 128B will then select the desired error correction bits 127g (l bit) according AS2 from the db, and sends it to a data terminal D 72 eRAM, thereby replacing the bit lines corresponding to the erroneous data. 上述"读后纠错"流程的时序图见图14DC。 A timing chart of the above-described "reading correction" process in Figure 14DC.

4. 软件的可升级性 4. Software scalability

软件在使用过程中, 一般会经历多次升级。 Software in use, usually through several upgrades. 每次升级过程中, 一部分原始码(最初发行的软件码)被升级码替代。 Each upgrade process, part of the source code (the initial release of the software code) is replaced by upgraded code. 一般认为:如使用掩膜编程只读存储器(MROM)来存储软件,则芯片出厂后,軟件无法升级。 Generally considered: such as the use of a mask programmable read only memory (MROM) to store software, shipped from the factory, the software can not be upgraded. 对常规MROM,这符合事实。 Conventional MROM, in line with the facts. 但是,对3D-M,该观点并不成立。 However, 3D-M, that view does not hold. 如前所述,存储原始码的3D-M可以很容易地与常规的嵌入式RWM集成在一起(即3DiM),这些RWM可以用来存储升级码,故3DiM支持软件升级。 As described above, the source code is stored 3D-M can be easily integrated with conventional RWM embedded together (i.e. 3DiM), which can be used to store RWM upgrade code, so 3DiM support software upgrades. 由于升级码所占空间比原始码小得多,RWM的容量要求不大,故整体存储成本不高。 Since the upgrade code occupies much less space than the source, not RWM capacity requirements, so that the overall storage cost is not high.

为了便于软件升级,软件设计最好模块化。 In order to facilitate software upgrades, modular software design best. 图15A表示一种软件在3D-M中的存储方式。 FIG 15A shows a manner of software stored in the 3D-M. 因为3D-M中最容易的数据替换方式是字线替换,即将整条字线上的数据一起替换,故软件模块最好以3D-M页为单位存放在3D-M阵列中,且软件模块之间最好不要共享同一3D-M 页。 Because 3D-M data easiest alternative is to replace the word line, the data are about to replace the entire word lines together, it is preferably a software module 3D-M in page units stored in the 3D-M array, and a software module between best not to share the same 3D-M page. 这里,3D-M页(如20S[0j)是指一条字线(如20[0j)上存储的所有数据。 Here, 3D-M pages (e.g., 20S [0j) refers to all data stored on a word line (e.g., 20 [0j). 在该实施例中,软件模块160a含有2047位数据,因一3D-M页含1024位数据,故160b被存储在两个3D-M页20S[0】、20S[lj中,其中,3D-M页20S[l】的最后1位lbz最好是一哑元。 In this embodiment, the software modules 160a containing 2047 data, due to a page containing 3D-M 1024 data, it is stored in two 160b 3D-M pages 20S [0], 20S [lj, in which, the 3D- M pages 20S [l] is preferably the last one is a dummy lbz. 如果软件模块160a需要被升级,则字线20[01、 20[11上的所有数据在输出时被升级码替换。 If the software modules 160a needs to be upgraded, the word lines 20 [01, 20 on all of the data [11 upgraded to be replaced when the output code. 这可通过机动码块来实现。 This may be achieved by motorized code blocks.

图15B -图15C表示两种机动码块。 FIG 15B - FIG. 15C show two motorized code blocks. 这些机动码块也可用来纠正字线错误。 The motor may also be used to correct code block error word line. 图15B中的第一机动码块166与图14B-图14C类似,它基于"读时替换"。 15B, a first motor 166 and the code blocks in FIG. 14C is similar to FIG. 14B-, which is based on "alternative reading." 该实施例含有二个升级组, 它们可以对两个3D-M页进行升级。 This embodiment comprises two groups upgrade, which can be upgraded to two 3D-M pages. 每个升级组存储有效位vwl (l位)以及需升级原始码的行地址wwl (IO位)和升级码dwl ( 1024位)。 Storing each set of active bit upgrade vwl (l bits) and row addresses need to upgrade the source wwl (IO bits) and upgrade code dwl (1024 bits). 有效位寄存器的选中端161s最好与cRD 75相连。 Select the end 161s of the valid bit register is preferably connected to cRD 75. 在读时,比较器162a比较AS2与wwl,如相符,则根据2c从dwl读出64位数 In reading, the comparator 162a and Comparative AS2 WWL, such as match, then read out from 2c according dwl 64 bits

15讲ii/w, 冗仁于z^赏伏i&t iir>vv e^hs市'jr付特raj双併资秋。 Lecture 15 ii / w, z ^ redundant kernel Rewards in volts i & t iir> vv e ^ hs City 'jr pay raj bis Laid-owned and autumn. ;t日乂旦処,y「^卜^岭'—、jh》jtt 级码。另外,机动码块也可以基于"读后替换"(参见图14DA),在此不再赘述。注意到, 如需对字线数据进行替换,则在此读周期内没有必要从3D-M阵列中读数据,故可以将3D-M 阵列强制进入"软断电"(参见图3DD),从而降低能耗并能迅速恢复工作。 ;. T qe day at once, y "^ ^ Bu Ridge '-, jh". Jtt stage codebook Further, the motor may be based on code block "alternative reading" (see FIG. 14 Da), are not repeated here noted, for the word line data replacement is not necessary in this read cycle data is read from the 3D-M array, it may be forced into an array of 3D-M "soft power-oFF" (see FIG 3DD), thereby reducing energy consumption and can quickly return to work.

图15C中的第二机动码块借用了计算机虛拟存储器中分页管理的概念,它将输入地址^见为虚拟地址,并对其进行地址转换而得到存储器的物理地址。 Second motorized code blocks in FIG. 15C borrowed physical address in a computer virtual memory paging management concept, it will see the input address is a virtual address ^, and its memory address translation obtained. 该实施例含有一升级块860、 一地址译码器164D和一地址转换块164T。 This embodiment comprises an update block 860, an address decoder and an address conversion block 164D 164T. 升级块860含有RWM,它存储升级码。 Block 860 contains upgrade RWM, it stores the code upgrade. 3D-M 0 和升级块860组成一统一存储空间86S。 3D-M 0 and 860 form a unified block upgrade storage space 86S. 这里,3D-M 0占据了统一存储空间86S的低1020 行R【00000 00000j-R[11111 11011】,升级块860占据高4行R【11111 11100】墨R[11111 11111】。 Here, 3D-M 0 occupies a unified memory space 86S of the lower row R [1020 00000 00000j-R [11111 11011], upgrade block 860 occupies a high row R [4] 1111111100 ink R [11111 11111]. 地址转换块164T实际上是一存储器,它的每一行存储一个86S的地址或准地址。 Address conversion block 164T is actually a memory which stores the address of each row or address of a registration of 86S. 所谓准地址,是指它需要经过一些运算后才能被视为物理地址。 The so-called quasi address, it refers to the need to go through some of the operations to be considered a physical address. 地址转换块164T的输入地址86A为输入地址的高10位A【13:4j,其输出86TA有10位TA【9:01,它们被最终送到地址译码器164D 作为统一存储空间86S的物理地址。 Address conversion block 86A 164T input address input of 10-bit address A [13: 4j, which has an output 10 86TA [9:01 TA, which are ultimately supplied to the address decoder 164D as a unified physical storage space 86S address. 地址译码器164D根据物理地址对86S提供地址译码。 The address decoder decodes the address 86S 164D provide the physical address. 当需要使用3D-M中的原始码时,物理地址指向3D-M 0:如86A是00000 00000 (即164T 的行165a) , 86TA为00000 00000,它指向3D-M 0中的行R[00000 00000】,即原始码。 When required the source 3D-M, the physical address points to 3D-M 0: 00000 00000 As is 86A (i.e., 164T line 165a), 86TA 00000 to 00000, which points to the line R 3D-M 0 in [00000 00000], that the source code. 当需要使用升级码时,物理地址指向升级块860:如86A是00000 00100 (即164T的行165d ), 86TA为11111 11110,它指向升级块860的行R[lllll 11110】,即升级码。 When the code required to upgrade, upgrade the physical address points to a block 860: 00000 00100 As is 86A (i.e., the line 165d 164T), 86TA 11111 11110 which points to the row blocks R upgrade 860 [lllll 11110], i.e. the code upgrade. 地址转换可以4艮方便地用在软件升级、缺陷字线纠错、单芯计算机(computer-on-a-chip)等应用中。 Address conversion may be conveniently used in Burgundy 4 software upgrade, correction defective word line, the single-core computer (computer-on-a-chip) and the like applications.

虽然以上说明书具体描述了本发明的一些实例,熟悉本专业的技术人员应该了解,在不远离本发明的精神和范围的前提下,可以对本发明的形式和细节进行改动,譬如说,本说明书中的3D-M阵列实施例为1024x1024,实际使用的3D-M阵列一般是〜10、104。 While the above description specifically describes some examples of the present invention, Those skilled in the art will appreciate, without remote from the spirit and scope of the present invention, changes may be made in form and detail of the invention, for example, the present specification Example 3D-M of the array of 1024x1024, 3D-M array of practical use is generally ~10,104. 这并不妨碍它们应用本发明的精神。 This does not prevent their use spirit of the present invention. 因此,除了根据附加的权利要求书的精神,本发明不应受到任何限制。 Thus, in addition to the appended claims according to the spirit of the present invention is not subject to any restrictions.

Claims (3)

1. 一种三维电编程只读存储器,其特征在于含有:一衬底电路(10);至少一堆叠在衬底电路上方的三维存储层(100),该三维存储层通过多个接触通道口(20v)与所述衬底电路相连;和一编程电压接线垫(12P),该编程电压接线垫为该三维存储层引入编程电压。 1. A three-dimensional electrically programmable read-only memory, characterized by comprising: a circuit substrate (10); at least a three-dimensional stacked memory layer (100) above the circuit substrate, the three-dimensional memory layer by a plurality of contact passage opening (20V) is connected to the circuit substrate; and a program voltage terminal pad (12P), the programming voltage for programming voltage introduction terminal pad layer of the three-dimensional storage.
2. 根据权利要求1所述的三维电编程只读存储器,其特征还在于:该三维电编程只读存储器为一次编程的三维电编程只读存储器。 2. The three-dimensional electrically programmable read-only memory according to claim 1, further characterized in that: the three-dimensional electrically programmable read only memory programmed once electrically programmable read only memory dimensional.
3. 根据权利要求1所述的三维电编程只读存储器,其特征还在于:所述衬底电路不含有编程电压产生电路。 The three-dimensional electrically programmable read-only memory according to claim 1, further characterized in that: the substrate does not contain a programming circuit voltage generating circuit.
CN 200610159412 2001-11-18 2002-11-17 Three-dimensional electric programming read-only memory CN100485942C (en)

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CN 200610159412 CN100485942C (en) 2001-11-18 2002-11-17 Three-dimensional electric programming read-only memory
CN 200810185313 CN101540318B (en) 2001-11-18 2002-11-17 Three-dimensional read only memory (3D-ROM) adopting crystallite semiconductor materials
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CN102262904B (en) * 2010-05-24 2014-12-24 张国飙 Large bit-per-cell three-dimensional mask-programmable memory
WO2013029531A1 (en) * 2011-09-01 2013-03-07 Zhang Guobiao Onsite repair system and method
CN105990351A (en) * 2015-02-26 2016-10-05 杭州海存信息技术有限公司 Separated three-dimensional vertical memory
CN105262457A (en) * 2015-09-24 2016-01-20 深圳市芯海科技有限公司 Bias circuit of RC oscillator capable of on-chip and off-chip frequency modulation
CN109102837A (en) * 2016-04-14 2018-12-28 杭州海存信息技术有限公司 Three-dimensional one-time programming memory containing dummy word line

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5835396A (en) 1996-10-17 1998-11-10 Zhang; Guobiao Three-dimensional read-only memory
CN1212452A (en) 1998-09-24 1999-03-31 张国飙 Three-dimensional read-only memory
US6004825A (en) 1996-06-07 1999-12-21 Micron Technology, Inc. Method for making three dimensional ferroelectric memory

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5358887A (en) 1993-11-26 1994-10-25 United Microelectronics Corporation Ulsi mask ROM structure and method of manufacture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6004825A (en) 1996-06-07 1999-12-21 Micron Technology, Inc. Method for making three dimensional ferroelectric memory
US5835396A (en) 1996-10-17 1998-11-10 Zhang; Guobiao Three-dimensional read-only memory
CN1212452A (en) 1998-09-24 1999-03-31 张国飙 Three-dimensional read-only memory

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