CN100480940C - Synchronous buck converter improvements - Google Patents

Synchronous buck converter improvements Download PDF

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CN100480940C
CN100480940C CN 03810054 CN03810054A CN100480940C CN 100480940 C CN100480940 C CN 100480940C CN 03810054 CN03810054 CN 03810054 CN 03810054 A CN03810054 A CN 03810054A CN 100480940 C CN100480940 C CN 100480940C
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converter
output
current
node
stage
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CN 03810054
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CN1650241A (en )
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J·张
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国际整流器公司
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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1588Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion
    • Y02B70/14Reduction of losses in power supplies
    • Y02B70/1458Synchronous rectification
    • Y02B70/1466Synchronous rectification in non-galvanically isolated DC/DC converters

Abstract

同步降压转换器在输出电流下降期间提供改进的输出电流读出电路(608)和改进的瞬变行为。 Provide an improved synchronous buck converter output current during the output current drops readout circuit (608) and an improved transient behavior. 还公开了一种多相位同步降压转换器,具有改进的输出电流共用能力,以及具有改进的负载平衡能力的多同步降压转换器。 Also disclosed is a multi-phase synchronous buck converter, having an improved output current capability sharing, and having an improved load balancing of multiple synchronous buck converter. 为实现输出电流读出(608),读出电路包括与并联MOSFET同步地开和关操作的采样开关以便采样并联MOSFET的R<sub>DS-ON</sub>两端的电压,以及向可变增益放大器提供采样电压。 To achieve the current sense output (608), readout circuit includes a sampling switch opening and closing operations in synchronization with the sampling in parallel to the MOSFET <sub> voltage DS-ON </ sub> across the parallel MOSFET of R, and to the variable voltage gain amplifiers provide samples. 读出电路还包括实现低通滤波器的RC电路,由此可变增益放大器的输出基本上与电感器的值以及输入到采样开关的信号的任何时间的变动分量的大小无关。 Readout circuit further comprises an RC circuit to achieve a low-pass filter, the variable gain amplifier whereby the output value is substantially independent of the inductor and the fluctuation component is input to the signal at any time the size of the sampling switch. 当该设备封装MCM时,基于R<sub>DS-ON</sub>的值,能微调电流读出电路(608)增益。 When the MCM package the device, based on R <sub> DS-ON </ sub> values, fine-tune current sense circuit (608) gain. 通过使用IC内的热敏设备,根据组件温度,也能调整电流读出增益以消除R<sub>DS-ON</sub>温度变化。 By using a thermal device in the IC, according to the assembly temperature, the read current can be adjusted to eliminate the gain R <sub> DS-ON </ sub> temperature. 以及根据门电压来消除由于门电压改变的R<sub>DS-ON</sub>变化。 And according to the gate voltage to eliminate the gate voltage change of R <sub> DS-ON </ sub> change. 对改进的输出电流共用(608),用于每个转换器级的读出电路根据来自多相位转换器的输出电压和表示输出节点处的所需电压的参考信号间的差值,以用于单个转换器级的开关晶体管的预定相位关系生成信号。 Improved current sharing of the output (608), for reading each converter stage output voltage from the circuit according to the multi-phase converter and a reference signal indicative of a difference between the desired voltage at the output node, for the predetermined phase relationship of the individual converter stage switching transistor generates a signal. 用于每个转换器级的占空比微调修改来自主控制器(PWM IC)的占空比控制信号以便尽可能地使由每个级提供的电流相等。 Duty cycle for each converter stage duty cycle control signal trim modifications from the main controller (PWM IC) so that the current supplied by each stage be as equal as possible. 用于每个转换器级的电流共用控制电路向占空比微调电路提供控制信号。 For each of the common current converter stage duty cycle control circuit to provide a control signal trimming circuit. 这用来提供特定级的实际电流输出和所有级电流的平均值、最小级电流或最大级电流间的差值信号。 This average is used to provide a particular level and all the output current of the current stage, the difference signal between the current minimum level or maximum current level.

Description

同步降压转换器改进 Improved Synchronous Buck Converter

相关申请 RELATED APPLICATIONS

本申请基于并要求2002年4月3日提交的,名为MULTI-CHIP MODULE CIRCUIT IMPROVEMENTS的US临时申请No.30/370,007 This application is based on and claims, US named MULTI-CHIP MODULE CIRCUIT IMPROVEMENTS 2002 April 3 Provisional Application No.30 / 370,007

的优先权,其内容在此引入以供参考。 It filed, which is incorporated herein by reference.

技术领域 FIELD

本发明涉及多相位同步降压转换器的改进,以及具体地说,涉及具有用于输出电流读出(current sensing)、用于组件间的电流共用,以及快速负载变化期间,提高的瞬变性能的改进技术。 The present invention relates to improved multi-phase synchronous buck converters, and in particular, relates to a current sharing between components, and a period for reading out an output current (current sensing) for rapid load changes, improved transient performance improved technology. 在多芯片组件(MCM)实现的环境中描述和示出了本发明,但所公开的改进也能应用于不同元件实现。 Described and illustrated in the present invention is implemented in a multi-chip module (MCM) environment, but the improvements disclosed can be applied to different elements implemented.

背景技术 Background technique

MCM是包括在具有由绝缘材料分开的多个互连层的共用衬底上的形成的多个集成电路(ICs)的电子封装。 An integrated circuit comprising a plurality of MCM (ICs) formed on a common substrate having a plurality of interconnect layers separated by an insulating material of an electronic package. 封装整个组件,而不是单个ICs。 Encapsulate the entire assembly, rather than individual ICs.

MCMs在由安装在传统的印刷电路板的单个芯片形成的电路上提供几个重要的好处。 MCMs offers several important benefits in the circuit formed by the single chip mounted on a conventional printed circuit board. 这些包括增加布线以及元件密度和低成本。 These include increasing the wiring and the element density and low cost. 同时, MCMs的紧密结构能产生更短的信号传输时间以及降低寄生阻抗,反过来,这提高了高速开关效率。 Meanwhile, the MCMs compact structure can produce a shorter signal propagation time and reduced parasitic resistance, in turn, improves the efficiency of high-speed switching. 同时,在MCM内包括有源元件使得MCM更可测试为具有必定提高可靠性的整个电源。 At the same time, including an active element in the MCM so that more can be tested with MCM necessarily improve the reliability of the entire power. (第2页第1至2 行)。 (Page 2, line 2 to 1).

MCM封装适合于大量应用,包括多相位同步降压转换器。 MCM package is suitable for a large number of applications, including multi-phase synchronous buck converter. 同步降压转换器是接收DC(或整流AC)输入和产生具有高输出电流的稳定低压输出的开关的DC电源。 Synchronous buck converter is a DC DC power switch receiving (or rectified AC) input and generates a stable voltage output of a high output current. 降压转换器特别用作用于微处理器操作设备以及大量其他数字电路应用的电源。 The buck converter as a power source in particular operating a microprocessor device, and a host of other digital circuit applications.

同步降压转换器的基本结构如图1所示,通常用IOO表示的电路包括具有在输入端104和第一信号节点106间连接的源-漏通路、通常为功率MOSFET等等的串联开关102、通常也为功率MOSFET等等的并联开关108,以及由串联电感器112和在信号输出节点116连接到电感器112并连接到地的并联电容器114组成的输出电路。 The basic structure of a synchronous buck converter as shown, generally indicated by IOO circuit comprises a source 1 having a first signal input terminal 104 and the node 106 is connected between the - drain path, the series switch 102 is typically a power MOSFET, etc. , usually parallel switch like a power MOSFET 108, and a series inductor 112 and a signal output node 116 is connected to an inductor 112 and parallel capacitor 114 is connected to the output circuit consists of a composition. 如果需要的话,也可以与MOSFET108并联提供并联二极管,诸如Shottky 二极管118以便在108的空载时间提供电导来降低与MOSFET108的内部本体二极管有关的二极管逆恢复损耗。 If desired, it may also be provided with MOSFET108 parallel diode connected in parallel, such as a Shottky diode 118 to provide electrical dead time inverse diode 108 to reduce the interior of the body diode recovery loss associated MOSFET108. 如果认为对外部Schottky来说,更高的开关损耗是最佳的,则不需要单独的二极管118。 If the external Schottky considered, the higher switching losses is the best, no separate diode 118.

在输入电容器111上,在输入端104和地间提供AD.C输入电压VIN,以及将小于Vw的输出电压VouT提供到连接在信号输出节点116 和地110间的负载124。 On the input capacitor 111 provided AD.C input voltage VIN, and the output voltage Vw is less than VouT supplied to the load 124 is connected at the signal output node 116 and ground 110 between the input 104 and ground.

通过有选择地改变MOSFETS102和108的占空比,提供输出电压的控制。 MOSFETS102 by selectively varying the duty cycle and 108, and a control output voltage. 这是通过连接到MOSFETS的栅极端、并由PWM发生器124 组成的脉冲宽度调制电路124驱动的门控制逻辑或驱动电路120来完成的,PWM发生器124将所需开关频率并具有固定最大值(峰值)和最小值(谷值)的斜坡信号与误差放大器126提供的信号进行比较。 This is accomplished by a gate terminal connected to the MOSFETS, a pulse width modulation circuit 124 by the PWM generator 124. The driving gate drive circuit 120 or the control logic to complete, the PWM generator 124 to the desired switching frequency and has a fixed maximum value (peak) and comparing the ramp signal with the error amplifier signal minimum (valley) 126 provided. 后者基于由信号线128上的反馈信号VpB表示的实际输出电压和在第 Which is based on the actual output voltage indicated by the feedback signal on the signal line 128 VpB first and

二输入端130提供的所需输出电压信号VREF间的差值,提供输出信号VE。 The difference between the desired output voltage signal VREF supplied two-input 130, providing an output signal VE.

在操作中,通过MOSFET102开以及MOSFET108关,电感器112 两端的电压等于VIN-VOUT,以及最终电流使电容器114充电。 In operation, it is equal to VIN-VOUT, and finally the capacitor 114 is charged by the current voltage 112 across the opening and MOSFET108 MOSFET102 off, inductor. 为维持电容器114两端的基本恒定的电压,预定值VE操作PWM电路124 和门驱动器120以便断开MOSFET102,以及导通MOSFET108。 In order to maintain a substantially constant voltage across the capacitor 114, a predetermined value VE operating PWM circuit 124 and gate driver 120 to disconnect the MOSFET 102, and MOSFET 108 is turned on. 当MOSFET108导电时,其非常低的源-漏电阻维持电路来支持流过电感器112的电流。 When MOSFET108 electrically conductive, which is very low source - drain current of the inductor resistance hold circuit 112 to flow through the support. 反过来,这允许电容器114充电,以及在MOSFETS 的几次开-关周期后,获得稳定状态输出电压。 In turn, this allows charging the capacitor 114, and the MOSFETS in several open - closed after cycle, the steady state output voltage is obtained. 图l所示的电路的运行对本领域的技术人员来说是非常公知的,以及为简洁起见,将省略进一步描述。 Operation of the circuit shown in Figure l to those skilled in the art is very well known, and for brevity, further description will be omitted.

在需要超出MOSFETS102和108的输出电流的情况下,可以采用多相位降压转换器,如由图2所示的电路200所示。 In the case where the output current needs exceed MOSFETS102 and 108 may be multi-phase buck converter circuit shown in FIG. 2 as 200 in FIG. 在此,N个同步降压级202A-202N连接在输入节点208和公共接地210间以及它们的 Here, N synchronous buck stages 202A-202N and 208 are connected between the common ground and the input node 210 thereof

13输出馈送输出节点212。 13 output feeds an output node 212. 因此每级贡献部分所需电流需求。 Therefore, the contribution of each level required part of the current demand.

转换器级202A包括输入电容器203、MOSFET对204、并联Shottky 二极管205、输入电感器206、输出电容器214以及门驱动电路216。 Converter stage 202A comprises an input capacitor 203, MOSFET 204 on, parallel Shottky diode 205, an input inductor 206, a capacitor 214, and the output of gate drive circuit 216. 类似地构成其他转换器级。 Other similarly constructed converter stages.

主PWM控制器218产生具有相位间360°/N相位延迟的交错或异相PWM信号。 PWM controller 218 generates the primary phase PWM signal having a phase between 360 ° / N phase delay staggered or different. 可以用任何适当的或所需方式构成主控制器218,以及可以由例如在FM-N《w操作的可调整频率主时钟220,其中N为相位数,以及fW是用于MOSFETS的预定开关频率、以频率U生成脉冲串的可编程计数器222、 一连串N个串联PWM电路224A-224N以及误差放大器226组成。 May be formed by any suitable or desired manner the main controller 218, and may be formed, for example, an adjustable frequency of the master clock in the FM-N "w operation 220, where N is the number of phases, and fW is a predetermined switching frequency MOSFETS to generate a frequency burst U programmable counter 222, a series of N series circuits 224A-224N and a PWM error amplifier 226 components. 后者提供公共输入来触发PWN电路,由此, 将一系列驱动信号PWM-1至PWM-N提供为转换器级202A-202N的门驱动器216的输入。 Which provides a common input to trigger the PWN circuit, whereby the drive signal PWM-1 series to provide a PWM-N to converters 202A-202N stage gate driver input 216.

按360/N的相位延迟,分开驱动信号,如图3所示,图3示例说明用于具有5MHz时钟频率以及lMHz开关频率的五相位转换器的同步信号的时序。 Press phase 360 ​​/ N delays, the partitioning-drive signal, shown in FIG. 3, FIG. 3 illustrates an example of timing with the clock frequency of 5MHz and a synchronization signal of a five-phase converter switching frequency lMHz. 由此,可以看出在五个连续lMHz开关周期期间,五个转换器级以参差方式操作,每个按(1/5) *10_6秒交错。 Thus, it can be seen lMHz during five successive switching cycles, the converter stage in five staggered manner, each by (1/5) * 10_6 second interleaving. 由于多相位同步降压转换器对本领域的技术人员来说是非常公知的,为简洁起见, 将省略图2所示的有关配置的详细描述(与图1的情形相同)。 Since the multi-phase synchronous buck converters to those skilled in the art is very well known, for brevity, will be (the same as the case of the FIG. 1) detailed description of the configuration shown in FIG. 2 will be omitted.

然而,还存在需要对同步降压转换器的现有的设计改进的某些方向,其中: However, there exists a need for a conventional synchronous buck converter design improved in certain directions, wherein:

(a)生成用于输入到PWM控制器的电流反馈信号的改进方式。 (A) generating an input to the improved way of current feedback signal PWM controller. 由用于MOSFETS的开关占空比控制在多相位转换器的单个转换器级中共用的输出电压和电流。 Controlling multi-phase converter of the single stage converter output voltage and current from the common to the switching duty for the MOSFETS. 由于高输出电流有利于"无损耗"型读出, 通常由诸如图4所示的采样和保持电路400来生成电流反馈信号。 Due to the high output currents favor "lossless" type sense circuit generating a current feedback signal 400 is typically held by the sample as shown in FIG. 4 and FIG. 在这里,在每个MOSFET开关周期期间,采样一次并联MOSFET402的RDs.加两端的电压。 Here, MOSFET switching during each cycle, the sampling time of a parallel RDs MOSFET402 voltage applied across. 采样和保持电路400包括晶体管404和406 (简单地示为开-关开关),以及电容器408。 Sample and hold circuit 400 includes transistors 404 and 406 (shown as a simple switch switches), and a capacitor 408.

另夕卜,如果Vm和VouT比率为串联FET具有大的占空比,就能采样串联MOSFET的RDS_0N两端,而不只是并联MOSFET的电压。 Another Bu Xi, if the ratio of Vm and VouT series FET having a large duty ratio, the sampling can ends RDS_0N the MOSFET in series, in parallel and not just the voltage of the MOSFET.

然而,每种方法获得通常小RDS-ON值,然而,必须通过放大器410 放大所采样的电压信号。 However, each method for obtaining a value usually smaller RDS-ON, however, a voltage signal must be amplified by the amplifier 410 is sampled. 该方法存在几个缺点。 This method has several disadvantages. 一个缺点是放大器410需要具有高带宽和高转换速率来精确地采样并联MOSFET402的Ros.oN两端的电压。 One disadvantage is the need for amplifier 410 with high bandwidth and slew rate to accurately sample the voltage across the parallel MOSFET402 Ros.oN. 同时,放大器410的输出花费时间来解决限制其高频率响应。 Meanwhile, the output of the amplifier 410 takes time to address the limitations of its high frequency response. 另外,在 In addition,

电感器电流中存在固有的大电流脉动内容,其反映在RDS-(^两端的脉 SUMMARY inherent large current ripple inductor current, which is reflected in the RDS - pulse (^ ends

动电压中。 Dynamic voltage. 根据采样的时序,所采样的信号可能不反映DC输出电流, 因此,电感器脉动电流大小和采样时间会导致电流读出误差。 The timing of the sampling, the sampled signal may not reflect the DC output current, and therefore, the inductor ripple current magnitude and causes a current sampling time readout errors.

(b) 转换器级中共用电流。 (B) common to current converter stage. MCM结构能有利地用于多相位同步降压转换器。 MCM structure can be advantageously used in multi-phase synchronous buck converter. 能为每个转换器级提供MCMs (如果需要的话,在转换器级组件中包括输入和输出电容器以及串联电感器)。 Providing the MCMs (if necessary, the converter stage includes an input assembly and an output capacitor and a series inductor) for each converter stage. 通常,提供单个控制器来控制电流共用,或将函数集成在主PWM控制器中,两种方法很复杂以及非常不适合于换算数。 Typically, a single controller to control current sharing, or a function integrated in the master PWM controller, the two methods is very complicated and not suitable in terms of number. 同时,由于大的输出电流,通常采用无损耗读出,具有如上所述的缺陷。 Meanwhile, due to the large output current, usually read without loss, having defects described above. 此外,选择电流读出增益不基于逐个级。 In addition, the read select a current gain is not on a per level. 这导致不确定的电流共用,因为在MCM结构中,并联MOSFET的RDS.oN能在组件间的改变,以及通过温度和门电压改变。 This current sharing results in uncertain because of MCM structure, the parallel between the MOSFET RDS.oN assembly can change, and by changing the gate voltage and temperature.

(c) 组件间导电损耗的变化。 Changes between the conduction losses (c) component. RDS.0N的组件对组件变化也能导致并联MOSFET中的不平衡导电损耗。 RDS.0N component to component variations can lead to an imbalance in parallel conduction losses in the MOSFET. 更具体地说,在多相位电源中, 可输送的总输出电流由最差,即最热运行组件确定。 More specifically, in the multi-phase power, the total output current can be delivered is determined by the worst, i.e., the hottest running assembly. 为最大化输出电流能力,应当访问最差组件来输送最小电流,因此,功率共用甚至比电流共用更重要。 To maximize the output current capability, the worst access component should be delivered minimum current, therefore, even more important to share common power current ratio.

传统的设计不提供有效的功率共用。 Conventional designs do not provide efficient power sharing. 为理解此,再参考图2,假定两级转换器,即N二2。 To understand this, again with reference to Figure 2, assume that two converters, i.e., N = 2. 还假定下述: It is also assumed the following:

并联MOSFET弁(组件202-l中)的RDS_ON=0.005Q Bian parallel MOSFET (202-l of the assembly) of RDS_ON = 0.005Q

并联MOSFET井(组件202-2中)的RDS_ON=0.006Q Parallel wells MOSFET (component 202-2) of RDS_ON = 0.006Q

输出电流IouT二20A Output current of 20A two IouT

Vin=12.0V Vin = 12.0V

VOUT=1.0V VOUT = 1.0V

使用传统的MOSFET RDS-0N电流读出,以及假定两个相位组件并联,每个相位中的电流实际上由有效并联电路确定。 Using conventional MOSFET RDS-0N current sense, and assuming two parallel assembly phase, the current in each phase is determined by the effective practically parallel circuit. 换句话说,组件202-1中的电流实际上为20*6/ (5+6) =10.9A,以及组件202-2中的电流实际上为20*5/ (5+6) =9.1A。 In other words, the current component 202-1 is actually 20 * 6 / (5 + 6) = 10.9A, and the current is practically assembly 202-2 20 * 5 / (5 + 6) = 9.1A . 因此,各个I2R损耗将为0.59W 禾口0.5W。 Therefore, each of Hekou I2R losses will 0.59W 0.5W. 每个组件以某种方式设计成正好提 Each component in some manner designed to provide exactly

供20A输出的IO.OA,组件202-1中的I2R损耗将为0.5W,以及组件202-2中为0.6W。 I2R losses IO.OA, 202-1 for assembly 20A will be outputted 0.5W, and a component 202-2 is 0.6W. 正如可以理解到,这种情形比具有更大的Rds.on不平衡更糟。 As can be appreciated, this situation has a greater imbalance worse than Rds.on.

(d)负载变化期间的不期望的瞬变行为。 Undesirable during (d) changes in load transient behavior. 当有快速负载转变时, When there are rapid load change,

不对称输出电压过冲以及由于Vw和Vout的大比率,观察到下冲。 And asymmetric output voltage overshoot due to the large ratio Vw and Vout observed undershoot. through

过降压负载下冲的输出电压通常大于具有升压负载下冲。 The antihypertensive punch load is generally greater than the output voltage of the boost load having a punch. 为防止电压过冲,通常使用大的且昂贵的输出电容器。 To prevent the overshoot voltage, typically using large and expensive output capacitor.

因此,根据现有技术,可以看出多相位同步降压转换器仍然存在问题。 Thus, according to the prior art, it can be seen a multi-phase synchronous buck converter remains problematic. 本发明试图减少这些问题的一部分。 The present invention seeks to reduce some of these problems.

发明内容 SUMMARY

根据本发明,用于生成用于输入到误差放大器中的电流读出反馈 According to the present invention, for generating a read out for input to the current error amplifier feedback

信号的改进电路包括通过低通滤波器,诸如RC平均电路连接到提供反馈信号Vra的放大器的采样开关。 Improved circuit comprises a signal through a low pass filter, such as RC averaging circuit connected to the switching amplifier provide samples of the feedback signal Vra. 与并联MOSFET—样,选通采样晶体管以便两者在同一时间均导通。 Parallel MOSFET- like, to both the gate of the sampling transistor are turned on at the same time. 如果需要或期望的话,可以在使MOSFET选通为导通的时间和在使平均电路导通前,采样以确保MOSFET完全导通的时间间提供稍微延迟。 If necessary or desired, may be in the MOSFET gate is turned on at a time and that the averaging circuit is turned on before sampling to ensure that the MOSFET is fully between the time to provide a slight delay. 另外,如果用于串联MOSFET的占空比长以及并联MOSFET短(例如,通过小的Vjn与V0UT比),能采样串联MOSFET的V两端的电压,而不是并联MOSFET。 Further, if the duty cycle of the MOSFET for the series and the parallel MOSFET short length (e.g., through a small Vjn and V0UT ratio), able to sample the voltage across the MOSFET series V, instead of parallel MOSFET.

通过采用低通滤波器,用于RC电路的电容器两端的DC电压将与电感器电流的DC值成比例,而与电感器值以及脉动电流大小无关。 By using a low pass filter, a DC voltage across the capacitor of the RC circuit will be proportional to the value of the inductor DC current, regardless of the value of the inductor ripple current and the size.

同时,如果将电流读出IC电路封装在具有转换器级的单个MCM 中,基于Rds.,信,可以微调电流读出增益。 Meanwhile, if the current sensing circuit IC MCM package having a single stage of the converter, based on Rds., The letter may be read out tune current gain. 还可以通过使用IC内的 You can also provided with an IC

热敏设备,根据组件温度来调整电流读出增益以消除RDS-on温度变化。 Thermal devices to adjust the current temperature readings assembly according to eliminate the gain RDS-on temperature change. 以及根据门电压来消除基于门电压变化的RDS-on变化。 And according to the gate voltage to eliminate the RDS-on voltage change based on a change of the door.

使用包括有选择地延迟输入PWM信号的前沿的占空比微调电路的门驱动器,提供根据本发明改进的电流共用,因此縮短串联MOSFET 的导通时间。 Use comprising selectively delaying the input door drive duty ratio of the PWM signal of the leading edge of the trimming circuit, according to the present invention to provide improved current sharing, thus shortening the conduction time of the MOSFET in series. 通过包括放大表示组件电流电平的信号和通过耦合电路, 共同连接到所有组件电流电平信号上的I-share总线上的信号间的电流差的放大器的电流共用控制电路来确定延迟时间。 Determining a delay time includes an enlarged current amplifier common current difference signal between the signal component and the current level through the coupling circuit is commonly connected to the current level of all components of the I-share bus signal control circuit. 在一个实施例中,耦合电路由每个组件中的各个电阻器组成以提供表示各个转换器级中的电流的平均值的总线信号。 In one embodiment, the coupling circuit by respective resistors each component to provide a composition represented by the average value of the current converter stage in each bus signal. 因此,每个级中的放大器的输入表示那个级中的实际测量电感器电流和所有级中的电感器电流的平均值间的差值。 Thus, each stage of the input of the amplifier represents the difference between the average value of the inductor current actual measured inductor current that stage and all stages. 由组件中的占空比微调电路来使用反映传播延迟RDS.0N和其他级间参数变化的这一差值以便微调占空比来将流过组件的电流平衡到每相位输出电流的平均值。 The duty ratio of component trimming circuit is used to reflect this difference in propagation delay between RDS.0N and other parameters in order to fine tune stage duty cycle average of the current flowing through each phase of the assembly to balance the output current. 作为上文的变形, 通过延长每个组件的PWM信号的前沿,有选择地增加占空比,能校正电流不平衡。 As a variant of the above, by extending the leading edge of each component of the PWM signal, selectively increases the duty cycle, the current imbalance can be corrected.

在另一实施例中,可以由充当AND电路、具有控制I-share电路的各个转换器级中的电流读出信号的最低值的二极管代替每个转换器级中的输入电阻器。 In another embodiment, it may be formed to act as an AND circuit, each current converter stage I-share control circuit having a diode lowest value read in place of each signal converter stage input resistors. 相当于最低电流值的信号因此出现在I-share总线上,作为每个求和/隔离放大器的输入以及每个求和/隔离放大器的输出将使得各种占空比微调电路降低占空比,因此,降低用于所有级的输出电流以便匹配最低电流级。 Corresponds to the lowest value of the current signal thus appears on the I-share bus, as each of the summing / isolation amplifier, and an output of each summing / isolation amplifier will be reduced so that the various duty ratio duty cycle trimming circuit, Thus, for all of the stages to reduce an output current to match the lowest current level.

作为另一变形,能连接I-share总线控制电路中的二极管以便共同用途具有控制I-share总线的各个转换器级中的电流读出信号的最高值。 As another modification, can be connected to I-share bus control circuit uses a diode for common control of the current I-share bus read highest signal of each converter stage has a. 在这一结构中,各个占空比微调电路将用来增加占空比,从而增加输出电流以便匹配最高电流级的输出电流。 In this structure, each of the trimming circuit will be used to increase the duty ratio of the duty ratio, thereby increasing the output current to match the current highest output current level.

为对多相位系统的转换器级间的功率损耗变化提供补偿,能在那个级的并联MOSFET的RDS.0N的实际测量值和用于所釆用的类型的并联MOSFET的Rds-cw僮的平均RAV间的差值,微调每个级中的电流读出放大器的增益。 Provide compensation for the power loss change between stages of the multi-phase converter system, the actual measurement value can RDS.0N that stage parallel MOSFET and Rds-cw for the average child in parallel with the MOSFET type Bian the difference between the RAV, each stage of the tune current readout gain of the amplifier. 这可以由例如来自产品的测试数据,历史地确定。 This can, for example, determined by historical data from the test product.

由于电流读出放大器和MOSFETS能放在MCM内,能在封装后步骤中微调电流读出放大器的增益。 Since the current sense amplifier MOSFETS and can be placed within the MCM, fine-tune current sense amplifier gain after packaging step. 在产生测试期间,当其导电时, 能将预定校准电流输入并联M0SFET中,以及以任何传统或所需方式, 例如,通过烧断内部熔丝来将放大器输出电路设置到相当于所需增益的电平来校准电路。 During test generation, when it is conductive, a predetermined calibration current can M0SFET input in parallel, and in any conventional or desired manner, for example, be provided through the amplifier output circuit to blow the internal fuse corresponding to a desired gain level to the calibration circuit.

通过在降压期间,通过禁用并联MOSFET108提供根据本发明的同步降压转换器级的改进的瞬变性能,特别是在负载降低期间。 During a down by, by disabling the parallel MOSFET108 provide improved transient performance according to the present invention, a synchronous buck converter stage, in particular during the load reduction. 因此, 电流将流过MOSFET的本体二极管以及并联Shottky 二极管118,而不是通过MOSFET的沟道,就象MOSFET导通一样。 Thus, current will flow through the body diode of the MOSFET and the parallel Shottky diode 118, rather than through the channel of the MOSFET, the same as MOSFET is turned on. 这很有利,因为本体二极管和Shottky 二极管两端的压降显著高于导电MOSFET的沟道两端的电压,因此,允许快速耗散瞬变电流。 This is advantageous, because the body diode and the voltage drop across the Shottky diode is significantly higher than the voltage across the conductivity channel of the MOSFET, therefore, allow for rapid dissipation of the transient current.

因此,本发明的目的是通过消除电流读出电路上的电感器脉动电流的影响,提供在同步降压转换器中的改进的电流读出。 Accordingly, an object of the present invention is to read the inductor current ripples on the circuit by eliminating current, provide improved current sensing synchronous buck converter.

本发明的另一目的是提供在同步降压转换器的转换器级中共用的改进的电流。 Another object of the present invention is to improve the current level is common to provide a synchronous buck converter of the converter.

本发明的另一目的是降低使用MCM技术构成的多相位同步降压转换器的组件间的导电损耗的变化。 Another object of the present invention is to reduce the conduction loss variation between components multi-phase synchronous buck converter configuration using MCM technology.

本发明的目的是改进同步降压转换器中,在负载变化期间的瞬变行为。 Object of the present invention to improve the synchronous buck converter, the transient behavior during load changes.

从下述结合附图的描述,本发明的其他目的和特征将变得显而易见。 From the following description in conjunction with the accompanying drawings, other objects and features of the invention will become apparent.

附图说明 BRIEF DESCRIPTION

图1是通常用在说明这些设备的操作中的同步降压转换器以及本发明的某些特征的示意图。 FIG 1 is a schematic diagram generally used in these devices instructions in synchronous buck converters, and certain features of the present invention.

图2是再次示例说明这些设备以及本发明的某些方面的基本特征的多相同步降压转换器的示意图。 FIG 2 is a schematic of a multiphase synchronous buck converter as well as the basic characteristics of these devices with certain aspects of the present invention described example again.

图3是表示用于多相位同步降压转换器的PWM脉冲间的关系的波形图。 FIG 3 is a waveform diagram showing a relationship between a PWM pulse for a multi-phase synchronous buck converter.

图4是使用Rds.on方法,用于电流读出的传统技术的示意图。 FIG 4 is a method using Rds.on, a schematic diagram of the conventional techniques for current sensing. 图5是根据去除脉动电流灵敏度的本发明,改进的采样和保持电路的示意图。 FIG 5 is removed according to the present invention, the sensitivity of the pulsating current, a schematic view of an improved sample and hold circuit.

图6是根据本发明,提供占空比微调控制来补偿允许级中的改进电流共用的多相位降压转换器中的转换器级间的参数变化的技术的示意图。 FIG 6 is according to the present invention, the duty ratio of the fine control to compensate schematic improve current stage common to multi-phase buck converter technology parameter changes between the converter stage allows.

图6A表示如图6所示的技术的变化。 6A shows variation of the technique shown in FIG. 6.

图7表示根据本发明,用于改进负载降压期间的瞬变性能的技术。 Figure 7 shows the present invention, the technical performance during transient load for improving the buck. 具体实施方式 Detailed ways

图5示例说明根据本发明,提供改进的平均电流读出的C读出电路500。 FIG 5 illustrates an example of the present invention, there is provided an improved C average current readout readout circuit 500. 这可以单独地,即作为具有转换器电路502的独立的电路。 This may be used alone, independent of the converter circuit has a circuit 502, i.e., as a. 电路500包括采样开关504,可以是任何适当的或所需类型,具有连接到转换器电路502中的MOSFET508和510间的共用信号节点506的信号输入。 Circuit 500 includes a sampling switch 504 may be any suitable or desired type, having a converter circuit 502 connected to the common signal node 510 and MOSFET508 between the signal input 506. 串联传感器530连接在共用信号节点506和输出节点之间。 Sensor 530 is connected in series between the common node 506 and the output signal node. 采样晶体管504的信号输出连接到任何适当或所需类型的低通滤波器, 例如,包括串联电阻器514和并联电容器516的RC平均电路512。 Sampling a signal output transistor 504 is connected to any suitable or desired type of low-pass filter, for example, comprising a series resistor 514 and shunt capacitor 516. RC circuit 512 average. 可以为跨导放大器(transconductance amplifier)或其等效的放大器518具有连接到并联电容器516的输入520以及提供与可变增益控制电阻器522 两端的输入电压成比例的输出电流。 It may be a transconductance amplifier (transconductance amplifier) ​​or the equivalent of an amplifier 518 having an input connected to the parallel capacitor 520,516 and provide variable gain control resistor 522 across a voltage output proportional to the input current. 跨导放大器的电压-电流增益(gm) 以及522的值确定电流读出增益。 Transconductance amplifier voltage - current gain (gm) and determines the current value readout 522 gain. 能调整gm和522以补偿初始RDS 522 gm and can be adjusted to compensate for the initial RDS

变化、温度和引起RDS变化的门电压。 Changes, temperature changes, and the gate voltage caused RDS.

采样晶体管的控制端524连同并联MOSFET510的栅极端连接到门驱动器528的输出526,以便开关504和MOSFET510在相同时间导通。 A control terminal 524 together with the gate terminal of the sampling transistor is connected to the parallel MOSFET510 gate driver outputs 526,528 so that the switch 504 is turned on and at the same time MOSFET510. 在一些实例中,有必要或期望在MOSFET510导通的时间和对RDS.,两端的电压进行采样以允许MOSFET有限导通的时间之间提供稍微延迟。 In some instances, it is necessary or desirable and MOSFET510 conduction time of the RDS., The voltage across the sampling to allow a slight delay between the MOSFET provide limited conduction time. 该延迟可以通过RC电路,或任何或适当的或所需方式,在门驱动器528中提供延迟(在任何一种情况下,将单独的输出提供到开关504)。 The delay may (in any case, a separate output to switch 504) via an RC circuit, or any suitable or desired manner or, providing a delay in the gate driver 528.

通过使用和MOSFET510的开关周期有关的低通滤波器,诸如RC 平均电路512,电容器516两端的DC电压将与电感器电流的DC值成比例,而与电感和脉动电流大小无关。 By using a low-pass filter and the switching period MOSFET510 related, such as RC averaging circuit 512, DC voltage across capacitor 516 is proportional to the value of the DC inductor current, regardless of the magnitude of the current ripple and inductor.

另外,如果电路500封装在具有转换器级502的MCM中,通过使用热敏电阻器或二极管连同增益调整电阻器522,能对由于温度变化的RDS.M的变化提供补偿,以控制放大器518的增益。 Further, if the circuit package 500 having the MCM converter stage 502, by using a thermistor or a diode together with a gain adjustment resistor 522, can change due to temperature change RDS.M provide compensation to control amplifier 518 gain. 特别地,以与随温度改变的RDS的变化的相同速率降低增益将维持恒定电流读出增益。 In particular, the same rate of change RDS and decreasing the gain changes with temperature to maintain constant current sense gain. 相同的规则应用于门电压补偿。 The same rule applies to the gate voltage compensation. 为部分地校准初始Ros变化,在测试期间,能将预定校准电流,例如lA输入到并联MOSFET510,以及调整增益直到Csence电压处于所需值,例如对50mV/A增益为50mAQ Ros initial calibration change portion, during a test, a predetermined calibration current can, for example, to the parallel input lA MOSFET 510, and adjusting the gain until the voltage at a desired value Csence, for example, 50mV / A gain 50mAQ

如本领域技术人员从上文描述将意识到,根据实际应用,能以各种方式实现低通滤波器。 As those skilled in the art will be appreciated from the above description, according to the practical application, the low pass filter can be realized in various ways. 在RC滤波器512的情况下,在损坏数据采样速度的情况下,选择长时间恒定将提供更精确的DC信息。 In the case of the RC filter 512, in the event of damage data sampling rate, a long time constant selected to provide more accurate information about DC. 另外,其他低通滤波器实现是可能的,例如能降低放大器的增益带宽,重要的概念是在信号通路的某处使用低带宽滤波器以消除脉动影响。 Further, the low pass filter of other implementations are possible, for example, can reduce the gain bandwidth of the amplifier, an important concept is the use of a low bandwidth filter somewhere in the signal path to eliminate the influence of pulsation.

本领域的技术人员从上文描述将意识到,采样并联MOSFET中的 Those skilled in the art will be appreciated from the above description, the sampling of the parallel MOSFET

RDS电流的图5所示的实现是有利的,因为当V!n与VouT比很大时, Shown in Figure 5 to achieve the current RDS is advantageous, because when V is! N-VouT ratio is large and,

其占空比很大。 A large duty cycle. 然而,在其他应用中,例如当V:n与Vchjt比更小的情况下,串联MOSFET将具有比并联MOSFET更长的占空比,以及将更方便地采样其Rds-on电压。 However, in other applications, for example, when V: n and Vchjt ratio smaller, the MOSFET having a series parallel longer than the duty cycle of the MOSFET, and it will be more convenient to Rds-on voltage sampled.

本领域的技术人员将进一步意识到可以由主控制器218 (见图2) 使用由放大器518提供的电流信息信号以执行电压配置或输出具有压降(降低具有更高I0UT的V0UT以具有方波型瞬变响应来完全地使用用于过冲和下冲的调节窗),或执行过电流保护。 Those skilled in the art will further appreciate that may be used by the master controller 218 (see FIG. 2) the information signal provided by the current amplifier 518 configured to perform a square-wave voltage output or the pressure drop (decrease V0UT to have a higher I0UT transient response type used completely for overshoot and undershoot of the adjustment window), or perform overcurrent protection. 换句话说,精确输出电流信息的可用性提供许多好处。 In other words, the availability of accurate output current information provides many benefits.

图6表示能用在多相位转换器系统中以提供改进的电流共用的电路。 Figure 6 shows a multi-phase converter can be used in the system to provide improved current sharing circuit. 在这里,输入PWM信号耦合到包括占空比微调电路602和传统的门驱动单元603的修改的门驱动电路600。 Here, the input PWM signal is coupled to the trimming circuit 602 comprises modifying the duty cycle, and the conventional door driving unit driving circuit 603 of the gate 600. 以任何适当或所需方式来构成占空比微调器602以有选择地延迟输入PWM信号的前沿,因而縮短串联MOSFET的导通时间。 In any suitable or desired manner to form the duty cycle spinner 602 to selectively delay the leading edge of the input PWM signal, thereby shortening the conduction time of the MOSFET in series. 由在来自电流共用控制电路606的线路604上提供的控制输入来确定延迟时间。 Provided by a control input on line 604 from a current sharing control circuit 606 determines the delay time.

电流共用控制电路606的一个优选实现由接收表示用于转换器级的平均电流输出值的端610处的第一输入的电流共用放大器608和通过求和电阻器614,连接到端610的第二输入端612组成。 A current sharing control circuit 606 is preferably implemented by receiving a current for a first input terminal 610 of the average value of the output current of the converter stage 608 and the common amplifier 614 connected to terminal 610 through a second summing resistor input 612 components. 在多相位系统的其他转换器组件的每一个中,也提供类似的电路配置。 In each of the other components of the multi-phase converter system is also provided a similar circuit configuration.

最佳实现是将具有包括如图6所示的驱动器IC的转换器级的C-sense电路,诸如图5所示的500集成在单个MCM中,从而获得如上所述的零件-零件参数差和环境变化的降低灵敏度的优点。 Is a preferred implementation includes a converter stage having a C-sense drive circuit shown in FIG. 6 IC's, such as 500 in FIG integrated in a single MCM shown in FIG. 5, as described above to obtain a part - and the part parameter difference the advantage of reducing environmental change the sensitivity. 然而,应理解到能采用其他电流读出电路,甚至采用与输出电感器串联的电阻器的损耗测量方法。 However, it should be understood that to be able to use other current sensing circuits, even using measurements loss inductor in series with the output resistor.

放大器输入612以及相当于输入612的其他转换器组件的每一个中的相应的放大器输入连接到I-share总线618。 Amplifier input 612, and a corresponding amplifier input corresponds to an input of each of the other transducer assembly 612 is connected to the I-share bus 618. 在所示的电路结构中, 在所有组件中的求和电阻器(相当于图6所示的电阻器614)共同用来提供I-share618总线上的信号,表示在各个转换器级中测量的电流的平均值。 In the circuit configuration shown, the summing resistors in all components (resistor shown in FIG. 6 corresponds to 614) for providing a signal on the common bus I-share618, it represents in each measurement transducer stage the average current.

因此,在图6所示的结构中,放大器608放大表示输入610处、 用于组件的实际测量电感器电流电平的信号和表示所有转换器级中的电感器电流的平均值的I-share总线618上的信号间的差值。 Thus, in the configuration shown in FIG. 6, the amplifier 608 amplifies the input 610 represents the actually measured inductor current level for a signal component representing the average inductor current of all the converter stages I-share the difference between the signals on the bus 618. 能由组件中的占空比微调电路使用反映传播延迟、RDS.0N和其他级间参数变化的这一差值来微调占空比以将流过组件的电流平衡到每个相位输出的平均值。 Reflect the propagation delay can be used by the trimming circuit component duty ratio, the difference between this and other RDS.0N level parameters to fine-tune the duty cycle of the current flowing through the assembly to balance the average phase of the output of each .

作为上文的变形,能通过延长每个组件的PWM的后沿,有选择地增加占空比来校正电流不平衡。 As a variant of the above, through the extension of the trailing edge of each PWM module, selectively increasing the duty cycle to correct the current imbalance.

也可以使用I-share总线618上的电压来提供反馈信号VFB,提供为误差放大器226 (见图2)的一个输入。 A voltage may also be used on the I-share bus 618 to provide a feedback signal VFB, provides an input to the error amplifier 226 (see FIG. 2). 在图6所示的结构中,I-share 总线电压与I0UT/N成比例,其中IouT是输出电流以及N是转换器级的数量。 In the configuration shown in FIG. 6, I-share bus voltage I0UT / N is proportional to the output current which is IouT and N is the number of the converter stages.

也可以用上述的各种方法结合使用图5所示的电流读出电路500 的C-sense输出来利用I-share总线电压。 May be combined current shown in FIG 5 by the above method of reading out the various C-sense output circuit 500 to use I-share bus voltage.

在第二实施例中,电阻器614以及其他转换器级的每一个中的相应的电阻器可以用二极管620代替,如图6A所示。 In the second embodiment, the resistor 614, and each of the other converter stage of the respective resistors may be replaced by a diode 620, shown in Figure 6A. 在这种配置中,二极管充当AND电路,在控制I-share总线618的各个转换器级中,具有电流读出信号的最低值。 In this configuration, the diode acts as an AND circuit, the I-share 618 controls the respective bus converter stage having the lowest value of current sense signal. 因此,相当于最低值的信号将出现在I-share618总线上,作为每个求和/隔离放大器,诸如放大器608的输入, 以及每个求和/隔离的输出将使得各个占空比微调电路降低占空比,因此,降低用于所有级的输出电流以匹配最低电流级的输出电流。 Thus, a signal corresponding to the minimum value will appear in the I-share618 bus, as each summing / isolation amplifiers, such as amplifier input 608, and each of the summation / output isolation trim circuit such that the duty ratio of each reduction duty cycle, thereby reducing the output current for all stages of the lowest current level to match the output current.

作为另一变形,能使二极管620和其他I-share控制电路中的相应的二极管与图6A所示的方向相反。 As another modification, to make the corresponding diode and the other diode 620 in FIG. I-share control circuit shown in FIG. 6A in the opposite direction. 在那个情况下,二极管共同充当具有控制I-share总线618的各个转换器级中,电流离信号的最高值的OR 电路。 In that case, the diode acts as a control joint I-share bus 618 of the respective converter stage, the current signal from the maximum value of the OR circuit. 因此,在其他I-share控制的每一个的输出处存在不同信号。 Thus, there are different signals at the output of the other I-share control of each. 在那种情况下,各个占空比微调电路将操作以增加占空比,因此,增加用于那些级的输出电流以匹配最高电流级的输出电流。 In that case, the duty ratio of each of the trimming circuit will operate to increase the duty cycle, thus increasing the current output for that stage to match the maximum output current of the current stage.

作为应用于图6和6A所示的拓扑结构的另一变形,相当于占空比微调器602的所有占空比微调器可以实现为形成为与驱动器IC分开的分立IC的单独的占空比微调控制器,或甚至可以是主PWM控制器的 As a further modification is applied to the topology shown in FIG. 6 and 6A, the duty cycle corresponding to the duty cycle spinner all spinner 602 may be implemented as a driver IC formed to separate individual discrete duty ratio IC spinner, or even may be a master PWM controller

一部分。 portion. 同样地,相当于电流共用控制电路606的电流共用控制电路也可以实现形成为与驱动器IC分开的分立IC的单独的占空比微调控制器,或甚至可以是主PWM控制器的一部分。 Similarly, a current corresponding to the current control circuit 606 share a common control circuit may also be implemented as a separate spinner formed with the duty cycle of the driver IC of separate discrete IC, or may even be part of the main PWM controller.

再参考图5,使用类似的原理,也可以补偿多相位系统的转换器级间的功率损耗变化。 Referring again to FIG. 5, a similar principle can also compensate the power loss change between the converter stage multi-phase system. 为实现此目的,可以使用,通过根据第I级的并联MOSFET的Rds.,的实际值和用于所采用的、例如由历史产品测试数据统计确定的类型的并联MOSFETS的RDS_0N值的平均值RAV间的差值, 设置电阻器522的值以及放大器的跨导增益,微调每个级中的电流读出放大器,诸如图5所示的放大器518的增益的方案,由此通过使用改变电流读出增益,改变电流分布来平衡功率。 For this purpose, it can be used by Class I according to the Rds of the MOSFET in parallel., And the actual value used for, e.g. RAV RDS_0N average statistical value is determined by the parallel MOSFETS historical test data product type the difference between the set value of the resistor 522 and the transconductance gain of the amplifier, each stage of the tune current sense amplifier, the gain of the amplifier, such as program 518 shown in FIG. 5, thereby changing the current read out by using gain, changing the current balance of power distribution.

根据本发明的这一方面,可以采用几个可能的算法来实现功率平衡。 According to this aspect of the present invention, several possible algorithms may be employed to achieve power balance. 一个最佳算法能利用下述关系- A preferred algorithm using the following relation -

其中,^是用于第I级组件的放大器增益,以及Ao是电流读出增益的额定值(设计值)。 Wherein ^ is a first-stage amplifier gain component I, and Ao is the nominal current sensing gain (design value). 使用这一方法,将使相当于图5的放大器518 的电流读出放大器的输出信号在所有组件中相同,但为根据方程式(l) 实现此目的,每个组件中的电流读出放大器将必须显示出可变增益, 以及对这个电流读出放大器来说,具有最大增益的组件将具有最低实际电流。 Using this method will allow the current amplifier 518 corresponds to the output signal of the sense amplifier of FIG. 5 are the same in all components, but as Equation (l) in accordance with this purpose, each component of the current sense amplifier will be It shows a variable gain, as well as the current sense amplifier, the assembly has a maximum gain will have the lowest actual current.

更精确地说,电流偏离平均值的百分比是Rds偏寓Rds平均信的一半。 More precisely, the current from the average percentage of partial blending is Rds Rds average signal half. 例如,具有高于平均值的10。 For example, having a higher than average 10. /。 /. RDs的组件需要具有高于额定值5。 The components need RDs 5 has a higher rating. /。 /. 的增益,因此,电流将小于平均值5%。 Gain, thus, it will be less than the current average value of 5%. 这将为所有组件提供相同的功率(I2RDS)损耗。 This will provide the same power (I2RDS) loss of all components.

再参考图5,通过将预定校准电流(例如lamp)输入到每级的并联MOSFET,在测试期间,能实现根据上述算法的功率损耗平衡校准。 Referring again to FIG. 5, by a predetermined calibration current (e.g. LAMP) is input to each stage in parallel with the MOSFET, during the test, the loss can be realized according to the power of the balance correction algorithm. 通过测量MOSFET两端的降压,能获得并联MOSFET的Rds.。 By measuring blood pressure across the MOSFET, the MOSFET can be obtained Rds parallel .. n値。 n Zhi. 然后基于上述方程式(1),以及测量的Rds.on値,能计算这一级的所有增益,以及调整图5的增益电阻器522直到在Csense节点获得期望输出电压。 5, then the gain resistor 522 until the desired output voltage at node Csense based on the equation (1), and measured Rds.on Zhi, which all can be calculated in a gain, and an adjustment in FIG. 如本领域的技术人员将意识到,根据通过使用转换器组件中的可变电流读出增益,改变电流分布平衡功率的基本原理,在转换器级中能采用其他算法来提供平衡的功率损耗。 As those skilled in the art will appreciate, the read out by using the variable gain current converter assembly, the basic principle of changing the current distribution of the power balance in the converter stage other algorithms can be employed to provide a balanced power loss.

再参考图1,现在描述在负载转变期间,用于改进同步降压转换器级的瞬变性能的技术。 Referring again to FIG. 1, will now be described during the load change, a technique for transient performance of the synchronous buck converter stage improved. 如所公知的,负载升压,即电流需求增加易于 As is well known, the load boost, i.e. an increase in current demand easy

驱动输出电压下降,这通过增加用于串联MOSFET102的导通时间, 以及减少并联MOSFET108的截止时间来补偿。 Driving the output voltage drops, this is compensated for by increasing the conduction time MOSFET102 series and parallel MOSFET108 reduce the deadline.

相反地,负载降压,即电流需求减少易于驱动输出电压升高,以及这通过减少串联MOSFET102的导通时间以及增加用于并联MOSFET108的截止时间来补偿。 Conversely, step-down load, i.e., the current demand decreases easy to drive the output voltage increases, and this is compensated for by reducing the conduction time MOSFET102 series and in parallel for increasing the off time of MOSFET108.

从图l,例如,如果VjN为12伏,以及VouT为l.OV,很显然,当导通串联MOSFET102以及截止并联MOSFET108来增加通过电感器112的电流,电感器112两端的电压将是ViN-VouT二llV,这驱动电感器电流上升。 From FIG. L, e.g., 12 volts if VjN, and VouT as l.OV, it is clear that, when turned off, and the series MOSFET102 MOSFET108 parallel to increase the current through the inductor 112, the voltage across the inductor 112 will be ViN- VouT two llV, which drive the inductor current rises. 当串联MOSFET102截止以及并联MOSFET108导通时, 电感器112两端的电压将应用-VouT二-lV,这将驱动电感器电流下降。 When the series and the parallel MOSFET108 MOSFET102 turned off, the voltage across the inductor 112 -VouT two -lv application, it will drive the inductor current decreases. 在稳态操作中,电流上升部分将与电感器112内的电流下降部分相同, 而用于电流的DC内容将与输出电流相同。 In steady state operation, the current will drop the current rising portion in the same part of the inductor 112, and the content of DC current for the same output current. 在负载降压时,电感器电流将高于输出电流以便电流差将流入输出电容器114以便产生输出电压过冲。 When the load down, the inductor current is higher than the difference between the output current so that the current flowing in the output capacitor 114 to produce an output voltage overshoot. 该过冲将不停止,直到电感器电流下降到降低的输出负载电流水平为止。 The overshoot will not stop until the inductor current drops to a reduced level until the output of the load current. 电流耗散的速率将影响过冲有多大,但它是由电感器两端的负电压确定的。 Current dissipation rate will affect how much overshoot, but it was determined by a negative voltage across the inductor.

因为过冲与输出电容成反比,通常使用大且昂贵的输出电容器来降低过冲。 Because the overshoot is inversely proportional to the output capacitor, usually large and expensive output capacitor to reduce the overshoot. 为避免此现象,根据本发明,发现通过在降压期间,完全禁止并联MOSFET108来更快速地使电感器中的能量放电。 To avoid this, according to the present invention, it was found during the step-down by completely prohibiting MOSFET108 parallel to more quickly the energy in the inductor discharge. 因此,电流将流过MOSFET108的本体二极管,以及并联Shottky 二极管118, 而不是通过MOSFET108的沟道,就像MOSFET导通一样。 Thus, current will flow through the body diode of MOSFET108, and the parallel Shottky diode 118, rather than channel MOSFET108, like the MOSFET is turned on.

这很有利,因为本体二极管和Shottky 二极管118两端的电压能显著地高于导电MOSFET的沟道两端的电压,允许电感器电流更快速地耗散。 This is advantageous because the voltage across the body diode 118 and Shottky diodes can be significantly higher than the voltage across the conductivity channel of the MOSFET, allowing the inductor current is more quickly dissipated. 在12V和预定l.OV输出的例子中,如果本体二极管和Shottky 二极管的电压降为约0.7V(典型值),在该例子中,电感器电压为V0UT, 或IV。 In the 12V output and a predetermined l.OV example, if the voltage of the body diode and Shottky diode drop of about 0.7V (typical), in this example, the inductor voltage VOUT, or IV. 通过在负载降压期间禁止的MOSFET108,该电压将增加到VOUT+VDIODE=1+0.7=1.7V,增加了70%,以及以快于传统方法41%的速率减少电感器电流。 By MOSFET108 prohibited during load down, which will increase the voltage VOUT + VDIODE = 1 + 0.7 = 1.7V, a 70% increase, and at a rate faster than the conventional method of 41% reduction of the inductor current. 因此,通过二极管,代替传送到输出电容器以产生电压过冲来吸收电感器能量的41%。 Therefore, through the diode instead of the capacitor to an output voltage overshoot to produce 41% of absorbed energy of the inductor.

为实现本发明的这一方面,能修改门驱动电路以便当用于串联MOSFET的占空比下降到零(如由监视PWM信号确定的)时,截止两个MOSFETS。 When To achieve this aspect of the invention, the gate drive circuit can be modified so that when the duty ratio for the series MOSFET drops to zero (as determined by monitoring the PWM signal), off two MOSFETS. 在单个相位转换器的情况下,用于实现此的最佳电路如图7所示,但其他适当的实现也是可能的,如根据上述描述,对本领域的技术人员来说显而易见的。 In the case of a single phase converter circuit for achieving this is best shown in FIG. 7, but other suitable implementations are possible, as according to the above description, those skilled in the art would be apparent.

如图7所示,修改的转换器700包括零百分比占空比检测器702, 用来提供表示要求串联MOSFET704在整个开关中,保持截止的输出信号。 As shown in FIG 7, a modified converter 700 comprises a zero percent duty cycle detector 702 for providing a series claim MOSFET704 represents the entire switch, the output signal remains off. 如果输出电压高于调节点,例如,由于由如上所述的负载下降导致的过冲,这将发生。 If the output voltage is higher than the regulation point, e.g., as described above, since the load shedding due to overshoot, which would occur.

从通过将误差电压VE与具有固定峰值和谷值的三角形斜坡进行比较,生成PWM124的输出的图1的描述可以想到,高于斜坡的峰值的Ve惶将要求100%占空比,以及低于斜坡的谷值的Ve信将要求0°/。 It is contemplated from the description of FIG error voltage VE by the triangular ramp having fixed peaks and valleys are compared to generate an output of 1 PWM124, Ve is higher than the peak ramp anxiety will require 100% duty cycle, and less than Ve letter valley slopes would require 0 ° /. 占空比。 Duty cycle. 因此,零占空比检测电路702能是连接到误差放大器706的输 Thus, the duty ratio zero detection circuit 702 can be connected to the input of the error amplifier 706

出以便检测VE是否低于固定斜坡谷值的电路。 A circuit to detect VE is below a fixed ramp valley.

来自零占空比检测器702的输出信号连接AND门708的一个输入。 Zero duty cycle of the output signal from detector 702 is connected to one input of AND gate 708. 通过用于串联MOSFET704的选通信号,通过反相器710提供第二输入。 By a series of MOSFET704 strobe signal, a second input through an inverter 710. AND电路709的输出驱动旁路MOSFET712的栅极,由此, 使两个MOSFETS截止以及当串联MOSFET的占空比为零时,电感器电流能通过旁路MOSFET712的本体二极管耗散。 Output of the AND circuit 709 drives the gate of the bypass MOSFET712 thereby, and the two MOSFETS, when off duty ratio of the MOSFET connected in series is zero, the inductor current through the body diode of the bypass MOSFET712 dissipation.

图1和7示例说明整个功能单相位控制器,很容易获得误差电压VE。 1 and 7 illustrate an example entire functional single phase controllers, it is easy to obtain an error voltage VE. 在图2所示的多相位系统中,Ve可以不到达每个转换器组件。 In the multi-phase system shown in FIG. 2, Ve can not reach each transducer assembly. 在那种情况下,通过由主控制器218 (见图2)提供专用输出,能生成用于旁路MOSFETS的单独的禁用信号。 In that case, by providing a dedicated output from the main controller 218 (see FIG. 2), you can generate a separate disable signal bypass the MOSFETS. 用于检测零占空比状态的这种实现或其等效电路根据在此公开的内容,对本领域的技术人员来将是显而易见的。 Such a state for detecting a zero duty cycle to achieve an equivalent circuit thereof in accordance with the disclosure herein, those skilled in the art will be apparent.

尽管根据特定的实施例描述了本发明,对本领域的技术人员来说许多其他变形和改进以及其他用途变得显而易见。 While the invention has been described in accordance with certain embodiments, those skilled in the art for many other variations and modifications and other uses will become apparent. 因此,意图是本发明不受在此特别公开的内容限定,而是由附加的权利要求书表示其整个范围。 Accordingly, it is intended that the present invention is not specifically disclosed herein in the context defined, but by the appended claims denotes the entire range.

Claims (49)

  1. 1. 一种提供改进的输出电流读出的同步降压转换器,包括:连接在输入节点和第一节点间的第一开关晶体管;连接在所述第一节点和第二节点间的第二开关晶体管;连接在所述第一节点与输出节点间的串联电感器;连接在所述输出节点和所述第二节点间的电容器;该同步降压转换器特征在于,包括:读出电路,用来生成表示所述转换器的输出电流的信号,所述读出电路由下述组成:采样开关,与所述第一和第二开关晶体管的一个同步地开和关操作;可变增益放大器;当完全导电时,耦合所述采样开关以便向所述可变增益放大器提供表示所述第一和第二开关晶体管的一个的两端的电压的采样信号;以及与所述可变增益放大器有关、实现低通滤波器的电路,由此,所述可变增益放大器的输出基本上与所述电感器的电感以及输入到所述采样开关的信号的 1. A method of providing improved readout output current synchronous buck converter, comprising: a first switching transistor connected between the input node and the first node; connected between said first node and a second node the switching transistor; a series inductor connected between the first node and an output node; a capacitor between the output node and the second node is connected; the synchronous buck converter, comprising: a readout circuit, used to generate a signal representative of the output current of the converter, the readout circuit is composed of: sampling switch, an open and close operations in synchronization with said first and second switching transistors; a variable gain amplifier ; when fully conductive, the sampling switch coupled to provide a signal representative of the first sample and the voltage across a second switching transistor to said variable gain amplifier; and associated with said variable gain amplifier, low pass filter circuit achieved, whereby the output of said variable gain amplifier substantially the inductance of the inductor and the input signal to the sampling switch 何时间变动分量的大小无关,以及驱动电路,用来根据由所述读出电路的电压输出和参考电压间的差值确定的可变占空比,使所述第一和第二开关晶体管导通和截止。 Irrespective of the size of any time varying component, and a driving circuit, according to a variable duty cycle determined by the difference between the output voltage and a reference voltage circuit by the readout, the first and second switching transistors on and off.
  2. 2. 如权利要求l所述的同步降压转换器,其特征在于,通过连接在所述第一和第二开关晶体管的一个和所述可变增益放大器的输入端间的RC电路,实现所述低通滤波器。 2. The synchronous buck converter according to claim l, wherein the variable RC circuit between the input terminal and a gain of the amplifier in the first and second switching transistors are connected via achieve the said low-pass filter.
  3. 3. 如权利要求2所述的同步降压转换器,其特征在于, 所述采样开关与所述第二开关晶体管同步地开和关操作;以及所述低通滤波器连接到所述第一节点,由此,所述采样信号表示所述第二开关晶体管两端的电压。 3. The synchronous buck converter according to claim 2, wherein the sampling switch and the second switching transistor in synchronization with the opening and closing operation; and a low pass filter connected to the first node, whereby the sampled signal representing the voltage across the second switching transistor.
  4. 4. 如权利要求2所述的同步降压转换器,其特征在于, 所述采样开关与所述第一开关晶体管同步地开和关操作;以及所述低通滤波器连接到所述输入节点,由此,所述采样信号表示所述第一开关晶体管两端的电压。 4. The synchronous buck converter according to claim 2, wherein the sampling switch and the first switching transistor in synchronization with the opening and closing operation; and a low pass filter connected to the input node whereby said sampling signal is representative of a first voltage across the transistor switch.
  5. 5. 如权利要求l所述的同步降压转换器,其特征在于,通过选择所述可变增益放大器的增益带宽,实现所述低通滤波器。 5. The synchronous buck converter according to claim l, characterized in that, by selecting the variable gain amplifier gain bandwidth, to achieve the low pass filter.
  6. 6. 如权利要求l所述的同步降压转换器,其特征在于,所述采样开关与所述第二开关晶体管同步地开和关操作。 6. The synchronous buck converter according to claim l, wherein the sampling switch and the second switching transistor in synchronization with the opening and closing operations.
  7. 7. 如权利要求l所述的同步降压转换器,其特征在于,所述采样开关与所述第一开关晶体管同步地开和关操作。 7. The synchronous buck converter according to claim l, wherein the sampling switch and the first switching transistor on and off in synchronization operation.
  8. 8. 如权利要求l所述的同步降压转换器,其特征在于,所述采样开关由所述驱动电路操作。 8. The synchronous buck converter according to claim l, wherein said sampling switch circuit is operated by the driver.
  9. 9. 如权利要求l所述的同步降压转换器,其特征在于,所述第一和第二开关晶体管是MOSFET。 9. The synchronous buck converter according to claim l, wherein said first and second switching transistor is a MOSFET.
  10. 10. 如权利要求1所述的同步降压转换器,其特征在于,除所述串联电感器和所述电容器外的整个同步降压转换器均包括在多芯片组件中。 10. The synchronous buck converter according to claim 1, characterized in that the entire synchronous buck converter in addition to the series inductor and the capacitor are included in a multi-chip assembly.
  11. 11. 如权利要求1所述的同步降压转换器,其特征在于,所述整个同步降压转换器均包括在多芯片组件中。 11. The synchronous buck converter according to claim 1, characterized in that the entire synchronous buck converter comprises a multi-chip assembly.
  12. 12. 如权利要求1所述的同歩降压转换器,其特征在于,所述读出电路封装在与所述同步降压转换器的其余部分分开的组件中。 12. The buck converter with ho according to claim 1, wherein the readout circuit is encapsulated in the rest of the synchronous buck converter with separate components.
  13. 13. 如权利要求1所述的同步降压转换器,其特征在于,所述可变增益放大器是跨导放大器。 13. The synchronous buck converter according to claim 1, wherein said variable gain amplifier is a transconductance amplifier.
  14. 14. 如权利要求l所述的同步降压转换器,进一步包括延迟电路, 用来在导通所述第一和第二开关晶体管的一个的时间和导通所述采样开关的时间间提供预定小的延迟。 14. Providing a predetermined synchronous buck converter as claimed in claim l, further comprising a delay circuit for a time in between turning on the first and the second switching transistor is turned on and the time the sampling switch small delay.
  15. 15. 如权利要求l所述的同步降压转换器,其特征在于, 所述读出电路、驱动电路以及第一和第二开关晶体管组装为一个多芯片组件;以及所述同步降压转换器进一步在所述多芯片组件内包括热敏设备, 用来改变所述可变增益放大器的增益以便当其处于导电状态时,补偿所述第一和第二开关晶体管的一个的电流通路的电阻中的温度相关变化。 15. The synchronous buck converter according to claim l, wherein the readout circuit, driving circuit and a first and second switching transistors of a multi-chip module assembly; and a synchronous buck converter further in the multi-chip module comprises a thermosensitive device, for changing the gain of said variable gain amplifier so that when it is in a conductive state, a resistance of the first compensation and the second switching transistor of the current path the temperature-dependent change.
  16. 16. 如权利要求15所述的同步降压转换器,其特征在于,所述热敏设备是二极管。 16. The synchronous buck converter according to claim 15, wherein the thermal device is a diode.
  17. 17. 如权利要求15所述的同步降压转换器,其特征在于, 所述第一和第二开关晶体管是MOSFETS;以及所述热敏设备用来与所述一个MOSFET中的RDS_oN的温度相关变化成比例地改变所述可变增益放大器的增益。 17. The synchronous buck converter according to claim 15, wherein said first and second switching transistors are of MOSFETS; and the temperature and the thermal device to a MOSFET of the relevant RDS_oN changes in proportion to changes in the gain of the variable gain amplifier.
  18. 18. 如权利要求1所述的同步降压转换器,其特征在于,所述读出电路、所述驱动电路、以及所述第一和第二开关晶体管组装为一个多芯片组件;以及所述同步降压转换器进一步在所述多芯片组件中包括压敏设备, 用于当第一和第二开关晶体管的一个处于由所述驱动电路提供的控制信号的电压的变化引起的导电状态中时,改变所述可变增益放大器的增益以补偿所述第一和第二开关晶体管的一个的电流通路的电阻中的变化。 18. The synchronous buck converter according to claim 1, wherein the readout circuit, the drive circuit, and said first and second switching transistors of a multi-chip module assembly; and the synchronous buck converter further comprises a pressure sensitive device, when used in the multi-chip module caused by a conduction state when the first switching transistor and a second control signal is supplied from the drive circuit changes the voltage of changing said variable gain amplifier to compensate for the gain of a first transistor and a second switching current path resistance variations.
  19. 19. 如权利要求1所述的同步降压转换器,其特征在于,设置所述可变增益放大器的增益以便当其处于导电状态时,为流过所述第一和第二开关晶体管的一个的预定电流提供预定输出信号以补偿当第一和第二开关晶体管的一个处于导电状态中时,补偿在所述第一和第二开关晶体管的一个的电流通路的电阻中的变化。 19. The synchronous buck converter according to claim 1, wherein said variable gain amplifier is provided to a gain when it is in a conductive state, to flow through said first and a second switching transistor providing a predetermined current to compensate for a predetermined output signal when one of the first and second switching transistors are in a conductive state, a resistance to compensate for changes in the first and second switching transistors in the current path.
  20. 20. 如权利要求l所述的同步降压转换器,其特征在于, 所述第一和第二开关晶体管是MOSFETS;以及设置所述可变增益放大器的增益以便向流过所述一个MOSFET的沟道的预定电流提供预定输出信号以补偿所述一个MOSFET的RDS_oN 中的变化。 20. The synchronous buck converter according to claim l, wherein said first and second switching transistors are of MOSFETS; and setting the gain of the variable gain amplifier so as to flow through the MOSFET is a providing a predetermined current channel to a predetermined output signal to compensate for a variation of the MOSFET is in RDS_oN.
  21. 21. —种提供改进的电流共用的多相位同步降压转换器,包括: 多个单相位降压转换器级,每个转换器级包括:连接在输入节点和第一节点间的第一开关晶体管; 连接在所述第一节点和第二节点间的第二开关晶体管; 连接在所述第一节点与输出节点间的串联电感器; 连接在所述输出节点和所述第二节点间的电容器, 所有所述转换器级的输出节点连接在一起以便向由所有所述转换器级驱动的负载提供输出电流;驱动电路,用来根据可变占空比,使所述第一和第二开关晶体管导通和截止,从而调整所述输出节点处的电压;以及读出电路,用来生成表示由该转换器级提供的输出电流的输出信号;主控制器,用来根据来自所述多相位同步降压转换器的反馈电压和表示所述输出节点处的所需电压的参考信号间的差值,按用于所述每个转换器级的所述第一和 21. - provides improved current sharing kind of multi-phase synchronous buck converter, comprising: a plurality of single phase buck converter stages, each stage converter comprising: an input node connected between the first node and the first the switching transistor; a second switching transistor connected between the first node and the second node; an inductor connected in series between the first node and an output node; connected between the output node and the second node capacitors, all of the output node of the converter stages are connected together to provide an output current to drive all of the load of the converter stage; driving circuit according to a variable duty cycle, said first and second and second switching transistor is turned off, thereby adjusting the voltage at the output node; and a readout circuit for generating an output signal indicative of the output current provided by the converter stage; master controller, according to from the feedback voltage multi-phase synchronous buck converter and the reference signal indicative of a difference between the desired voltage at the output node, each of the converter according to the first stage and 二开关晶体管的预定相位关系,提供占空比控制信号;所述多相位同步降压转换器特征在于,包括-耦合在所述主控制器和用于每个转换器级的驱动电路间的占空比微调控制器;以及电流共用控制器,向所述占空比微调控制器提供控制信号,所述控制信号表示所述各个级的输出电流和反映相等的级电流的所需电流输出间的差值;占空比微调控制器响应所述控制信号来修改用于所有所述转换器级的所述占空比控制信号以基本上使所有所述转换器级的输出电流相同。 Second switching transistor predetermined phase relationship, there is provided a duty control signal; said multi-phase synchronous buck converter comprising - accounted coupled between the master controller and a driving circuit for each stage of the converter trim-air ratio controller; and a current share controller, provides control signals to the duty of the spinner, the control signal is representative of a desired level between the respective output current and the output current is equal to reflect the current level difference; duty cycle spinner controller responsive to said control signal for modifying the duty cycle of all of the converter stage so that substantially the same control signal to the output current of all said converter stage.
  22. 22. 如权利要求21所述的同步降压转换器,其特征在于,每个电流共用控制器包括与每个转换器级有关的放大器,每个放大器具有:连接到用于相关转换器级的所述读出电路的输出的第一输入端; 第二输入端,通过电阻器连接到所述第一输入端,以及还连接到提供表示用于所有转换器级的输出电流的平均值的信号的电流共用总线;放大器,用来提供表示在它们的各自的第一和第二输入端间的差值的输出信号以便分别控制所述占空比微调控制器的输入端;所述占空比微调控制器用来根据各自的放大器输出信号,调整每个所述转换器级的第一和第二开关晶体管的占空比以便使由所有所述转换器级提供的输出电流相等。 22. The synchronous buck converter according to claim 21, characterized in that each amplifier comprises a current sharing controller associated with each of the converter stages, each amplifier comprising: a converter connected to the correlation stage for a first input terminal of the output from the readout circuit; a second input terminal connected to the first input terminal through a resistor, and is further connected to provide an average value for all represented converter stage output current signal current share bus; amplifier, for providing an output signal indicative of the difference between their respective first and second input terminals for respectively controlling the duty trim controller input; the duty the spinner to a respective amplifier output signal, adjusting the duty cycle of the first and second switching transistors for each stage of the converter so that the output current is provided by all stages of the converter are equal.
  23. 23. 如权利要求21所述的同歩降压转换器,其特征在于,所述电流共用控制器包括与每个转换器级有关的放大器,每个放大器具有:连接到用于相关转换器级的所述读出电路的输出的第一输入端;第二输入端,通过二极管连接到所述第一输入端,以及还连接到提供表示用于所有转换器级的输出电流的最小值的信号的电流共用总线;放大器,用来提供表示在它们的各自的第一和第二输入端间的差值的输出信号以便分别控制所述占空比微调控制器的输入端;所述占空比微调控制器用来根据各自的放大器输出信号,调整每个所述转换器级的第一和第二开关晶体管的占空比以便使由所有所述转换器级提供的输出电流相等。 23. The same ho buck converter according to claim 21, wherein said common controller comprises a current amplifier associated with each of the converter stages, each amplifier comprising: a converter connected to the correlation stage for a first input terminal of the readout circuit of the output; and a second input terminal connected to the first input terminal through a diode, and is also connected to provide a signal represents a minimum value of all the output current of the converter stage of current share bus; amplifier, for providing an output signal indicative of the difference between their respective first and second input terminals for respectively controlling the duty trim controller input; the duty the spinner to a respective amplifier output signal, adjusting the duty cycle of the first and second switching transistors for each stage of the converter so that the output current is provided by all stages of the converter are equal.
  24. 24. 如权利要求21所述的同步降压转换器,其特征在于,所述电流共用控制器包括与每个转换器级有关的放大器,每个放大器具有:连接到用于相关转换器级的所述读出电路的输出的第一输入端; 第二输入端,通过二极管连接到所述第一输入端,以及还连接到提供表示用于所有转换器级的输出电流的最大值的信号的电流共用总线;放大器,用来提供表示在它们的各自的第一和第二输入端间的差值的输出信号以便分别控制所述占空比微调控制器的输入端;所述占空比微调控制器用来根据各自的放大器输出信号,调整每个所述转换器级的第一和第二开关晶体管的占空比以便使由所述所有转换器级提供的输出电流相等。 24. The synchronous buck converter according to claim 21, wherein said common controller comprises a current amplifier associated with each of the converter stages, each amplifier comprising: a converter connected to the correlation stage for reading out the first input terminal of the output circuit; a second input terminal connected through a diode to the first input terminal, and is also connected to the maximum value signal represents the output current of the converter stage all of current share bus; amplifier, for providing an output signal indicative of the difference between their respective first and second input terminals for respectively controlling the duty ratio of the input end of the spinner; fine tuning the duty the controller for a respective amplifier output signal, adjusting the duty cycle of the first and second switching transistors for each stage of the converter so that the output current provided by the converter stage all equal.
  25. 25. 如权利要求23所述的同步降压转换器,其特征在于,所述电流共用总线上的信号提供为所述主控制器的反馈信号。 25. The synchronous buck converter according to claim 23, wherein said common current signal on the bus to provide a feedback signal to the master controller.
  26. 26. 如权利要求22或23所述的同步降压转换器,其特征在于, 所述占空比微调控制器包括:用于每个转换器级的占空比微调电路,每个占空比微调电路包括: 连接到与那级有关的放大器的输出端的控制输入端-, 连接到所述主控制器的相位有关的输出的一个的信号输入端;以及连接以控制用于那级的驱动电路的输出端。 26. The synchronous buck converter of claim 22 or claim 23, wherein the duty trim controller comprising: a converter stage duty cycle of each of the trimming circuit, each duty cycle trimming circuit comprising: an input terminal connected to the control stage associated with that of the output of the amplifier - is connected to the input of a signal output from the phase related to the master controller; and a connection to a control stage for a drive circuit that an output terminal.
  27. 27. 如权利要求26所述的同歩降压转换器,其特征在于,所述微调电路用来有选择地延迟输入的由所述主控制器提供的占空比控制信号的前沿,因此,缩短所述第一开关晶体管的导通时间。 27. The buck converter with ho according to claim 26, wherein said trimming circuit for selectively delaying the leading edge of the duty cycle control signal supplied from the master controller input, and therefore, shortening the conduction time of the first switching transistor.
  28. 28. 如权利要求26的任何一个所述的同歩降压转换器,其特征在于,所述微调电路用来有选择地延迟由所述主控制器提供的输入占空比控制信号的后沿,因此,增加所述第一开关晶体管的导通时间。 28. Any ho with a buck converter according to claim 26, wherein said trimming circuit for selectively delaying said main controller provided by the trailing edge of the input signal duty cycle control Therefore, increasing the conduction time of said first switching transistor.
  29. 29. 如权利要求22、 23、或24的任何一个所述的同步降压转换器,其特征在于,所述放大器、连接所述放大器的所述第一和第二输入端的部件以及用于每个转换器级的占空比微调电路与所述第一和第二开关晶体管和用于每个转换器级的驱动电路一起组装在各自的每个多芯片组件中。 29. claimed in claim 22, 23, or any of a synchronous buck converter of claim 24, wherein said amplifier means connected to said first and second amplifier input terminal, and for each of a converter stage duty cycle trimming circuit and the first and second switching transistors and a drive circuit for each stage of the converter is assembled in a respective each multi-chip assembly together.
  30. 30. 如权利要求27所述的同步降压转换器,其特征在于,所述放大器、连接所述放大器的所述第一和第二输入端的部件以及用于每个转换器级的占空比微调电路与所述第一和第二开关晶体管和用于每个转换器级的驱动电路一起组装在各自的每个多芯片组件中。 30. The synchronous buck converter according to claim 27, wherein said amplifier means connected to said first and second amplifier input terminal, and for each of the converter stage duty cycle trimming circuit and the first and second switching transistors and a drive circuit for each stage of the converter is assembled in a respective each multi-chip assembly together.
  31. 31. 如权利要求21所述的同歩降压转换器,其特征在于,将表示所需级输出电流的信号提供为所述主控制器的反馈信号。 31. The same ho buck converter according to claim 21, characterized in that the signal representing the desired output current level to provide a feedback signal to the master controller.
  32. 32. —种提供功率损耗平衡的多相位同步降压转换器,包括: 多个单相位降压转换器级,每个转换器级包括:连接在输入节点和第一节点间的第一开关晶体管; 连接在所述第一节点和第二节点间的第二开关晶体管; 连接在所述第一节点与输出节点间的串联电感器; 连接在所述输出节点和所述第二节点间的电容器, 所有所述转换器级的输出节点连接在一起以便向由所有所述转换器级驱动的负载提供输出电流;驱动电路,用来根据可变占空比,使所述第一和第二开关晶体管导通和截止,从而调整所述输出节点处的电压;以及读出电路,包括可变增益电流读出放大器,用来当其导电时,确定通过所选择的所述第一和第二开关晶体管的一个的电流, 由此生成表示由该转换器级提供的输出电流的输出信号;以及主控制器,用来根据来自所述多相位同步降压 32. - balance method of providing a multi-phase power loss synchronous buck converter, comprising: a plurality of single phase buck converter stages, each stage converter comprising: an input node connected between the first node and the first switch transistor; connected between the first node and the second node of the second switching transistor; the first node and connected in series between the output node of the inductor; connected between the output node and the second node capacitors, all of the output node of the converter stages are connected together to provide an output current to drive all of the load of the converter stage; driving circuit according to a variable duty cycle, the first and second switching transistor is turned off and to adjust the voltage at the output node; and a readout circuit comprising a variable gain current sense amplifier, is used when it is conductive, it is determined by said selected first and second a switching transistor current, thereby generating an output signal indicative of the output current provided by the converter stage; and a main controller according to the multi-phase synchronous buck from 转换器的输出电压和表示所述输出节点处的所需电压的参考信号间的差值,按用于所述转换器级的所述第一和第二开关晶体管的预定相位关系,提供占空比控制信号;预定每个转换器级中的电流读出放大器的增益以便来自所有电流读出放大器的输出信号基本上相等,由此通过使用变动电流读出增益调整所述输出电流来平衡所有转换器级中的功率损耗,以便补偿所选择的第一和第二开关晶体管的导电通路电路中的变化。 The output voltage of the converter and the reference signal indicative of a difference between the desired voltage at the output node, according to a predetermined phase relationship of the first stage of the converter and a second switching transistor, there is provided a duty ratio control signal; predetermined current converter stage in each sense amplifier to the gain of the current output signals from all the sense amplifiers are substantially equal, whereby said output current by using a current sensing gain adjustment change to balance all conversion stage power loss, so that changes in the first and second conductive via circuit switching transistor in the selected compensation.
  33. 33. 如权利要求32所述的同歩降压转换器,其特征在于,根据所选择的第一和第二开关晶体管的导电通路电阻的实际值和在每个所述转换器级中采用的类型的第一和第二开关晶体管的导电通路的电阻的平均值RAV间的差值,预定所述电流读出放大器的增益。 33. The buck converter with ho according to claim 32, characterized in that an actual value of the resistance of the conductive paths of the first and second switching transistors selected and employed at each stage of the converter RAV difference between the average value of resistance of the conductive path of the first and second switching transistors of the type, the predetermined current sense amplifier gain.
  34. 34. 如权利要求32所述的同步降压转换器,其特征在于,根据下述关系,预定所述电流读出放大器的增益:其中,A,是用于第I转换器级的放大器增益,Ao是额定设计增益值,RDS.i是第I转换器级中所选择的第一和第二开关晶体管的导电通路的实际电阻,RAV是用在每个所述转换器级中的类型的所选择的开关晶体管的导电通路的电阻的平均值。 34. The synchronous buck converter according to claim 32, characterized in that, according to the following relation, the predetermined current sense amplifier gain: wherein, A, I, is a converter stage amplifier gain, Ao is the nominal design gain value, RDS.i I is the actual resistance of the first converter stage in a selected conductive path of the first and second switching transistors, RAV is used in each stage of the converter of the type the average value of resistance of the switch transistor conductive path is selected.
  35. 35. 如权利要求32所述的同步降压转换器,其特征在于, 所述第一和第二开关晶体管是MOSFETS;以及根据各个选择的MOSFETS的实际RDs.,值和用在所述转换器级的类型的MOSFETS的Rds-,的平均僵RAv间的差值,预定所述电流读出放大器的增益。 35. The synchronous buck converter according to claim 32, wherein said first and second switching transistors are of MOSFETS; RDs MOSFETS and the actual respective selected value for use in the converter. the difference between MOSFETS Rds- type level, average stiff RAV, the predetermined current sense amplifier gain.
  36. 36. 如权利要求32所述的同步降压转换器,其特征在于, 所述第一和第二开关晶体管是MOSFETS; 根据下述关系,预定所述电流读出放大器的增益:其中,At是用于第I转换器级的放大器增益,A。 36. The synchronous buck converter according to claim 32, wherein said first and second switching transistors are of MOSFETS; according to the following relation, the predetermined current sense amplifier gain: wherein, At is I used for the first converter stage amplifier gain, a. 是额定设计增益值,RDs.,是第I转换器级中所选择的MOSFET的实际RDs-oN, IW是用在所述转换器级中的类型的MOSFET的RDS.oN的平均值。 Is the nominal design gain value, RDs., I first converter stage the selected MOSFET actual RDs-oN, IW is the converter stage type MOSFET of the average RDS.oN.
  37. 37.如权利要求33-36的任何一个所述的同步降压转换器,其特征在于,RAV是由历史产品测试数据统计确定的。 Any one of the synchronous buck converter of claim 37. 33-36, wherein, the historical data generated by the RAV product testing is statistically determined.
  38. 38. 如权利要求32所述的同步降压转换器,其特征在于,所选择的开关晶体管是第二开关晶体管。 The synchronous buck converter as claimed in claim 32, 38, characterized in that the switching transistor is selected by the second switching transistor.
  39. 39. —种用于在多相位同步降压转换器中提供平衡功率损耗的方法,所述多相位同步降压转换器包括具有连接在一起以提供输出电流的输出的多个单相位降压转换器级,每个转换器级包括连接在输入节点和第一节点间的第一开关晶体管,连接在所述第一节点和第二节点间的第二开关晶体管,连接在所述第一节点与输出节点间的串联电感器,连接在所述输出节点和所述第二节点间的电容器,调整所述输出节点处的电压的驱动电路,以及包括可变增益电流读出放大器的读出电路,主控制器,用来根据来自所述多相位转换器的输出电压和表示所述输出节点处的所需电压的参考信号间的差值,按用于所有转换器级的所述第一和第二开关晶体管的预定相位关系,提供占空比控制信号;所述方法包括步骤:预定每个转换器级中的可变增益电流读出放大器的增益以 39. - Method to provide a balanced power consumption in a multi-phase synchronous buck converter types, said multi-phase synchronous buck converter comprising a plurality of connected together to a single output providing an output current of phase buck converter stages, each stage includes a first converter switching transistor connected between the input node and the first node, a second switching transistor connected between the first node and the second node, the first node is connected and the series inductor between the output node, a capacitor connected between the output node and the second node, the drive circuit adjusting a voltage at the output node, and a read sense amplifier comprises a variable gain current circuit , the main controller for the reference signal based on the difference between the desired output voltage from the voltage converter and the multi-phase representing at the output node, according to all the first converter stage and the predetermined phase relationship of the second switching transistor, there is provided a duty control signal; said method comprising the steps of: a predetermined variable gain current stage of each converter is read out to the gain of the amplifier 便当所述开关晶体管处于导电状态时,响应通过所选择的所述第一和第二开关晶体管的一个的预定校准电流,所述放大器均提供基本上相等的输出;以及当晶体管导电时,确定通过所述各个选择的第一和第二开关晶体管的电流以便生成表示由各个转换器级提供的输出电流的可变增益电流读出放大器输出信号。 Lunch when the switching transistor is in a conductive state, in response to a predetermined calibration current through said selected one of the first and second switching transistor, the amplifiers provide a substantially equal output; and when the transistor is conducting, is determined by said first and second current switch transistors each selected so as to generate the variable gain represents an output current of the current supplied by the respective converter stage sense amplifier output signal.
  40. 40. 如权利要求39所述的方法,其特征在于,根据所选择的第一和第二开关晶体管的导电通路电阻的实际值和在每个所述转换器级中采用的类型的所选择的开关晶体管的导电通路的电阻的平均值Rav间的差值,预定所述电流读出放大器的增益。 40. The method according to claim 39, wherein the selected value of the actual conductive path of a first resistor and a second switching transistor and the selected type employed in each stage of the converter Rav the average difference between the resistance of the conductive path of the switching transistor, a predetermined current sense amplifier gain.
  41. 41. 如权利要求40所述的方法,其特征在于,RAv是由历史产品测试数据统计确定的,以及通过测量各个导电通路两端的压降,确定所述导电通路电阻的实际值。 41. The method according to claim 40, wherein, the historical data item RAV test statistic is determined, and by measuring the voltage drop across the respective conductive paths, determining the actual value of the resistance of the conductive path.
  42. 42. 如权利要求39所述的方法,其特征在于,根据下述关系,预定所述电流读出放大器的增益:其中,A:是用于第I转换器级的放大器增益,A。 42. The method according to claim 39, characterized in that, according to the following relation, the predetermined current sense amplifier gain: wherein, A: I is a first converter stage amplifier gain, A. 是额定设计增益值,Rdw是第I转换器级中所选择的第一和第二开关晶体管的导电通路的实际电阻,RAV是用在所述每个转换器级中的类型的开关晶体管的导电通路的电阻的平均值。 Is the nominal design gain value, Rdw I is the actual resistance of the first converter stage in a selected conductive path of the first and second switching transistors, RAV in the conductive stage of each converter type switching transistor with the average value of the resistance path.
  43. 43. 如权利要求39所述的方法,其特征在于, 所述第一和第二开关晶体管是MOSFETS;以及根据各个选择的MOSFETS的实际RDs-,值和用在每个所述转换器级的类型的MOSFETS的Rds.,的平均植RAv间的差值,预定所述电流读出放大器的增益。 43. The method according to claim 39, wherein said first and second switching transistors are MOSFETS; and The actual RDs- MOSFETS each selected value used in each of the converter stages Rds types of MOSFETS., the difference between the average plant RAV, the predetermined current sense amplifier gain.
  44. 44. 如权利要求39所述的方法,其特征在于, 所述第一和第二开关晶体管是MOSFETS; 根据下述关系,预定所述电流读出放大器的增益:其中,A,是用于第I转换器级的放大器增益,Ao是额定设计增益值,Rdw是第I转换器级中所选择的MOSFET的实际RDS.0N, Rav是用在每个所述转换器级中的类型的MOSFET的Rds-,的平均僮。 44. The method according to claim 39, wherein said first and second switching transistors are of MOSFETS; according to the following relation, the predetermined current sense amplifier gain: wherein, A, for the first I converter stage amplifier gain, Ao is the nominal design gain value, Rdw first converter stage I selected MOSFET actual RDS.0N, Rav is used in each stage of the converter of the type of MOSFET Rds-, the average child.
  45. 45. 如权利要求42-44的任何一个所述的方法,其特征在于,RAV 是由历史产品测试数据统计确定的,以及通过测量各个所述导电通路两端的压降,确定RDS.,的实际值。 45. The actual method of any one of claims 42-44, wherein, the RAV was determined by historical statistical product test data, and by measuring the voltage drop across each of the conductive paths, determining RDS., The value.
  46. 46. 如权利要求44所述的方法,其特征在于,所选择的MOSFET 是第一开关晶体管。 46. ​​The method according to claim 44, wherein the selected first switching transistor is a MOSFET.
  47. 47. —种在输出电流下降期间,具有改进的瞬变响应的同步降压转换器,包括连接在输入节点和第一节点间的第一开关晶体管; 连接在所述第一节点和第二节点间的第二开关晶体管; 连接在所述第一节点与输出节点间的串联电感器; 连接在所述输出节点和所述第二节点间的电容器, 第一驱动电路,用来根据由表示所述转换器的电压输出和参考电压之间的差值的误差信号确定的可变占空比,使所述第一开关晶体管导通和截止;读出电路,用来当用于所述第一开关晶体管的占空比为零时,担任控制信号输出;以及第二驱动电路,响应所述读出电路的控制信号以截止所述第二开关晶体管。 47. - species during the output current drops, with an improved transient response synchronous buck converter comprising a first switching transistor connected between the input node and the first node; connected between the first node and the second node between the second switching transistor; an inductor connected in series between the first node and an output node; a capacitor connected between the output node and the second node, a first driving circuit according to a representative of the the error signal is a difference between the output voltage of said converter and a reference voltage determined by a variable duty cycle, said first switching transistor is turned on and off; readout circuit, when used for the first when the duty ratio of the switching transistor is zero, as control signal output; and a second drive circuit responsive to said read control signal to turn off the circuit of the second switching transistor.
  48. 48. 如权利要求47的同步降压转换器,其特征在于, 所述第一开关晶体管为连接在所述输入节点和所述第一节点间的串联MOSFET;所述第二开关晶体管是连接在所述第一节点和所述第二节点间的旁路MOSFET;所述串联电感器连接在所述第一节点与输出节点间; 连接在所述输出节点和所述第二节点间的输出电容器; 所述第一驱动电路用来根据所述可变占空比,使所述串联MOSFET导通和截止;所述读出电路用来当用于所述串联MOSFET的占空比为零时,提供控制信号输出;以及所述第二驱动电路响应所述读出电路的控制信号输出以截止所述旁路MOSFET。 48. The synchronous buck converter of claim 47, wherein said first switching transistor connected in series with the input MOSFET and a node between the first node; a second switching transistor is connected the bypass MOSFET between the first node and the second node; said inductor is connected in series between the first node and an output node; connected between the output node and the second node of the output capacitor ; for the first drive in accordance with the variable duty cycle circuit, the MOSFET is turned on and off in series; said readout circuit is used for the series when the duty ratio of the MOSFET is zero, providing a control output signal; and said second driving circuit in response to the read signal output of the control circuit to turn off the bypass MOSFET.
  49. 49. 如权利要求47或48所述的同步降压转换器,其特征在于: 所述第一驱动电路包括生成具有预定最大和最小值的重复斜坡波形的电路,以及通过将所述误差信号与所述斜坡波形进行比较,生成表示所述可变占空比的信号;以及当所述误差信号具有比所述斜坡波形的最小值更低的大小时,所述读出电路生成控制信号。 49. The synchronous buck converter of claim 47 or claim 48, wherein: said first driving circuit comprises generating a predetermined repeated maximum and minimum values ​​of the ramp waveform circuit, and by the error signal comparing the ramp waveform to generate the variable duty cycle signal represents; and when said error signal having a magnitude lower than the minimum value of the ramp waveform, the readout circuitry generates a control signal.
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