CN100478966C - Chip massive module array layout method - Google Patents

Chip massive module array layout method Download PDF

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CN100478966C
CN100478966C CN 200710139510 CN200710139510A CN100478966C CN 100478966 C CN100478966 C CN 100478966C CN 200710139510 CN200710139510 CN 200710139510 CN 200710139510 A CN200710139510 A CN 200710139510A CN 100478966 C CN100478966 C CN 100478966C
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layout
module
chip
array
modules
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CN 200710139510
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CN101122931A (en
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周永川
廖春连
张卫华
纯 曹
斌 李
田素雷
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中国电子科技集团公司第五十四研究所
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Abstract

本发明公开了一种对芯片中的海量模块进行阵列布局的方法,它涉及集成电路领域中对数字信号处理芯片版图进行合理布局的技术。 The present invention discloses a method of mass chip array layout module, which relates to the technical field of integrated circuits in a digital signal processing chip layout for rational distribution. 本发明基于传统的模块布局原则,根据模块在逻辑上的相关性,参考标准单元的阵列方式来排布模块。 The present invention is based on the principle of a conventional layout module, the module according to the logical correlation, a reference to an array of standard cell layout module. 应用本方法,优点是改善了由传统的模块靠边布局造成的引线过长、个别延时难以满足的问题,同时减轻了模块过多给芯片面积带来的压力。 Application of the method, the advantage of improved leads from the traditional layout of the module aside due to too long, the problem is difficult to meet the individual delay, while reducing the chip area to excessive pressure module caused. 从而本发明能够实现对芯片海量模块设计的版图优化。 The present invention thus enables mass chip layout optimization module design.

Description

对芯片中的海量模块进行阵列布局的方法技术领域本发明涉及集成电路领域中一种对芯片中的海量模块进行阵列布局的方法,它特别适用于对具有大量模块,模块面积占芯片面积一半以上的数字信号处理芯片电路设计布局,能够实现芯片布局的优化。 Mass of the chip module array layout method Technical Field The present invention relates to the field of integrated circuit chip of one of the massive array layout of modules, it is particularly suitable for a large number of modules, the chip area accounts for more than half of the area digital signal processing circuit chip design layout can be optimized chip layout. 背景技术集成电路布局布线是当前数字电路设计流程里最重要的环节之一,对芯片的时序能否满足设计要求,芯片最终的成品率等都有着很大的影响。 BACKGROUND Integrated circuit layout is one of the most important aspects of the current digital circuit design process, the timing of the chip can meet the design requirements, the final chip yield and so has a great impact. 当芯片达到一定规模以后,尤其是釆用大量宏模块与标准单元进行混合设计的情况下,对宏模块进行合理处理以满足时序与供电要求成为芯片设计过程中的一个重要问题。 When the case where the chip reaches a certain size, in particular preclude the use of hybrid design for a large number of standard cells and macroblock for macroblock reasonable processing power to meet the timing requirements of the chip become an important issue in the design process. 数字信号处理芯片的电路设计中调用了很多RAM,ROM和其它逻辑模块,这些模块的摆放将极大程度影响到最终的布局布线情况, 对于传统的集成电路布局原则,通常期望能够将宏模块布置在芯片内壁的四周,以便于构建供电网络,使得芯片的电源布线更为容易。 Digital signal processing chip circuit design is called a lot RAM, ROM and other logic modules, these modules will be placed in the greatly affect the final layout, the principles for a conventional integrated circuit layout is generally desirable to be able to macroblock disposed around the inner wall of the chip, in order to construct the power supply network, so that the power supply wiring chip easier. 但是如果在设计中用到的宏模块数目较大,则必须在宏模块间留出必需的布局布线空间以摆放宏模块周边电路,以更为有效的利用布线资源,提高布通率,因而对海量模块布局要通过合理的方法来实现芯片版图的布局优化,同时也要兼顾电源供电的需求。 However, if the number of macro block used in the design of large, it must allow the required layout space placed between the macroblock to macroblock peripheral circuit, a more efficient use of routing resources, improve routability, thus massive layout module layout optimization to be achieved by the chip layout reasonable approach, while taking care of the needs of power supply. 发明内容本发明所要解决的技术问题就是提供一种能够实现芯片版图的布局优化,也能兼顾电源供电需求的对芯片中的海量模块进行阵列布局的方法,本发明使芯片设计中涉及的大量IP模块和宏模块阵列摆放,能更有效的利用布线资源,提高布通率。 SUMMARY OF THE INVENTION Problems to be solved is to provide a possible layout optimization die layout also take into account the chip power supply requirements in massive modules method of an array layout, the present invention enables a large number of IP chip design involved and an array of display modules macroblock, more effective use of routing resources, improve routability. 同时也缓解了芯片规模给面积带来的压力,使整体性能得到了提高。 But also eased the pressure on chip scale to bring the area, so that the overall performance has been improved. 本发明的目的是这样实现的,它包括步骤:① 根据电原理图逻辑设计提交的网表,分析芯片模块之间的布局关系;② 根据版图布局用到的单元库,分析芯片调用模块的特性参数;③ 根据第①、②步骤分析的结果,将模块按标准单元的摆放方式, 进行集中阵列式摆放,实现优化时序的设计;④ 基于传统的靠边缘摆放原则,阵列式摆放也先从芯片边缘开始,并根据模块面积进行调整,实现芯片布局面积最小化,完成对芯片中的海量模块进行阵列布局。 Object of the present invention is implemented, comprising: ① From a layout relationship between the electrical schematic of the logic netlist submitted designs, the analysis chip module; ② the layout of a layout used in the cell library, a characteristic analysis chip calling module parameters; ③ according ①, ② the step of analyzing the result of the display module according to the standard cell, the centralized display array, optimized design of timing; ④ placed against the edge based on the traditional principles, display array also start chip edge begins, and adjust the area of ​​the module, implemented to minimize chip layout area, complete chip module massive array layout. 本发明第(D步中所述的模块之间的布局关系,其包括不同模块间耦合松紧度、模块间连接关系、数据在不同模块间流动方向的布局关系。本发明第②步中所述的模块的特性参数,其包括走线复杂性、端口负载电容、天线效应系数、输出负载系数的特性参数。本发明与背景技术相比,具有如下优点-(1)本发明将海量模块以标准单元的阵列方式摆放,在模块间留出了必须的布局布线空间以便模块周边电路走线,这样能更有效利用布线资源,提高布通率。(2)本发明采用阵列式摆放,模块布局紧凑。相对于传统的摆放方式,这样能够减小芯片面积,随着芯片设计规模的增加,优势更为明显。附图说明图1是本发明对芯片中的海量模块进行阵列布局后的版图示意图。图1中正方形四边的黑色区域是输入输出单元(即I/O单元),正方形内的大量黑色空心矩形为设计 Layout relationship between the first (in the step D module of the present invention, which comprises coupling tightness between the different modules, inter-module connection relationship, the relationship between the layout direction of data flow between the different modules. Step ② of the present invention, . characteristic parameter module, comprising alignment complexity, port load capacitance, the antenna effect coefficient, the characteristic parameters of the output load factor of the present invention compared to the background art, has the following advantages - (1) the mass of the present invention is a standard module an array of display unit, the layout space aside so as to block the peripheral circuit must be routed between modules, so that more efficient use of routing resources, improve routability. (2) the present invention employs an array type display module compact layout with respect to the conventional display mode, so that the chip area can be reduced, with the increase in size of the chip design, the advantage is more obvious. FIG. 1 is a chip of the present invention, the mass after the array layout module schematic layout. four sides of the square in FIG. 1 is a black area input-output unit (i.e., I / O units), the large black square hollow rectangular design 使用的RAM和ROM模块, 由这些模块组成的"门"开口空隙形区域即为宏模块布局区域,在宏模块间留出必需的布局布线空间以摆放宏模块周边电路。具体实施方式本发明方法包括步骤:① 根据电原理图逻辑设计提交的网表,分析芯片模块之间的布局关系。本发明模块之间的布局关系,其包括不同模块间耦合松紧度、 模块间连接关系、数据在不同模块间流动方向的布局关系。② 根据版图布局用到的单元库,分析芯片调用模块的特性参数。 本发明模块的特性参数,其包括走线复杂性、端口负载电容、天线效应系数、输出负载系数的特性参数。 —③ 根据第①、②步骤分析的结果,将模块按标准单元的摆放方式, 进行集中阵列式摆放,实现优化时序的设计。④ 基于传统的靠边缘摆放原则,阵列式摆放也先从芯片边缘开始,并根据模块面积进行调整,实现 The use of RAM and ROM modules, these modules "door" open area is the void shaped layout area macroblock, inter macroblock leave the necessary space for placing layout macroblock peripheral circuit. DETAILED DESCRIPTION The present invention the method comprising the steps of:. ① layout relationship between the module of the present invention, which includes a coupling tightness between the different modules, inter-module connection relation according to the layout relationship between the electrical schematic of the logic netlist submitted designs, the analysis chip module, data layout relationship between the different modules according to the direction of flow cell library layout placement .② used, characteristic parameter analysis chip of the calling module. characteristic parameter module of the present invention, which comprises a complex traces, port load capacitance, the antenna effect coefficient, the output characteristic parameter load factor. -③ according ①, ② the step of analyzing the result of the display module according to the standard cell, the centralized display array, designed to optimize the timing .④ conventional placed against the edge based on the principle , also display array chip edge begins to start, and adjust the area of ​​the module, implemented 片布局面积最小化,完成对芯片中的海量模块进行阵列布局。 Chip layout area is minimized, the mass of the complete chip module array layout.

实施例中本发明第①、②步所述的模块相互关系和模块特性参数都要综合考虑,充分考虑不同模块间耦合松紧度、模块间连接关系、 数据在不同模块间流动方向的布局关系、走线复杂性、端口负载电容、 天线效应系数、输出负载系数等因素的影响,对模块在芯片上的位置及相互之间的位置进行合理布局,使得阵列摆放可以更好的满足模块的特性参数所造成的影响。 The first embodiment of the present invention ①, ② the step module and the relationship between the characteristic parameters to be taken into account module, different modules take full account of the coupling tightness, inter-module connection relationship, the relationship between the direction of flow of layout data between different modules, characteristic factors traces complexity, port load capacitance, the antenna effect coefficient, coefficient output load, mutual position between the position of the module on the chip and rational distribution, so that the display can better meet the array module the impact caused by the parameters.

实施例中本发明第③步将芯片调用的海量模块以标准单元常用的阵列方式进行集中摆放,通过这种摆放方式,能够有效的降低模块连接所需的走线长度,提高芯片所能达到的时序性能,利用功能模块的方式进行布局优化,也能够降低局部布线拥塞,增加布通率,降低布线时间。 Step ③ embodiment of the present invention, chip modules invoked embodiment massive focus placed in a standard cell array common way, by placing such a manner, it is possible to effectively reduce the required connection modules trace length, can improve the chip timing performance achieved by using the function module layout optimization manner, it is possible to reduce the local routing congestion, routability increases, reducing the wiring time.

实施例中本发明第④步根据模块面积进行布局调整,布局以功能驱动而非传统优先边角排布,使得芯片宏模块整体布局于功能逻辑区域中,降低了局部走线拥塞度,因为不拘于按边缘摆放,使布局调整的灵活性增加,更利于减小芯片面积,如图1所示。 Example embodiments of the present invention the first step ④ be adjusted according to the layout area of ​​the module, rather than the traditional layout to function driver corners preferentially arranged such that the overall layout of the chip macroblock functional logic region, reducing the local routing congestion degree, because informal in place by the edge of the layout adjustment increased flexibility, more conducive to reduce the chip area, as shown in FIG.

图1是本发明对芯片中的海量模块进行阵列布局后的版图的示 FIG. 1 is a layout of the present invention, after the mass of the chip module array layout shown

意图。 intention. 图1中正方形四边的黑色区域是输入输出单元(即i/o单元), Four sides of the square in FIG. 1 is a black area input-output unit (i.e., i / o Unit),

正方形内的大量黑色空心矩形为设计中使用的RAM和ROM模块, 由这些模块组成的"门"开口空隙形区域即为宏模块布局区域,由于数目众多,总共二百多个,面积和达到芯片面积的70%以上,如果用传统布局原则,将模块沿边缘放置,难度很大,采用独特的模块阵列方式进行布局,在宏模块间留出必须的布局布线空间以摆放宏模块周边电路,以更为有效的利用布线资源,提高布通率。 Large number of black squares in the hollow rectangular RAM and ROM modules used in the design, these modules "door" open area is the void shaped macroblock layout area due to the large number, more than 200 in total, and reach the chip area area of ​​more than 70%, if the principle of the traditional layout, the modules are placed along the edge, it is very difficult, unique module an array layout, the layout space must be left in place between the macroblock to macroblock peripheral circuit, a more efficient use of routing resources, improve routability.

Claims (1)

1.一种对芯片中的海量模块进行阵列布局的方法,其特征在于包括步骤: ①根据电原理图逻辑设计提交的网表,分析芯片模块之间的布局关系:包括不同模块间耦合松紧度、模块间连接关系、数据在不同模块间流动方向的布局关系; ②根据版图布局用到的单元库,分析芯片调用模块的特性参数:其包括走线复杂性、端口负载电容、天线效应系数、输出负载系数的特性参数; ③根据第①、②步骤分析的结果,将模块按标准单元的摆放方式,进行集中阵列式摆放,实现优化时序的设计; ④基于传统的靠边缘摆放原则,阵列式摆放也先从芯片边缘开始,并根据模块面积进行调整,实现芯片布局面积最小化,完成对芯片中的海量模块进行阵列布局。 A mass of chip array layout method of modules, comprising: ① From a layout relationship between the electrical schematic of the logic netlist submitted designs, the analysis chip module: the tightness of the coupling between the different modules connection relationship between modules, the flow direction of the data layout relationship between the different modules; ② the characteristic parameters used in the layout of the layout cell library, call the analysis chip module: including alignment complexity, port load capacitance, the antenna effect coefficient, characteristic parameters of the output load factor; ③ according ①, ② the step of analyzing the result of the display module according to the standard cell, the centralized display array, optimized design of timing; ④ placed against the edge based on the traditional principles , also display array chip edge begins to start, and adjust the area of ​​the module, implemented to minimize chip layout area, complete chip module massive array layout.
CN 200710139510 2007-09-28 2007-09-28 Chip massive module array layout method CN100478966C (en)

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CN1591430A (en) 2003-09-04 2005-03-09 扬智科技股份有限公司 Integrated circuit layout designing method capable of automatic layout and layout designing software
CN1801159A (en) 2005-01-03 2006-07-12 新思公司 Method and apparatus for placing assist features
CN1828864A (en) 2005-03-03 2006-09-06 联华电子股份有限公司 Method for realizing circuit layout

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CN1591430A (en) 2003-09-04 2005-03-09 扬智科技股份有限公司 Integrated circuit layout designing method capable of automatic layout and layout designing software
CN1801159A (en) 2005-01-03 2006-07-12 新思公司 Method and apparatus for placing assist features
CN1828864A (en) 2005-03-03 2006-09-06 联华电子股份有限公司 Method for realizing circuit layout

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