CN100464424C - 集成电路及其形成方法 - Google Patents

集成电路及其形成方法 Download PDF

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CN100464424C
CN100464424C CN 200610093198 CN200610093198A CN100464424C CN 100464424 C CN100464424 C CN 100464424C CN 200610093198 CN200610093198 CN 200610093198 CN 200610093198 A CN200610093198 A CN 200610093198A CN 100464424 C CN100464424 C CN 100464424C
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B·A·安德森
E·J·诺瓦克
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国际商业机器公司
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    • Y10S257/903FET configuration adapted for use as static memory cell

Abstract

本发明公开了一种通过在体晶片上的硅锗鳍片上外延生长硅鳍片对形成晶体管对的方法。在一个实施例中,鳍片之间的栅极导体与体晶片上的导体层隔离,由此形成前栅极。在另一个实施例中,鳍片之间的栅极导体与体晶片上的导体层接触,由此形成背栅极。在另外一个实施例中,在同一体晶片上同时形成前面两种结构。本方法允许形成的晶体管对具有各种特征(例如,应变鳍片,两个鳍片之间的间隔约为单个鳍片宽度的.5到3倍,每对鳍片的内侧壁上的第一介质层与每对鳍片的外侧壁上的第二介质层具有不同的厚度和/或不同的介质材料等)。

Description

集成电路及其形成方法

技术领域

本发明通常涉及鳍片型场效应晶体管(FinFET),更具体地说,涉及 用于制造具有密集间距的多鳍片的方法。

背景技术

鳍片型场效应晶体管(FinFET )是一类具有包括沟道区和源极和漏极 区的鳍片的晶体管。双栅极FinFET是在鳍片的两側上都具有栅极导体的 FinFET。栅极导体覆盖鳍片的沟道区,而鳍片的源极和漏极区延伸超过栅 极导体的覆层。Hu等(下文中为"Hu,,)的美国专利6,413,802中详细讨 论了 FinFET,在此通过参考结合。FinFET可以只包括前和/或背栅极导 体。前栅极导体通常与衬底中任何导电材料相隔离,并从上面蚀刻与前栅 极导体的接触。背栅极导体通常与衬底中的导电材料电连接,并从下面蚀 刻与背栅极导体的接触。为了对现有技术加以改进,制造者们继续努力于 增加集成电路上的器件密度,并同时在不影响性能的情况下降低制造集成 电路的成本。通常使用绝缘体上硅(SOI)晶片实现FinFET工艺,这是 因为对前栅极隔离的需求和易于限定鳍片的高度。以此方式形成FinFET 的缺点包括SOI晶片的高成本和器件尺寸缩小的限制,更具体地说,是器 件之间间距的限制。

发明内容

虑及上述原因,本发明包括包括在体晶片上具有密集间距的晶体管对 的集成电路结构以及用于形成所述晶体管对的方法。本发明公开了三种结 构:第一种结构具有第一对硅鳍片,在该硅鳍片对之间具有背栅极,第二

种结构具有第二对硅鳍片,在该硅鳍片对之间具有前栅极(例如,上栅极), 而第三种结构在同一晶片上同时包括所述第 一和第二种结构。鳍片都具有 近似相等的宽度和内侧壁和外侧壁。每个鳍片位于体晶片上的导体层(硅 锗层)上的绝缘层(例如,二氧化硅)上。所述硅鳍片对使用外延工艺在 硅锗上形成,如果需要,所述工艺允许鳍片应变。两个鳍片之间的间隔具 有近似等于一个硅鳍片宽度(例如,.5到3倍)的宽度(即,硅鳍片的宽

度近似等于鳍片之间间隔的宽度(例如,1/3到2倍))。所述第一种结 构在与所述第一对鳍片的内侧壁相邻的所述第一间隔中可以包括用作背斗册 极的第一栅极导体(例如,电连接到所述导体层)。所述第二种结构在与 所述第二对鳍片的内侧壁相邻的所述第二间隔中可以包括用作前栅极的第 二栅极导体(例如,通过另一介质层与所述导体层电隔离)。所述鳍片对 每个都具有限制到所述鳍片之间间隔的宽度加一个鳍片宽度的间距(即,

所述鳍片中心点之间的距离)。所述第一和第二种结构也可以包括与每对 鳍片外侧壁相邻的附加栅极导体。附加栅极导体可以包括分别与所迷第一 和第二栅极导体相同或不同的导电材料。另外,鳍片对(例如,第一和/ 或第二鳍片对)可以在每个鳍片的内侧壁上具有第一栅极介质层而在每个 鳍片的外侧壁上具有第二栅极介质层。所迷第一栅极介质层可以包括与所 述第二栅极介质层不同的介质材料,并具有与其不同的厚度。

形成晶体管对的方法的实施例包括使用体晶片在绝缘层上形成硅鳍片 对,以使每个鳍片具有所述两个鳍片之间的所述间隔宽度的约1/3到2倍 的宽度。更具体地说,在体晶片上形成硅锗层。所述硅锗层被构图并蚀刻 部分近入硅锗层,以形成具有预定宽度的硅锗鳍片。然后在与所述硅锗鳍 片的下部分相邻的硅锗层上形成绝缘层。然后,通过在硅锗鳍片上外延生 长硅层(此硅层可以或者不应变)来形成硅鳍片对。氧化所迷硅层的顶表 面,然后在所述硅层上淀积导电材料。除去所述硅铐鳍片顶表面上的膜。 一旦暴露所述硅锗鳍片的顶表面,除去所述硅锗鳍片的上部分,以用剩余 硅层形成硅鳍片对,并在两个硅鳍片之间留下间隔。所述间隔的宽度近似 等于最初的硅锗鳍片的预定宽度(例如, 一个硅鳍片宽度的.5-3倍)。使

用两步工艺在每个硅鳍片上形成第一和第二栅极介质层。当氧化所述硅层 的表面时,在所述鳍片对的外侧壁上形成第二介质层。为了形成第一介质 层,除去所述硅锗鳍片的上部分,由此暴露所述鳍片对的内侧壁。氧化暴 露的内侧壁,以形成所述第一栅极介质层。所述第一栅极介质层可以具有 与所述第二栅极介质层不同的厚度和/或不同的介质材料。另外,当除去所

述硅锗鳍片的上部分时,在所述导体层上保留下部分。 一旦氧化硅鳍片对 的暴露的内侧壁,同时氧化所述硅锗鳍片的剩余下部分,并形成附加介质 层。此附加介质层将所述栅极导体与所述导体层电隔离,以使可以利用另 外的工艺在两个鳍片之间形成前栅极。另外,在形成所述附加介质层之后 并在形成所述栅极导体之前,可以除去所述附加介质层。除去所述附加介 质层允许所述栅极导体接触所述导体层,以使可以利用另外的工艺在两个 鳍片之间形成背栅极。

另外,此方法可以包括在同一体晶片上同时形成至少两对晶体管,以 使第 一对用于两个鳍片之间的背栅极而第二对用于两个鳍片之间的前栅极 (例如,双栅极)。例如,此方法可以包括在同一体晶片上同时形成至少 两对鳍片(以第一间隔分开的第一对鳍片和以第二间隔分开的第二对鳍 片),以及如上所述的之后的工艺步骤。然而, 一旦所述第一和第二间隔 中的所述硅锗鳍片的剩余下部分被氧化,所述第二间隔中形成的附加介质 层将被掩蔽。然后,除去所述第一间隔中形成的附加介质层并接着除去所 述掩膜。再次,如上所迷继续进行工艺。

当结合下面的描述和附图考虑时,本发明的这些和其它方面和目的将 更明显而且更好理解。然而,应该理解,尽管给出的下述描述包含本发明 的实施例及其许多具体细节,但它们用于示意而非限制。在不脱离本发明 精神的情况下,可以在本发明的范围内进行许多改变和修改,而且本发明 包括所有这些修改。

附图说明

参考附图,通过下面的详细描述将更好地理解本发明,所述附图包括: 图1为示意图,

图2为流程图, 图3为示意图, 图4为示意图, 图5为示意图, 图6为示意图, 图7为示意图, 图8为示意图, 图9为示意图, 图IO为示意图 图11为示意图

具体实施方式

将参考附图中所示的并在下面的描述中详述的非限制性实施例更加完 全地解释本发明及其各种特征和优点的细节。应该注意,附图中所示的特 征没有必要按比例绘制。为了使本发明显得明晰,公知的元件和工艺技术 的描述将^L省略。在此^f吏用的示例仅仅旨在帮助理解可以实践本发明的方 法,并使本领域内的技术人员能够实践本发明。因此,不应该将所述示例 解释为限制本发明的范围。

如上所述,为了对现有技术加以改进,制造者们继续努力于增加集成 电路上的器件密度,并同时在不影响性能的情况下降低制造集成电路的成 本。通常使用绝缘体上硅(SOl)晶片实现FinFET工艺,这是因为对前 栅极隔离的需求和易于限定鳍片的高度。以此方式形成FinFET的缺点包 括SOI晶片的高成本和器件尺寸缩小的限制,更具体地说,是在器件之间 建立密集间距的限制。外延生长用于双栅极金属氧化物半导体场效应晶体 管(MOSFET)的半导体结构是公知的(参见1997年2月18日公开的 Taur等的美国专利No. 5,604,368,在此通过参考结合)。然而,最近的发 明公开了通过在弛豫硅锗层的侧壁上外延生长硅层,形成用于FinFET器

示出了本发明的完成的结构100、 200和300;

示出了本发明的方法;

示出了本发明的部分完成的结构;

示出了本发明的部分完成的结构;

示出了本发明的部分完成的结构;

示出了本发明的部分完成的结构;

示出了本发明的部分完成的结构;

示出了本发明的部分完成的结构;

示出了本发明的部分完成的结构; ,示出了本发明的部分完成的结构;以及 ,示出了本发明的部分完成的结构。

件的硅鳍片的方法(参见2004年9月2日公开的Rim发明的美国专利申 请公开No. US2004/0169239,在此通过参考结合)。Rim的发明在SO【晶 片上形成了硅鳍片,或作为选择,在硅衬底上的緩变硅锗层上形成硅鳍片。 本发明对Rim的发明进行了改进。具体地说,本发明公开了具有多个密集 间距的薄硅鳍片的集成电路结构,以及在体晶片上形成此结构以降低成本 的相关方法。

如上所述,本发明公开了具有密集间距的晶体管对的集成电路结构及 其形成方法。图1中示出了本发明的结构100、 200和300。具体地,结构 100示出了用于第 一对硅鳍片1之间的第 一 间隔31中背栅极的密集间距双 鳍片集成电路结构。结构200示出了用于第二对硅鳍片2之间的第二间隔 32中前栅极(例如,双栅极)的密集间距双鳍片集成电路结构。结构300 示出了相同体晶片IO上的两个密集间距双鳍片结构100和200。每对鳍片 1、 2都具有近似相等的宽度7以及反向的内侧壁41和外侧壁42。每个鳍 片位于绝缘层12 (例如,二氧化硅)上。第一和第二对鳍片1、 2使用硅 锗上的外延工艺形成,如果需要,此工艺允许使鳍片产生应变。第一和第 二对硅鳍片1、 2之间的第一和第二间隔31、 32分别具有近似相等的宽度 8。间隔31、 32的宽度8近似等于(例如,.5到3倍)硅鳍片的宽度7。 绝缘层12形成于导体层11 (例如,硅锗膜层)上,而所述导体层形成于 体晶片10上。可以在与第一对鳍片1的内侧壁41相邻的第一间隔31中形 成第一栅极导体21,用于结构100的背栅极。可以在与第二对鳍片2的内 侧壁42相邻的第二间隔32中形成第二栅极导体22,用于结构200的前栅 极。每对鳍片1、 2具有限制于间隔31或32的宽度8加一个鳍片宽度7 的间距(即,鳍片中心点之间的距离)。结构100和200都可以包括与每 个鳍片的外侧壁42相邻的附加栅极导体28。附加栅极导体28可以包括与 第一和第二栅极导体21、 22相同的导电材料,或不同的导电材料(例如, 不同的高掺杂多晶硅材料或例如TiN的金属材料)。另外,每个鳍片可以 在反向的内侧壁41和外侧壁42上具有第一栅极介质层5和第二栅极介质 层4。与第二栅极介质层4相比,第一栅极介质层5可以包括不同的介质材料,并可以具有与厚度14不同的厚度18。参考结构100,第一栅极导体 21可以延伸穿过绝缘层12并接触导体层11,以可以在下一步工艺期间形 成背栅极。作为选择,参考结构200,第二栅极导体22可以通过位于第一 栅极导体层22和导体层11之间的附加介质层23与导体层11隔离,以可 以在下一步工艺期间形成前栅极(例如,双栅极)。

结合图l参考图2,形成多鳍片集成电路结构100或200的方法的实 施例包括形成硅锗鳍片16 (201)。具体地,在体晶片11上形成厚硅锗导 体层ll。在导体层ll上淀积并光刻构图光致抗蚀剂层,并进行蚀刻工艺, 以使形成硅锗鳍片16并将一部分导体层U保留在体晶片10上。光致抗蚀 剂将被构图,以使硅锗鳍片16具有近似等于硅鳍片对之间的预期间隔(例 如,硅鳍片宽度7的.5-3倍)的预定宽度8 (例如,现有技术的最小光刻 尺寸)。 一旦形成硅锗鳍片16,在与硅锗鳍片16的下部分16.2相邻的导 体层11上形成绝缘层12 (202,参见图3)。由此,硅锗鳍片16延伸穿过 绝缘层12。

可以通过在硅锗鳍片16上外延生长薄硅层3来形成第一和/或第二对 硅鳍片1、 2 (参见图1) (204,参考图4)。外延工艺可以是这样的,生 长的硅层3被应变并且是硅锗鳍片16的预定宽度8的1/3到2倍。在工艺 204中形成硅层3之后,在硅层3的外表面上形成介质层(例如,通过淀 积介质材料、通过氧化硅层的顶表面等),由此将最终在每对硅鳍片1、 2 上形成第二栅极介质层4 (206,参见图5)。然后在硅锗鳍片16上淀积例 如高掺杂多晶硅或金属(例如,TiN)的第一导电材料28。此第一导电材 料28最终形成了图1的附加栅极导体28 ( 208,参见图6)。然后,实施 抛光工艺(例如,化学机械抛光(CMP)),以从硅锗鳍片16的顶表面 17除去硅层3 (210,参见图7)。

一旦在工艺210中暴露了硅锗鳍片16的顶表面】7,除去绝缘层12之 上的硅锗鳍片16的上部分16.1 (例如,通过选择性蚀刻) > 以用剩余的硅 层3形成一对硅鳍片(例如,第一对硅鳍片1和第二对硅鳍片2) (212, 参见图8)。由此,一对硅鳍片的每个硅鳍片之间的间隔(例如,第一对

鳍片1之间的第一间隔31和第二对鳍片2之间的第二间隔32)等于硅锗 鳍片16的宽度,并近似为一对鳍片中的单个鳍片宽度的.5到3倍。更具体 地说,将硅锗鳍片16的上部分16.1选择性蚀刻到绝缘层12的表面24之 下的水平26。所得每对鳍片(例如,第一对1和第二对2)都包括氧化的 外侧壁42 (即,外侧壁42上的第二栅极介质层4)和暴露的内側壁41。 然后氧化每个鳍片的暴露的内硅侧壁41,以在每对鳍片1、 2中的每个硅 鳍片的内侧壁41上形成第一栅极介质层5(214,参见图9)。第一栅极介 质层5的厚度18可以与第二栅极介质层4的厚度14不同。或者,第一和 第二介质层4、 5可以由不同的介质材料形成。

除了形成第一栅极介质层5,氧化工艺214同样氧化硅锗鳍片16的剩 余下部分16.2,此部分残留于绝缘层12的表面24之下的导体层11上。形 成于间隔31和32中的此附加介质层23可用于将上面间隔中形成的栅极导 体与导体层ll上电隔离。应该注意,尽管鳍片的暴露的内側壁41与硅锗 鳍片16的剩余部分16.2同时被氣化,但是形成的附加介质层23的厚度19 可以大于第一介质层5的厚度18,这是因为珪锗氧化的速率更快。

直到此时,可以使用上述相同工艺形成结构100和200。结构200可 以通过在鳍片对2之间的间隔32中的附加介质层23上淀积笫二导电材料 20 (例如,高掺杂多晶硅或金属)来完成(216,参见图11)。此第二导 电材料20可以与工艺208中淀积的第一导电材料28的材料相同或不同。 然后抛光导电材料20 (例如,通过CMP),并由此形成结构200的第二 栅极导体22 ( 218,参见图1 )。 一旦在工艺218中形成结构200的第二栅 极导体22,可以进行附加FiiiFET工艺以形成结构200的两个FinFET(例 如,蚀刻栅极接触)(220)。

作为选择,可以在淀积第二导电材料20 (226)之前,通过从间隔31 中除去附加的介质层23来形成结构100 ( 224)。例如,在形成附加介质 层23之后,可以在间隔31内淀积薄多晶硅层。然后,可以使用隔离物蚀 刻工艺从间隔M选择性除去附加介质层23。如上面关于结构200的论述, 此第二导电材料20可以与工艺208中淀积的第一导电材料28相同或不同。 然后抛光第二导电材料20 (例如,通过CMP),并由此形成结构100的 第一栅极导体21 (218,参见图1)。 一旦在工艺218中形成结构100的第 一栅极导体21,可以进行附加FinFET工艺以形成结构100的两个FinFET (例如,蚀刻栅极接触)(220 )。为了形成背栅极,在除去附加介质层 23的工艺224中允许第一栅极导体21与导体层11接触。

形成组合结构300的方法的实施例包括,在相同的体晶片10上同时形 成两个可选择的结构100和200。再次参考图2,为了在同样的晶片10上 形成结构100和200,在工艺201中形成多个硅锗鳍片16。这些多个硅锗 鳍片16可以用于在相同的体晶片10上同时形成多个结构100和/或多个结 构200。为了用结构100和200的组合形成结构300,接着要完成如上所述 的工艺201-214,以形成至少一个第一对硅鳍片l和至少一个第二对硅鳍 片2。然后,在每对硅鳍片1、 2之间形成的间隔31和32内淀积薄多晶硅 层(232)。掩蔽第二对鳍片2之间的间隔32 (234)并除去第一对硅鳍片 l之间的介质层23(例如,通过隔离物蚀刻工艺)(236),并除去掩才莫(238; 参考图10)。然后可以通过在隔离32中的介质层23上和间隔31中的导 体层11上淀积第二导电材料20 (例如,高掺杂多晶硅或金属)来形成结 构300 ( 216,参考图ll)。如上关于结构100和200的论述,用于形成第 一栅极导体21的第二导电材料20可以与工艺208中淀积的第一导电材料 29的导电材料不同。然后抛光第二导电材料20 (例如,通过CMP),并 由此形成结构100的第一栅极导体21和结构200的第二导体22 ( 218,参 见图1)。然后可以进行附加FinFET工艺以形成各个FinFET (例如,形 成用于结构200的前栅极接触和用亍结构IOO的背栅极接触)(220 ),

因此,上面公开了通过在体晶片上的硅锗鳍片上外延生长一对硅鳍片 形成一对晶体管的方法。在一个实施例中,鳍片之间的栅极导体与体晶片 上的导体层隔离,由此形成前栅极。在另一个实施例中,鳍片之间的栅极 导体接触体晶片上的导体层,由此形成背栅极。在另外一个实施例中,同

时在同一个体晶片上形成前面两种结构。本方法允许形成的晶体管对具有 各种特征(例如,应变鳍片,两个鳍片之间的间隔约为单个鳍片宽度的.5

到3倍,每对鳍片的内侧壁上的第一介质层与每对鳍片的外侧壁上的第二 介质层具有不同的厚度和/或不同的介质材料等)。

Claims (20)

1.一种集成电路结构,包括:体晶片;硅锗导体层,在所述体晶片上;绝缘层,在所述导体层上;硅鳍片对,在所述绝缘层上,其中所述硅鳍片对以一间隔分开,所述间隔近似等于一个所述硅鳍片的宽度;以及栅极导体,在所述硅鳍片对之间的所述间隔中。
2. 根据权利要求l的结构,其中所述栅极导体与所述导体 层接触并包括背栅极。
3. 根据权利要求l的结构,其中所述栅极导体与所述导体 层电隔离并包括前栅极。
4. 根据权利要求l的结构,其中所^鳍片对具有与所述 栅极导体相邻的内侧壁和外側壁,并且其中所述结构还包括:第一介质层,具有第一厚度,在所述内側壁上;以及 第二介质层,具有第二厚度,在所述外側壁上,其中所述第 一厚度与所述第二厚度不同。
5. 根据权利要求l的结构,其中所述硅鳍片对具有与所述 栅极导体相邻的内侧壁和外侧壁,并且其中所述结构还包括:第一介质层,在所述内侧壁上;以及第二^h质层,在所述外侧壁上, 其中所述第 一介质层包括与所迷第二介质层不同的介质材料。 '
6. 根据权利要求l的结构,其中每个所^鳍片包括应变 硅。
7. 根据权利要求l的结构,还包括:第二对硅鳍片,在所述绝缘层上,其中所述第二对硅鳍片以 第二间隔分开;以及第二栅极导体,在所述第二间隔中;其中所述第一栅极导体与所述导体层接触并包括背栅极;以及其中所述第二栅极导体与所述导体层隔离并包括前栅极。
8. 根据权利要求l的结构,其中所i^鳍片对具有与所述 栅极导体相邻的内侧壁和外側壁,其中所述结构还包括与所述外侧壁相邻的附加^fr极导体,并且其中所述附加^fr极导体包括与所 述栅极导体不同的导电材料。
9. 一种形成鳍片型场效应晶体管(FinFET)对的方法,所 述方法包括以下步骤:在体晶片上形成具有预定宽度的硅锗鳍片; 在所述硅锗鳍片上外延生长硅层,其中所述硅生长的宽度约 等于所述预定宽度;暴露所i^锗鳍片的顶表面;除去所il^锗鳍片的上部分,以使形成以一间隔分开的硅鳍 片对;以及在所述间隔中形成栅极导体。
10. 根据权利要求9的方法,其中所述形成所ii^锗鳍片的 步骤包括:提供所述体晶片; 在所述体晶片上形成硅锗层; 构图所il^锗辨片以具有所迷预定宽度;以及 蚀刻所ii^锗鳍片部分ifX所^锗层,以使一部分所述硅 锗层保留在所述体晶片上。
11. 根据权利要求9的方法,还包括在所述生长所ilvJ^层的 步骤之前,在与所述硅锗鳍片的下部分相邻的体层上形成绝缘 层,以在所述绝缘层上形成所述硅鳍片对。
12. 根据权利要求9的方法,其中所述生长所i^层的步骤 还包括生长应变硅层。
13. 根据权利要求9的方法,还包括以下步骤: 在所述生长所述硅层的步稞之后,在所^层上形成介质层并在所ii^层上淀积朵一导电层;以及在所述形成所i^鳍片对的步骤之后,在所述硅鳍片对的内 侧壁上形成第一栅极介质层,并在所^鳍片对的外侧壁上形成 第二栅极介质层。
14. 根据权利要求13的方法,其中所述笫一栅极介质层形 成为具有与所述笫二栅极介质层的第二厚度不同的第 一厚度。
15. 根据权利要求13的方法,其中所述第一栅极介质层包 括与所述第二栅极介质层不同的介质材料。
16. 根据权利要求9的方法,还包括以下步骤: 在除去所述硅锗鳍片的所述上部分之后,氧化所述硅锗鳍片的剩余下部分,以将所述栅极导体与所述体晶片上的导体层隔 离。
17. 根据权利要求9的方法,还包括以下步骤: 在除去所i^i锗鳍片的所述上部分之后,氣化所i^^锗鳍片的剩余下部分,以将所述栅极导体与所述体晶片上的导体层隔 离;以及除去所述硅锗鳍片的所述氧化的下部分,以形成与所述导体 层接触的所述栅极导体。
18. —种形成多对鳍片型场效应晶体管(FinFET)的方法,所述方法包括以下步骤:在体晶片上的导体层上形成具有预定宽度的至少两个硅锗鳍片;在所述硅锗鳍片上外延生长硅层,其中所逸眭生长的宽度约等于所述预定宽度;暴露所述>^锗鳍片的顶表面;除去所述珪锗鳍片的上部分,以形成以第一间隔分开的第一 对硅鳍片和以第二间隔分开的笫二对砝鳍;以及在所述第 一 间隔中形成第 一栅极导体并在所述第二间隔中 形成第二栅极导体,其中所述第一栅极导体与所述体晶片上的所 述导体层电连接,而所述第二栅极导体与所述导体层电隔离。
19. 根据权利要求18的方法,其中所述形成所ii^锗辨片 的步骤包括::R供所述体晶片; 在所述体晶片上形成导体层; 构图所il^锗鳍片以具有所述预定宽度;以及 蚀刻所^锗鳍片部分iiA所ity^锗层,以使一部分所述硅 锗层保留在所述体晶片上。
20. 根据权利要求18的方法,还包括在所述生长所述硅层 的步骤之前,在与所述硅锗鳍片的下部分相邻的体层上形成绝缘 层,以在所述绝缘层上形成所述第一对硅鳍片和所述第二对硅鳍 片。 3
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