CN100455160C - Flexible circuit board mounted with semiconductor chip and method for mounting semiconductor chip - Google Patents

Flexible circuit board mounted with semiconductor chip and method for mounting semiconductor chip Download PDF

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CN100455160C
CN100455160C CN 200410070310 CN200410070310A CN100455160C CN 100455160 C CN100455160 C CN 100455160C CN 200410070310 CN200410070310 CN 200410070310 CN 200410070310 A CN200410070310 A CN 200410070310A CN 100455160 C CN100455160 C CN 100455160C
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wiring
pattern
semiconductor chip
region
form
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CN 200410070310
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Chinese (zh)
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CN1585591A (en )
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大峡秀隆
松田厚志
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日本东北先锋公司
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0263High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • H05K1/0265High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985Flexible insulating substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12044OLED
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/189Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/094Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727Varying width along a single conductor; Conductors or pads having different widths
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09736Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product
    • Y02P70/60Greenhouse gas [GHG] capture, heat recovery or other energy efficient measures relating to production or assembly of electric or electronic components or products, e.g. motor control
    • Y02P70/611Greenhouse gas [GHG] capture, heat recovery or other energy efficient measures relating to production or assembly of electric or electronic components or products, e.g. motor control the product being a printed circuit board [PCB]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

一种半导体芯片安装用挠性布线基板。 A semiconductor chip is mounted by a flexible wiring substrate. 该挠性布线基板(10)具有,在绝缘基片(11)上与半导体芯片的输出端子电连接的形成规定图形的布线(12a、12b)。 The flexible printed circuit board (10) having a predetermined pattern forming a wiring (12a, 12b) on an insulating substrate (11) and an output terminal electrically connected to the semiconductor chip. 而且形成有由同一形式的布线(12a)形成了一个图形的第一布线区域(12A)和由同一形式的布线(12b)形成了一个图形的第二布线区域(12B)。 And there is formed a region formed of a first wiring pattern (12A) by the same form of a wiring (12a) and forming a second wiring pattern in a region (12B) of the same form wirings (12b). 此挠性布线基板(10)在不同布线形式的相邻布线区域(12A、12B)之间,形成有用于消除因布线形式的差异所造成的连接不良的图形过渡区域(13)。 This flexible printed circuit board (10) in the region adjacent wirings of different wiring forms (12A, 12B) is formed between the transition region for eliminating pattern (13) connected to form a wiring failure due to a difference caused by. 由此,当在形成有不同布线形式的多种由同一形式的布线形成一个图形的布线区域的挠性基板上进行半导体芯片的输出端子的连接时,可消除布线与输出端子之间的连接不良。 Thus, when the flexible substrate when the wiring regions are formed in a variety of different forms of a wiring formed of the same form a wiring pattern connected to the output terminal of the semiconductor chip can eliminate a poor connection between the wiring and the output terminal .

Description

半导体芯片安装用挠性布线基板及半导体芯片的安装方法 The semiconductor chip mounting method for mounting the flexible wiring substrate and the semiconductor chip

技术领域 FIELD

本发明涉及一种挠性布线基板、半导体芯片安装用挠性布线基板、 显示装置、半导体芯片安装方法。 The present invention relates to a flexible wiring substrate, a semiconductor chip is mounted by a flexible printed circuit board, a display device, a semiconductor chip mounting method.

背景技术 Background technique

对于便携式电话机或PDA (Personal Digital Assistant:便携式信息终端设备)等要求小型、轻量、高性能化的电子设备,要求其提高电子部件在印刷电路板上的安装密度。 For portable phone or a PDA (Personal Digital Assistant: a portable information terminal device) and the like required to be small, lightweight, high performance electronic equipment, which requires the density mounting of electronic components on printed circuit boards. 特别是对于安装在这种电子设备上的薄型扁平屏幕显示装置,希望其显示画面尽可能大,所以要求提高配置在其周边的驱动布线部件的安装密度,为了满足该要求,通过将挠性布线基板的布线直接与半导体芯片的输出端子连接,将半导体芯片安装在挠性布线基板上的COF (薄膜芯片Chip On Film),近年来得到了广泛应用。 Especially for thin flat screen is mounted on an electronic apparatus such a display device, it is desirable that a display screen as large as possible, it is required to improve the mounting density of the drive lines arranged member of its periphery, in order to meet this requirement, the flexible printed circuit a wiring board connected directly to the output terminals of the semiconductor chip, the semiconductor chip mounted on the flexible wiring board COF (chip film chip on film), has been widely used in recent years.

在该COF中,需要对应半导体芯片的输出端子(焊盘)的图形而在挠性布线基板上形成布线图形。 In the COF, the need for a corresponding graphical output terminal (pad) of a semiconductor chip and a wiring pattern formed on the flexible wiring board. 作为此时的挠性布线基板的图形形成技术,多采用下述专利文献1记载的被称为半添加法或全添加法的技术。 At this time, as the pattern forming technique of the flexible wiring substrate, the use of technique called semi-additive process or full additive method described in Patent Document 1 below.

根据图1说明该现有技术,首先,如该图(a)所示,在挠性绝缘基片100的表面上形成成为引线镀层的晶种层101,然后如该图(b)所示, 为了形成所期望的布线图形,在晶种层101的表面上形成使用光致抗蚀剂材料等的掩模图形102。 The explanatory view of the prior art 1, first, as in FIG. (A), is formed on the surface of the flexible insulating substrate 100 to become a lead plating seed layer 101, and as shown in FIG. (B), in order to form a desired wiring pattern, a mask pattern 102 is formed using a photoresist material on the surface of the seed layer 101. 并且,如该图(c)所示,利用电镀法在露出晶种层101的区域覆盖镍、铜等导电性材料,形成布线图形103,根据需要,在这些布线图形103的表面上,利用电镀法或溅射法或蒸镀等成膜法形成使用金等异种金属的表面导电层104。 Further, as in FIG. (C), by plating on the exposed region of the seed layer 101 covering the nickel, copper or other conductive material, the wiring pattern 103 is formed, as needed, on the surfaces of the wiring pattern 103 by electroplating It is formed using a dissimilar metal such as gold or the like, or vapor deposition or sputtering surface of the conductive layer 104 forming method. 并且,如该图(d)所示, 通过去除掩模图形102和位于其底部的晶种层101,在绝缘基片100上形 Further, as in FIG. (D), by removing the mask pattern 102 and the seed layer 101 at the bottom thereof, formed on the insulating substrate 100

成具有由晶种层部分101A、布线图形103、表面导电层104构成的所期望的布线图形的挠性布线基板。 To have a flexible printed circuit board wiring pattern desired by the seed layer portion 101A, the wiring pattern 103, the surface of the conductive layer 104 thereof.

另一方面,半导体芯片的输出端子(焊盘)的排列图形虽然是根据驱动对象的电子设备的端子排列和半导体芯片内部的电路块的结构决定的,但一般不排列成相同图形的端子形式,而多数情况是排列大小不同的焊盘,而且是排列成相同大小的焊盘相对集中、形成大小焊盘不均匀的状态。 On the other hand, the semiconductor chip arrangement pattern output terminal (pad), although the structure of the arrangement and is inside the electronic device driven semiconductor chip circuit terminal block is determined, but generally not the same patterns are arranged in the form of terminal, the majority of cases are arranged in a different size pads, and pads are arranged in the relative concentration of the same size, the size of an uneven pad state.

专利文献1 2000—286536号公报 Publication 2000-286536 Patent Document No. 1

在安装了具有上述的不同大小焊盘的半导体芯片的C0F中,为了高精度地将焊盘与挠性布线基板上的布线连接,需要对应焊盘的大小形成不同布线宽度的布线图形。 In the semiconductor chip mounting pad has a different size of C0F above, in order to wiring pads on the flexible wiring board connected with high precision, requires different corresponding to the size of the pad is formed of a wiring width of the wiring pattern. 这种布线图形的形成,在以驱动电流的大小将大大影响设备性能的电子设备为对象的情况下,将成为重要的设计项目。 This wiring pattern is formed, the size of the electronic device in order to drive current will greatly affect device performance for the case where the object will become an important design projects. 特别是近年来作为自发光型平板显示器而被注目的有机EL显示装置, 由于驱动电流的大小直接影响显示性能,所以在与其连接的挠性布线基板上必须设计上述布线图形。 Especially in recent years as a self-luminous display device is a flat panel display the EL organic attention, since the size of the driving current directly affect the display performance, it is necessary to design the wiring pattern on the flexible wiring board connected thereto.

但是,采用现有技术所示的布线图形形成技术来形成这种不同宽度的布线图形时,明显存在以下的问题。 However, the wiring pattern is formed using the prior art technique shown in this wiring pattern are formed of different widths, the following problems significantly.

艮口,如果通过电镀形成不同宽度的布线图形,则产生在宽度较宽的布线上覆盖的布线材料厚、在宽度较窄的布线上覆盖的布线材料薄的现象。 Gen port, if a wiring pattern is formed by plating different widths, the material thickness of the wiring generates coverage over a wider wiring width, the wiring material covered on a wiring width narrower thin phenomenon. 其原因是在进行电镀时,宽度较宽的布线与宽度较窄的布线相比, 因电阻形成的电位下降小,但如果布线图形中产生这种厚度差,则在通过各向异性导电膜利用热压接来将挠性布线基板的布线图形与半导体芯片的焊盘连接时,存在着在相邻布线之间的形成阶梯的部分的周边容易产生压接不良的问题。 The reason is that during electroplating, compared with a wider width of the wiring line width narrower, the resistance due to the potential formation of small drops, but if the thickness of the wiring pattern produce this difference, the anisotropic conductive film by using thermocompression bonding to connect the wiring pattern and the semiconductor chip pad when the flexible wiring substrate, there is likely to occur in the problem of the poor crimping a peripheral portion forming a step between adjacent wirings.

下面,结合图2所示示例进行更具体地说明。 Hereinafter, in conjunction with the example shown in FIG. 2 in more detail. 在挠性布线基板1上, 形成由与宽度较宽的布线la相同形式的布线形成一个图形的第1布线区域1A,并且形成由与宽度较窄的布线lb相同形式的布线形成一个图形的第2布线区域1B。 1 on a flexible wiring substrate, forming a wiring of the same form as the wider wiring width la of a wiring pattern of the first region. 1A, and is formed by a first wiring formed in the same form as a narrow width of a wiring pattern lb 2 wiring region 1B. 另一方面,在半导体芯片2上,形成由与宽度较宽的焊盘2a相同形式的焊盘形成一个图形的第1焊盘区域2A,并且形成由与宽度较窄的焊盘2b相同形式的焊盘形成一个图形的第2焊盘区域2B。 On the other hand, on the semiconductor chip 2 is formed with a wide width is formed by a pad of the same form a pad pattern 2a of the first pad region. 2A, and is formed of the same form as the width of the narrow pad 2b the second pad region forming a pad pattern FIG. 2B. 布线la和焊盘2a或布线lb和焊盘2b分别具有大致相同的宽度且具有相同图形,通过各向异性导电膜3相互对接,在加热状态下施加压力P进 La wirings or wirings and the pad 2a and the pad 2b lb each have approximately the same width and have the same pattern, an anisotropic conductive film 3 by abutting each other, the intake pressure P is applied in a heated state

行热压接。 Line thermo-compression bonding.

此处,在第1布线区域1A和第2布线区域1B的相邻部位,如上所述,根据布线宽度而产生布线厚度差异,成为在布线接触面形成有阶梯差的状态。 Here, the adjacent portion of the first wiring region and the second wiring region 1A and 1B, as described above, the difference in thickness is generated in accordance with a wiring width of the wiring, a step difference in a state of a contact surface formed on the wiring. 如果在该状态下进行热压接,在形成阶梯差的部分的周边部分A,由于该阶梯差的影响,不能施加上充足的压力,在该周边部分A产生压接不良,发生连接不良的问题。 If the thermocompression bonding in this state, the peripheral portion of the portion A step is formed due to the influence of the level difference, sufficient pressure is not applied, pressure bonding failure is generated in the peripheral portion A, the problem of connection failure occurs .

为了消除该问题,只要使第1布线区域1A的布线la和第2布线区域1B的布线lb的厚度相同即可,但是为了使不同形式的布线厚度成为相同厚度需要特殊的加工处理,致使挠性布线基板的成本升高,并且还有对微细的布线图形实施加工处理相当困难的问题。 To solve the problem, as long as the thickness of the wiring lb in the first wiring region 1A and the second wiring line la region 1B can be the same, but the thickness of the wiring to be different forms of the same thickness requires special processing, resulting in the flexible the cost of the wiring board is increased, and also the wiring pattern of the embodiment of a fine processing very difficult problem.

发明内容 SUMMARY

本发明将解决这种问题作为课题之一。 The present invention will solve this problem as one of the topics. 即,本发明的目的是,向对 That is, an object of the present invention, on the

各种不同布线形式形成了多个利用相同形式的布线形成一个图形的布线 Various forms of wirings formed a plurality of wiring a wiring formed using the same in the form of a pattern

区域的挠性布线基板连接半导体芯片的输出端子时,不使布线和输出端 When the output terminal is connected to the flexible wiring substrate of the semiconductor chip area, no wiring and an output terminal

子之间产生连接不良,针对具有不同大小的输出端子的半导体芯片,通过形成与其相适应的布线图形来获得高精度的连接,由此,消除因连接 Connection failure between the promoter, the output terminal for the semiconductor chips having different sizes, a wiring pattern is formed by its adapting to obtain a highly accurate connection, thereby, eliminate the connection

电阻的偏差造成的驱动电流的不均,确保电子设备、特别是驱动电流的大小直接影响显示性能的有机EL显示装置的良好性能等。 Good performance of the device, and the like of the driving current variation caused by the variation in resistance, to ensure that the electronic device, in particular the amount of current driving performance directly affect the display of the organic EL display. 为了达到上述目的,本发明至少具备以下各发明的结构。 To achieve the above object, the present invention includes at least the following structure of the invention. 本发明提供一种挠性布线基板,具有与半导体芯片的输出端子电连接的规定图形的布线,其特征在于,对每种不同布线形式形成多个由相同形式的所述布线形成一个图形的布线区域,在布线形式不同的相邻的所述布线区域之间,形成用于消除因布线形式的差异造成的连接不良的图形过渡区域。 The present invention provides a flexible printed circuit board having a predetermined wiring pattern is electrically connected to the output terminal of the semiconductor chip, characterized in that a wiring formed of the wiring pattern is formed by a plurality of the same form for each of the different forms wirings region, the wiring area between the different forms of adjacent wirings, to eliminate a transition region forming a pattern of connection failure due to the difference in the form of the wiring caused.

本发明还提供一种半导体芯片的安装方法,通过将半导体芯片的规 The present invention further provides a method of mounting a semiconductor chip, the semiconductor chip by the rules

定图形的输出端子和与挠性布线基板的所述输出端子对应的图形的布线电连接,将所述半导体芯片安装在所述挠性布线基板上,其特征在于, 使用对每种不同布线形式形成多个由相同形式的所述布线形成一个图形的布线区域,在布线形式不同的相邻的所述布线区域之间,形成用于消除因布线形式的差异造成的连接不良的图形过渡区域的挠性布线基板, 使所述输出端子的图形与所述布线区域的各布线图形相互对应,进行电连接。 Predetermined pattern and an output terminal of a flexible wiring board electrically wiring pattern corresponding to said output terminal is connected to the semiconductor chip mounted on the flexible wiring board, wherein, for each use different forms wirings the plurality of wirings are formed by the same pattern in the form of a wiring region formed between the wiring area of ​​the wiring in the form of different adjacent transition region pattern is formed due to poor connection caused by the difference in the form of a wiring for eliminating the the flexible printed circuit board, each wiring pattern of the wiring pattern and the output terminal of the region correspond to each other are electrically connected.

附图说明 BRIEF DESCRIPTION

图l是现有技术(挠性布线基板的图形形成技术)的说明图。 Figure l is a diagram illustrating the prior art (flexible printed circuit board pattern formed technology).

图2是说明现有技术的问题的说明图。 FIG 2 is a diagram illustrating problems of the prior art described in FIG.

图3是表示本发明实施方式的挠性布线基板的说明图。 FIG 3 is an explanatory view of a flexible wiring board according to an embodiment of the present invention.

图4是表示本发明实施方式的半导体芯片安装用挠性布线基板的说明图。 FIG 4 is an explanatory view of a flexible wiring substrate a semiconductor chip mounted embodiment of the present invention.

图5是表示本发明其他实施方式的半导体芯片安装用挠性布线基板的说明图。 FIG 5 is an explanatory view of the flexible wiring substrate according to the present invention, a semiconductor chip mounted to another embodiment.

图6是表示本发明其他实施方式的半导体芯片安装用挠性布线基板的说明图。 FIG 6 is an explanatory view of the flexible wiring substrate according to the present invention, a semiconductor chip mounted to another embodiment.

图7是表示作为设置有本发明实施方式的半导体芯片安装用挠性布线基板的电子设备的一例的显示装置的俯视图。 7 is a semiconductor chip provided as embodiments of the present invention a top view showing an example of an electronic device with a flexible wiring substrate of the display device is mounted.

图中:IO挠性布线基板;ll绝缘基片;12a、 12b、 12c、 12d布线; 12e、 12f虚拟布线;12A、 12B布线区域;13图形过渡区域;20半导体芯片;21a、 21b、 21c焊盘(输出端子);21A、 21B焊盘区域;30各向异性导电膜;40显示装置;40A引出电极;50 PWB。 FIG: IO flexible wiring board; LL insulating substrate; 12a, 12b, 12c, 12d wiring; 12e, 12f virtual wiring; 12A, 12B wiring area; transition region 13 pattern; semiconductor chip 20; 21a, 21b, 21c Welding disc (output terminal); 21A, 21B pad region; anisotropic conductive film 30; 40 a display means; extraction electrode 4OA; 50 PWB.

具体实施方式 detailed description

以下,参照附图说明本发明的实施方式。 The following describes embodiment of the present invention with reference to embodiments. 图3是表示本发明的一实施方式的挠性布线基板的说明图。 FIG 3 is an explanatory view of a flexible wiring board according to an embodiment of the present invention. 挠性布线基板10具有在绝缘基片11 上与半导体芯片的输出端子电连接的规定图形的布线12a、 12b。 The flexible wiring board 10 has a predetermined upper insulating substrate 11 is connected to the output terminal of the semiconductor chip of the wiring patterns 12a, 12b. 并且, and,

形成有由相同形式的布线12a形成了一个图形的第1布线区域12A,形成有由相同形式的布线12b形成了一个图形的第2布线区域12B。 Formed with the first wiring 12a is formed a pattern region 12A of the wiring by the same form, 12b there is formed a second wiring region by a pattern wiring 12B formed in the same form. 作为布线区域12A、 12B,不限于图示的两种形式,只要按照每个不同的布线形式 As the wiring region 12A, 12B, is not limited to the illustrated two forms, as long as each of the different forms in accordance with wirings

形成多个布线区域即可。 Forming a plurality of wiring region can be.

在图示示例中,布线形式的差异是基于布线宽度的布线厚度的差异, 布线12a是宽度较宽的厚布线,布线12b是宽度较窄的薄布线。 In the illustrated example, the wiring form of a wiring thickness difference is the difference based on the wiring width, the wiring 12a is a thick line width wider, narrower width of the wiring 12b is a thin wire. 因此, 在布线区域12A和布线区域12B的相邻部位,根据布线宽度在布线厚度上产生差异,成为在布线的接触面形成有阶梯差t的状态。 Thus, the adjacent region 12A and the wiring portion of the wiring region 12B, a difference in the thickness of the wiring according to the wiring width, there is a state of the step difference t is formed on the contact surface of the wiring.

在这种挠性布线基板10中,在本发明的实施方式中是在布线形式不同的相邻的布线区域12A、 12B之间,形成用于消除因布线形式的差异造成的连接不良的图形过渡区域13。 In this flexible wiring board 10, in the embodiment of the present invention is in the form of different adjacent wirings of the wiring region. 12A, 12B between, for forming transition to eliminate defective connection due to differences in the wiring pattern form caused by 13 area.

作为该图形过渡区域13,在图3所示实施方式中,形成具有比相邻的布线区域12A、 12B的各布线间距P1、 P2都宽的布线间隔P的区域。 Examples of the pattern transition region 13, in the embodiment shown in FIG. 3, a wiring having a wiring region. 12A than the adjacent, 12B each wiring pitch P1, P2 are wide region P interval.

图4表示在这种挠性布线基板10的布线12a、 12b电连接作为半导体芯片20的输出端子的焊盘21a、 21b的半导体芯片安装用挠性布线基板。 FIG. 4 shows the wires 12a, 12b which is electrically connected to the flexible wiring substrate 10 as an output terminal pad of the semiconductor chip 20 of the semiconductor chips 21a, 21b of the flexible wiring substrate is mounted.

此处,半导体芯片20具有大小不同的焊盘21a、 21b,形成由与宽度较宽的焊盘21a相同形式的焊盘形成了一个图形的第1布线区域21A, 并且形成由与宽度较窄的焊盘21b相同形式的焊盘形成了一个图形的第2 布线区域21B。 Here, the semiconductor chip 20 having different sizes of pads 21a, 21b, forming a first wiring pattern region 21A by a wide width in the form of pads 21a of the same pad, and is formed by a narrow width pad 21b form the same pad area is formed a second wiring pattern 21B. 因此,挠性布线基板10的布线12a、 12b的布线形式形成为对应焊盘21a、 21b的大小具有不同的布线宽度的状态。 Thus, the wiring form of a wiring 12a, 12b of the flexible wiring substrate 10 is formed corresponding to the pads 21a, 21b having the size of the wiring width different state. 并且,该布线12a和焊盘21a或布线12b和焊盘21b分别通过各向异性导电膜30相互对接,通过在加热状态下加压并进行热压接。 Then, the wirings 12a and the pad 21a or the wiring 12b and the pad 21b are butted to each other through an anisotropic conductive film 30 by thermocompression bonding under heating and pressure. 另外,此处利用隔着各向异性导电膜30的热压接来进行布线12a和焊盘21a或布线12b和焊盘21b 的电连接,但不限于此,也可以利用共晶接合或环氧树脂接合、金属接合等其他接合来实施电连接。 Further, where using a hot press via an anisotropic conductive film 30 is connected to wiring 12a or the wiring 12b and the pads 21a and 21b are electrically connected to the pad, but is not limited thereto, and may be epoxy or eutectic bonding using resin bonded, metal bonded and other embodiments are electrically connected to joining.

根据该实施方式的挠性布线基板10或在该挠性布线基板10安装了半导体芯片20的半导体芯片安装用挠性布线基板,通过形成上述的图形过渡区域13,使位于相邻部位的布线12a和布线12b形成为相互隔开间 The flexible wiring board 10 of this embodiment or the flexible wiring board 10 is attached to the semiconductor chip 20. The semiconductor chip mounting the flexible wiring substrate, by forming the pattern of the transition region 13, located adjacent to the wiring part 12a and a wiring 12b is formed spaced apart from each other between

隔P,利用该间隔P吸收阶梯差t,所以各布线区域12A、 12B的所有布线12a、 12b可以在没有阶梯差t的影响的情况下与半导体芯片20的焊盘21a、 21b良好连接。 P spacer, using the spacer P absorption step difference t, so that each wiring regions 12A, 12B of all the wiring 12a, 12b can 21a, 21b a good connection to the semiconductor chip pad 20 in the absence of the influence of the case where a step difference t.

图5是表示本发明的其他实施方式的挠性布线基板10或在该挠性布线基板10安装了半导体芯片20的半导体芯片安装用挠性布线基板的说明图。 FIG 5 is an explanatory view 10 or the flexible wiring substrate according to another embodiment of the present invention, the flexible wiring substrate 10 of the semiconductor chip mounted semiconductor chip 20 is mounted by a flexible wiring board. 对和上述实施方式相同的部分赋予相同符号,并省略一部分重复说明。 They are given the same reference numerals and the above-described embodiments the same parts, and redundant description will be omitted portion. 在该实施方式中,使图形过渡区域13成为形成有具有相邻的布线区域12A、 12B的各布线形式的中间形式的布线12c、 12d的区域。 In this embodiment, the transition region 13 be so formed pattern having a region adjacent wirings. 12A, an intermediate form of the wiring form of a wiring 12B 12c, area 12d. 此处, 示出了在图形过渡区域13形成两个布线12c、 12d的示例,但只要至少形成对应焊盘21b的一个布线即可。 Here, an example shows two wirings 12c are formed in the pattern transition region 13, 12d, but as long as a wiring is formed at least corresponding to the lands 21b.

并且,该布线12c、 12d是布线区域12A、 12B的布线12a、 12b的中间形式,所以此处形成宽度和厚度为布线12a和布线12b的中间尺寸的布线。 And, the wirings 12c, 12d. 12A is a wiring area, the wiring 12a, 12b of the intermediate form and 12B, so here a width and a thickness of the wiring line 12a and the intermediate size wire 12b.

根据该实施方式的挠性布线基板10或在该挠性布线基板10安装了半导体芯片20的半导体芯片安装用挠性布线基板,利用形成于图形过渡区域13的中间形式的布线12c、 12d分阶段地吸收阶梯差t的影响,所以各布线区域12A、 12B以及图形过渡区域13的所有布线12a、 12b、 12c、 12d可以在没有阶梯差t的影响的情况下与半导体芯片20的焊盘21a、 21b良好连接。 The flexible wiring board 10 of this embodiment or the flexible wiring board 10 wiring 12c of the semiconductor chips of the semiconductor chip 20 is mounted with a flexible wiring board by pattern formed on the intermediate form of the transition region 13, 12d in the phases absorb the impact of a step difference t, all wiring 13 12a, 12b, 12c, 12d can each wiring pad regions 12A, 12B and the pattern in the transition region did not affect the level difference t of the semiconductor chip 20 in the case 21a, 21b well connected.

图6是表示本发明的其他实施方式的挠性布线基板10或在该挠性布线基板10安装了半导体芯片20的半导体芯片安装用挠性布线基板的说明图。 10 or FIG. 6 is an explanatory view showing another embodiment of the flexible wiring substrate of the embodiment of the present invention, the flexible wiring substrate 10 of the semiconductor chip mounted semiconductor chip 20 is mounted to the flexible wiring substrate. 对和上述实施方式相同的部分赋予相同符号,并省略一部分重复说明。 They are given the same reference numerals and the above-described embodiments the same parts, and redundant description will be omitted portion. 在该实施方式中,使图形过渡区域13成为形成有信号传输中不使用的虚拟布线12e、 12f的区域。 In this embodiment, the transition region 13 becomes a virtual pattern wirings 12e are formed in the transmission signal is not used, 12f region.

即,在半导体芯片20侧形成在形式不同的焊盘区域21A和21B之间不进行布线连接的虚拟端子即焊盘21c,由此使与其对应形成的图形过渡区域13的布线12e、 12f成为虚拟布线。 That is, in the semiconductor chip 20 side is formed in the pad region is not different forms of connection between the wiring 21A and 21B, i.e. the dummy terminal pads 21c, whereby the pattern corresponding to the wiring 12e formed in the transition region 13, 12f becomes a virtual wiring.

根据该实施方式的挠性布线基板10或在该挠性布线基板10安装了半导体芯片20的半导体芯片安装用挠性布线基板,使形成于因阶梯差t的影响容易形成压接不良的图形过渡区域13的虛拟布线12e、 12f和与其对应的焊盘12c处于不使用状态,所以实际使用的各布线区域12A、 12B 的所有布线12a、 12b可以在没有阶梯差t的影响的情况下与半导体芯片20的焊盘21a、 21b良好连接。 The flexible wiring board 10 of this embodiment or the flexible wiring board 10 is attached to the semiconductor chip 20 of the semiconductor chip is mounted by a flexible wiring substrate to the step difference formed in t due to the influence of a transition pattern is easily formed crimping failure dummy wiring region 13 12e, 12f and 12c corresponding pads left unused, so that each wiring region 12A practical use, all of the wiring 12B 12a, 12b may not affect the semiconductor chip in the case where the step difference t the pad 21a 20, 21b a good connection.

下面,说明采用了上述的各实施方式的挠性布线基板10或在该挠性布线基板10安装了半导体芯片20的半导体芯片安装用挠性布线基板的半导体芯片的安装方法。 Next, using the above-described embodiments of the flexible wiring board 10 mounting a semiconductor chip or a semiconductor chip 20 of the semiconductor chip mounting the flexible wiring substrate of the flexible wiring board 10 is installed. 使用所述的各实施方式的挠性布线基板10,使半导体芯片20的焊盘21a、21b的图形与布线区域12A、12B的各布线12a、 12b的图形对应,在布线12a、 12b和焊盘21a、 21b之间隔着各向异性导电膜30,对挠性布线基板10和半导体芯片20进行热压接。 Using each of the flexible wiring board 10 according to the embodiment, the semiconductor chip and the wiring pad pattern region 12A 21a, 21b 20, each corresponding to a wiring pattern 12B 12a, 12b, and the wiring 12a, 12b and the pad 21a, 21b interposed between the anisotropic conductive film 30, on the flexible wiring board 10 and the semiconductor chip 20 by thermocompression bonding.

此时,挠性布线基板10的布线区域12A、 12B的布线图形可以根据半导体芯片20的焊盘图形,利用上述的半添加法或全添加法来形成。 At this time, the wiring region 12A of the flexible wiring substrate 10, the wiring pattern 12B according to the pattern of the semiconductor chip pad 20, formed using the semi-additive method or a full additive method.

并且,象上述的图3或图4所示实施方式的挠性布线基板10那样, 在将图形过渡区域13形成为间隔P的情况下,在形成布线图形时,只要隔开布线形式不同的相邻部位的间隔来形成间隔P即可。 Further, as described above in FIG. 3 or FIG flexible wiring board 10 as the embodiment 4, in the case where the pitch P of the pattern transition region 13 is formed, when forming the wiring pattern, the wiring form as long as the different phases are separated o interval P interval portion can be formed. 此时,半导体芯片20侧的焊盘图形可以根据具有间隔P的布线图形来设计焊盘图形, 或者可以不考虑间隔P来形成焊盘图形自身,使对应间隔P的部位的焊盘成为虚拟端子。 In this case, the land pattern 20 side of the semiconductor chip can be designed according to a wiring pattern having a land pattern pitch P, or spacing P may not consider itself to form a pad pattern, the interval corresponding to the pad portion P becomes the dummy terminal .

另外,象上述的图5所示实施方式的挠性布线基板10那样,在图形过渡区域13形成中间形式的布线12c、 12d的情况下,在形成布线图形 Further, like the above-described embodiment shown in FIG. 5, as the flexible wiring substrate 10, 13 formed in the transition region intermediate the graphic form wirings 12c, 12d of the case, the wiring pattern is formed

时,可以通过在布线形式不同的相邻部位形成中间宽度的掩模图形来形成布线12c、 12d。 , It is possible to form a wiring 12c, 12d forming a mask pattern width of the intermediate portion at the adjacent wirings by different forms.

另外,象上述的图6所示实施方式的挠性布线基板10那样,在图形过渡区域13形成虚拟布线12e、 12f时,可以仅使挠性布线基板10侧的布线图形自身单纯地对应半导体芯片20的焊盘图形来形成。 Further, as the above-described embodiment shown in FIG flexible wiring board 6 as embodiment 10, the transition region 13 is formed in the graphics virtual wirings 12e, 12f time, only the wiring pattern can be made flexible wiring substrate 10 side corresponding to the semiconductor chip itself is simply 20 to form the pad pattern. 通过连接挠性布线基板10和半导体芯片20,形成作为与成为半导体芯片20的虚拟端子的焊盘21c对应的布线的虚拟布线12e、 12f。 Is connected by flexible wiring board 10 and the semiconductor chip 20, it becomes a virtual terminal is formed as a pad 20 of the semiconductor chip 21c corresponding to the virtual routing wirings 12e, 12f.

这种挠性布线基板10侧的布线图形的变更可以通过形成布线图形时的掩模图形的设计来简单进行,所以本发明的实施方式的半导体芯片 This change of the wiring pattern of the flexible wiring substrate 10 side can be simply carried out by forming a mask pattern when the wiring pattern design, the semiconductor chip according to the present embodiment of the invention.

的安装方法与现有技术相比,在成本方面不会产生大的负担。 Compared with the prior art installation, without a large burden in terms of cost.

图7是表示设置有安装了上述实施方式的半导体芯片的挠性布线基板的电子设备的一例的显示装置的俯视图。 FIG 7 is a plan view showing a display is provided with a device according to an example of the electronic apparatus of the flexible wiring substrate according to the embodiment of the semiconductor chip is mounted. 此处,表示将向挠性布线基板10安装了半导体芯片20的半导体芯片安装用挠性布线基板(C0F)连接有机EL显示装置、液晶显示装置(LCD)、电场放射显示装置(FED)、 等离子显示装置(PDP)等的平板显示装置40的一例。 Here, it represents a flexible wiring board 10 will be mounted a semiconductor chip of the semiconductor chip 20 is mounted by a flexible wiring substrate (C0F) connected to an organic EL display device, a liquid crystal display device (LCD), field emission display apparatus (FED), plasma flat panel display devices (PDP), etc. the example of the display device 40. 该半导体芯片安装用挠性布线基板可以连接形成于显示装置40的一边的引出电极40A, 并且可以连接PWB (硬质基板)50等的其他电路部件。 Mounting the semiconductor chip may be connected to the flexible wiring board formed on one side of the lead-out electrodes 40A and a display device 40, and may be connected to a PWB (hard substrate) 50 and the like of other circuit components.

根据这种设置有本实施方式的半导体芯片安装用挠性布线基板的显示装置,在C0F中采用与半导体芯片的焊盘形式相符的挠性布线基板的布线形式,可以高精度地连接各焊盘和布线,所以能够向显示装置提供所设定的没有偏差的驱动电流。 According to such a display device is provided with a flexible wiring board according to the present embodiment, the semiconductor chip is mounted using a wiring form of a flexible wiring substrate consistent with the pad of the semiconductor chip in C0F can be accurately connected to each pad and wiring means for providing a driving current can be set without variation to the display. 由此,特别是在驱动电流的大小直接影响显示性能的有机EL显示装置中,能够获得良好的显示性能。 Thus, in particular, directly affect the display performance of the magnitude of the driving current to the organic EL display device, it is possible to obtain good display performance.

如上所述,根据本发明的实施方式,在向按照每个不同布线形式形成有多个由相同形式的布线形成了一个图形的布线区域的挠性布线基板连接半导体芯片的输出端子时,可以消除布线与输出端子之间的连接不良。 As described above, according to the embodiment of the present invention, at the time of forming a plurality of output terminals of the flexible printed circuit board wiring pattern is connected to a region of the semiconductor chip by a wiring formed in the same form as each of the different forms of the wiring can be eliminated poor connection between the wiring and the output terminal. 并且,针对具有不同大小的输出端子的半导体芯片,通过形成与其相适应的布线图形,可以获得高精度的连接。 Further, for semiconductor chips having different sizes of the output terminal, through a wiring pattern formed adapted thereto, is connected with high precision can be obtained. 另外,由此消除因连接电阻的偏差造成的驱动电流的不均,确保特别是驱动电流的大小直接影响显示性能的有机EL显示装置的良好的显示性能。 Further, thereby eliminating unevenness due to variations in driving current caused by connection resistance, to ensure excellent display performance of the device, particularly the size of the driving current directly affects the display performance of the organic EL display.

Claims (12)

  1. 1.一种半导体芯片安装用挠性布线基板,具有与半导体芯片的输出端子电连接的规定图形的布线,其特征在于, 每种不同布线形式涉及多个由相同形式的所述布线形成一个图形的布线区域,在布线形式不同的相邻的所述布线区域之间,形成用于消除因布线形式的差异造成的连接不良的图形过渡区域, 所述图形过渡区域是具有比相邻的所述布线区域的各布线间距的任一个都宽的布线间隔的区域, 所述布线形式的差异是基于布线宽度的布线厚度的差异。 A semiconductor chip is mounted by a flexible wiring substrate having a predetermined wiring pattern is electrically connected to the output terminal of the semiconductor chip, wherein each of the different forms of directed wirings of the wiring by the same plurality of forming a pattern in the form of wiring region, the wiring area between the wiring form different adjacent transition region pattern is formed for eliminating defective connection due to the difference in the form of the wiring caused by the pattern of the transition area having a ratio of adjacent any region of the wiring of each wiring pitch of a wiring area are widely spaced, the printed wiring form difference is the difference based on the thickness of the wiring width.
  2. 2. 根据权利要求1所述的半导体芯片安装用挠性布线基板,其特征在于,所述半导体芯片具有大小不同的输出端子,所述布线对应所述输出端子的大小,具有不同的布线宽度。 The semiconductor chip according to claim 1 mounted flexible wiring board, wherein the semiconductor chip having an output terminal of different sizes, corresponding to the magnitude of the output terminal wirings having different wiring widths.
  3. 3. —种半导体芯片安装用挠性布线基板,具有与半导体芯片的输出端子电连接的规定图形的布线,其特征在于,每种不同布线形式涉及多个由相同形式的所述布线形成一个图形的布线区域,在布线形式不同的相邻的所述布线区域之间,形成用于消除因布线形式的差异造成的连接不良的图形过渡区域,所述图形过渡区域是至少形成有一个具有相邻的所述布线区域的各布线形式的中间形式的布线的区域,所述布线形式的差异是基于布线宽度的布线厚度的差异。 3. - semiconductor chip is mounted by a flexible wiring substrate having a predetermined wiring pattern is electrically connected to the output terminal of the semiconductor chip, wherein each of the different forms of directed wirings of the wiring by the same plurality of forming a pattern in the form of wiring region, the wiring between the wiring area adjacent different forms, forming a transition region pattern is formed in the transition region pattern for eliminating defective connection due to the difference caused by the wiring in the form of having at least a neighboring form an intermediate region of the wiring of the wiring of the wiring region in the form of the wiring in the form of the difference is the difference in thickness of the wiring on the wiring width.
  4. 4. 根据权利要求3所述的半导体芯片安装用挠性布线基板,其特征在于,所述半导体芯片具有大小不同的输出端子,所述布线对应所述输出端子的大小,具有不同的布线宽度。 The semiconductor chip according to claim 3 mounted flexible wiring board, wherein the semiconductor chip having an output terminal of different sizes, corresponding to the magnitude of the output terminal wirings having different wiring widths.
  5. 5. —种半导体芯片安装用挠性布线基板,具有与半导体芯片的输出端子电连接的规定图形的布线,其特征在于,每种不同布线形式涉及多个由相同形式的所述布线形成一个图形的布线区域,在布线形式不同的相邻的所述布线区域之间,形成用于消除因布线形式的差异造成的连接不良的图形过渡区域, 所述图形过渡区域是形成有在信号传输中不使用的虛拟布线的区域,所述布线形式的差异是基于布线宽度的布线厚度的差异。 5. - semiconductor chip is mounted by a flexible wiring substrate having a predetermined wiring pattern is electrically connected to the output terminal of the semiconductor chip, wherein each of the different forms of directed wirings of the wiring is formed by a plurality of the same pattern in the form of a wiring region between adjacent wirings of different forms of the wiring region, form a transition region connecting pattern for eliminating failure caused due to the difference in the form of wires, the transition region pattern is not formed in the signal transmission region of the virtual wirings used, the difference in a wiring form of a wiring thickness differences based on the wiring width.
  6. 6. 根据权利要求5所述的半导体芯片安装用挠性布线基板,其特征在于,所述半导体芯片具有大小不同的输出端子,所述布线对应所述输出端子的大小,具有不同的布线宽度。 The semiconductor chip as claimed in claim 5, wherein the flexible wiring board is mounted, wherein the semiconductor chip having an output terminal of different sizes, corresponding to the magnitude of the output wiring terminals having different wiring widths.
  7. 7. —种半导体芯片安装方法,通过将半导体芯片的规定图形的输出端子和对应于挠性布线基板的所述输出端子的图形的布线电连接,将所述半导体芯片安装在所述挠性布线基板上,其特征在于,每种不同布线形式涉及多个由相同形式的所述布线形成一个图形的布线区域,使用这些区域,在布线形式不同的相邻的所述布线区域之间, 形成用于消除因布线形式的差异造成的连接不良的图形过渡区域的挠性布线基板,使所述输出端子的图形与所述布线区域的各布线图形相互对应,进行电连接,所述图形过渡区域是具有比相邻的所述布线区域的各布线间距宽的布线间隔的区域,所述布线形式的差异是基于对应所述输出端子的大小而形成的布线宽度的布线厚度的差异。 7. - The method of mounting semiconductor chip, and the wiring is electrically connected by an output terminal of a predetermined pattern of the semiconductor chip corresponding to said flexible wiring board output terminal pattern, the semiconductor chip mounted on the flexible wiring on a substrate, wherein each of the different forms of wiring a plurality of the same wiring region relates to the form of a wiring pattern is formed, the use of these areas, the wiring between the wiring area adjacent different forms, forming the elimination of the flexible wiring board connected to the transition region pattern failure due to the difference in the form of the wiring caused by the respective wiring pattern of the wiring pattern and the output terminal of the region correspond to each other are electrically connected, the transition region is a pattern difference in thickness of the wiring a wiring region having a width wider than each of the wiring pitch of the wiring region adjacent wires spaced form said wiring is formed on the basis of the difference corresponding to the magnitude of the output terminals.
  8. 8. 根据权利要求7所述的半导体芯片安装方法,其特征在于,在所述布线与所述输出端子之间隔着各向异性导电膜进行所述各布线与所述输出端子的电连接。 The semiconductor chip mounting method according to claim 7, wherein, for each of the electrical wiring and the output terminal is connected via the anisotropic conductive film between the wiring and the output terminal.
  9. 9. 一种半导体芯片安装方法,通过将半导体芯片的规定图形的输出端子和对应于挠性布线基板的所述输出端子的图形的布线电连接,将所述半导体芯片安装在所述挠性布线基板上,其特征在于,每种不同布线形式涉及多个由相同形式的所述布线形成一个图形的布线区域,使用这些区域,在布线形式不同的相邻的所述布线区域之间, 形成用于消除因布线形式的差异造成的连接不良的图形过渡区域的挠性布线基板,使所述输出端子的图形与所述布线区域的各布线图形相互对应,进行电连接, 所述图形过渡区域是至少形成有一个具有相邻的所述布线区域的各布线形式的中间形式的布线的区域,所述布线形式的差异是基于对应所述输出端子的大小而形成的布线宽度的布线厚度的差异。 A method of mounting a semiconductor chip, and the wiring is electrically connected by an output terminal of a predetermined pattern of the semiconductor chip corresponding to said flexible wiring board output terminal pattern, the semiconductor chip mounted on the flexible wiring on a substrate, wherein each of the different forms of wiring a plurality of the same wiring region relates to the form of a wiring pattern is formed, the use of these areas, the wiring between the wiring area adjacent different forms, forming the elimination of the flexible wiring board connected to the transition region pattern failure due to the difference in the form of the wiring caused by the respective wiring pattern of the wiring pattern and the output terminal of the region correspond to each other are electrically connected, the transition region is a pattern differences in thickness of the wiring width of the wiring is formed at least in the form of an intermediate form of the wiring of the wiring having a region adjacent to a region of a wiring, the wiring is formed form based on the difference corresponding to the magnitude of the output terminals.
  10. 10.根据权利要求9所述的半导体芯片安装方法,其特征在于,在所述布线与所述输出端子之间隔着各向异性导电膜进行所述各布线与所述输出端子的电连接。 10. A method of mounting a semiconductor chip according to claim 9, wherein, for each of the electrical wiring and the output terminal is connected via the anisotropic conductive film between the wiring and the output terminal.
  11. 11. 一种半导体芯片安装方法,通过将半导体芯片的规定图形的输出端子和对应于挠性布线基板的所述输出端子的图形的布线电连接,将所述半导体芯片安装在所述挠性布线基板上,其特征在于,每种不同布线形式涉及多个由相同形式的所述布线形成一个图形的布线区域,使用这些区域,在布线形式不同的相邻的所述布线区域之间, 形成用于消除因布线形式的差异造成的连接不良的图形过渡区域的挠性布线基板,使所述输出端子的图形与所述布线区域的各布线图形相互对应,进行电连接,所述图形过渡区域是形成有在信号传输中不使用的虚拟布线的区域,所述布线形式的差异是基于对应所述输出端子的大小而形成的布线宽度的布线厚度的差异。 A method of mounting a semiconductor chip, and the wiring is electrically connected by an output terminal of a predetermined pattern of the semiconductor chip corresponding to said flexible wiring board output terminal pattern, the semiconductor chip mounted on the flexible wiring on a substrate, wherein each of the different forms of wiring a plurality of the same wiring region relates to the form of a wiring pattern is formed, the use of these areas, the wiring between the wiring area adjacent different forms, forming the elimination of the flexible wiring board connected to the transition region pattern failure due to the difference in the form of the wiring caused by the respective wiring pattern of the wiring pattern and the output terminal of the region correspond to each other are electrically connected, the transition region is a pattern virtual wiring is not used in a signal transmission area is formed, said wiring is in the form of difference based on the difference of thickness of the wiring corresponding to the wiring of the magnitude of the output terminal width is formed.
  12. 12.根据权利要求ll所述的半导体芯片安装方法,其特征在于,在所述布线与所述输出端子之间隔着各向异性导电膜进行所述各布线与所述输出端子的电连接。 The semiconductor chip mounting method as claimed in claim ll, wherein, for each of the wirings via an anisotropic conductive film between the wiring and the output terminal and the output terminal is electrically connected.
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