CN100455024C - Image compression chip based on image block dynamic division vector quantization algorithm - Google Patents
Image compression chip based on image block dynamic division vector quantization algorithm Download PDFInfo
- Publication number
- CN100455024C CN100455024C CNB2006100428132A CN200610042813A CN100455024C CN 100455024 C CN100455024 C CN 100455024C CN B2006100428132 A CNB2006100428132 A CN B2006100428132A CN 200610042813 A CN200610042813 A CN 200610042813A CN 100455024 C CN100455024 C CN 100455024C
- Authority
- CN
- China
- Prior art keywords
- code book
- address
- control unit
- image
- distortion factor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The present invention relates to an image compression chip based on an image block dynamic division vector quantization algorithm. A PDVQ algorithm is adopted for the chip. The present invention comprises an external memory, a control unit, a data buffer, a sort module, an address encoder for a code book, a code book memory, a distortion calculation unit, a prediction controller, a quantization controller and a value memory, wherein the data buffer is connected with the external memory through a 16-bit data line and is also respectively connected with the distortion calculation unit, the sort module and the control unit through the 16-bit data line; the sort module is connected with the code book memory through the address encoder for a code book; the code book memory is connected with the distortion calculation unit which is respectively connected with the prediction controller and the quantization controller; the control unit is respectively connected with the data buffer, the sort module, the code book memory, the predication controller and the quantization controller; the control unit controls each functional module through an enabling signal, and each functional module reports operation states towards the control unit through a work completion signal.
Description
Technical field
The invention belongs to the compression transmission field of integrated circuit (IC) design technical field and image thereof, be specifically related in VQ (vector quantization) hardware is realized, to the special designs of part Key Circuit, obtain coding rate fast, have higher compression ratios, reduction picture quality higher dynamically divide the image compression chip of vector quantization (PDVQ) algorithm based on image block.
Background technology
Since the eighties in 20th century, people just are devoted to the research of image coding technique, constantly propose new encryption algorithm, and in conjunction with new technology existing algorithm are improved.Eighties of last century nineties, rest image expert group (JointPhotographic Experts Group) proposes digital coding standard---the Joint Photographic Experts Group of many gray scales rest image.Simultaneously, Motion Picture Experts Group (Moving Pictures Experts Group) in conjunction with Joint Photographic Experts Group and H.261 standard international compression standard---the MPEG series standard of moving image is proposed.JPEG expert group combined with wavelet transformed technology again proposes the JPEG2000 standard, has strengthened the code efficiency of rest image greatly.To be people go out to eliminate data redundancy according to the bulk redundancy sexual development of view data these standards is the coding techniques of purpose, therefore is called as first generation video coding technique.Now people invest second generation video coding technique to sight, and its coding techniques takes into full account the visual characteristic of human eye, are purpose to eliminate the video redundancy, and the most representative be exactly the 4th generation moving picture experts group standard MPEG-4 of MPEG.
Though there are various image compression algorithms that image is compressed, but realize that at present image Real Time Compression transmission still will lean on image compression chip, therefore realizing based on the hardware of the compression algorithm of VLSI technology, is a focus of research both at home and abroad, has obtained many achievements in research.As the image compression chip ADV-JP2000 of ADI (ADI) issue, be that first supports the chip of JPEG2000 image compression encoding standard in the world.Domestic also have unit in the research of carrying out this respect, and the problem of studying as Tsing-Hua University's integrated circuit and systems design laboratory based on wavelet transformation " based on the design of the image compression chip system of JPEG2000 " still is in conceptual phase at present.In view of image Compression to civilian especially military significant, be very important so develop the image compression chip of function admirable with independent intellectual property right.And the domestic image compression chip appearance that independent intellectual property right is not also arranged at present, so this is a very urgent job.
In order to popularize the communication system that can transmit the acceptance pattern picture, particularly towards individual's portable equipment, urgent hope can develop a kind of fast operation, be easy to hard-wired compression coding algorithm.
Vector quantization (Vector Quantization, VQ) technology is the data compression technique that grows up a kind of later stage seventies 20th century, method for compressing image based on the VQ technology is the high correlation of utilizing between the adjacent image data, image data sequence grouping with input forms a k dimension space R
kIn a vector, then this vector is quantized only transmission or storage vector address, thereby can improve compression ratio greatly.Compression ratio is big because the VQ technology has, the algorithm characteristic of simple, therefore is very suitable for hardware and realizes.But because the macrooperation amount of the encryption algorithm of vector quantization and high complexity have restricted its application in high speed and real-time coding system.
Summary of the invention
The purpose of this invention is to provide a kind of image compression chip based on image block dynamic division vector quantization algorithm, this chip has higher compression ratio, coding rate is fast, reduction back picture quality is higher.
In order to realize above-mentioned task, the present invention adopts following technical solution:
A kind of image compression chip based on the PDVQ algorithm is characterized in that, this image compression chip comprises:
An external memory storage is used to preserve image to be encoded;
One control unit is used for being responsible for coordinating the normal operation of whole system;
A data buffer is used to deposit 8 * 8 image blocks, and image block comprises the data of current subimage block CV and adjacent sub-images piece DV, RV and RDV;
A sort module is used for current subimage block CV is classified;
A code book address scrambler is used for relative address with sort module output and is converted into code word and calculates in the actual physical address of code book, and the code book memory is exported in code book address as a result;
A code book memory is used for the vector of corresponding address in distortion factor computing unit output code book;
A distortion factor computing unit is used to finish the distortion factor and calculates;
A predictive controller is used to finish prediction;
A quantization controller, the distortion factor and the current minimum distortion degree that are used for obtaining compare, and upgrade the minimum distortion degree, simultaneously record and the corresponding code word of minimum distortion degree address;
One and value memory should be connected with sort module with the value memory;
Data buffer links to each other with external memory storage by 16 position datawires; Data buffer also is connected with distortion factor computing unit, sort module and control unit respectively by 16 position datawires; Sort module is connected with the code book memory by the code book address scrambler, the code book memory links to each other with distortion factor computing unit, distortion factor computing unit links to each other with quantization controller with predictive controller respectively, and control unit links to each other with quantization controller with data buffer, sort module, code book memory, predictive controller respectively; Control unit is controlled each functional module by enable signal, and each functional module is finished signal to the control unit state of reporting by work.
Image compression chip based on dynamic division Vector Quantization algorithm of the present invention, the technique effect that brings is:
(1) if use common VQ technology, when the code book of selecting 1024 for use, compression ratio is 12.8.As can be seen, the compression ratio of PDVQ image encoding is greatly improved, such as: for the image of more details, it is about about 10% that its compression ratio can improve, and reaches 14.22; For medium detail pictures, compression ratio can reach 18.66, has improved about 46%; Effect is apparent that the coding for the less image of details most, and its compression ratio reaches 23.76, has improved about one times.
It can also be seen that simultaneously that (2) when improving compression ratio, the PSNR value just slightly reduces with respect to common VQ, about about 0.3%, therefore guaranteed quality of reconstructed images greatly.By to using the reconstructed image contrast after common VQ and PDVQ encode to standard picture " Peppers ", as can be seen, the visual effect of PDVQ reconstructed image is gratifying.
(3) in addition, the applicant tests the coding rate of PDVQ again, and test environment is P4-1.4GHz, test platform is Matlab6.0, its result is: common VQ carries out once full coding on average needs 67 seconds, and PDVQ only needs about 45 seconds, and speed has improved 30%.This result and prediction result are quite identical.No matter be theory analysis, or experimental result, can the authentication image piece dynamically divide the performance of (PDVQ) technology.The objective of the invention is to make full use of the advantage of this chip, picture quality is not being had under the situation of special requirement, use the PDVQ technology to carry out the VQ coding, reach and improve image compression rate and coding rate, taken into account the raising requirement very little of these performances simultaneously the influence of reconstructed image quality.
Use proof through the applicant, the intended purposes that reaches.
Description of drawings
Fig. 1 is the pie graph of vector quantization image encoding system;
Fig. 2 is the signature of image subblock;
Fig. 3 is a PDVQ image encoding system hardware structure diagram;
Fig. 4 is the partitioned searching circuit structure diagram;
Fig. 5 is a bulk prediction circuit structure chart;
Fig. 6 is the discriminant classification circuit structure diagram;
Fig. 7 is based on and is worth the block research circuit structure diagram;
Fig. 8 is the sorting code number circuit structure diagram.
The explanation of relation between the above-mentioned figure: the circuit structure among Fig. 3 in the frame of broken lines has comprised the partitioned searching circuit of Fig. 4, the discriminant classification circuit of Fig. 6 and Fig. 7 based on value block research circuit structure.
Fig. 4 is the detailed structure that the partitioned searching circuit is realized in the frame of broken lines among Fig. 3.
Fig. 5 is the distortion factor computing unit (Distortion) in the position corresponding diagram 3 of bulk prediction circuit in whole system.
Sort module (Sort) in the position corresponding diagram 3 of Fig. 6 discriminant classification circuit in whole system.
Fig. 7 be among Fig. 3 in the frame of broken lines based on the detailed structure of value block research circuit realization.
Below in conjunction with accompanying drawing the present invention is described in further details.
Embodiment
Image compression chip concrete structure based on image block dynamic division vector quantization algorithm of the present invention is referring to Fig. 3, and this chip comprises external memory storage, control unit, data buffer, sort module, code book address scrambler, code book memory, distortion factor computing unit, predictive controller, quantization controller and value memory; Image to be encoded is kept in the external memory storage, and buffer (Cache) is deposited 8 * 8 image blocks data of (comprising current subimage block CV and adjacent sub-images piece DV, RV and RDV).Data buffer (Cache) links to each other with external memory storage by 16 position datawire data_im, at signal shift_load_n from control unit (Controller), shift_en_n, ram_wr_n, under the ram_oe_n control, its output pixel value is given distortion factor computing unit (distortion) and sort module (Sort).
Be connected between data buffer (Cache) and the distortion factor computing unit (distortion) by 16 position datawire data_cv and data_xv and realize.Transmit the pixel value of current subimage block CV by 16 position datawire data_cv, transmit the pixel value of adjacent sub-images piece DV, RV and RDV by 16 position datawire data_xv.
Be connected by 16 position datawire data_cv_in between data buffer (Cache) and the sort module (Sort), transmit the pixel value of current subimage block CV.
Sort module (Sort) work under from the control of the signal Sort_en of control unit (Controller), after classification was finished, (Controller) returned the Sort_end signal to control unit; Export the reference address addr_top that current subimage block CV is encoded to the code book address scrambler.
The code book address scrambler is according to the reference address addr_top signal of input, finish relative address with sort module output and be converted into the actual physical address of code word in code book and calculate, and code book address addr_cb is as a result exported to code book memory (ROM_CB).
Code book memory (ROM_CB) work under from the control of the signal rom_cb_oe of control unit (Controller), the vector data_cb of corresponding address addr_cb in distortion factor computing unit (distortion) output code book.
Distortion factor computing unit (distortion) is finished the distortion factor and is calculated, and the result is exported to predictive controller (pred_CTR) and quantization controller (encd_CTR) by 12 position datawire distortion.
Predictive controller (pred_CTR) work under from the control of the signal pred_en of control unit (Controller) after prediction is finished, is exported to control unit (Controller) with flag bit signal Flag and prediction end signal pred_end;
Distortion factor computing unit (distortion) all will be worked at forecast period and quantization stage.When subimage block is carried out quantization encoding, distortion factor computing unit (distortion) is according to the pixel value of subimage block to be quantified and carry out the distortion factor from the vector data_cb of code book memory (ROM_CB) and calculate, and the result is exported to quantization controller (encd_CTR) by 12 position datawire distortion.
Quantization controller work under from the control of the signal encd_en of control unit (Controller) according to the distortion factor that obtains, compares with current minimum distortion degree, upgrades the minimum distortion degree, simultaneously record and the corresponding code word of minimum distortion degree address.When quantizing to finish, this module output coupling code word corresponding address sign indicating number addr_match and quantification are finished signal (encd_end), the match address of the common composing images piece of Flag that this address code and forecasting institute produce.
Control unit (Controller) is responsible for coordinating the normal operation of whole system.Control unit by enable signal (_ en) control each functional module, each functional module by work finish signal (_ end) to the control unit state of reporting.
The relatedness computation of image block has adopted the method for distortion measure, thus for whole system except summing circuit commonly used, topmost arithmetic element is exactly distortion factor computing unit (Distortion).Owing to quantize to carry out in the different stages, in hardware system, only need a distortion factor computing unit with relatedness computation.The use of distortion factor computing unit is managed by control unit.When carrying out the image block relatedness computation or quantizing distortion factor computing unit is assigned to predictive controller or quantization controller respectively, other times then make distortion factor module be in idle condition by enable signal, to reduce power consumption.
Its concrete preparation method, carry out in the following manner:
1, by the partitioned searching circuit
In order to eliminate the redundant computation amount of VQ coding, researchers' new code word matching algorithm of design usually replace the exhaustive search algorithm, improve coding rate with this, as multi-stage vector quantization (MVQ), predictive vector quantification (PVQ) etc., and the partitioned searching algorithm that proposes among the design is the higher matching algorithm of a kind of efficient.Can also reach the purpose of eliminating the redundant computation amount by reducing effective image block vector to be encoded in addition.
2, dynamically divide vector quantization (PDVQ) technology and circuit thereof by image block
It is exactly by determining the correlation between the adjacent image piece, only irrelevant image block being carried out quantization encoding, thereby reduced the quantity of efficient coding vector that the image block that proposes among the design is dynamically divided vector quantization (PDVQ) technology.
The PDVQ algorithm is to use at special chip, the fast algorithm of on traditional VQ algorithm basis, developing, its core texture is divided into three parts: the bulk prediction, type identification and based on the value block research.
1. bulk prediction circuit:
Original view data is divided into 8 * 8 image block, these pieces further are divided into 44 * 4 subimage block, calculate the similarity relation between each subimage block, if it is similar, think that this image block of 8 * 8 is level and smooth, only need one of them piece of 4 * 4 is carried out vector quantization coding, the coding result of other each pieces is consistent with it.If unsmooth, then need each sub-piece is all carried out vector quantization coding.
2. discriminant classification circuit:
When being added up, each subimage block of 4 * 4 finds that image exists level, vertical, and the diagonal angle isotropy.Therefore can sort to code book in advance according to this characteristic, when image block is encoded, only need earlier image block to be carried out type identification, can in the code book scope of correspondence, carry out vector matching, dwindle operand so greatly.
3. based on value block research circuit:
When hardware was realized, the vector matching criterion of employing was a norm, and image block and a value and a norm between exist enantiomorphic relationship.This shows: for any image vector, finish after the coupling with codebook vector, that codebook vector of a norm minimum with value often also near image vector and value.So just can be in advance to codebook vector according to sorting with value, be divided into several region.Before carrying out matching operation first computed image piece and value, then to and be worth and carry out matching operation in the immediate zone, can reduce amount of calculation like this.
Above-mentioned three parts comprehensively to together, are reasonably chosen relevant parameter, just constituted the PDVQ algorithm.
3, by the sorting code number circuit
The researcher improves the VQ coding efficiency by the institutional framework of optimizing code book, and the sorting code number algorithm that proposes among the design just is based on the VQ fast coding algorithm that the classification code book proposes.
The present invention will propose the design of complete VQ encoder, and provide the ASIC structure of encoder under 0.35um CMOS technology in conjunction with three kinds of algorithms such as PDVQ, sorting code number algorithm and partitioned searching algorithms.In order to reduce computation complexity, the present invention adopts average absolute value error (MAE) as distortion measure, and this has been proved to be very effective.
The specific implementation process of PDVQ coding is as follows:
1) image block reads.Read one 8 * 8 image block in the image to be encoded from external memory storage, as the target image piece of PDVQ technology.This image block is divided into four number of sub images pieces according to shown in Figure 2, and is converted into a n dimensional vector n, be labeled as shown in the figure respectively: CV, DV, RV and RDV.
2) relatedness computation.Calculate the degree of correlation of CV and DV, RV, RDV respectively, and according to formula (3-1) mark.
3) comparison of the degree of correlation between the subimage block vector and degree of correlation threshold value.The degree of correlation that step (2) is obtained compares with degree of correlation threshold value T respectively, if satisfy relational expression (3-2), then representing 8 * 8 image blocks that read is the associated picture piece, only need carry out vector quantization to CV, and the coding flow process enters step (4); Otherwise, then represent this 8 * 8 image block not satisfy the correlation requirement, need carry out vector quantization to each subimage block vector, the coding flow process enters step (6).
(C
CR＜T)&(C
CD＜T)&(C
CRD＜T)……………(3-2)
3) quantification of associated picture piece.If 8 * 8 images that read are the associated picture piece, then only subimage block vector CV is carried out vector quantization, obtain the match address sign indicating number of CV, and with the address code of this address code as whole 8 * 8 image blocks, promptly the match address sign indicating number of DV, RV and RDV is identical with CV.
4) generation of associated picture piece match address sign indicating number.In order to distinguish, as mentioned above, need additional mark position Flag, so complete match address sign indicating number is shown in formula (3-3) with irrelevant image block.In formula (3-9), the Match_Index representative has added the complete match address sign indicating number behind the flag bit Flag, the match address sign indicating number that the Match_Address representative draws by vector quantization.
Match_Index＝{Flag，Match_Address}………(3-3)
5) quantification of irrelevant image block.If judge that 8 * 8 image blocks that read are irrelevant image block, then need each subimage block vector is carried out vector quantization.PDVQ quantizes the subimage block vector respectively according to the order of CV → DV → RV → RDV, and the match address sign indicating number that obtains is delivered to step (7).
6) generation of irrelevant image block match address sign indicating number.Identical with step (5).Need to prove: for the associated picture piece, Flag is set at ' 0 ', and the code length of match address sign indicating number is 9 bits; For irrelevant image block, Flag is set at ' 1 ', and the code length of match address sign indicating number is 4 * 9 bits.
7) current image block end-of-encode continues to read next 8 * 8 image blocks, and repeating step (1)～(8) are up to the entire image end-of-encode.
Referring to Fig. 4, subimage block x to be encoded, warp and value computing unit calculate and are worth S (x), give and are worth matching unit, obtain mating and be worth corresponding code book piece j most with subimage block and value; Then the code word of this code book piece being exported to the distortion factor calculates and comparing unit; The distortion factor calculate and comparing unit to the subimage block x to be encoded of delayed cell processing and carry out computing from the code word of code book, output is i as a result.
Referring to Fig. 5, the data load unit is under the control from the signal pred_en of PREDICTIVE CONTROL unit, export current subimage block pixel value data_cv and face subimage block pixel value data_xv mutually to distortion factor computing unit, distortion factor computing unit is under the control from the carry signal pixe_carry of PREDICTIVE CONTROL unit, output is calculated intermediate object program data_temp and is added up and comparing unit, obtains final distortion factor value distortion and exports to the PREDICTIVE CONTROL unit.After prediction finished, the flag bit determining unit was exported to final distortions degree value distortion in the PREDICTIVE CONTROL unit, and the flag bit determining unit is determined flag bit flag and output according to the value of predetermined threshold value TH_VALUE and distortion.
Referring to Fig. 6, the data load unit reads in 4 * 4 image blocks (16 pixel values), gives 2 * 2 division unit by data wire In_Data_Bus, obtains 42 * 2 image blocks; Pixel value after 2 * 2 division unit outputs are divided is given and the value computing unit, obtain the pixel value and the In_SB1 of 42 * 2 image blocks respectively, In_SB2, In_SB3, In_SB4 gives subtraction and comparing unit, through subtraction and comparison operation, export 6 group carry signals, Carry23, Carry14, Carry24, Carry13, Carry34, Carry12 give the type determining unit, and the type determining unit is under the control from the classification end signal sort_end of sorting control, according to 6 group carry signals, determine the type out_type and the output of 4 * 4 image blocks of input.
Referring to Fig. 7, image block data data_im to be encoded, give and be worth computing unit, calculate and be worth data_sum and give the reference address determining unit, the reference address determining unit reaches and value data_sum according to the type information type_value of this picture block, information in utilization and the value code book, definite reference address refer_addr with value corresponding code book piece in code book that mate most with value with this image subsection piece also exports.
Referring to Fig. 8, the address updating block to data load unit OPADD addr (signal bit wide 11), is exported to the address determining unit with the least-significant byte of addr simultaneously under the control of the enable signal encd_en that comes the own coding control unit; Data load unit basis is from the code book address signal addr (signal bit wide 11) of the input of address updating block, export the pixel value data_cv of current image block to be encoded and give distortion factor computing unit from the code word data_cb of code book corresponding address addr (signal bit wide 11), distortion factor computing unit send distortion factor comparing unit with result of calculation dist (distortion), obtains repeatedly distortion factor value dist_min minimum in the distortion factor result of calculation and exports to the coding control unit; After end-of-encode, the coding control unit is by changing value from ence_en to the address updating block that send, the address updating block is stopped to data load unit OPADD, simultaneously, the address determining unit is exported the address of the code word of corresponding minimum distortion degree as final coded address addr_match.
Table 1 has provided VQ image encoding system simulation result, and table 2 has provided the PDVQ chip performance parameter that adopts method of the present invention to obtain.
Table 1:VQ image encoding system simulation result
| Image | PSNR(dB) | Compression ratio (CR: 1) | Scramble time (second) |
| Man | 25.85 | 16.38 | 20 |
| Peppers | 27.43 | 17.74 | 17 |
| Airplane | 26.69 | 21.52 | 14 |
| Boats | 26.34 | 19.90 | 15 |
| Lena | 27.73 | 19.19 | 16 |
| Splash | 30.00 | 27.24 | 11 |
Table 2PDVQ chip performance parameter:
| Logic gate | 27704Gates |
| RAM | |
| 16× | |
| ROM | |
| 16 * 2048Bit (classification code book) |
| 20 * 64Bit (feature and value) | |
| Maximum operating frequency | 100MHz@3V |
| Chip size | 2.08×2.08mm |
| Dynamic power consumption | 332mW@3V |
| The leakage current power consumption | 9.01uW@3V |
Claims (2)
1. the image compression chip based on image block dynamic division vector quantization algorithm PDVQ is characterized in that, this image compression chip comprises:
An external memory storage is used to preserve image to be encoded;
One control unit is used for being responsible for coordinating the normal operation of whole system;
A data buffer is used to deposit 8 * 8 image blocks, and image block comprises the data of current subimage block CV and adjacent sub-images piece DV, RV and RDV;
A sort module is used for current subimage block CV is classified;
A code book address scrambler is used for relative address with sort module output and is converted into code word and calculates in the actual physical address of code book, and the code book memory is exported in code book address as a result;
A code book memory is used for the vector of corresponding address in distortion factor computing unit output code book;
A distortion factor computing unit is used to finish the distortion factor and calculates;
A predictive controller is used to finish prediction;
A quantization controller, the distortion factor and the current minimum distortion degree that are used for obtaining compare, and upgrade the minimum distortion degree, simultaneously record and the corresponding code word of minimum distortion degree address;
One and value memory should be connected with sort module with the value memory;
Data buffer links to each other with external memory storage by 16 position datawires; Data buffer also is connected with distortion factor computing unit, sort module and control unit respectively by 16 position datawires; Sort module is connected with the code book memory by the code book address scrambler, the code book memory links to each other with distortion factor computing unit, distortion factor computing unit links to each other with quantization controller with predictive controller respectively, and control unit links to each other with quantization controller with data buffer, sort module, code book memory, predictive controller respectively; Control unit is controlled each functional module by enable signal, and each functional module is finished signal to the control unit state of reporting by work;
Described code book memory is worked under the control from the signal of control unit, the vector of corresponding address in distortion factor computing unit output code book; Distortion factor computing unit is finished the distortion factor and is calculated, and the result is exported to predictive controller and quantization controller by 12 position datawires; Predictive controller is worked under the control from the signal of control unit, after prediction is finished, flag bit signal Flag and prediction end signal is exported to control unit; Distortion factor computing unit all will be worked at forecast period and quantization stage, when subimage block is carried out quantization encoding, distortion factor computing unit is according to the pixel value of subimage block to be quantified and carry out the distortion factor from the vector of code book memory and calculate, and the result is exported to quantization controller by 12 position datawires; Quantization controller is worked under the control from the signal of control unit, according to the distortion factor that obtains, compares with current minimum distortion degree, upgrades the minimum distortion degree, simultaneously record and the corresponding code word of minimum distortion degree address; When quantizing to finish, this module output coupling code word corresponding address sign indicating number and quantification are finished signal, the match address of the common composing images piece of Flag that this address code and forecasting institute produce.
2. the image compression chip based on the PDVQ algorithm as claimed in claim 1, it is characterized in that, described code book address scrambler is according to the reference address signal of input, and the relative address of finishing sort module output is converted into the actual physical address calculating of code word in code book.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100428132A CN100455024C (en) | 2006-05-15 | 2006-05-15 | Image compression chip based on image block dynamic division vector quantization algorithm |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100428132A CN100455024C (en) | 2006-05-15 | 2006-05-15 | Image compression chip based on image block dynamic division vector quantization algorithm |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1878313A CN1878313A (en) | 2006-12-13 |
| CN100455024C true CN100455024C (en) | 2009-01-21 |
Family
ID=37510575
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100428132A Expired - Fee Related CN100455024C (en) | 2006-05-15 | 2006-05-15 | Image compression chip based on image block dynamic division vector quantization algorithm |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100455024C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009127097A1 (en) | 2008-04-16 | 2009-10-22 | Huawei Technologies Co., Ltd. | Method and apparatus of communication |
| CN102025998B (en) * | 2010-12-28 | 2013-05-08 | 重庆邮电大学 | Code book designing method for vector quantization of digital image signal |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5313298A (en) * | 1992-03-05 | 1994-05-17 | Rubin, Bednarek And Associates, Inc. | Video companding method and system |
| EP0765085A2 (en) * | 1995-09-21 | 1997-03-26 | AT&T Corp. | Method and apparatus for image processing using model-based localized quantization |
| CN1332576A (en) * | 2000-09-29 | 2002-01-23 | 深圳市中兴通讯股份有限公司 | Quantization and code stream control method for image compressing transmission |
-
2006
- 2006-05-15 CN CNB2006100428132A patent/CN100455024C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5313298A (en) * | 1992-03-05 | 1994-05-17 | Rubin, Bednarek And Associates, Inc. | Video companding method and system |
| EP0765085A2 (en) * | 1995-09-21 | 1997-03-26 | AT&T Corp. | Method and apparatus for image processing using model-based localized quantization |
| CN1332576A (en) * | 2000-09-29 | 2002-01-23 | 深圳市中兴通讯股份有限公司 | Quantization and code stream control method for image compressing transmission |
Non-Patent Citations (2)
| Title |
|---|
| "基于矢量量化技术的图像编码系统的设计". 马龙文.西安理工大学学位论文. 2005 |
| "基于矢量量化技术的图像编码系统的设计". 马龙文.西安理工大学学位论文. 2005 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1878313A (en) | 2006-12-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Choi et al. | Deep feature compression for collaborative object detection | |
| CN100484247C (en) | Improved block transform and quantization for image and video coding | |
| CN100547615C (en) | Become the encoding scheme of the data stream of graphical model during expression | |
| CN111147862B (en) | End-to-end image compression method based on target coding | |
| CN105374054A (en) | Hyperspectral image compression method based on spatial spectrum characteristics | |
| CN101917622B (en) | 14-bit width image compression hardware coder | |
| CN102215385B (en) | Real-time lossless compression method for image | |
| Tsai et al. | A 6.4 Gbit/s embedded compression codec for memory-efficient applications on advanced-HD specification | |
| CN100455024C (en) | Image compression chip based on image block dynamic division vector quantization algorithm | |
| Zhang et al. | SAR image compression using discretized Gaussian adaptive model and generalized subtractive normalization | |
| CN102082950A (en) | Methods, devices and systems for compressing and decompressing images | |
| Wang et al. | Fractal image coding using SSIM | |
| CN107690069A (en) | A kind of cascade method for video coding of data-driven | |
| CN114386595B (en) | SAR image compression method based on super prior architecture | |
| Wang et al. | A high performance fully pipelined architecture for lossless compression of satellite image | |
| CN102088607A (en) | Memory quotient (MQ) coding method and circuit based on JPEG (joint photographic experts group) 2000 standard | |
| Shin et al. | RL-SPIHT: reinforcement learning-based adaptive selection of compression ratios for 1-D SPIHT algorithm | |
| CN105376578A (en) | Image compression method and device | |
| CN104320661A (en) | Image coding quality predicting method based on difference entropy and structural similarity | |
| Savitri et al. | Digital medical image compression algorithm using adaptive Huffman coding and graph based quantization based on IWT-SVD | |
| CN110349228B (en) | Triangular mesh compression method for data-driven least square prediction | |
| Lu et al. | Image Compression Based on Mean Value Predictive Vector Quantization. | |
| CN113949880A (en) | Extremely-low-bit-rate man-machine collaborative image coding training method and coding and decoding method | |
| Li et al. | Hybrid Implicit Neural Image Compression with Subpixel Context Model and Iterative Pruner | |
| CN109218726A (en) | Laser induced breakdown spectroscopy image damages lossless joint compression method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090121 Termination date: 20110515 |