CN100446124C - Method for detecting information gating signal - Google Patents
Method for detecting information gating signal Download PDFInfo
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- CN100446124C CN100446124C CNB2004100738820A CN200410073882A CN100446124C CN 100446124 C CN100446124 C CN 100446124C CN B2004100738820 A CNB2004100738820 A CN B2004100738820A CN 200410073882 A CN200410073882 A CN 200410073882A CN 100446124 C CN100446124 C CN 100446124C
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Abstract
The present invention relates to a method for detecting data strobe signals. A data receiving unit is used for forecasting the arrival time of data output from a double data rate synchronous dynamic random access memory (DDR SDRAM). At the beginning of operation, a data read program is executed on the DDR SDRAM and the latency time of the reading operation is recorded so as to forecast the arrival time of the preamble parts of the data stroke signals in the follow-up data read operation.
Description
Technical field
The present invention relates to a kind of about detecting double data transfer rate synchronous dynamic random-access memory body (Double Data Rate Synchronous DRAM, the method of output data gating (strobe) signal DDR SDRAM), particularly relate to a kind of during about DDR SDRAM output data, the method for detecting information gating signal.
Background technology
In at present general data processing system (data process system), (Synchronous DRAM, SDRAM) framework often is used in memory cell to synchronous dynamic access/memory body.The running of itself and system synchronization, each data access action is all carried out under the positive edge (rising edge) of system's clock pulse triggers, therefore can more traditional clock pulse independently memory architecture data transfer efficiency faster is provided.
(Double Data Rate, DDR) the SDRAM framework of SDRAM are similar to general SDRAM framework and a new generation is called as the double data transfer rate.But different is, the positive edge of system's clock pulse and negative edge (falling edge) all can trigger a document access action, therefore DDR SDRAM can provide the data that doubles general SDRAM framework transfer efficiency in theory, and the modification that only must make a little on framework gets final product.But along with system's clock pulse constantly promotes, some new problems are also following.
See also shown in Figure 1ly, it reads sequential chart for classic method to the data of DDR SDRAM.Wherein, signal CLK is system's clock pulse, after low logic level (lowlogic level) the enable signal RC that DDR SDRAM is sent a clock pulse is as reading command (read command), and hide (latency) time 102 through one section, data just can appear at data line DQ with the speed of two of clock pulses and go up for reading, can read eight documents in data reading operation of this hypothesis, promptly data D0 is to data D7.When data being provided to data line DQ, DDR SDRAM can provide simultaneously one with data line DQ on data gating (strobe) the signal DQS of data synchronous operation, its each positive edge and negative edge are all represented the arrival of the last document of data line DQ, and the first stroke data D0 on data line DQ prerequisite occurs and supplies preposition (preamble) 104 of low logic level in a clock pulse cycle to be about to arrive with the expression data, and in the end represent that with the low logic level postposition (post amble) 106 in half clock pulse cycle data line DQ goes up the end of data, outside these situations, signal DQS all is in a high impedance (highimpedance between high logic level (high logic level) and low logic level state, HI-Z) state, so information gating signal DQS is a ternary signal.
After DDR SDRAM had returned data and information gating signal DQS, next step was the data on the data line DQ will be received.In general, receiving element can be opened input activation (input enable) signal TNI and receive data line DQ and information gating signal DQS after a period of time that reading command signal RC sends.When input enable signal TNI detecting information gating signal DQS preposition 104 after, the enabled status that can keep high logic level is till rearmounted 106.During the activation of input enable signal TNI, the data receiving element can provide one to read signal ZI in order to doing the control that data receives with the synchronous data of information gating signal DQS, and the data receiving element can read the positive edge of signal ZI and negative edge in data and all the data on the data line DQ be done the action of reading.
But because not equal all factors that institute's memory body module that uses and motherboard connect up in the lifting of system's clock pulse and each product, making latent time 102 non-between different products is certain value, it can change along with the difference of product and product behaviour in service, and related preposition 104 time of occurrences of information gating signal DQS that make also can and then change.And input enable signal TNI is after being to send reading command signal RC on traditional way, promptly the preposition of information gating signal DQS detected through a set time.Make input enable signal TNI detect the high impedance part of information gating signal DQS as if the prolongation because of latent time 102 this moment, can make data read the state that signal ZI produces a unknown (unknow).Again if because of the shortening of latent time 102, input enable signal TNI is detected after missing information gating signal DQS preposition, then can cause missing of data.These situations all can produce the data read error, have seriously reduced the reading efficiency of data.
This shows that above-mentioned existing method obviously still has inconvenience and defective, and demands urgently further being improved.In order to solve the problem that existing method exists, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but does not see always that for a long time suitable design finished by development.
Because the defective that above-mentioned existing method exists, from the above, can the mode that data receiving element detecting information arrives be improved, the preposition of information gating signal captured more accurately, to reduce missing of data, improve the reading efficiency of data reading unit to DDR SDRAM data.
Summary of the invention
The objective of the invention is to, overcome the defective of the method existence of existing detecting information gating signal, and the method for output data arriving signal is provided in a kind of new detecting DDR SDRAM framework.
Another object of the present invention is to, a kind of data method for detecting to DDR SDRAM framework is provided, in order to improve the reading efficiency of data.
A further object of the present invention is, a kind of data method for detecting that is used in the data receiving element is provided, and when using this kind data receiving element receive data in the DDR SDRAM module under various condition, all can keep certain data reading efficiency.
The object of the invention to solve the technical problems realizes by the following technical solutions.The preposition method of a kind of detecting information gating signal according to the present invention's proposition, may further comprise the steps: at first estimate a latent time, may further comprise the steps: when sending a reading command signal, activation one first signal and the state that determines a secondary signal according to the accurate voltage in position and a reference voltage of this information gating signal relatively; When this first signal transfers activation to by disabled, begin to calculate a count value with reference to clock pulse according to one; And when this secondary signal transfers the disabled state to by enabled status, stop to calculate this count value with reference to clock pulse according to this; Resulting count value is this latent time; Then, when sending another reading command signal, according to this latent time with describedly count with reference to clock pulse; When count value equals this latent time, send a signal in order to indicate the preposition of this information gating signal.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The method of aforesaid detecting information gating signal, wherein said reference voltage range is between the low logic level voltage of the high impedance status voltage of this information gating signal and this data gating signal.
The method of aforesaid detecting information gating signal, wherein if the accurate voltage in position of this information gating signal greater than this reference voltage, this secondary signal of disabled then, if the accurate voltage in position of this information gating signal is less than this reference voltage, this secondary signal of activation then.
The method of aforesaid detecting information gating signal, the original state of wherein said first signal are the disabled state, and the original state of this secondary signal is the disabled state.
The method of aforesaid detecting information gating signal, the disabled position of wherein said first signal is accurate for hanging down logic level, and activation position standard is high logic level.
The method of aforesaid detecting information gating signal, the disabled position standard of wherein said secondary signal is high logic level, the activation position is accurate for hanging down logic level.
The method of aforesaid detecting information gating signal, wherein this method is the data that is used to read a double data transfer rate synchronous dynamic random memory body.
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known,, must at the beginning the time, send a data reading command to the memory cell of being formed by DDR SDRAM framework earlier earlier, make memory cell send data in order to reach aforementioned goal of the invention.When the data reading command was sent, the enabling counting device began to count in proper order, stopped counting when waiting to receive the first stroke data of being sent by memory cell, and count value is at this moment stored.After in the data reading operation to same memory cell, utilize this storage values time of arriving of detecting information effectively.
Via as can be known above-mentioned, the invention relates to a kind of method of detecting information gating signal, it is to be used for the data receiving element, be used for predicting time of arrival by double data transfer rate synchronous dynamic random memory body (DoubleData Rate Synchronous Dynamic Random Access Memory, the DDR SDRAM) data of exporting.Operation is initial carries out the data fetch program one time to DDR SDRAM earlier, and (latency) time of hiding that is spent in the middle of this reading operation noted down, be beneficial in the follow-up data reading operation, can be predicted the time of arrival of preposition in the information gating signal (preamble) part.
In sum, the method for the detecting information gating signal that the present invention is special can initially reach in the operation in System Operation, regularly or momentarily carry out, reads the numerical value of latent time with data for updating, continues the data reading efficiency that keeps best; Simultaneously, a kind of data method for detecting that is used in the data receiving element provided by the invention when using this kind data receiving element receive data in the DDRSDRAM module under various condition, all can be kept certain data reading efficiency.It has above-mentioned many advantages and practical value, and in class methods, do not see have similar design to publish or use and really genus innovation, no matter it is all having bigger improvement on method or on the function, have large improvement technically, and produced handy and practical effect, and the method for more existing detecting information gating signal has the multinomial effect of enhancement, thus be suitable for practicality more, and have the extensive value of industry, really be a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of instructions, below with preferred embodiment of the present invention and conjunction with figs. describe in detail as after.
Description of drawings
To be classic method read sequential chart to the data of DDR SDRAM to Fig. 1.
Fig. 2 is the method sequential chart that acquisition data of the present invention reads latent time.
Fig. 3 is the method flow diagram that calculates latent time in the inventive method.
Fig. 4 is a method flow diagram of the present invention.
102: latent time 104: preposition
106: rearmounted 202: latent time
204: signal is born edge 206: the positive edge of signal
208: the positive edge 210 of signal: signal is born edge
212: the positive edge of signal
310:TINDQS signal and ZIX signal are the original state of decapacitation
320: when sending the reading command signal, activation TINDQS signal also begins counting
330: according to the state of reference clock pulse and information gating signal DQS decision ZIX signal
340: when the ZIX signal transfers the decapacitation state to by enabled status, stop counting
350: storing this count value is latent time
410: estimate latent time
420: when sending read command signal, according to beginning counting latent time
430: when gate time equals latent time, send a signal in order to indicate the preposition of information gating signal
CLK: the clock pulse RC of system: reading command signal
DQ: data line DQS: information gating signal
TNI: input enable signal ZI: data reads signal
D0-D7: data TNDQS: signal
ZIX: signal COUNT: counting working storage
PHASE: counting working storage
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, its embodiment of method, method, step, feature and the effect thereof of the detecting information gating signal that foundation the present invention is proposed, describe in detail as after.
From the above, in different information products, when just like CPU (central processing unit) (CentralProcess Unit, during action that data receiving element CPU) reads as data the mnemon of a DDR SRAM framework, the time point of memory cell passback data and information gating signal is might be different and cause the difficulty of data receiving element on the time point of design detecting and reception data.Therefore, in embodiments of the present invention, be will not detect time point to be designed to certain value, but when coming into operation in system, earlier count out and record the latent time that data is read, then according to this count value just deducibility go out time of arrival preposition in data and the information gating signal, detect information gating signal this moment again, after information gating signal being had detecting accurately, can do efficient data to memory cell and read.
See also shown in Figure 2ly, it is the method sequential chart that acquisition data of the present invention reads latent time.As shown in Figure 2, it has described an embodiment of this method, and wherein the effect of system's clock pulse CLK, reading command signal RC, data line DQ and information gating signal DQS and action are all with aforementioned same.And the purpose of this method is the latent time 202 of will the data of counting out reading.
In the present embodiment, at first define a signal TNDQS, it can be high logic level or low logic level enable signal, is high logic level enable signal in this example.When the data access unit produced reading command signal RC, drive signal TNDQS produced the positive edge 208 of activation, and drove the negative edge 210 of generation decapacitation by first positive edge 206 of information gating signal DQS.That is to say, be similar to latent time 202 during the activation of signal TNDQS, but, therefore must define a signal ZIX again because having some between the negative edge 210 of its decapacitation and first positive edge 206 of information gating signal DQS postpones to exist.
Signal ZIX can be high logic level or low logic level enable signal equally, is low logic level enable signal in this example.Signal ZIX is a signal of being controlled by information gating signal DQS and signal TNDQS in principle.When signal TNDQS is the decapacitation state, promptly be in when hanging down logic level, signal ZIX then is the decapacitation state of high logic level.And when signal TNDQS in enabled status, when promptly being in high logic level, signal ZIX is then synchronous with information gating signal DQS.But wherein the high impedance status of information gating signal DQS then can be converted into the decapacitation state of high logic level in signal ZIX, and this program of changing paramount logic level by high impedance status can be utilized and be generally the known voltage comparative approach of this skill person and realized.For example, can utilize a reference voltage and an information gating signal DQS between low logic level voltage and high impedance status voltage to do voltage ratio.Because the voltage when information gating signal DQS is high logic level or high impedance status all can be than reference voltage height, can export a high logic level voltage so suppose this moment, and this high logic level voltage can make just signal ZIX become the decapacitation state of the accurate position of high logic.
As shown in Figure 2, the positive edge 212 of signal ZIX can be close to the first positive edge 206 of information gating signal DQS synchronously.And the positive edge 208 of TNDQS signal activation is to latent time 202 that the data of being during this period of time in the middle of the positive edge 212 of signal ZIX read, so can utilize positive edge 208 to start initial value is that 0 counting working storage COUNT counts in proper order with counting working storage PHASE, utilize positive edge 212 to stop again, and count value breech lock (latch) is being counted working storage COUNT and counted in the working storage PHASE.Wherein, counting working storage COUNT is a counting working storage with the speed counting that doubles the clock pulse CLK of system, counting working storage PHASE then is a counting working storage with the speed counting that is four times in the clock pulse CLK of system, so that higher temporal resolution (resolution) to be provided.Visual demand designs the counting rate of counting working storage in the application of reality, is not limited by present embodiment.At this moment, the numerical value among counting working storage COUNT and the counting working storage PHASE all can be as input enable signal TNI among Fig. 1, the preposition time point foundation of detecting in follow-up data reading operation.For example, after the data receiving element sends out a reading command signal once again, can start a counting working storage identical simultaneously and begin counting with counting working storage COUNT, represent when counting up to the numerical value identical with the storage values of counting working storage COUNT through one period latent time when this counting working storage, just the input of activation at this moment enable signal TNI is to carry out reading of data line DQ and information gating signal DQS.Perhaps, also can start another counting working storage identical and begin counting with counting working storage PHASE, when this counting working storage counted up to the numerical value identical with the storage values of counting working storage PHASE, just activation input enable signal TNI was to carry out reading of data line DQ and information gating signal DQS.By comparison, utilize the foundation of counting working storage PHASE, higher temporal resolution can be provided as detecting.
See also shown in Figure 3ly, it is the method flow diagram that calculates latent time in the inventive method.As shown in Figure 3, in step 310, the state of first initializing signal TINDQS and signal ZIX is an original state.In step 320, when the reading command signal was issued, signal TINDQS was enabled (high logic level), and began counting.In step 330, the logic state that relatively determines signal ZIX according to a logic level voltage and the reference voltage of information gating signal DQS, if this moment is the current potential of information gating signal DQS during greater than reference voltage, then signal ZIX is decapacitation state (a high logic level), if the current potential of information gating signal DQS is during less than reference voltage, then signal ZIX signal is the state (low logic level) of activation.In step 340, when treating that signal ZIX changes into the decapacitation state by activation, stop counting.In step 350, the counting after will stopping to count directly stores, and this count value just is similar to latent time.
See also shown in Figure 4ly, it is a method flow diagram of the present invention.As shown in Figure 4, at first in step 410, earlier memory cell is sent a data reading command, the reading command signal RC as shown in Fig. 1 and Fig. 2, and according to said method obtain one latent time value.Then in step 420 according to latent time value begin to count; In step 430, when gate time equaled to be worth latent time, this moment, signal TIN was enabled, in order to indicate the time point of preposition arrival at last.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (7)
1, the preposition method of a kind of detecting information gating signal is characterized in that it may further comprise the steps:
Estimate a latent time, may further comprise the steps:
When sending a reading command signal, activation one first signal and the state that determines a secondary signal according to the accurate voltage in position and a reference voltage of this information gating signal relatively;
When this first signal transfers activation to by disabled, begin to calculate a count value with reference to clock pulse according to one; And
When this secondary signal transfers the disabled state to by enabled status, stop to calculate this count value with reference to clock pulse according to this;
Resulting count value is this latent time;
When sending another reading command signal, according to this latent time with describedly count with reference to clock pulse; And
When count value equals this latent time, send a signal in order to indicate the preposition of this information gating signal.
2, the preposition method of detecting information gating signal according to claim 1 is characterized in that wherein said reference voltage range is between the low logic level voltage of the high impedance status voltage of this information gating signal and this information gating signal.
3, the preposition method of detecting information gating signal according to claim 2, it is characterized in that wherein if the accurate voltage in position of this information gating signal greater than this reference voltage, this secondary signal of disabled then, if the accurate voltage in position of this information gating signal is less than this reference voltage, this secondary signal of activation then.
4, the preposition method of detecting information gating signal according to claim 1, the original state that it is characterized in that wherein said first signal is the disabled state, the original state of this secondary signal is the disabled state.
5, the preposition method of detecting information gating signal according to claim 1 is characterized in that the disabled position of wherein said first signal is accurate for hanging down logic level, and activation position standard is high logic level.
6, the preposition method of detecting information gating signal according to claim 1 is characterized in that the disabled position standard of wherein said secondary signal is high logic level, and the activation position is accurate for hanging down logic level.
7, the preposition method of detecting information gating signal according to claim 1 is characterized in that this method is the data that is used to read a double data transfer rate synchronous dynamic random memory body.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6198674B1 (en) * | 1998-12-30 | 2001-03-06 | Hyundai Electronics Industries Co., Ltd. | Data strobe signal generator of semiconductor device using toggled pull-up and pull-down signals |
| CN1392464A (en) * | 2002-07-08 | 2003-01-22 | 威盛电子股份有限公司 | Gate signal and parallel data signal output circuit |
| CN1508804A (en) * | 2002-12-10 | 2004-06-30 | ���ǵ�����ʽ���� | Synchronous semiconductor storage device and method for generating output control signal in same |
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- 2004-09-07 CN CNB2004100738820A patent/CN100446124C/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6198674B1 (en) * | 1998-12-30 | 2001-03-06 | Hyundai Electronics Industries Co., Ltd. | Data strobe signal generator of semiconductor device using toggled pull-up and pull-down signals |
| CN1392464A (en) * | 2002-07-08 | 2003-01-22 | 威盛电子股份有限公司 | Gate signal and parallel data signal output circuit |
| CN1508804A (en) * | 2002-12-10 | 2004-06-30 | ���ǵ�����ʽ���� | Synchronous semiconductor storage device and method for generating output control signal in same |
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