CN100437947C

CN100437947C - Method of manufacturing flash memory device

Info

Publication number: CN100437947C
Application number: CNB2006100777222A
Authority: CN
Inventors: 李熙耆
Original assignee: Hynix Semiconductor Inc
Current assignee: SK Hynix Inc
Priority date: 2005-04-22
Filing date: 2006-04-24
Publication date: 2008-11-26
Anticipated expiration: 2026-04-24
Also published as: KR100719695B1; KR20060111380A; CN1851884A

Abstract

The method includes sequentially forming a tunnel oxide film, an oxide film, and a first conductive layer on a semiconductor substrate, infiltrating a first etchant between grains of the first conductive layer to form a plurality of nano-crystal points in the oxide film, removing the first conductive layer using a second etchant, wherein during the process of removing the first conductive layer, portions of the nano-crystal points of the oxide film are removed by the second etchant, thereby forming a plurality of nano-crystal formation holes in the oxide film, filling the plurality of holes with a non-conductive layer to form a plurality of nano-crystals respectively having an isolated shape, sequentially forming a dielectric layer and a second conductive layer on the oxide film including the plurality of nano-crystals, and sequentially patterning the second conductive layer, the dielectric layer, the oxide film including the nano-crystals, and the tunnel oxide film.

Description

The manufacture method of flush memory device

Technical field

The present invention relates to a kind of manufacture method of semiconductor device.More specifically, the present invention relates to a kind of manufacture method of flush memory device.

Background technology

Different with volatile memory spare, even when they are not provided power supply, non-volatile memory device also is configured to stored information.Therefore, the non-volatile memory device such as flush memory device is widely used in file system, storage card, portable unit etc.

Nonvolatile memory device has stacked gate architectures, and wherein tunnel oxide film, floating grid, deielectric-coating and control grid electrode sequentially are stacked on the channel region of Semiconductor substrate.

Nonvolatile memory cell with stacked gate structure can be programmed by injecting hot electron.In other words, high voltage is applied to control grid and between source electrode and drain region, produce electrical potential difference.As a result, in channel region, produce hot electron near drain electrode.These hot electrons need enough energy to overcome the potential barrier of tunnel oxide film and be injected into floating grid.If electronics is injected floating grid, then increased the threshold voltage of transistor (or memory cell).If the voltage that is applied to the control grid is less than the threshold voltage that increases, then transistor remain off and electric current do not flow through the unit.Above process is used to stored information and reads information from non-volatile device.

To be injected into electronics release in the floating grid by F-N tunnelling phenomenon, be stored in canned data in the nonvolatile memory cell with stacked gate architectures thereby can wipe.In other words, source area is applied with high voltage, and control grid electrode and substrate are provided with 0V, and drain electrode is floated.Therefore, produced highfield, caused the F-N tunnelling to take place thus at source area and floating grid.

Because use conducting film to form floating grid, so during storage operation, can near source area, remove nearly all electronics that is injected into floating grid by the F-N tunnelling.

Yet the nonvolatile memory cell with stacking gate electrode structure may have and the relevant problem of electronics maintenance.In other words, keep the information of programming in order to make nonvolatile memory cell, this nonvolatile memory cell must keep being injected into the electronics of floating gate electrode.Yet if be present in tunnel oxide film such as the defective of pin hole, the electronics that is injected into floating grid can be overflowed from defective.Because floating grid is formed by conducting film, so produced significant leakage current by the defective in the tunnel dielectric film.

In addition, because floating grid is formed by conducting film and electronics migration therein freely, so too much electronics can discharge from floating grid during erase operation.

Summary of the invention

The step that comprises of the manufacture method of flush memory device is according to an embodiment of the invention: sequentially form tunnel oxide film, oxidation film and first conductive layer on Semiconductor substrate; Intergranule at first conductive layer permeates first etchant to form a plurality of nanocrystalline points in oxidation film; Use second etchant to remove first conductive layer, wherein during removing the technology of first conductive layer, removed the nanocrystalline point of the oxidation film of part, in oxidation film, form a plurality of nanocrystalline formation hole thus by second etchant; Filling a plurality of holes with non-conductive layer forms to have respectively and isolates a plurality of nanocrystalline of shape; Comprising that order forms the dielectric layer and second conductive layer on a plurality of nanocrystalline oxidation films; And order composition second conductive layer, dielectric layer, comprise nanocrystalline oxidation film and tunnel oxide film.

Description of drawings

Detailed description below when in conjunction with the accompanying drawings, passing through this moment, the advantage of understanding more completely of the present invention and many existence of the present invention will better be understood and more obvious along with becoming, and similar in the accompanying drawings reference marker is represented same or analogous element, wherein:

Fig. 1 to 7 is profiles that the method for making flush memory device according to an embodiment of the invention is shown.

Embodiment

In the following detailed description, only show by way of example and specific one exemplary embodiment of the present invention has been described.As those skilled in the art will recognize that described embodiment can realize with various method, and do not break away from the spirit or scope of the present invention.Therefore, to be considered to be illustrative and nonrestrictive in essence for accompanying drawing and explanation.The similar element of reference number indication that the application is similar in the whole text.

With reference to figure 1, order forms tunnel oxide film 12, oxidation film 14 and has first conducting film 16 of crystal grain G on Semiconductor substrate 10.First conductive layer 16 can be formed by polysilicon.

With reference to figure 2, at etch-back technics or the wet soaking technology of first conductive layer, 16 enterprising enforcements with first etchant, thereby first etchant is in the intergranule infiltration of first conductive layer 16.Therefore, a plurality of nanocrystalline some 14P are formed in the oxidation film 14.During etch-back technics or wet soaking technology, first conductive layer 16 is in given thickness etching and therefore become level and smooth.First etchant can be for comprising the etchant of HF.

With reference to figure 3, use second etchant to remove first conductive layer 16.When removing first conductive layer 16, second etchant continues to permeate between the crystal grain G of first conductive layer 16.Therefore,, and remove by second etchant subsequently,, in oxidation film 14, form a plurality of nanocrystalline formation hole 14H thus up to the top surface exposure of oxidation film 14 with the part expansion of nanocrystalline some 14P.Second etchant can be for comprising the etchant of HF.Because first and second etchants are permeated, thus remove nanocrystalline some 14P rapidly, but first and second etchants also do not have the part of the oxidation film 14 of infiltration to remain unchanged and are not removed.

With reference to figure 4, form therein and form non-conductive layer 18 on the oxidation film 14 of hole 14H.Can use such as the polysilicon of non-doping or the non-conducting material of nitride and form non-conductive layer 18.

With reference to figure 5, (CMP) removes non-conductive layer 18 by chemico-mechanical polishing, up to the top surface exposure of oxidation film 14.Therefore, a plurality of hole 14H fill with non-conductive layer 18, form to have a plurality of nanocrystalline 18N that isolates shape respectively.Nanocrystalline 18N is as floating grid.

With reference to figure 6, order forms the dielectric layer 20 and second conductive layer 22 on the oxidation film 14 that comprises a plurality of nanocrystalline 18N.Second conductive layer 22 can use the material that is used to form the control grid to form.

With reference to figure 7, order composition second conductive layer 22, dielectric layer 20, comprise that the oxidation film 14 of nanocrystalline 18N and tunnel oxide film 22 form gate electrode pattern GP.Carry out the source/drain ion injection technology and come in Semiconductor substrate 10, to form source area 24 and drain region 26.

Thereafter, with describe nonvolatile memory cell according to an embodiment of the invention programming, read and erase operation.

By control grid electrode 22 and source area 24 are applied voltage and with drain region 26 ground connection, can carry out the programming operation of first type.Therefore produced hot electron near the source area 24.

Hot electron needs enough energy to overcome the potential barrier of tunnel oxide film 12 and is injected into a plurality of nanocrystalline 18N near source area 24 then.When hot electron was injected into these nanocrystalline 18N, the threshold voltage of nonvolatile memory cell (Vth) increased.The increase of this threshold voltage can be used to stored information in nonvolatile memory cell.Because nanocrystalline 18N, can not easily move among other nanocrystalline 18N so be injected into the electronics of given nanocrystalline 18N from being separated from each other by oxidation film 14 and dielectric layer 20.

In the present embodiment, use non-conducting material to form nanocrystalline 18N.Therefore, even defective is present near in the tunnel oxide film 12 or dielectric layer 20 of nanocrystalline 18N, also can prevent leakage current.

Except above-mentioned, can use the programming operation of second type this device of programming, it relates to source area 24 and drain region 26 ground connection, and applies voltage for control grid electrode 22 and Semiconductor substrate 10, thereby causes the F-N tunneling effect.This moment, electronics is injected among the nanocrystalline 18N equably by the F-N tunneling effect.Because nanocrystalline 18N is arranged in the oxidation film 14, so, also can prevent leakage current even defective is present in tunnel oxide film 12 or the control grid electrode 22.

By control electrode 22 and drain region 26 are applied voltage and with source area 24 ground connection, can carry out read operation.If hot electron has been injected among the nanocrystalline 18N, the gate voltage (Vg) that is applied to control grid electrode 22 can be lower than the threshold voltage of transistor (or memory cell).If so, then channel current does not flow through the unit that hot electron wherein has been injected into nanocrystalline 18N.This state is interpreted as binary condition " 0 " in the present embodiment.

Yet, if the unit does not have the hot electrons that have been injected in a large number nanocrystalline 18N, because unit or transistorized initial threshold voltage remain unchanged and the gate voltage (Vg) that applies will be higher than initial threshold voltage, so this unit of conducting or transistor.Therefore electric current flows through this unit.This state is interpreted as binary condition " 1 " in the present embodiment.

Use hot hole to inject and to carry out erase operation.In other words, negative voltage is applied to control grid electrode 22 and produces hot hole near source area 24.The voltage that is applied to control grid electrode 22 is pulled through the energy barrier of tunnel oxide film 12 with hot hole, and causes the hole to be injected among the nanocrystalline 18N near source area 24.The hot hole that is injected among the nanocrystalline 18N is compound with the hot electron that has been injected among the nanocrystalline 18N in the past.

Nanocrystalline 18N minimizes the possibility of over-erasure thus from being separated from each other and being formed by non-conducting material.In addition, during the first type programming operation, hot electron be injected near among the nanocrystalline 18N of source area 24 and be maintained at the there.Therefore, the erase operation that on nanocrystalline 18N, can use hot hole to inject near source area 24.

On the other hand, injected the situation (that is, the programming operation of second type) of nanocrystalline 18N equably by the F-N tunnelling, can use the F-N tunnelling to carry out erase operation at electronics.In other words, negative voltage is applied to control grid electrode 22 and positive voltage is applied to Semiconductor substrate 10.Therefore, wipe the electronics that is injected among the nanocrystalline 18N by the electronics that is released among the nanocrystalline 18N.

As mentioned above, according to embodiments of the invention, adopt the nanocrystalline electronics that keeps.Therefore, can avoid or minimize the leakage current that the defective by the existence in tunnel oxide film or the dielectric layer causes.During erase operation, can also minimize the generation of over-erasure.

Though the present invention has been described in conjunction with being considered to one exemplary embodiment at present, be appreciated that the present invention is not limited to disclosed embodiment, but opposite, be intended to cover the various modifications that comprise in the spirit and scope of claim and be equal to setting.

Claims

1, a kind of manufacture method of flush memory device, the step that described method comprises is:

Sequentially on Semiconductor substrate, form tunnel oxide film, oxidation film and comprise first conductive layer of a plurality of crystal grain;

Intergranule at described first conductive layer permeates first etchant to form a plurality of nanocrystalline points in described oxidation film;

Use second etchant to remove described first conductive layer, wherein during the technology of removing described first conductive layer, by the nanocrystalline point of described second etchant removal described oxidation film partly, in described oxidation film, form a plurality of nanocrystalline formation hole thus;

Filling described a plurality of hole with non-conductive layer forms to have respectively and isolates a plurality of nanocrystalline of shape;

Sequentially form the dielectric layer and second conductive layer comprising on described a plurality of nanocrystalline oxidation film; And

Sequentially described second conductive layer of composition, described dielectric layer, comprise described nanocrystalline oxidation film and described tunnel oxide film.

2, the method for claim 1, wherein said first conductive layer is formed by polysilicon.

3, the method for claim 1, wherein said first and second etchants are the etchants that comprise HF.

4, the method for claim 1 wherein by using the etch-back technics or the wet soaking technology of described first etchant, allows the intergranule infiltration of described first etchant at described first conductive layer, thereby has formed a plurality of nanocrystalline points.

5, the method for claim 1, wherein by on described oxidation film, forming non-conductive layer, and on described non-conductive layer, carry out CMP up to the top surface that exposes described oxidation film, thereby form described a plurality of nanocrystallinely, fill described a plurality of hole with described non-conductive layer thus.

6, the method for claim 1 wherein uses the polysilicon of non-doping or nitride to form described non-conductive layer.