CN100428459C - 封装体 - Google Patents

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Publication number
CN100428459C
CN100428459C CNB2005101277239A CN200510127723A CN100428459C CN 100428459 C CN100428459 C CN 100428459C CN B2005101277239 A CNB2005101277239 A CN B2005101277239A CN 200510127723 A CN200510127723 A CN 200510127723A CN 100428459 C CN100428459 C CN 100428459C
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China
Prior art keywords
projection
linear dimension
packaging body
conductive pad
mentioned
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CNB2005101277239A
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CN1835218A (zh
Inventor
卢思维
李新辉
王忠裕
李明机
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Microsoft Technology Licensing LLC
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN1835218A publication Critical patent/CN1835218A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Abstract

本发明提供一种封装体。上述封装体具有：第一导体垫于一半导体基底上；第二导体垫于一封装基底上；以及一凸块连接于上述第一导体垫与上述第二导体垫之间，其中上述凸块与上述第一导体垫具有第一界面，上述第一界面具有第一线性尺寸，而上述凸块与上述第二导体垫具有第二界面，上述第二界面具有第二线性尺寸，上述第一线性尺寸与上述第二线性尺寸的比值为0.7至1.7，上述凸块为实质上无铅、或其铅含量高于80%。本发明所述的封装体，有效的解决了封装领域无铅与高铅软焊料凸块的破裂问题。且不需要使用高强度的底胶材料，而可避免对低介电常数材料造成伤害。

Description

封装体
技术领域
本发明是有关于封装体，特别是关于封装体的凸块结构。
背景技术
一倒装法(filp chip)封装体包含以面朝下的方式经由凸块连接垫与基板连接的电子元件，上述基板为陶瓷基板、电路板、或载体(carrier)等等。倒装法封装正快速地取代传统以面朝上的方式经由焊线连接的封装方式。
上述用于倒装法封装的电子元件大多数为半导体元件，然而其他元件例如无源滤波器(passive filter)、侦测器阵列(detectorarrays)、与存储元件等亦适用于倒装法封装的技术。与其他的封装技术相比，倒装法封装的优点在于具有较高速的电性表现。焊线的移除减少了因线路中的电感与电容所造成的信号延迟，且实质上缩减了传递路径，而增加了晶片外的传递速度。
倒装法封装亦提供了较坚固耐用的结构。当使用环氧树脂等底胶充填(underfill)的结构时，倒装法封装可通过严苛的可靠度试验。另外在自动化量产时，倒装法封装可以是成本最低廉的连接方式。
在倒装法封装中，是将软焊料(solder)材质的凸块置于一硅晶片上，而使用软焊料凸块的倒装法封装制程通常包含以下步骤：
(1)提供上述晶片；
(2)将软焊料凸块形成或置于上述晶片上；
(3)将上述晶片装于一电路板、基板、或载体上；
(4)形成底胶充填的粘结物而完成封装。
倒装法封装体中的凸块可提供下列功能：
(1)作为晶片与基板之间电性连接的路径；
(2)将热量自晶片传导至基板；
(3)作为晶片与基板之间缓冲应变(strain)的结构。
软焊料凸块常常使用铅与锡的共晶(eutectic)合金，通常含63％的锡与37％的铅，其具有合适的熔点与较低的阻值。
铅为一种有毒物质，因为法令的规范与业界的需求，而需要无铅凸块。在业界供应链中的企业正积极地寻求锡-铅软焊料的替代品。然而，常见的无铅软焊料例如锡-银、锡-银-铜及其介金属组成物的脆性过高，而会有破裂的问题。另一方面，在高电迁移(electro-migration)效能的应用方面，业界又有高铅凸块的需求。在凸块中加入铅可增加抗蚀性、降低纯锡的再流焊(reflow)温度、与降低纯锡的表面张力等作用。高铅凸块亦有高脆性、且易于破裂的问题。
导致凸块破裂的原因通常是应力的作用。在封装体中引发应力的主要原因之一，在于其组成之间热膨胀系数的不匹配(mismatch)。例如，硅基底的热膨胀系数通常大于3ppm/℃、低介电常数介电质的热膨胀系数通常大于20ppm/℃、而封装基底的热膨胀系数通常大于17ppm/℃。热膨胀系数的显著差异将会因温度的变化，在结构中引发应力。解决上述问题的一个选项，在于使用底胶填充的制程，将液态的环氧树脂注入晶片的一侧或两侧，以将晶片与封装基底之间的空隙填满。环氧树脂的底胶可帮助应力的分散，并对凸块提供保护。
因为低介电常数介电质已广泛用于集成电路制程中，而在保护凸块与低介电常数介电质的使用上，则面临无法两全的困境。对凸块提供保护时，需要高强度的底胶，但是低介电常数介电质却会因高强度底胶的使用而产生伤害，造成低介电常数介电质脱层(delamination)等问题。
因此，在使用低介电常数介电质时，必须保护无铅与高铅凸块，又不能使用高强度的底胶。现有的针对凸块破裂问题的解决方案，是聚焦于材料方面。因此，从结构的考量寻求解答才是有价值的解决方案。
发明内容
有鉴于此，本发明的主要目的是提供一种封装体，其具有较佳的抗凸块破裂问题的结构。
为达成本发明的上述目的，本发明是提供一种封装体，包含：第一导体垫于一半导体基底上；第二导体垫于一封装基底上；以及一实质上无铅的凸块(bump)连接于上述第一导体垫(pad)与上述第二导体垫之间，其中上述凸块与上述第一导体垫具有第一界面，上述第一界面具有第一线性尺寸(linear dimension)，而上述凸块与上述第二导体垫具有第二界面，上述第二界面具有第二线性尺寸，上述第一线性尺寸与上述第二线性尺寸的比值为0.7～1.7。
本发明是又提供一种封装体，包含：第一导体垫于一半导体基底上；第二导体垫于一封装基底上；以及一实质上高铅含量的凸块连接于上述半导体基底与上述封装基底之间，其中上述凸块与上述第一导体垫具有第一界面，上述第一界面具有第一线性尺寸，而上述凸块与上述第二导体垫具有第二界面，上述第二界面具有第二线性尺寸，上述第一线性尺寸与上述第二线性尺寸的比值为0.7～1.7。
本发明是提供一种封装体，包含：具第一线性尺寸的接触垫于一半导体基底上；具第二线性尺寸的凸块连接垫于一封装基底上，其中上述第一线性尺寸与上述第二线性尺寸的比值为0.7～1.7；以及一铅含量低于5％的凸块(bump)连接上述接触垫与上述凸块垫之间。
本发明是提供一种封装体，包含：具第一线性尺寸的接触垫于一半导体基底上；具第二线性尺寸的凸块连接垫于一封装基底上，其中上述第一线性尺寸与上述第二线性尺寸的比值为0.7～1.7；以及一铅含量高于80％的凸块(bump)连接上述接触垫与上述凸块垫之间。
本发明是这样实现的：
本发明提供一种封装体，所述封装体包含：一第一导体垫于一半导体基底上；一第二导体垫于一封装基底上；以及一凸块连接于该第一导体垫与该第二导体垫之间，其中该凸块与该第一导体垫具有一第一界面，该第一界面具有第一线性尺寸，而该凸块与该第二导体垫具有一第二界面，该第二界面具有第二线性尺寸，该第一线性尺寸与该第二线性尺寸的比值为0.7至1.7。
本发明所述的封装体，半导体基底包含至少一低介电常数介电层，其介电常数小于3.3。
本发明所述的封装体，该凸块的铅含量低于5％。
本发明所述的封装体，该凸块的铅含量高于80％。
本发明所述的封装体，该第一线性尺寸与该第二线性尺寸的比值为0.8至1.5。
本发明所述的封装体，该第二导体垫包含铜、铝、或上述的组合。
本发明所述的封装体，该第二导体垫为一保护层，包含镍、金、或上述的组合。
本发明所述的封装体，该第一线性尺寸及该第二线性尺寸均为30至200μm。
本发明所述的封装体，该凸块的高度为30至200μm，且该凸块的高度与该第一线性尺寸的比值为0.5至1，该凸块的高度与第二线性尺寸的比值为0.5至1。
本发明所述的封装体，该第一导体垫为凸点下金属层。
本发明所述的封装体，有效的解决了封装领域无铅与高铅软焊料凸块的破裂问题。且本发明所提供的解决方案，可相容于现有生产线的制程与其他条件，而不会额外衍生其他的副作用或额外的成本负担。另外，本发明不需要使用高强度的底胶材料，而可避免对低介电常数材料造成伤害。
附图说明
图1为一剖面图，是显示具有软焊料凸块的晶片；
图2为一剖面图，是显示一封装基底；
图3为一系列的剖面图，是显示本发明较佳实施例的封装体；
图4为一系列的剖面图，是显示本发明另一较佳实施例的封装体。
具体实施方式
为了让本发明的上述和其他目的、特征和优点能更明显易懂，下文特举数个较佳实施例，并配合所附图示，作详细说明如下：
本发明较佳实施例的封装体中，是使用无铅或高铅含量(以下称“高铅”)的凸块，请参考图1至图4所示。
在本实施例中，软焊料凸块是形成于具有集成电路的晶片上；但是亦可形成于封装基底上。请参考图1，半导体基底2具有形成于一导体垫上的软焊料凸块10，上述导体垫即为图中的凸点下金属层(under bump metallurgy；UBM)8。有时半导体基底2为一晶片。半导体基底2较好为包含低强度的低介电常数介电质，半导体基底2中至少一低介电常数介电层的介电常数较好为低于3.3。一保护层4，较好为介电材料例如氮化物、氧化物、聚酰亚胺(polyimide)、或其他性质相近的材料，是形成于半导体基底2的表面上。接触垫6是电性连接于半导体基底2内的集成电路(未绘示)，较好为铜、铝、铝铜合金、或其他性质相近的材料。一凸点下金属层8为一导体垫，较好为形成于接触垫6上。凸点下金属层8可在接触垫6与凸块10之间提供良好的接着强度，其通常具有复合的多层结构，并可作为一扩散阻障层、软焊料润湿层、或氧化阻障层，其形成方法例如为溅镀、蒸镀、电镀、或其他方法。多层结构的凸点下金属层8是依序沉积而形成的，其最上层的润湿层通常为一导体材料例如铜、镍、钯、或上述的合金。凸点下金属层8的形状通常为正方形或长方形。凸点下金属层8的最宽值，以下称为其线性尺寸W1，较好为30～200μm，更好为约100μm。“线性尺寸”一辞的使用，并不使凸块接触垫或凸点下金属层的形状限制于正方形与长方形，而可以是任何形状。“线性尺寸”可以是圆的直径。一晶片通常具有多个接触垫与凸点下金属层，其间距或是凸块10之间的距离较好为100～300μm，更好为150～250μm。
沉积凸点下金属层8之后，将软焊料凸块10形成于凸点下金属层8上，其形成方法可以是蒸镀、溅镀、网印法、或植球等方法。软焊料凸块10的材质并无特别限制，而本发明的封装体特别适用于无铅或高铅材质的软焊料凸块10。无铅的软焊料凸块10可包含锡、银、或选择性地加入铜，例如为95％～97％的锡、3％～4％的银、与0.5％～1.5％的铜。另一方面，“无铅”的软焊料凸块10可定义为铅含量小于5％的软焊料凸块。高铅的软焊料凸块10可包含95％～97％的铅、3％～5％的锡，而较好为约95％的铅与5％的锡。另一方面，“高铅”的软焊料凸块10可定义为铅含量大于80％的软焊料凸块。
图2是显示一封装基底12。封装基底12的形成材料较好为聚合物、陶瓷、与印刷电路。凸块接触垫16较好为包含铜、铝、或铝铜合金。形成于封装基底12上的防焊层14是用以防止软焊料粘着于封装基底12中不能粘着软焊料的部分。防焊层开口24是形成于防焊层14中，用以暴露凸块接触垫16。防焊层开口24较好为正方形或长方形，其最宽值，以下称为其线性尺寸W2，较好为30～200μm，更好为约100μm。保护层18为一导体垫，可视需要形成于凸块接触垫16上。保护层18的厚度较好为100～10000
Figure C20051012772300091
而其材质较好为镍、金、或其合金。导线22是用以电性连接凸块接触垫16与另一凸块接触垫20，凸块接触垫20的作用容后再述。
将图1所示的半导体基底2与图2所示的封装基底12予以组装后，形成图3所示的封装体23，半导体基底2是为面朝下的状态。在将二者结合之前，是将助焊剂(flux)置于半导体基底2或封装基底12上，然后将软焊料凸块10再流焊(reflow)，作为两导体垫之间的接合物。在一较佳实施例中，上述两导体垫分别为凸点下金属层8与凸块接触垫16，亦可以是凸点下金属层8与保护层18。
上述再流焊处理是改变软焊料凸块10的形状，其最宽值，以下称为线性尺寸Wm较好为100～300μm，其高度H与线性尺寸Wm的比值较好为0.5～1.0。软焊料凸块10与凸点下金属层8之间的上界面26的大小通常为凸点下金属层8的大小所定义；软焊料凸块10与保护层18之间的下界面28的大小通常为防焊层开口24的大小所定义。上界面26与下界面28的大小实质不同时，软焊料凸块10呈非均衡的状态。非均衡状态的软焊料凸块10在尺寸较小的一端(上界面26或下界面28)会有较大的应力，而使其有较大的破裂倾向。因此，软焊料凸块10较好为呈现均衡的状态，亦即是凸点下金属层8的W1值实质上近似于防焊层开口的W2值。W1/W2的比值较好为0.7～1.7，更好为0.8～1.5，又更好为0.9～1.3。在软焊料凸块10的再流焊之后，介金属化合物(inter-metallic components)(未绘示)会形成于上界面26与下界面28。
使用有机基底形成具高铅凸块的封装体时，较好为形成一前软焊料(pre-solder)层。图4为是显示本发明另一较佳实施例的封装体，其中一前软焊料层36是形成于软焊料凸块10与凸块接触垫16上。前软焊料层36较好为共晶材料，例如63％的锡和37％的铅的合金或其他性质相近的材料。因此，软焊料凸块10的下界面的尺寸，通常为前软焊料层36的大小所定义。如前所述，前软焊料层36的线性尺寸W2较好为30～200μm，更好为约100μm。为了使软焊料凸块10呈现均衡状态以减少上界面26或下界面28的应力，W1/W2的比值较好为0.7～1.7，更好为0.8～1.5，又更好为0.9～1.3。
请再参考图3，封装基底12通常为层状结构。软焊料凸块10是经由封装基底12内的导线22电性连接于多个球栅阵列(ballgrid array；BGA)的球状接点30的其中之一。球状接点30是形成于封装基底12下，而用以将半导体基底2中的集成电路(未绘示)连接至一外部元件例如为一印刷电路板40。球状接点30较好为无铅材质，且为铅含量低于5％的软焊料。而球状接点30亦可以是锡铅的共晶合金。
低介电常数材料是广泛地用于集成电路中，作为层间介电层。低介电常数材料通常为低强度，且有些低介电常数材料为多孔质，因此会很容易受到伤害或发生脱层(delamination)，特别是与其他高强度的材料一起使用时。在半导体基底2中使用低介电常数材料会限制高强度底胶材料的使用，而减少对软焊料凸块10的保护，而使无铅与高铅的软焊料凸块及其介金属化合物易于破裂。在使用现有呈现非均衡状态的软焊料凸块时，已发现在可靠度试验中，有相当程度数量的样本无法通过热循环的试验，裂缝通常形成于软焊料凸块中，接近界面尺寸较小一端之处。使用不恰当的底胶材料时，亦会因低介电常数材料的脱层或底胶材料的脱层，而无法通过可靠度试验。而本发明的封装体，其具有均衡状态的软焊料凸块10，其在可靠度试验的表现中，有显著的改善，所有的样本都通过热循环试验。
在上述本发明的较佳实施例中，是在封装的领域针对无铅与高铅软焊料凸块的破裂问题，提供了有效的解决方案。相对于现有技术存在着无铅与高铅软焊料凸块易于破裂的问题，本发明的结果是显示本发明的软焊料凸块10，其具有均衡的尺寸，而不会有上述易于破裂的问题。而且本发明所提供的解决方案，可相容于现有生产线的制程与其他条件，而不会额外衍生其他的副作用或额外的成本负担。通过本发明所提供的解决方案，不需要使用高强度的底胶材料，而可避免对低介电常数材料造成伤害。
虽然本发明已通过较佳实施例说明如上，但该较佳实施例并非用以限定本发明。本领域的技术人员，在不脱离本发明的精神和范围内，应有能力对该较佳实施例做出各种更改和补充，因此本发明的保护范围以权利要求书的范围为准。
附图中符号的简单说明如下：
2：半导体基底
4：保护层
6：接触垫
8：凸点下金属层
10：软焊料凸块
12：封装基底
14：防焊层
16：凸块接触垫
18：保护层
20：凸块接触垫
22：导线
23：封装体
24：防焊层开口
26：上界面
28：下界面
30：球状接点
36：前软焊料层
40：印刷电路板
H：高度
W1：线性尺寸
W2：线性尺寸
Wm：线性尺寸

Claims (10)

1.一种封装体，其特征在于，所述封装体包含：
一第一导体垫于一半导体基底上；
一第二导体垫于一封装基底上；以及
一凸块连接于该第一导体垫与该第二导体垫之间，其中该凸块与该第一导体垫具有一第一界面，该第一界面具有第一线性尺寸，而该凸块与该第二导体垫具有一第二界面，该第二界面具有第二线性尺寸，该第一线性尺寸与该第二线性尺寸的比值为0.7至1.7。
2.根据权利要求1所述的封装体，其特征在于，半导体基底包含至少一低介电常数介电层，其介电常数小于3.3。
3.根据权利要求1所述的封装体，其特征在于，该凸块的铅含量低于5％。
4.根据权利要求1所述的封装体，其特征在于，该凸块的铅含量高于80％。
5.根据权利要求1所述的封装体，其特征在于，该第一线性尺寸与该第二线性尺寸的比值为0.8至1.5。
6.根据权利要求1所述的封装体，其特征在于，该第二导体垫包含铜、铝、或上述的组合。
7.根据权利要求1所述的封装体，其特征在于，该第二导体垫为一保护层，包含镍、金、或上述的组合。
8.根据权利要求1所述的封装体，其特征在于，该第一线性尺寸及该第二线性尺寸均为30至200μm。
9.根据权利要求1所述的封装体，其特征在于，该凸块的高度为30至200μm，且该凸块的高度与该第一线性尺寸的比值为0.5至1，该凸块的高度与第二线性尺寸的比值为0.5至1。
10.根据权利要求1所述的封装体，其特征在于，该第一导体垫为凸点下金属层。
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