CN100426271C - Serial peripheral interface control device, system and determining method thereof - Google Patents
Serial peripheral interface control device, system and determining method thereof Download PDFInfo
- Publication number
- CN100426271C CN100426271C CNB2006101707814A CN200610170781A CN100426271C CN 100426271 C CN100426271 C CN 100426271C CN B2006101707814 A CNB2006101707814 A CN B2006101707814A CN 200610170781 A CN200610170781 A CN 200610170781A CN 100426271 C CN100426271 C CN 100426271C
- Authority
- CN
- China
- Prior art keywords
- peripheral interface
- high speed
- interface device
- string
- instruction fetch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Stored Programmes (AREA)
Abstract
The invention provides a serial peripheral interface control device, system and method of judgment. The serial peripheral interface system consists of serial peripheral interface controller and serial peripheral interface devices. The controller is used to respond the driving signal from south bridge to provide read instructions, which are high speed read instructions. The device stores pre-defined data in determined address, and responds read instructions to output the data to serial peripheral interface control devices. During this period, the serial peripheral interface control device can judge whether the output data is essentially equal to the pre-stored data. If so, the serial peripheral interface control device provides high speed read instructions to access serial peripheral interface device.
Description
Technical field
The invention relates to a kind of serial circumference interface (Serial PeripheralInterface, SPI) system, and particularly whether support the serial circumference interface system of high speed reads instruction fetch (Fast Read Command) form relevant for a kind of string peripheral interface device of detecting wherein.
Background technology
Please refer to Fig. 1, it illustrates is the calcspar of conventional serial perimeter interface system.(Serial Peripheral Interface, SPI) system 100 is applied to computer system to serial circumference interface.When computer system power-on, the reading command CMDR that the south bridge of SPI control device 110 receiving computer systems (South Bridge) chip produces, and it is write control working storage (Control Register) 112.Control working storage 112 afterwards and export reading command CMDR to SPI device 120 reading its data via logical circuit 114, and output output data SD.Wherein, SPI device 120 for example is a flash ROM (FlashRom), data wherein for example are Basic Input or Output System (BIOS) (the BasicInput Output System of computer system, BIOS) procedure code, and reading command CMDR is the instruction for reading command (Read Command) form.Yet SPI system 100 has some problems.
Because SPI control device 110 adopts the hardware structure of control working storages, it needs to read data in the SPI device 120 via the numerous and diverse control working storage 112 of controlled step.So, will make the data read usefulness of SPI system 100 reduce.And if desire to make SPI control device 110 can support high speed reads instruction fetch (Fast Read Command) form, promote the data read usefulness that reads SPI device 120, then need in control working storage 112, to increase extra working storage and support high speed reads instruction fetch form, and the bios program sign indicating number in the SPI device 120 also need carry out extra design and supports high speed reads instruction fetch form.So will make the big and bios program sign indicating number exploitation difficulty of area of control working storage 112, and cause the cost of traditional SPI system 100 higher.
In addition, because SPI control device 110 can't judge with the SPI device 120 of its collocation whether support high speed reads instruction fetch form, thereby traditional SPI control device more than 110 need are controlled SPI device 120 with its collocation with supportive higher reading command when computer system power-on.Via operator's manual adjustment SPI control device 110 after computer system power-on finishes it be diverted via by the high speed reads instruction fetch afterwards and control SPI device 120.So, SPI control system 100 has more the comparatively loaded down with trivial details shortcoming of operation steps that can't control SPI device 120 and operator before computer system power-on is finished via the high speed reads instruction fetch.
Summary of the invention
In view of this, the present invention provides a kind of serial circumference interface (SerialPeripheral Interface, SPI) system and judge whether the SPI device supports the method for high speed reads instruction fetch form, it has, and the read performance of SPI system is higher, the bios program sign indicating number change less, can judge whether the SPI device is supported high speed reads instruction fetch form and can be when computer system power-on be read SPI device, area is less and operator's operation steps is comparatively simplified advantage via the high speed reads instruction fetch.
The present invention proposes a kind of SPI control device, be applied to a computer system, (Serial Peripheral Interface, SPI) control device reads in the SPI device via this serial circumference interface and the South Bridge chip of computer system (South Bridge) is in order to provide drive signal.The SPI control device comprises solidus device, logical circuit and control working storage.The solidus device provides reading command in response to drive signal, and it is to be high speed reads instruction fetch (Fast Read Command).Logical circuit and SPI device couple, in order to read the SPI device in response to reading command.The control working storage receives the instruction that writes that this South Bridge chip provides, and according to this SPI device is carried out the operation that data write.Wherein, South Bridge chip is to read the SPI device via the SPI control device in the mode of direct memory access (Memory Access Direct).
The present invention proposes a kind of SPI system, is applied to computer system, and the south bridge of computer system (South Bridge) chip is in order to provide drive signal.The SPI system comprises SPI device and SPI control device.SPI is installed on presumptive address and stores tentation data, and the SPI device is exported output data in response to reading command.The SPI control device reads the tentation data of the presumptive address that is stored in the SPI device in order to provide reading command in response to drive signal, and reading command is high speed reads instruction fetch (Fast Read Command) form.Wherein, the SPI control device is more in order to receive and to judge whether output data equals tentation data in fact, represents that when output data equals tentation data in fact the SPI device can support high speed reads instruction fetch form.So, the SPI control device provides the instruction of high speed reads instruction fetch form to read the SPI device.
The present invention proposes a kind of determination methods of SPI device, and it is to comprise following step.At first, provide SPI device, the presumptive address of this SPI device has tentation data.Then, provide reading command to the SPI device, reading command is high speed reads instruction fetch (Fast ReadCommand).Then, the SPI device is in response to high speed reads instruction fetch output output data.Then, judge whether output data equals tentation data.Afterwards, when output data equaled tentation data, expression SPI device was supported high speed reads instruction fetch form.So, provide the high speed reads instruction fetch to read the SPI device.When output data was not equal to tentation data, expression SPI device was not supported high speed reads instruction fetch form.
The determination methods of serial peripheral interface control device of the present invention, system and control device, can improve tradition can support the SPI control device of high speed reads instruction fetch form that the higher working storage of quantity need be set effectively and cause that area is big, the bios program sign indicating number need carry out extra particular design and the higher shortcoming of cost, area is little, the bios program sign indicating number need not design or change and lower-cost advantage especially and have in fact.
Description of drawings
It is the calcspar of conventional serial perimeter interface system that Fig. 1 illustrates.
Fig. 2 illustrates the calcspar according to the serial circumference interface system of a preferred embodiment of the present invention.
It is the detailed block diagram of SPI control device 21 among Fig. 2 that Fig. 3 illustrates.
It is the detailed circuit diagram of solidus device 23 among Fig. 3 that Fig. 4 illustrates.
It is whether the SPI device of judging of present embodiment supports the process flow diagram of the method for high speed reads instruction fetch form that Fig. 5 illustrates.
Embodiment
For foregoing of the present invention can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Serial circumference interface of the present invention (Serial Peripheral Interface, SPI) system is provided with a solidus device, with the instruction of output high speed reads instruction fetch (Fast ReadCommand) form, judge whether the SPI device is supported high speed reads instruction fetch form and can the method with direct memory access (Memory AccessDirect) be read the SPI device via its hardware paths.
Please refer to Fig. 2, it illustrates the calcspar according to the serial circumference interface system of a preferred embodiment of the present invention.SPI system 20 comprises: SPI control device 21 and SPI device 22.SPI system 20 for example designs in computer system (not illustrating), for example (Peripheral ComponentInterconnect, PCI) bus 30 is connected with south bridge (South Bridge) chip (not illustrating) of computer system SPI control device 21 via Peripheral Component Interconnect.
When computer system power-on, computer system provides drive signal SA to SPI system 20 via South Bridge chip, reads SPI device 22.SPI device 22 stores a tentation data in its a presumptive address, in the present embodiment, presumptive address for example is 100, and tentation data for example is capitalization English letter A.SPI device 22 is in order to export output data SO in response to reading command CMD.
When output data SO equaled A in fact, expression SPI device 22 can be understood reading command CMD and also can support high speed reads instruction fetch form.So, in ensuing start and other read in the operation of SPI device 22 backward, SPI control device 21 all provides the instruction of high speed reads instruction fetch form to carry out read operation.And when output data SO was not equal to A, expression SPI device 22 can not be understood reading command CMD that is not support high speed reads instruction fetch form.So, in ensuing start and other read in the operation of SPI device 22 backward, SPI control device 21 all provides the instruction of reading command form to carry out read operation.
Please refer to Fig. 3, it illustrates is the detailed block diagram of SPI control device 21 among Fig. 2.SPI control device 21 comprises solidus device 23 and logical circuit 25.Solidus device 23 is in order to providing reading command CMD in response to drive signal SA, and whether equals A in fact in order to output data SO relatively.Wherein, when output data SO equaled A in fact, solidus device 23 read SPI device 22 in order to the instruction that high speed reads instruction fetch form is provided; And when output data SO was not equal to A, solidus device 23 read SPI device 22 in order to the instruction that the reading command form is provided.
By above-mentioned operation as can be known, the SPI system 20 of present embodiment can judge in start process whether SPI device 22 supports high speed reads instruction fetch form.So, the SPI system 20 of present embodiment can detect SPI device 22 and whether support high speed reads instruction fetch form in start process, and provides the instruction of high speed reads instruction fetch form to read SPI device 22 in start process, to promote the read performance of SPI system 20.
Please refer to Fig. 4, it illustrates is the detailed circuit diagram of solidus device 23 among Fig. 3.Solidus device 23 comprises comparer 232 and multiplexer (Mux) 234.Comparer 232 is in order to relatively output data SO and tentation data, and produces according to comparative result and to select signal S.When output data SO equaled tentation data in fact, selecting signal S for example was first standard; When output data SO was not equal to tentation data, selecting signal S for example was second standard.
By above-mentioned operation as can be known, the read operation of the SPI control device 21 of present embodiment by its solidus device 23 providing reading command CMD in response to drive signal SA, but not via as the control working storage 112 of traditional SPI control device 110 provide reading command so that SPI device 120 is controlled.So, in the present embodiment, South Bridge chip can see through solidus device 23 and read SPI device 22 in the mode of direct memory access (Memory Access Direct).So, the SPI system 20 of present embodiment can read SPI device 22 via the direct memory access method, simplifies traditional South Bridge chip control working storage 27 is set trivial step and flow process, and can promote the data read usefulness of SPI system 20.
Please refer to Fig. 5, it illustrates is whether the SPI device of judging of present embodiment supports the process flow diagram of the method for high speed reads instruction fetch form.At first, as step 502, provide SPI device 22, presumptive address therein has a tentation data.In the present embodiment, presumptive address for example is 100, and tentation data for example is A.Then,, provide reading command CMD to SPI device 22, read the data that are stored in its address 100 as step 504.Reading command CMD for example is the instruction of high speed reads instruction fetch form.
Then, as step 506, SPI device 22 is in response to high speed reads instruction fetch output output data SO.Afterwards, as step 508, solidus device 23 judges whether output data SO equals A in fact, whether supports high speed reads instruction fetch form to judge SPI device 22.Afterwards, as step 510, when output data SO equaled A in fact, expression SPI device 22 was supported high speed reads instruction fetch form.So, in read operation backward, solidus device 23 all provides the instruction of high speed reads instruction fetch form to read SPI device 22.
After step 508, more comprise step 512, when output data SO was not equal to A, expression SPI device 22 was not supported high speed reads instruction fetch form.So, in read operation backward, solidus device 23 all provides the instruction of reading command form to read SPI device 22.
The SPI system of present embodiment is provided with the solidus device in the SPI control device, read the particular data of particular address in the SPI device that is stored in the SPI system with the instruction of output high speed reads instruction fetch form, and whether judge correctly according to the data that read whether the SPI device supports high speed reads instruction fetch form.So, the SPI system of present embodiment can improve traditional SPI system effectively can't detect the shortcoming whether SPI device is wherein supported high speed reads instruction fetch form and can't control and read the SPI device with the instruction of high speed reads instruction fetch form before computer system power-on is finished, and have in fact and can whether support high speed reads instruction fetch form, and can when start, directly provide the instruction of high speed reads instruction fetch form to read the advantage of SPI device in when start detecting SPI device.
In addition, the SPI system of present embodiment more can read the SPI device with the method for direct memory access (Memory Access Direct) via the hardware paths of solidus device.So, the SPI system of present embodiment more can improve traditional SPI system effectively to be needed read the SPI device and cause the lower shortcoming of data read usefulness via the hardware structure of control working storage, and has data read performance advantage of higher in fact.
In addition, the SPI control device of present embodiment is to be hardware structure with the solidus device, and can support high speed reads instruction fetch and reading command form.So, the SPI control device of present embodiment more can improve tradition effectively and can support the SPI control device of high speed reads instruction fetch form that the higher working storage of quantity need be set to cause that area is big, the bios program sign indicating number need carry out extra particular design and the higher shortcoming of cost that area is little, the bios program sign indicating number need not design or change and lower-cost advantage especially and have in fact.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
100,20: the serial circumference interface system
110,21: serial peripheral interface control device
112,27: the control buffer
114,25: logic circuit
120,22: string peripheral interface device
23: the solidus device
232: comparer
234: multiplexer
30: the Peripheral Component Interconnect bus
CMDR, CMD: reading command
SD, SO: output data
SA: drive signal
WC: write instruction
WD: write data 502～510: operation steps
Claims (13)
1. serial peripheral interface control device, this serial peripheral interface control device is applied to a computer system, one South Bridge chip of this computer system reads a serial peripheral interface device in order to a drive signal to be provided via this serial peripheral interface control device, it is characterized in that this serial peripheral interface control device comprises:
One solidus device provides a reading command in response to this drive signal, and this reading command is a high speed reads instruction fetch form;
One logical circuit couples with this string peripheral interface device, in order to read this string peripheral interface device in response to this reading command; And
One control working storage receives the instruction that writes that this South Bridge chip provides, and according to this this string peripheral interface device is carried out the operation that data write;
Wherein, this South Bridge chip is to read this string peripheral interface device via this serial peripheral interface control device in the mode of direct memory access.
2. serial peripheral interface control device according to claim 1 is characterized in that this string peripheral interface device stores a tentation data in a presumptive address, and this string peripheral interface device is exported an output data in response to this reading command.
3. serial peripheral interface control device according to claim 2 is characterized in that, this solidus device is more in order to provide this reading command to this peripheral interface device in response to this drive signal;
Wherein, this solidus device is more in order to receive and to judge whether this output data equals this tentation data in fact, when this output data equals this tentation data in fact, represent that this string peripheral interface device can support high speed reads instruction fetch form, this solidus device provides the instruction of high speed reads instruction fetch form, reads this string peripheral interface device and this logical circuit is the instruction of the high speed reads instruction fetch form that provides in response to this solidus device.
4. according to claim 2 or 3 described serial peripheral interface control devices, it is characterized in that, when this output data is not equal to this tentation data, represent that this string peripheral interface device do not support high speed reads instruction fetch form, this solidus device provides the instruction of reading command form, and this logical circuit is to read this string peripheral interface device in response to the instruction of reading command form.
5. according to claim 2 or 3 described serial peripheral interface control devices, it is characterized in that this solidus device comprises:
One comparer in order to relatively this output data and this tentation data, and produces one according to comparative result and selects signal; And
One multiplexer, in order to the instruction of the instruction of exporting the reading command form in response to this selection signal or high speed reads instruction fetch form to this logical circuit, to read this string peripheral interface device via this logical circuit.
6. serial circumference interface system, this serial circumference interface system applies is in a computer system, and a South Bridge chip of this computer system is characterized in that in order to a drive signal to be provided this serial circumference interface system comprises:
One serial peripheral interface device stores a tentation data in a presumptive address, and this string peripheral interface device is exported an output data in response to a reading command; And
One serial peripheral interface control device, in order to provide this reading command in response to this drive signal, to read this tentation data of this presumptive address that is stored in this string peripheral interface device, this reading command is a high speed reads instruction fetch form;
Wherein, this serial peripheral interface control device is more in order to receive and to judge whether this output data equals this tentation data in fact, represent that when this output data equals this tentation data in fact this string peripheral interface device can support high speed reads instruction fetch form, this serial peripheral interface control device provides the instruction of high speed reads instruction fetch form to read this string peripheral interface device.
7. serial circumference interface according to claim 6 system is characterized in that this serial peripheral interface control device comprises:
One solidus device, in order to providing this reading command, and relatively this output data and this tentation data in response to this drive signal, when this output data and this tentation data when equating in fact, this solidus device provides the high speed reads instruction fetch; And
One logical circuit reads this string peripheral interface device in order to the high speed reads instruction fetch that provides in response to this solidus device;
Wherein, this South Bridge chip is to read this string peripheral interface device via this solidus device in the direct memory access mode.
8. serial circumference interface according to claim 7 system, it is characterized in that, when this output data and this tentation data when being unequal, this solidus device provides the instruction of reading command form, and this logical circuit reads this string peripheral interface device in response to the instruction of reading command form.
9. according to claim 7 or 8 described serial circumference interface systems, it is characterized in that this solidus device comprises:
One comparer in order to relatively this output data and this tentation data, and produces one according to comparative result and selects signal; And
One multiplexer, in order to the instruction of the instruction of exporting the reading command form in response to this selection signal or high speed reads instruction fetch form to this logical circuit, to read this string peripheral interface device via this logical circuit.
10. according to any described serial circumference interface system in the claim 6 to 8, it is characterized in that this serial peripheral interface control device more comprises:
One control working storage, what receive that this South Bridge chip provides one writes instruction, and according to this this string peripheral interface device is carried out the operation that data write.
11. the determination methods of a string peripheral interface device, the determination methods of this string peripheral interface device is in order to judge that whether this string peripheral interface device supports high speed reads instruction fetch form, is characterized in that this method comprises following step:
One serial peripheral interface device is provided, and a presumptive address of this string peripheral interface device has a tentation data;
Provide a reading command to this string peripheral interface device, this reading command is a high speed reads instruction fetch form;
This string peripheral interface device is exported an output data in response to this high speed reads instruction fetch;
Judge whether this output data equals this tentation data;
When this output data equals this tentation data, represent this string peripheral interface device support high speed reads instruction fetch form, so, provide the instruction of high speed reads instruction fetch form to read this string peripheral interface device; And
When this output data is not equal to this tentation data, represent that this string peripheral interface device do not support high speed reads instruction fetch form.
12. the determination methods of string peripheral interface device according to claim 11 is characterized in that, judges whether this output data equals more to comprise after the step of this tentation data:
When judging this string peripheral interface device and do not support high speed reads instruction fetch form, provide the instruction of reading command form to read this string peripheral interface device.
13. the determination methods according to claim 11 or 12 described string peripheral interface devices is characterized in that, is to read this string peripheral interface device via the direct memory access mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101707814A CN100426271C (en) | 2006-12-22 | 2006-12-22 | Serial peripheral interface control device, system and determining method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101707814A CN100426271C (en) | 2006-12-22 | 2006-12-22 | Serial peripheral interface control device, system and determining method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1975699A CN1975699A (en) | 2007-06-06 |
| CN100426271C true CN100426271C (en) | 2008-10-15 |
Family
ID=38125776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101707814A Active CN100426271C (en) | 2006-12-22 | 2006-12-22 | Serial peripheral interface control device, system and determining method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100426271C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101324873B (en) * | 2008-07-08 | 2010-04-21 | 锐迪科微电子（上海）有限公司 | Compatible type non-standard bit wide serial perimeter interface and data transmission method among interfaces |
| CN101661323B (en) * | 2008-08-29 | 2011-09-21 | 智微科技股份有限公司 | Main control device |
| CN101819560B (en) | 2009-02-27 | 2012-05-30 | 杭州晟元芯片技术有限公司 | Method and device for executing program of SPI interface memory |
| CN106022021A (en) * | 2016-05-20 | 2016-10-12 | 合肥联宝信息技术有限公司 | Electronic device and method for locking hardware thereof |
| TWI808328B (en) * | 2020-06-19 | 2023-07-11 | 新唐科技股份有限公司 | System on chip and control method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030046619A1 (en) * | 2001-08-31 | 2003-03-06 | Fujitsu Limited | Access control device and testing method |
| US20060164072A1 (en) * | 2005-01-21 | 2006-07-27 | Microsoft Corporation | Design for test for a high speed serial interface |
| EP1705627A1 (en) * | 2005-03-23 | 2006-09-27 | Seiko Epson Corporation | Data transfer control device and electronic apparatus |
-
2006
- 2006-12-22 CN CNB2006101707814A patent/CN100426271C/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030046619A1 (en) * | 2001-08-31 | 2003-03-06 | Fujitsu Limited | Access control device and testing method |
| US20060164072A1 (en) * | 2005-01-21 | 2006-07-27 | Microsoft Corporation | Design for test for a high speed serial interface |
| EP1705627A1 (en) * | 2005-03-23 | 2006-09-27 | Seiko Epson Corporation | Data transfer control device and electronic apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1975699A (en) | 2007-06-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7310726B2 (en) | Booting from non-linear memory | |
| CN106990958B (en) | Expansion assembly, electronic equipment and starting method | |
| EP2453358A1 (en) | Method and system for diagnosing apparatus | |
| CN100426271C (en) | Serial peripheral interface control device, system and determining method thereof | |
| EP0657818A1 (en) | Non-volatile memory chip enable signal encoding method and system | |
| JPH07113907B2 (en) | card | |
| US20120060023A1 (en) | Methods for booting an operating system using non-volatile memory | |
| CN109936716A (en) | A kind of realization method and system of display driving | |
| US6519716B1 (en) | Electronic device initialization with dynamic selection of access time for non-volatile memory | |
| TWI397822B (en) | Serial peripheral interface controlling apparatus and system thereof and judging method for serial peripheral interface device supporting fast read command | |
| US20050198425A1 (en) | Combined optical storage and flash card reader using single ide or sata port and method thereof | |
| US7437503B2 (en) | Method and apparatus for handling data transfers | |
| CN106951268A (en) | A kind of Shen prestige platform supports the implementation method of NVMe hard disk startups | |
| US7036005B2 (en) | Method and apparatus for modifying the contents of revision identification register | |
| US20040210716A1 (en) | Apparatus and method for simulating virtual floppy disk and virtual hard disk | |
| CN112395017A (en) | UEFI starting method, UEFI and computer | |
| US5537664A (en) | Methods and apparatus for generating I/O recovery delays in a computer system | |
| US6182213B1 (en) | Method for attachment of a bios device into a computer system using the system memory data bus | |
| TWI230859B (en) | Method and related system for accessing LPC memory or firmware memory in a computer system | |
| CN101866310B (en) | Computer device capable of displaying operational state and floppy drive module | |
| CN2859656Y (en) | Peripheral part connecting interface burn-in card with vary testing modules | |
| CN117908759A (en) | Bridging control chip and related signal processing method | |
| KR101389922B1 (en) | Apparatus and method for setting up of Chip Set | |
| US20040216017A1 (en) | Control circuit and method for testing memory control modle | |
| US7466647B2 (en) | Efficient muxing scheme to allow for bypass and array access |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |