CN100421096C - High-speed data transmission equipment and its transmission method - Google Patents
High-speed data transmission equipment and its transmission method Download PDFInfo
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- CN100421096C CN100421096C CNB021190429A CN02119042A CN100421096C CN 100421096 C CN100421096 C CN 100421096C CN B021190429 A CNB021190429 A CN B021190429A CN 02119042 A CN02119042 A CN 02119042A CN 100421096 C CN100421096 C CN 100421096C
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Abstract
The present invention relates to high-speed data transmission equipment and a transmission method thereof. A phase locking loop is used for generating a clock pulse signal with low frequency; the clock pulse signal on an input end is used for processing data with long data bit length; a correct selective signal is matched for realizing the purpose that all kinds of effective data bit time on a data output end are identical. Therefore, the present invention solves the unbalance problem of all the kinds of effective data bit time on the existing data output end.
Description
Technical field
The present invention relates to a kind of data link and transmission method thereof, particularly a kind ofly utilize the phase-locked loop to produce low clock frequency and realize that high speed data transfer and valid data bit time (Data BitTime) can be with the data link and the transmission methods thereof of work period (Duty Cycle) change of time clock signal.
Background of invention
The processing frequency of computer system chip internal core constantly promotes in recent years, but the transmission speed of output input bus (I/O Bus) can't correspondingly significantly promote.The transmission speed that its reason is to export input bus can be subject to the design of transmitter (Transmitter)/receiver (Receiver), the type of encapsulation (Package), substrate (Substrate) design, and the influence of circuit board wiring (Routing).Therefore, how can break through the bottleneck of exporting frequency range restriction on the input bus at a high speed is to become an important problem.
Fig. 1 (a) is the existing data link that is used for multiple data transmission rate (Double Data Rate).This data link 10 can respectively be exported data on the rise and fall limit of clock pulse signal (hereinafter to be referred as CK_0).In general, the input end of data link 10 and output terminal are all with reference to identical clock frequency (being above-mentioned CK_0), and in order to realize the multiple data transmission rate, the handled data bit length of data link 10 input ends must become the multiple relation with output terminal.Its principle is as follows:
At first, must provide a phase-locked loop (not illustrating) in order to produce according to CK_0 frequency identical and with previous time clock all time clock of phasic difference 90 degree (1/4 cycle) mutually.That is, postpone 90 clock pulse signals (hereinafter to be referred as CK_90) of spending, postpone the clock pulse signals (hereinafter to be referred as CK_180) of 180 degree, and the clock pulse signals (hereinafter to be referred as CK_270) that postpone 270 degree.
Then, high-order trigger group 12 is also exported the output terminal (DXH) of high position data (DH) in high-order trigger group 12 in regular turn according to the rising edge breech lock of CK_270.In like manner, low level trigger group 14 is also exported low data (DL) in low level trigger group 14 output terminals (DXL) in regular turn according to the rising edge breech lock that postpones 90 degree time clock (hereinafter to be referred as CK_90).
And multiplexer 16 can export DXH and DXL to the output terminal (TX_D) of multiplexer 16 in regular turn according to the high level of CK_0 and low level, and exports the output input bus that data link 10 is connected to by output input pad (IO Pad) circuit 18.So, can realize the data link of multiple data transmission rate.
Also can clearly be understood by the waveform sequential chart shown in Fig. 1 (b), low data (DL) can be along with CK_90 exports DXL in regular turn (as 1,3, data shown in 5), in like manner, high position data (DH) can be along with CK_270 exports DXH (data shown in 2,4) in regular turn to.And the data on the DXL may be output to the output terminal TX_D of multiplexer 16 when CK0 is low level, and the data when CK0 is high level on the DXH may be output to the output terminal TX_D of multiplexer 16.Therefore on TX_D, can export 1,2,3,4 in regular turn, 5 data.
In general, clock pulse signal is to input to the phase-locked loop by gate generator to produce in the computer system.Therefore, the quality of clock pulse signal can determine to export the valid data bit time that data occur on the input bus.In order to obtain consistent valid data bit time, the balance of clock pulse signal work period is extremely important, that is the work period is 50%.Yet, because can not providing, now gate generator stablizes work period of 50%, and the big appointment of the work period of clock pulse signal is floated between 48%～52%, so also have identical problem by the work period of all clock pulse signals that the phase-locked loop produced.Therefore, be used as the selection signal of multiplexer 16 with unbalanced CK_0 of work period, on the output input bus, inconsistent situation of effective data bit time can be occurred, thereby setting-up time (Set Up Time) can be significantly reduced and the margin (Margin) of hold time (HoldTime).
Moreover the output input bus be in order to realize more and more faster data rate, and is relatively, more difficult and have more challenge in order to phase-locked loop design meeting that various phase differential clock pulse signals are provided.
Therefore, realize the High-Speed Data Link of valid data bit time unanimity, then want the problem that solves for a long time for industry as the phase-locked loop design of lower frequency how.
Summary of the invention
The invention provides a kind of data link, data transmission is carried out in control according to N clock pulse signal, wherein the phase differential between identical and adjacent two clock pulse signals of the period T of N clock pulse signal is T/N, and this data link comprises: a time clock compositor, its according to the level toggle edges of a described N clock pulse signal and corresponding generation N select signal, described selection signal respectively to have an effective time and be to be distributed in regular turn in this period T described effective time with waiting number of times and non-overlapping; And a multiplexer, be electrically connected on this time clock compositor, receive the different input signal of N data content respectively and be subjected to the control of described selection signal, in this effective time of corresponding this selection signal, to export described input signal in turn.
According to above-mentioned conception, in data link of the present invention, the level toggle edges of this clock pulse signal can be the rising edge of this clock pulse signal.
According to above-mentioned conception, in data link of the present invention, the level toggle edges of this clock pulse signal can be the trailing edge of this clock pulse signal.
According to above-mentioned conception, in data link of the present invention, can equal phase differential T/N this effective time.
According to above-mentioned conception, in data link of the present invention, a described N clock pulse signal can by a phase-locked loop according to one-period the reference clock pulse signal by T/2 produced.
According to above-mentioned conception, in data link of the present invention, N can equal 4, and the phase differential between identical and adjacent two clock pulse signals of the period T of these 4 clock pulse signals is T/4, and these 4 select this effective time that signal had also for T/4 and non-overlapping be evenly distributed among this period T.
According to above-mentioned conception, in data link of the present invention, also can include a trigger group, be electrically connected with this multiplexer, receive N/2 clock pulse signal and N input signal in the described N clock pulse signal, its trigger according to level toggle edges of N clock pulse signal and in regular turn breech lock live a described N input signal and export this multiplexer to.
According to above-mentioned conception, in data link of the present invention, this time clock compositor can be made of N the identical selection signal generation unit of structure, and this selection signal generation unit is to be to carry out a logical operation between adjacent two clock pulse signals of T/N to obtain this selection signal with phase differential.
Another aspect of the present invention is a kind of data link, data transmission is carried out in control according to a plurality of clock pulse signals, phase differential between identical and adjacent two clock pulse signals of the period T of described clock pulse signal is a fixed value, and this data link comprises: a time clock compositor, according to the level toggle edges of described clock pulse signal and a plurality of selection signals of corresponding generation, it is etc. that number of times ground is distributed in this period T in regular turn that described selection signal respectively has an effective time and described effective time; And a multiplexer, be electrically connected on this time clock compositor, receive the different input signal of a plurality of data contents respectively and be subjected to the control of described selection signal, in this effective time of corresponding this selection signal, to export described input signal in turn.
According to above-mentioned conception, in data link of the present invention, the level toggle edges of this clock pulse signal can be the rising edge of this clock pulse signal.
According to above-mentioned conception, in data link of the present invention, the level toggle edges of this clock pulse signal can be the trailing edge of this clock pulse signal.
According to above-mentioned conception, in data link of the present invention, can equal this phase differential this effective time.
According to above-mentioned conception, in data link of the present invention, a described N clock pulse signal can by a phase-locked loop according to one-period the reference clock pulse signal by T/2 produced.
According to above-mentioned conception, in data link of the present invention, more can include a trigger group, be electrically connected and this multiplexer, receive described clock pulse signal and described input signal, its be according to the level toggle edges of described clock pulse signal trigger and in regular turn breech lock live described input signal and export this multiplexer to.
According to above-mentioned conception, in data link of the present invention, this time clock compositor can be made of the identical selection signal generation unit of a plurality of structures, and this selection signal generation unit is will to carry out a logical operation between adjacent two clock pulse signals and obtain this selection signal.
Of the present invention is a kind of data transmission method more on the one hand, it is to carry out data transmission according to the control of N clock pulse signal, wherein the phase differential between identical and adjacent two clock pulse signals of the period T of N clock pulse signal is T/N, and this data transmission method comprises the following step: according to the level toggle edges of a described N clock pulse signal and corresponding generation N select signal, described selection signal respectively to have an effective time and be to be distributed in regular turn in this period T described effective time with waiting number of times and non-overlapping; And receive the different input signal of N data content respectively and be subjected to the control of described selection signal, in this effective time of corresponding this selection signal, to export described input signal in turn.
According to above-mentioned conception, in data transmission method of the present invention, the level toggle edges of this clock pulse signal can be the rising edge of this clock pulse signal.
According to above-mentioned conception, in data transmission method of the present invention, the level toggle edges of this clock pulse signal can be the trailing edge of this clock pulse signal.
According to above-mentioned conception, in data transmission method of the present invention, can equal phase differential T/N this effective time.
According to above-mentioned conception, in data transmission method of the present invention, a described N clock pulse signal can by a phase-locked loop according to one-period the reference clock pulse signal by T/2 produced.
According to above-mentioned conception, in data transmission method of the present invention, N=4, and the phase differential between identical and adjacent two clock pulse signals of the period T of these 4 clock pulse signals is T/4, and these 4 select this effective time that signal had also for T/4 and non-overlapping be evenly distributed among this period T.
Another aspect of the present invention is a kind of data transmission method, data transmission is carried out in control according to a plurality of clock pulse signals, phase differential between identical and adjacent two clock pulse signals of the period T of described clock pulse signal is a fixed value, and this data transmission method comprises the following step: according to the level toggle edges of described clock pulse signal and a plurality of selection signals of corresponding generation, it is etc. that number of times ground is distributed in this period T in regular turn that described selection signal respectively has an effective time and described effective time; And receive the different input signal of a plurality of data contents respectively and be subjected to the control of described selection signal, in this effective time of corresponding this selection signal, to export described input signal in turn.
According to above-mentioned conception, in data transmission method of the present invention, the level toggle edges of this clock pulse signal can be the rising edge of this clock pulse signal.
According to above-mentioned conception, in data transmission method of the present invention, wherein the level toggle edges of this clock pulse signal can be the trailing edge of this clock pulse signal.
According to above-mentioned conception, in data transmission method of the present invention, can equal this phase differential this effective time.
According to above-mentioned conception, in data transmission method of the present invention, a described N clock pulse signal can by a phase-locked loop according to one-period the reference clock pulse signal by T/2 produced.
Description of drawings
Fig. 1 (a) and (b) are to be used for the doubly block schematic diagram and the coherent signal waveform sequential synoptic diagram of the available data transmitter of fast data transmission rate;
Fig. 2 (a) and (b) are preferred embodiment block schematic diagram and coherent signal waveform sequential synoptic diagram of High-Speed Data Link of the present invention;
Fig. 3 (a) and (b) are preferred embodiment block schematic diagram and coherent signal waveform sequential synoptic diagram of this time clock compositor in the High-Speed Data Link of the present invention.
Embodiment
Fig. 2 (a) is a High-Speed Data Link of the present invention.At first, phase-locked loop used in the present invention (not illustrating) produces frequency halving and phase place and previous time clock according to clock pulse signal (hereinafter to be referred as CK) and differs the input end that the 90 various time clock of spending (1/4 cycle) are used in data link.That is frequency is half of CK and the CK2_0 that does not have phase differential, and frequency is half of CK and the CK2_90 of 90 degree phase differential, and frequency is half of CK and the CK2_180 of 180 degree phase differential, and frequency is half of CK and the CK2_270 of 270 degree phase differential.
And in order to realize the multiple data transmission rate, the handled data bit length of data link input end must quadruple to count and concern with output terminal.Its principle is as follows:
The input end of data link 40 has four groups of data to be D1, D2, D3, D4 in regular turn by lowest order digit certificate to most significant digit data, and imports the first trigger group 20, the second trigger group 22, the 3rd trigger group 24, the 4th trigger group 26 in regular turn.Wherein, the first trigger group 20 and the second trigger group 22 are come breech lock D1 and D2 according to the rising edge of CLK_270 and by output terminal TX_D1 and TX_D2 output; In like manner, the 3rd trigger group 24, the 4th trigger group 26 are come breech lock D3 and D4 according to the rising edge of CLK_90 and by output terminal TX_D3 and TX_D4 output.
Time clock compositor (Clock Synthesis) 36 receives CK2_0, CK2_90, CK2_180 and CK2_270 and selects signal in order to produce four, according to present embodiment, first selects signal (S1) only high level to occur between the rising edge of CK2_0 and CL2_90 in one-period, and other then is a low level.Second selects signal (S2) only high level to occur between the rising edge of CK2_90 and CL2_180 in one-period, and other then is a low level.The 3rd selects signal (S3) only high level to occur between the rising edge of CK2_180 and CL2_270 in one-period, and other then is a low level.The 4th selects signal (S4) only high level to occur between the rising edge of CK2_270 and CL2_0 in one-period, and other then is a low level.
Fig. 2 (b) is the signal waveform sequential synoptic diagram of the preferred embodiment of High-Speed Data Link of the present invention, can be well understood to by this figure, and at the rising edge of CK2_270, the data of D1 and D2 can be by breech lock in the first trigger group 20 and the second trigger group 22.In like manner, at the rising edge of CK2_90, the data of D3 and D4 can be by breech lock in the 3rd trigger group 24 and the 4th trigger group 26.Therefore, the first trigger group 20 can the rising edge of CK2_270 in regular turn breech lock live 1,5,9 data to TX_D1.The second trigger group 22 can the rising edge of CK2_270 in regular turn breech lock live 4,8,12 data to TX_D2.The 3rd trigger group 24 can the rising edge of CK2_90 in regular turn breech lock live 3,7,11 data to TX_D3.The 4th trigger group 26 can the rising edge of CK2_90 in regular turn breech lock live 4,8,12 data to TX_D4.
And high level appears in four selection signals in regular turn.Therefore, TX_D1, TX_D2, TX_D3, can be output to TX_D in regular turn with data on the TX_D4.That is when high level appearred in S1, the data on the TX_D1 can export TX_D to.When high level appearred in S2, the data on the TX_D2 can export TX_D to.When high level appearred in S3, the data on the TX_D3 can export TX_D to.When high level appearred in S4, the data on the TX_D4 can export TX_D to.So TX_D is last will to occur 1,2,3 in regular turn ..., 12 data.
Because the work period of existing clock pulse signal is wayward, cause the valid data bit time of multiplexer output data can not be consistent.And the selection signal of time clock compositor 36 outputs of the present invention is the time of deciding its high level appearance according to the rising edge of clock pulse signal.And because the phase-locked loop can provide various phase delays accurate clock pulse signal, therefore various selection signals time of high level appears and can be identical, and irrelevant with the work period of clock pulse signal.So the valid data bit time of multiplexer 32 output datas can control to identical, so the valid data bit time of available data can not consistent problem can achieve a solution fully.
Fig. 3 (a) is the partial circuit figure of time clock compositor, and as shown in the figure, CK_0 inputs to Sheffer stroke gate 60 after inputing to the not gate 52,54 of serial connection.And input to Sheffer stroke gate 60 behind the not gate 56 that CK_90 inputs to serial connection and the transmission lock (Transmission gate) 58.And Sheffer stroke gate 60 outputs promptly become the first selection signal (S1) through another not gate 62 again.In like manner, second select signal (S2), the 3rd to select signal (S3) and the 4th to select signal (S4) all can realize according to this circuit.Coherent signal waveform sequential chart then please refer to shown in Fig. 3 (b) therebetween.
Certainly, The present invention be directed to the multiple data transmission rate and design, so the time clock speed of input end and deal with data bit length must cooperatively interact.Because time clock slow phase-locked loop design is simpler, therefore the present invention utilizes the lower phase-locked loop of clock pulse signal frequency to handle long data bit length, and cooperation selects signal to realize that the valid data bit time is identical accurately.
Therefore, the invention has the advantages that and propose a kind of High-Speed Data Link, it uses the phase-locked loop to produce the lower clock pulse signal of frequency in order to the long data bit length of processing, and cooperation selects signal to realize that the valid data bit time on the data output end is identical accurately.
In sum; though the present invention discloses as above by preferred embodiment; yet it is not in order to limit the present invention; the those of ordinary skill of the industry without departing from the spirit and scope of the present invention; can carry out various changes and retouching, so protection scope of the present invention should be with being as the criterion that claims define.
Claims (10)
1. a data link carries out data transmission according to the control of N clock pulse signal, and wherein the phase differential between identical and adjacent two clock pulse signals of the period T of N clock pulse signal is T/N, it is characterized in that this data link comprises:
One time clock compositor, its according to the level toggle edges of a described N clock pulse signal and corresponding generation N select signal, described selection signal respectively have an effective time and described effective time be etc. number of times and non-overlapping be distributed in this period T; And
One multiplexer is electrically connected on this time clock compositor, receives the different input signal of N data content respectively and is subjected to the control of described selection signal, to export described input signal in turn in this effective time of corresponding this selection signal.
2. data link as claimed in claim 1, the level toggle edges that it is characterized in that described clock pulse signal are to be selected from one of the rising edge of this clock pulse signal and trailing edge of this clock pulse signal, and be to equal phase differential T/N this effective time.
3. data link as claimed in claim 1, it is characterized in that described N=4, these 4 clock pulse signals be by a phase-locked loop according to one-period the reference clock pulse signal by T/2 produced, and the phase differential between identical and adjacent two clock pulse signals of the period T of these 4 clock pulse signals is T/4, and these 4 select this effective time that signal had also for T/4 and non-overlapping be evenly distributed among this period T.
4. data link as claimed in claim 1, it is characterized in that also including N trigger group, be electrically connected with this multiplexer, N/2 clock pulse signal and N input signal in this N the described N of trigger group of received clock pulse signal, its be according to the level toggle edges of N clock pulse signal trigger and in regular turn breech lock live a described N input signal and export this multiplexer to, and this time clock compositor is to be made of N the identical selection signal generation unit of structure, and this selection signal generation unit is to be to carry out a NAND Logic computing between adjacent two clock pulse signals of T/N to obtain this selection signal with phase differential.
5. a data link carries out data transmission according to the control of a plurality of clock pulse signals, and the phase differential between identical and adjacent two clock pulse signals of the period T of described clock pulse signal is a fixed value, it is characterized in that this data link comprises:
One time clock compositor, according to the level toggle edges of described clock pulse signal and a plurality of selection signals of corresponding generation, it is etc. that number of times ground is distributed in this period T in regular turn that described selection signal respectively has an effective time and described effective time; And
One multiplexer is electrically connected on this time clock compositor, receives the different input signal of a plurality of data contents respectively and is subjected to the control of described selection signal, to export described input signal in turn in this effective time of corresponding this selection signal.
6. data transmission method, data transmission is carried out in control according to N clock pulse signal, wherein the phase differential between identical and adjacent two clock pulse signals of the period T of N clock pulse signal is T/N, it is characterized in that this data transmission method comprises the following step:
According to the level toggle edges of a described N clock pulse signal and corresponding generation N select signal, described selection signal respectively to have an effective time and be to be distributed in regular turn in this period T described effective time with waiting number of times and non-overlapping; And
Receive the different input signal of N data content respectively and be subjected to the control of described selection signal, in this effective time of corresponding this selection signal, to export described input signal in turn.
7. data transmission method as claimed in claim 6, the level toggle edges that it is characterized in that described clock pulse signal is one of to be selected from the trailing edge of the rising edge of this clock pulse signal and this clock pulse signal, and equals phase differential T/N this effective time.
8. data transmission method as claimed in claim 6, it is characterized in that described N=4, these 4 clock pulse signals be by a phase-locked loop according to one-period the reference clock pulse signal by T/2 produced, and the phase differential between identical and adjacent two clock pulse signals of the period T of these 4 clock pulse signals is T/4, and these 4 select this effective time that signal had also for T/4 and non-overlapping be evenly distributed among this period T.
9. data transmission method, data transmission is carried out in control according to a plurality of clock pulse signals, phase differential between identical and adjacent two clock pulse signals of the period T of described clock pulse signal is a fixed value, it is characterized in that this data transmission method comprises the following step:
According to the level toggle edges of described clock pulse signal and a plurality of selection signals of corresponding generation, it is etc. that number of times ground is distributed in this period T in regular turn that described selection signal respectively has an effective time and described effective time; And
Receive the different input signal of a plurality of data contents respectively and be subjected to the control of described selection signal, in this effective time of corresponding this selection signal, to export described input signal in turn.
10. data transmission method as claimed in claim 9 is characterized in that equaling this phase differential described effective time, and a described N clock pulse signal be by a phase-locked loop according to one-period the reference clock pulse signal by T/2 produced.
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| CNB021190429A CN100421096C (en) | 2002-05-08 | 2002-05-08 | High-speed data transmission equipment and its transmission method |
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| CN100421096C true CN100421096C (en) | 2008-09-24 |
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| US7302508B2 (en) * | 2003-06-10 | 2007-11-27 | Via Technologies, Inc. | Apparatus and method for high speed data transfer |
| CN104052567A (en) * | 2013-03-11 | 2014-09-17 | 联咏科技股份有限公司 | Generation device and transmission method for clock embedded data |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO1999019806A1 (en) * | 1997-10-10 | 1999-04-22 | Rambus Incorporated | Method and apparatus for fail-safe resynchronization with minimum latency |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO1999019806A1 (en) * | 1997-10-10 | 1999-04-22 | Rambus Incorporated | Method and apparatus for fail-safe resynchronization with minimum latency |
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