CN100414838C - Negative voltage effective transmission circuit of standard logic process - Google Patents
Negative voltage effective transmission circuit of standard logic process Download PDFInfo
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- CN100414838C CN100414838C CNB2005101321602A CN200510132160A CN100414838C CN 100414838 C CN100414838 C CN 100414838C CN B2005101321602 A CNB2005101321602 A CN B2005101321602A CN 200510132160 A CN200510132160 A CN 200510132160A CN 100414838 C CN100414838 C CN 100414838C
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Abstract
The present invention discloses a negative voltage effectively transmission circuit based on standard logic technology. The present invention comprises a clock circuit, a low-voltage output channel and a negative-voltage output channel, wherein the clock circuit outputs alternatively high-level clock signals and low-level clock signals; the low-voltage output channel outputs low voltage, and the input of the low-voltage output channel is connected with the output of the clock circuit; when the clock signals output by the clock circuit become a low level from a high level, the low-voltage output channel is triggered to be switched into conduction, and low voltage is output; the negative-voltage output passage outputs negative voltage, the input of the negative-voltage output passage is connected with the output of the clock circuit, and the output of the negative-voltage output passage is connected with the output of a zero-voltage output passage so as to be as the output of the entire circuit; when the clock signals output by the clock circuit become high level from the low level, electric charges stored by a transistor used as a coupling capacitor are utilized to trigger a transmission gate of the negative-voltage output passage to be switched into conduction so as to output negative voltage. The present invention provides a determined initial state for transmission gate control voltage, effectively controls the transmission of the negative voltage and ensures the consistency of negative voltage transmission.
Description
Technical field
The present invention relates to be suitable for the negative-voltage effective transmission circuit of dynamic memory, the negative-voltage effective transmission circuit on particularly a kind of standard logic process.
Background technology
The dynamic memory that uses standard logic process to make in order to reduce to enter in the memory cell stored charge of transistorized subthreshold value electric leakage and maximization storage capacitance, needs to use positive voltage that is higher than power supply vdd and the negative voltage that is lower than power supply ground vss.
Standard logic process is a kind of semiconductor chip manufacturing technology, and this technology only provides one deck polysilicon, and single trap or two well structure are provided simultaneously.In the dynamic memory circuit, be transferred to the negative voltage that word line is higher than the positive voltage of power supply vdd and is lower than power supply ground vss by word line driving circuit, this positive voltage and negative voltage are produced by power circuit.
In the standard logic technology, for preventing the forward conduction of parasitic PN junction in the transistor, the substrate P trap of nmos pass transistor connects power supply ground.Transmit negative voltage in the ifs circuit, the source electrode of NMOS or drain electrode will be connected with negative voltage.For deep submicron process, because transistorized threshold voltage is lower, the source or the less negative voltage that drains not only can cause the subthreshold value electric leakage of nmos pass transistor, and the forward that can cause the transistor parasitic PN junction leaks electricity, cause the waste of circuit power consumption, therefore must take measures to reduce transistorized electric leakage.Prior art, by a large amount of word line driving circuits is divided into groups, reduce the source electrode of word line pull-down transistor NMOS and the number of connection of negative voltage, thereby reduced the forward electric leakage of transistor parasitic PN junction, but do not had to handle the subthreshold value electric leakage that causes nmos pass transistor by negative voltage.
Effective transmission negative voltage not only can reduce the electric leakage that caused by negative voltage in the circuit, and performance that can stabilizing circuit.Dynamic memory circuit is opened the transistor that enters in the memory cell by using negative voltage, realizes read-write capability.The transmission quality of negative voltage signal directly influences the working condition of word line driving circuit, the speed that signal changes on the decision word line.
Prior art is used the conducting of capacitance coupling circuit control transmission door and is ended, thus the transmission of control negative voltage, the connection state of pull-down transistor source electrode in this transmission gate control negative voltage and the word line driving circuit.Simultaneously, utilize the initial condition of the transistor controls transmission gate grid voltage of diode connection, this transistor is connected between transmission gate grid and the negative voltage, and such connected mode can cause the uncertainty of transmission gate initial voltage, and size changes between 0 volt and a transistor threshold voltage.The uncertainty of transmission gate grid voltage can cause the variation of transmission gate conducting resistance, thereby influences the transmission quality of negative voltage.
How effectively controlling the transmission of negative voltage, improve the consistency that the memory word lineman makes state, reduce the electric leakage of circuit, is problem to be solved by this invention.
Summary of the invention
The purpose of this invention is to provide the negative-voltage effective transmission circuit on a kind of standard logic process, utilize the PMOS transistor to do negative voltage transmission in the coupling capacitance control circuit.
According to a first aspect of the invention, the negative-voltage effective transmission circuit that is provided comprises:
A clock circuit of alternately exporting high level and low level clock signal;
The low-voltage output channel of an output LOW voltage, its input connect described clock circuit output, when the clock signal of described clock circuit output when high level becomes low level, trigger this conducting of low-voltage output channel, output LOW voltage thus;
The negative voltage output channel of an output negative voltage, its input connects described clock circuit output, its output connects the output of described no-voltage output channel with the output as entire circuit, when the clock signal of described clock circuit output when low level becomes high level, the transistor stored charge that coupling capacitance is served as in utilization triggers the transmission gate conducting of this negative voltage output channel, exports negative voltage thus.
Wherein, described negative voltage output channel comprises:
First inverter, its input connects the output of clock circuit;
The first transistor that serves as first coupling capacitance, its effective capacitance first end connects the output of clock circuit;
The transistor seconds that serves as second coupling capacitance, its effective capacitance first end connects the output of first inverter;
The 3rd transistor that serves as first transmission gate, its grid connects effective capacitance second end of transistor seconds, and its drain electrode connects effective capacitance second end of described the first transistor;
The 4th transistor that serves as second transmission gate, its grid connects effective capacitance second end of the first transistor, and its drain electrode connects effective capacitance second end of transistor seconds;
The 5th transistor that serves as the 3rd transmission gate, its grid connects effective capacitance second end of transistor seconds, and its source electrode connects negative voltage, and its drain electrode is as the output of entire circuit.
Wherein, described low-voltage passage comprises:
Second inverter, its input connects the output of clock circuit;
Serve as the 6th transistor of the 4th transmission gate, its grid connects the output of second inverter, and its drain electrode connects described the 5th transistor drain.
Wherein, the inverter that described second inverter is connected and composed by PMOS transistor and nmos pass transistor complementation, the source electrode of nmos pass transistor wherein connect described the 6th transistor drain.
Wherein, effective capacitance first end of described the first transistor is the terminal that source electrode and drain electrode are connected to form, and effective capacitance second end of described the first transistor is the terminal that grid forms;
Effective capacitance first end of described transistor seconds is the terminal that source electrode and drain electrode are connected to form, and effective capacitance second end of described transistor seconds is the terminal that grid forms.
Wherein, described transistor is a field-effect transistor.
Wherein, described clock circuit is the delay buffer that connects clock signal.
Wherein, described low-voltage is a no-voltage.
Wherein, the described transistor that serves as first, second and the 3rd transmission gate is the PMOS transistor, and its substrate all connects low-voltage.
Wherein, the described transistor that serves as first coupling capacitance and second coupling capacitance is the PMOS transistor.
According to a second aspect of the invention, the negative-voltage effective transmission circuit that is provided comprises:
A clock circuit of alternately exporting high level and low level clock signal;
The low-voltage output channel of an output LOW voltage, its input connect described clock circuit output, when the clock signal of described clock circuit output when low level becomes high level, trigger this low-voltage output channel conducting, output LOW voltage;
The negative voltage output channel of an output negative voltage, its input connects described clock circuit output, its output connects the output of described no-voltage output channel with the output as entire circuit, when the clock signal of described clock circuit output when high level becomes low level, the transistor stored charge that coupling capacitance is served as in utilization triggers the transmission gate conducting of this negative voltage output channel, exports negative voltage thus.
According to a third aspect of the invention we, the negative-voltage effective transmission circuit that is provided comprises:
The negative voltage output channel of an output negative voltage, according to the high level or the low level conducting of the clock signal of being imported, the negative voltage that output is inserted, wherein said negative voltage output channel comprises:
First inverter, its input connects the output of clock circuit;
The first transistor that serves as first coupling capacitance, its effective capacitance first end connects the output of clock circuit;
The transistor seconds that serves as second coupling capacitance, its effective capacitance first end connects the output of first inverter;
The 3rd transistor that serves as first transmission gate, its grid connects effective capacitance second end of transistor seconds, and its drain electrode connects effective capacitance second end of described the first transistor;
The 4th transistor that serves as second transmission gate, its grid connects effective capacitance second end of the first transistor, and its drain electrode connects effective capacitance second end of transistor seconds;
The 5th transistor that serves as the 3rd transmission gate, its grid connects effective capacitance second end of transistor seconds, and its source electrode connects negative voltage, and its drain electrode is as the output of entire circuit.
Because the word line driving circuit of dynamic memory need use negative voltage, effectively transmits negative voltage, can guarantee that the word line driving circuit in the disparate modules obtains identical negative voltage, guarantee the consistency of different word line work.In no triple-well standard logic process, for the NMOS structure, because substrate ground connection if source or drain electrode are connected to negative voltage, has both made negative voltage be lower than transistorized threshold voltage, negative voltage also can cause very strong subthreshold value electric leakage and the electric leakage of transistor parasitic PN junction.
Prior art by the control transmission door conducting and end the transmission of control negative voltage.The operating state of control transmission door how rationally, the transmission course of decision negative voltage.Because the transmission gate of prior art control voltage initial condition exists uncertain, therefore transmission gate conducting control voltage exists uncertain, the transmission speed that causes negative voltage thus changes, and further influences the operating state of word line, causes the variation of memory performance.In the prior art, when the drain electrode of nmos pass transistor connect negative voltage, the shutoff voltage of grid was 0 volt, and the weak conducting that this has just caused the NMOS pipe has caused unnecessary leakage current, has increased power consumption.
The present invention has controlled the transmission of negative voltage effectively for transmission gate control voltage provides the initial condition of determining, has guaranteed the consistency of negative voltage transmission; Revise the grid-control voltage of nmos pass transistor simultaneously, reduced the electric leakage that causes by negative voltage.
By reference following detailed and accompanying drawing, can clearer understanding be arranged to the present invention.
Description of drawings
Fig. 1 is a circuit theory schematic diagram of the present invention;
Fig. 2 shows respectively in operating process, voltage waveform on the position 100,101,102,103,104 among Fig. 1.
Embodiment
At first referring to Fig. 1, negative-voltage effective transmission circuit of the present invention comprises:
Clock circuit of alternately exporting high level and low level clock signal (by inverter 11 and 12, inverter 15 and 16, inverter 17 and 18, inverter 19 and 20 and inverter 13 and NAND gate 14 form, their constitute the delay buffer of clock signal);
The low-voltage output channel (8-10 forms by transistor) of an output LOW voltage, its input connects described clock circuit output (being the output of inverter 11), when the clock signal of described clock circuit output when high level becomes low level, triggering this no-voltage output channel conducting (is transistor 10 conductings, the concrete course of work will be described below), output LOW voltage vss;
The negative voltage output channel (1-7 forms by transistor) of an output negative voltage, its input connects described clock circuit output (being the output of inverter 13), its output connects the output of described no-voltage output channel with the output as entire circuit, when the clock signal of described clock circuit output when low level becomes high level, the transmission gate conducting that transistor 2 charge stored that coupling capacitance is served as in utilization trigger this negative voltage output channel (is transistor 4 conductings, the concrete course of work will be described below), export negative voltage vnb thus.
Described negative voltage output channel comprises:
First inverter (connecting and composing) by PMOS transistor 6 and nmos pass transistor 7 complementations, its input connects the output (being the output of inverter 13) of clock circuit;
The first transistor 1 that serves as first coupling capacitance, its effective capacitance first end (being connected to form with drain electrode by source electrode) are connected the output (being the output of inverter 13) of clock circuit;
The transistor seconds 2 that serves as second coupling capacitance, its effective capacitance first end (being connected to form with drain electrode by source electrode) are connected the output (being the drain electrode of transistor 6,7) of first inverter;
The 3rd transistor 3 that serves as first transmission gate, its grid connects effective capacitance second end (being the grid of transistor 2) of transistor seconds 2, and its drain electrode connects effective capacitance second end (being the grid of transistor 1) of described the first transistor 1;
The 4th transistor 5 that serves as second transmission gate, its grid connects effective capacitance second end (being the grid of transistor 1) of the first transistor 1, and its drain electrode connects effective capacitance second end (being the grid of transistor 2) of transistor seconds 2;
The 5th transistor 4 that serves as the 3rd transmission gate, its grid connects effective capacitance second end (being the grid of transistor 2) of transistor seconds 2, and its source electrode connects negative voltage vnb, and its drain electrode is as the output of entire circuit.
Described low-voltage passage comprises:
Second inverter (connecting and composing) by PMOS transistor 8 and nmos pass transistor 9 complementations, its input connects the output (output of inverter 11) of clock circuit;
The 6th transistor 10 that serves as the 4th transmission gate, its grid connect the output (being the drain electrode of transistor 8 and 9) of second inverter, and its drain electrode connects the drain electrode of one the 5th transistor 4.
The inverter that described second inverter is connected and composed by PMOS transistor 8 and nmos pass transistor 9 complementations, the source electrode of nmos pass transistor 9 wherein connects the drain electrode of described the 6th transistor 10.
Effective capacitance first end of described the first transistor 1 is the terminal that source electrode and drain electrode are connected to form, and effective capacitance second end of described the first transistor 1 is the terminal that grid forms; Effective capacitance first end of described transistor seconds 2 is terminals that source electrode and drain electrode are connected to form, and effective capacitance second end of described transistor seconds 2 is terminals that grid forms.
Wherein said transistor is a field-effect transistor, and described low-voltage is a no-voltage.
In addition, by the output signal of clock circuit is carried out simple reverse process or similar processing, can make above-mentioned low-voltage output channel in the conducting when low level becomes high level of the clock signal of clock circuit output, with output LOW voltage; And the clock signal that makes negative voltage output channel clock circuit output conducting when high level becomes low level is with the output negative voltage.
The present invention can also directly utilize above-mentioned negative voltage output channel transmission negative voltage, such negative-voltage effective transmission circuit comprises: the negative voltage output channel (1-7 forms by transistor) of an output negative voltage, it is according to the high level or the low level conducting of the clock signal of being imported, the negative voltage vnb that output is inserted, wherein said negative voltage output channel comprises:
First inverter (connecting and composing) by PMOS transistor 6 and nmos pass transistor 7 complementations, its input connects the output (being the output of inverter 13) of clock circuit;
The first transistor 1 that serves as first coupling capacitance, its effective capacitance first end (being connected to form with drain electrode by source electrode) are connected the output (being the output of inverter 13) of clock circuit;
The transistor seconds 2 that serves as second coupling capacitance, its effective capacitance first end (being connected to form with drain electrode by source electrode) are connected the output (being the drain electrode of transistor 6,7) of first inverter;
The 3rd transistor 3 that serves as first transmission gate, its grid connects effective capacitance second end (being the grid of transistor 2) of transistor seconds 2, and its drain electrode connects effective capacitance second end (being the grid of transistor 1) of described the first transistor 1;
The 4th transistor 5 that serves as second transmission gate, its grid connects effective capacitance second end (being the grid of transistor 1) of the first transistor 1, and its drain electrode connects effective capacitance second end (being the grid of transistor 2) of transistor seconds 2;
The 5th transistor 4 that serves as the 3rd transmission gate, its grid connects effective capacitance second end (being the grid of transistor 2) of transistor seconds 2, and its source electrode connects negative voltage vnb, and its drain electrode is as the output of entire circuit.
Below with reference to Fig. 1 and Fig. 2 structure of the present invention and operation principle are further specified,
Referring to Fig. 1, the main composition of circuit is inverter, two input nand gates, PMOS coupling capacitance and PMOS transmission gate.The input/output signal of circuit has vdd, vss, vnb, bs and vdown, wherein, bs is the clock control signal of circuit, vdd is the working power voltage of circuit, vss is the place of working voltage (size is 0 volt) of circuit, vnb is the present invention's negative voltage signal to be processed, and vdown is the output signal of circuit of the present invention.
Among Fig. 1, inverter 11 and 12, inverter 15 and 16, inverter 17 and 18, inverter 19 and 20 and inverter 13 and NAND gate 14 form delay buffers.MOS transistor 1,2,3,4,5,6,7,8,9 and 10 is core circuits of the present invention, and wherein, transistor 6 and 7,8 and 9 is formed inverter, and transistor 1 and 2 is made coupling capacitance, and transistor 3,4,5,10 is made transmission gate, controls the transmission of negative voltage jointly.
During operation, circuit changes according to the height of bs clock signal, at vdown end output negative voltage vnb or low level vss.When the bs signal is high level (size is vdd), vdown end output negative voltage vnb; When the bs signal is low level vss, vdown end output low level vss.The output signal that is the vdown end is changed between vss and vnb according to the variation of bs signal.The conducting of the voltage-controlled transistor 5 of P0_g end or end, the voltage-controlled transistor 3 of Pcap_g end and 4 conducting or end, the conducting of the voltage-controlled transistor 10 of N2_g end or end.
Behind the circuit energized vdd, bs signal initial condition is low level vss, and transistor 6 and 7 is output as high level vdd, and the output I13-y of inverter 13 is low level vss, and inverter 11 is output as low level vss, and the voltage of N2_g end is high level vdd.For the voltage of P0_g end and Pcap_g end,, be low level vss because two nodes do not have over the ground the direct path with power supply, so will keep its reset condition.It is low level state simultaneously that P0_g end and Pcap_g hold, and only appears at this end between circuit energized and first rising edge of bs signal in the time, perhaps under the out-of-work situation of circuit.The low level of P0_g end and Pcap_g end makes transistor 3,4 and 5 be in cut-off state, and the high level of N2_g end makes transistor 10 be in conducting state, so vdown end output voltage is low level vss.
After the bs signal became high level vdd, transistor 6 and 7 output became low level, according to coupling capacitance charge stored amount the principle of transition can not take place, and the quantity of electric charge at coupling capacitance 2 two ends will keep vdd*C2, and C2 is the effective capacitance of transistor 2.Therefore the voltage of Pcap_g end becomes following value by vss:
vdd2＝-C2*vdd/(C2+C3+C4+Cd5)＝λ*vdd(-1＜λ＜-0.5)
C3, C4 and Cd5 are respectively the effective capacitance of transistor 3, the effective capacitance of transistor 4 and the drain parasitic capacitance of transistor 5.The voltage vdd2 of Pcap_g end can make transistor 3 and 4 conductings, and is sufficient conducting.The conducting of transistor 3 makes P0_g end link to each other with vss, so the voltage that P0_g holds still keeps low level vss, and promptly transistor 5 still is in cut-off state.Ending of transistor 5 remains unchanged the voltage vdd2 of Pcap_g, and the abundant turn-on transistor 4 of vdd2 makes the output of vdown become negative voltage vnb, and makes the equivalent resistance between vdown and the vnb drop to minimum, has reduced the voltage drop on the transistor 4.
After the bs signal became low level by high level, the output of inverter 13 became low level.Equally, according to the principle of coupling capacitance, the voltage of P0_g end becomes following value by vss:
vdd1＝-C1*vdd/(C1+C5+Cd3)＝γ*vdd(-1＜γ＜-0.5)
C1, C5 and Cd3 are respectively the effective capacitance of transistor 1, the effective capacitance of transistor 5 and the drain parasitic capacitance of transistor 3.The voltage vdd1 of P0_g end can make transistor 5 abundant conductings, and the conducting of transistor 5 makes Pcap_g link to each other with vss, so the voltage of Pcap_g end becomes low level vss by vdd2.The low level of Pcap_g end is ended transistor 3 and 4, so the voltage vdd1 of P0_g end remains unchanged vdown end output becoming low level vss.
In the circuit operation process, low level vss alternately appears in P0_g end and Pcap_g end, be transistor 3 and 5 alternate conduction with the bs clock signal, the voltage that P0_g and Pcap_g are held alternately fully is initialised to the low level vss of circuit, can prevent outside interference thus effectively, the consistency of vdd1 and vdd2 voltage when guaranteeing each the operation.Stablizing of vdd2 voltage, the equivalent resistance of transistor 4 is constant when guaranteeing each the operation, thereby guarantees that vdown exports the consistency of negative voltage and the consistency that the memory word lineman does.
For the connection that N0_s holds, if directly connect vss, be between high period at the bs signal, the voltage that N2_g holds is low level vss, because vdown end level this moment is a negative voltage, so the weak conducting of transistor 10 meeting formation, cause electric leakage.Usually, the threshold voltage of the nmos pass transistor in the deep submicron process is lower than the conducting voltage of diode, the source electrode of transistor 9 is received vdown, can make the grid-control voltage of transistor 10 is to be in negative voltage vnb between high period at the bs signal, transistor 10 is fully ended, thereby eliminate the electric leakage path.At the bs signal is between low period, and the voltage of N2_g end keeps high level, and promptly transistor 10 is in conducting state, and vdown is connected with vss, and the output voltage of vdown end keeps low level vss.At the bs signal is between high period, and the voltage of N2_g end keeps negative voltage vnb, and promptly transistor 10 is in cut-off state, makes the output voltage of vdown end keep negative voltage vnb.
In sum, as shown in Figure 2, along with the height variation of control signal bs, voltage conversion between negative voltage vnb and low level vss of vdown end; Voltage conversion between low level vss and negative voltage vdd1 of P0_g end; Voltage conversion between negative voltage vdd2 and low level vss of Pcap_g end.In the operating process, the cross-couplings loop alternately fully is initialised to low level vss with the initial voltage of P0_g and Pcap_g end, has guaranteed the consistency of vdown output negative voltage, thereby guarantees the consistency of word line driving circuit output signal; The electric leakage path has effectively been eliminated in the reduction of transistor 10 gate off voltage, has reduced power consumption.According to the present invention, negative voltage has reduced power consumption when effectively being transmitted, because can remain in the controlled range of tens uA at the leakage current of negative voltage duration of work, compares with operating current tens mA of memory, can ignore.
Above example only is used for explanation; rather than be used for limiting the present invention; those of ordinary skills can spirit according to the present invention make various modifications to above-mentioned example, and therefore the various modifications of being done according to the above-mentioned principle of the present invention all should fall into protection scope of the present invention.
Claims (10)
1. negative-voltage effective transmission circuit comprises:
A clock circuit of alternately exporting high level clock signal and low level clock signal;
The low-voltage output channel of an output LOW voltage, its input connects described clock circuit output, when the clock signal of described clock circuit output when high level becomes low level or the clock signal of described clock circuit output when low level becomes high level, trigger the included conducting of no-voltage output channel, the output LOW voltage thus of described low-voltage output channel;
The negative voltage output channel of an output negative voltage, its input connects described clock circuit output, its output connects the output of described no-voltage output channel with the output as entire circuit, corresponding clock signal when the output of described clock circuit with top description when low level becomes high level or the clock signal of described clock circuit output when high level becomes low level, the transistor stored charge that coupling capacitance is served as in utilization triggers the transmission gate conducting of this negative voltage output channel, export negative voltage thus, wherein, described negative voltage output channel comprises:
First inverter, its input connects the output of clock circuit;
The first transistor that serves as first coupling capacitance, its effective capacitance first end connects the output of clock circuit;
The transistor seconds that serves as second coupling capacitance, its effective capacitance first end connects the output of first inverter;
The 3rd transistor that serves as first transmission gate, its grid connects effective capacitance second end of transistor seconds, and its drain electrode connects effective capacitance second end of described the first transistor;
The 4th transistor that serves as second transmission gate, its grid connects effective capacitance second end of the first transistor, and its drain electrode connects effective capacitance second end of transistor seconds;
The 5th transistor that serves as the 3rd transmission gate, its grid connects effective capacitance second end of transistor seconds, and its source electrode connects negative voltage, and its drain electrode is as the output of entire circuit.
2. negative-voltage effective transmission circuit according to claim 1, wherein said low-voltage passage comprises:
Second inverter, its input connects the output of clock circuit;
Serve as the 6th transistor of the 4th transmission gate, its grid connects the output of second inverter, and its drain electrode connects described the 5th transistor drain.
3. negative-voltage effective transmission circuit according to claim 2, wherein said second inverter is connected and composed by PMOS transistor and nmos pass transistor complementation, and the source electrode of nmos pass transistor wherein connects described the 6th transistor drain.
4. negative-voltage effective transmission circuit according to claim 1, wherein,
Effective capacitance first end of described the first transistor is the terminal that source electrode and drain electrode are connected to form, and effective capacitance second end of described the first transistor is the terminal that grid forms;
Effective capacitance first end of described transistor seconds is the terminal that source electrode and drain electrode are connected to form, and effective capacitance second end of described transistor seconds is the terminal that grid forms.
5. require each described negative-voltage effective transmission circuit according to aforesaid right, wherein said transistor is a field-effect transistor.
6. according to each described negative-voltage effective transmission circuit of claim 1-2, wherein said clock circuit is the delay buffer that connects clock signal.
7. require 1 described negative-voltage effective transmission circuit according to aforesaid right, wherein said low-voltage is a no-voltage.
8. require 1 described negative-voltage effective transmission circuit according to aforesaid right, the wherein said transistor that serves as first, second and the 3rd transmission gate is the PMOS transistor, and its substrate all connects low-voltage.
9. require 1 described negative-voltage effective transmission circuit according to aforesaid right, the wherein said transistor that serves as first coupling capacitance and second coupling capacitance is the PMOS transistor.
10. negative-voltage effective transmission circuit comprises:
The negative voltage output channel of an output negative voltage, according to the high level or the low level conducting of the clock signal of being imported, the negative voltage that output is inserted, wherein said negative voltage output channel comprises:
First inverter, its input connects the output of clock circuit;
The first transistor that serves as first coupling capacitance, its effective capacitance first end connects the output of clock circuit;
The transistor seconds that serves as second coupling capacitance, its effective capacitance first end connects the output of first inverter;
The 3rd transistor that serves as first transmission gate, its grid connects effective capacitance second end of transistor seconds, and its drain electrode connects effective capacitance second end of described the first transistor;
The 4th transistor that serves as second transmission gate, its grid connects effective capacitance second end of the first transistor, and its drain electrode connects effective capacitance second end of transistor seconds;
The 5th transistor that serves as the 3rd transmission gate, its grid connects effective capacitance second end of transistor seconds, and its source electrode connects negative voltage, and its drain electrode is as the output of entire circuit.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108336988A (en) * | 2018-03-07 | 2018-07-27 | 马彪 | A kind of negative pressure driving circuit of MOS switch |
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| CN109102832B (en) * | 2018-09-12 | 2021-07-06 | 中国电子科技集团公司第五十八研究所 | Negative voltage transmission circuit |
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| US6147914A (en) * | 1998-08-14 | 2000-11-14 | Monolithic System Technology, Inc. | On-chip word line voltage generation for DRAM embedded in logic process |
| US6468855B2 (en) * | 1998-08-14 | 2002-10-22 | Monolithic System Technology, Inc. | Reduced topography DRAM cell fabricated using a modified logic process and method for operating same |
| US6744676B2 (en) * | 1998-08-14 | 2004-06-01 | Monolithic System Technology, Inc. | DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same |
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|---|---|---|---|---|
| US6147914A (en) * | 1998-08-14 | 2000-11-14 | Monolithic System Technology, Inc. | On-chip word line voltage generation for DRAM embedded in logic process |
| US6468855B2 (en) * | 1998-08-14 | 2002-10-22 | Monolithic System Technology, Inc. | Reduced topography DRAM cell fabricated using a modified logic process and method for operating same |
| US6744676B2 (en) * | 1998-08-14 | 2004-06-01 | Monolithic System Technology, Inc. | DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108336988A (en) * | 2018-03-07 | 2018-07-27 | 马彪 | A kind of negative pressure driving circuit of MOS switch |
| CN108336988B (en) * | 2018-03-07 | 2022-01-25 | 中科德诺微电子(深圳)有限公司 | Negative voltage driving circuit of MOS switch |
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