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CN100403551C - High-tension element structure - Google Patents

High-tension element structure Download PDF

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CN100403551C
CN100403551C CN 200510054315 CN200510054315A CN100403551C CN 100403551 C CN100403551 C CN 100403551C CN 200510054315 CN200510054315 CN 200510054315 CN 200510054315 A CN200510054315 A CN 200510054315A CN 100403551 C CN100403551 C CN 100403551C
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high
tension
element
structure
tension element
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CN 200510054315
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Chinese (zh)
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CN1832197A (en )
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徐尉伦
李文芳
林育贤
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联华电子股份有限公司
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Abstract

一种高压元件结构设于一第一导电类型的一基底中,包含具有第二导电类型的一第一阱区及一第二阱区位于基底中、具有一第一长度的一源极扩散区及一漏极扩散区分别位于第一阱区及第二阱区中以及具有一第二长度的一导体栅极层位于基底表面。 A high voltage element structure disposed on a substrate of a first conductivity type, comprising a first well region and a second well region of a second conductivity type located in the substrate, a source diffusion region having a first length and a drain diffusion region are located in the first well region and the second well region and the substrate surface is located a conductor layer having a second gate length. 其中第二长度大于第一长度,因此形成二突出区域于导体栅极层两侧。 Wherein the second length is greater than the first length, thus forming two projection regions on both sides of the gate conductor layers. 本发明还包括二窗口分别位于各突出区域。 The present invention further includes two windows are located at the respective projecting regions. 其中该导体栅极层所覆盖的该基底表面还包括一栅极氧化层,且所述窗口暴露出部分该栅极氧化层。 Wherein the surface of the conductor substrate covered gate layer further comprises a gate oxide layer, and said window exposing a portion of the gate oxide layer.

Description

高压元件结构技术领域本发明涉及一种高压元件结构,特别是涉及一种可以抑制寄生电流(parasitical current)的高压元件结构。 Element structure of a high pressure FIELD The present invention relates to a high element structure, particularly to a high-voltage element structure can suppress a parasitic current (parasitical current) is. 背景技术近年来,随着移动电话等电子通讯产品的蓬勃发展,其所应用的液晶显示器(liquid crystal display; LCD)的驱动器显得格外的重要。 In recent years, with the rapid development of mobile phones and other electronic communication products, which it is applied LCD (liquid crystal display; LCD) driver is particularly important. 现今业界已开发出32伏特、0.18微米高压工艺技术的产品,以应用于可携式单芯片薄膜晶体管液晶显示器(thin film transistor liquid crystal display; TFT LCD)等领域, 这项技术的特点是可以为栅极驱动、源极驱动及控制器提供不同的电压,使其能够嵌入超高密度的静态随机存取存储器(static random access memory; SRAM)元件中,并制造出面积更小的芯片。 Today the industry has developed a 32 volt, 0.18 micron technology products and a high pressure to be applied to a single chip portable TFT LCD (thin film transistor liquid crystal display; TFT LCD) and other art that this technique is that the characteristics may be a gate driver, a source driver and a controller to provide different voltages, it is possible to embed ultra-high density static random access memory (static random access memory; SRAM) element, and producing a smaller chip area. 请参考图1,图1为现有高压元件结构IO的上视图。 Please refer to FIG. 1, FIG. 1 is a top view of the structure of the conventional high voltage elements of the IO. 如图1所示,高压元件结构IO形成于一P型基底(图未显示)中,包括一第一N型阱区12(如虛线所示区域)、 一第二N型阱区14(如虛线所示区域)、 一连接部分第一N型阱区12与第二N型阱区14的通道扩散区(channel diffusion) 16(如虛线所示区域)及一覆盖于通道扩散区16上方的多晶硅栅极18。 1, the high voltage element formed on an IO structure P-type substrate (not shown), including 12 (shown as a dotted line area) a first N-type well region, a second N-type well region 14 ( the area shown in phantom), a connecting portion 12 and the channel diffusion region (channel diffusion) second N-type well region 14 of the first N-type well region 16 (shown as a dotted line area) and a channel covering the diffusion region 16 above the polysilicon gate 18. 高压元件结构10还包括一源极扩散区20位于第一N型阱区12中、 一漏极扩散区22位于第二N 型阱区14中,以及浅沟隔离(shallow trench isolation )24位于P型基底(图未显示),用以将源极扩散区20、漏极扩散区22及通道扩散区16作良好的隔离。 High voltage element structure 10 further includes a source diffusion region 20 located between the first N-type well region 12, a drain diffusion region 22 in the second N-type well region 14, and a shallow trench isolation (shallow trench isolation) 24 is located in P type substrate (not shown) for the source diffusion region 20, the drain diffusion region 22 and the channel diffusion region 16 as good isolation. 其中,源极扩散区20、漏极扩散区22及多晶硅栅极18分别藉由接触插塞26、 28、 30、 32及34连接外部电路(图未显示)。 Wherein the source diffusion region 20, the drain diffusion region 22 and the polysilicon gate electrode 18 by a contact plug 26, respectively, 28, 30, 32 and 34 are connected to an external circuit (not shown). 为了避免通道扩散区的角落产生漏电流的现象,根据现有技术,高压元件结构10经过改良,使得通道扩散区16的长度大于源极扩散区20及漏极扩散区22的长度。 To avoid corners of the channel diffusion region to generate a leakage current phenomenon, according to the prior art, an improved high-voltage through the element structure 10, such that the length of the channel diffusion region 16 is larger than the length of the source diffusion region 20 and the drain diffusion region 22. 然而,现今元件的尺寸越缩越小,造成通道扩散区16长于源极扩散区20及漏极扩散区22的突出区域36及38具有高栅极电压的地方产生许多寄生电流(parasitical current),并造成不可预测的输出电流电压特性(IV characteristic)曲线。 Today, however, the reduced size of the element is smaller, resulting in the channel diffusion region 16 is longer than the protruding region 20 and source diffusion region 22 and the drain diffusion regions 36 and 38 where the high gate voltage is generated having a number of parasitic current (parasitical current), and cause the output current-voltage characteristic (IV characteristic) curve unpredictable. 发明内容有鉴于此,本发明的主要目的在于提供一种高压元件结构,以解决前述的问题。 SUMMARY OF THE INVENTION Accordingly, the main object of the present invention is to provide a high voltage device structure to solve the foregoing problems. 为达上述目的,根据本发明的优选实施例,本发明的高压元件结构设于一第一导电类型的一基底中,且高压元件结构包含具有第二导电类型的一第一阱区及一第二阱区位于基底中、具有一第一长度的一源极扩散区及一漏极扩散区分别位于第一阱区及第二阱区中以及具有一第二长度的一导体栅极层位于基底表面。 To achieve the above object, according to a preferred embodiment of the present invention, a high-pressure device structure of the present invention is provided on a substrate of a first conductivity type, and a high-voltage device structure including a first well region of a second conductivity type and having a first the second well region located in the substrate, having a source diffusion region and a drain diffusion region of a first length and are located in the first well region and a second well region of the conductive gate layer having a second length located in the basal surface. 其中,第二长度大于第一长度,因此形成二突出区域于导体栅极层两侧。 Wherein the second length is greater than the first length, thus forming two projection regions on both sides of the gate conductor layers. 本发明还包括一栅极氧化层位于导体栅极层所覆盖的基底表面、 一通道扩散区位于被导体栅极层所覆盖的基底中并位于部分第一阱区及第二阱区上方、至少一浅沟隔离位于基底中以隔离源极扩散区、漏极扩散区及通道扩散区以及二窗口分别位于各突出区域。 The present invention further includes a gate oxide layer located on the substrate surface of the conductive layer covered by the gate, a channel located in the base diffusion region is covered by the gate conductive layer and the first well region is located in the upper portion and a second well region, at least a substrate positioned to STI isolation source diffusion region, the drain diffusion regions and a channel region, and two diffusion windows are located in each projection region. 其中,各窗口暴露出部分栅极氧化层。 Wherein each of the gate oxide layer exposing a portion of the window. 由于本发明形成二窗口于导体栅极层两侧突出的区域,故可有效地抑制寄生电流(parasitical current)的产生,并仍保有现有高压元件结构的长通道扩散区可避免通道扩散区的角落产生漏电流现象的优点,因此本发明非常有利于小尺寸的高压元件的制作。 Since the present invention is formed on the conductive gate layer two windows on both sides of the protruding area, it can effectively suppress generation of a parasitic current (parasitical current) and still retains long channel diffusion region prior high pressure passage member structure can avoid diffusion region corner leak current phenomenon to advantage, the present invention is thus very beneficial to production of small-sized high-voltage components. 为了进一步了解本发明的特征及技术内容,请参阅以下有关本发明的详细说明与附图。 To further understand features and technical contents of the present invention, please see the following detailed description and appended drawings of the present invention. 然而附图仅供参考与辅助说明用,并非用来对本发明加以限制。 However, for reference to the accompanying drawings and described with auxiliary, it is not intended to limit the present invention. 附图说明图1为现有高压元件结构的上视图。 Figure 1 is a top view of the conventional high voltage element structure. 图2为本发明的高压元件结构的上视图。 View of a high pressure on the element structure of FIG 2 of the present invention. 图3为图2中沿切线AA,的剖面示意图。 3 is a schematic cross-sectional view in FIG. 2 along the tangent line AA, of. 图4为图2中沿切线BB,的剖面示意图。 FIG 4 is a schematic cross-sectional view in FIG. 2 along the tangent line BB, of. 简单符号说明10 高压元件结构12 第一N型阱区14 第二N型阱区16 通道扩散区18 多晶硅栅极 20 源极扩散区22 漏极扩散区 24 浅沟隔离26 4矣触插塞 28 才妻触插塞30 接触插塞 32 接触插塞34 接触插塞 36 突出区域38 突出区域 50 高压元件结构52 第一阱区 54 第二阱区56 源极扩散区 58 漏极扩散区60 导体栅极层 62 通道扩散区64 突出区域 66 突出区域68 窗口 70 窗口72 接触插塞 74 接触插塞76 接触插塞 78 接触插塞80 接触插塞 82 浅沟隔离84 基底 86 栅极氧化层具体实施方式请参考图2,图2为本发明的高压元件结构50的上视图。 Simple high-pressure element 12 REFERENCE SIGNS 10 first N-type well region 14 the structure 16 of the second N-type well region 18-channel polysilicon gate diffusion region 20 of the source diffusion region 22 drain diffusion region 24 STI 264 carry contact plug 28 wife only contact plug contacts 30 plug contacts 32 plug contacts 34 of the plug 54 of the second well region 36 projecting regions 38 projecting element structure of the high-pressure region 52 50 first well region 56 of the source diffusion region 58 drain diffusion region 60 of the gate conductor projecting window 70 the window 64 region 68 region 66 protruding electrode diffusion layer 62, the channel region 72 in contact with the contact plug 74 plug contacts 76 plug contacts 78 plug contacts 80 of the plug 84 of the substrate 82 a shallow trench isolation gate oxide layer 86 DETAILED DESCRIPTION Please refer to FIG. 2, a top view of a high pressure member 2 of the present invention the structure of FIG. 50. 如图2所示, 本发明的高压元件结构50设于一第一导电类型的一基底(图未显示)中,且该高压元件结构包含具有第二导电类型的一第一阱区52(如虛线所示区域)及一第二阱区54(如虛线所示区域)位于基底中、具有一第一长度L,的一源极扩散区56及一漏极扩散区58分别位于第一阱区52及第二阱区54中、具有一第二长度L2的一导体栅极层60位于基底表面、 一通道扩散区62(如虛线所示区域)位于被导体栅极层60所覆盖的基底中并位于部分第一阱区52及第二阱区54上方以及一栅极氧化层(图未显示)位于导体栅极层60所覆盖的基底表面。 2, the structure of the high-pressure device 50 of the present invention a first conductivity type disposed on a substrate (not shown), and the high-voltage element structure comprises a first well region of a second conductivity type 52 (e.g. the broken line 54 (as indicated by dashed line region area), and a second well region) is located in the substrate, having a first length L, a source diffusion region 56 and a drain diffusion region, respectively, a source 58 located in the first well region 52 and the second well region 54 having a length L2 of a second conductive gate layer 60 is located in the substrate surface 62 (as indicated by a broken line region) is located in a channel diffusion region is covered by the gate conductor layer 60 substrate and located above the first well region 52 and the second well region 54 and a gate oxide layer (not shown) located on the base surface of the conductive gate layer 60 covers. 其中,第一导电类型具有P型掺杂者,第二导电类型具有N型掺杂者, 以使高压元件结构50位于P型掺杂的基底中并具有N型掺杂的第一阱区52 与第二阱区54,或者第一导电类型具有N型掺杂者,第二导电类型具有P 型掺杂者,以使高压元件结构50位于N型掺杂的基底中并具有P型掺杂的第一阱区52与第二阱区54。 Wherein the first conductivity type having a P-type doped by the second conductivity type are N-type dopant having to make structural member 50 is located in the high pressure P-type doped substrate and having a first N-type doped well regions 52 and 54, a first or second conductivity type having an N-type well region doped by the second conductivity type having a P-type dopant are, so that the high pressure structural member 50 is located in the N-type doped substrate and a P-type dopant the first well region 52 and the second well region 54. 导体栅极层60可由多晶硅(poly-silicon)或金属多晶硅化合物与多晶硅所结合的双层结构等等所构成。 The gate conductor layer 60 may be formed of polycrystalline silicon (poly-silicon) of polycrystalline silicon or metal compound bound to the polysilicon-layer structure constituted like. 上述第二长度L2大于第一长度L,,因此导体栅极层60的长度L2大于源极扩散区56及漏极扩散区58的长度L,,于是形成二突出区域64与66 于导体栅极层60两侧,且导体栅极层60两侧的突出区域64与66具有二窗口68与70以暴露出部分栅极氧化层。 The second length L2 is greater than the first length so that the length L ,, L2 conductive gate layer 60 is greater than the length of the source diffusion region 56 and the drain diffusion region 58 thus forming two L ,, protruding region 64 and the gate electrode 66 to the conductor both layers 60, 60 and the conductor layers on both sides of the gate region 64 and the projection 66 has two windows 68 and 70 to expose a portion of the gate oxide layer. 其中,本发明于定义出导体栅极层60 的时候,亦同时形成窗口68与70。 Wherein, when the present invention is to define the conductive gate layer 60, while also forming a window 68 and 70. 通道扩散区62的长度大于源极扩散区56及漏极扩散区58的长度,因此本发明可有效避免通道扩散区62的角落产生漏电流的现象。 Diffusion length of the channel region 62 is larger than the source diffusion region 56 and the drain diffusion zone length 58, and thus the present invention can effectively prevent the corner 62 of the channel diffusion region leakage current phenomenon. 本发明的高压元件结构50还包括接触插塞72、 74、 76、 78及80分别位于源极扩散区56、漏极扩散区58及导体栅极层60的突出区域64上方以连接外部电路(图未显示)以及至少一浅沟隔离(shallow trench isolation)82位于基底中以隔离源极扩散区56、漏极扩散区58及通道扩散区62。 High voltage device structure of the present invention further includes a contact 50 of the plug 72, 74, 76, 78 and 80 are located between the source diffusion region 56, the drain diffusion regions over the protruding region 58 and the gate conductor layer 60 is connected to an external circuit 64 ( not shown) and at least one shallow trench isolation (shallow trench isolation) 82 located in the substrate to isolate the source diffusion region 56, the drain diffusion region 58 and the channel diffusion region 62. 为了更清楚说明本发明的高压元件结构,请参考图3及图4,图3为图2中沿切线AA,的剖面示意图及图4为图2中沿切线BB,的剖面示意图。 To more clearly illustrate the structure of a high-pressure device according to the present invention, please refer to FIG. 3 and FIG. 4, FIG. 2 FIG. 3 is a tangential AA, of a cross-sectional schematic in FIG. 4 and FIG. 2 is a tangential BB, a schematic cross-sectional view. 如图3所示,本发明的高压元件结构50位于第一导电类型的基底84中,包含具有第二导电类型的第一阱区52及第二阱区54位于基底84中、源极扩散区56及漏极扩散区58分别位于第一阱区52及第二阱区54中、导体栅极层60位于基底84表面、通道扩散区62位于被导体栅极层60所覆盖的基底84 中并位于部分第一阱区52及第二阱区54上方、栅极氧化层86位于导体栅极层60与基底84表面之间以及浅沟隔离82位于基底84中以隔离源极扩散区56、漏极扩散区58及通道扩散区62。 3, the structure of the high-pressure device 50 of the present invention, first conductive type substrate 84, comprising a first well region of a second conductivity type well region 52 and the second substrate 54 is positioned 84, the source diffusion region drain diffusion regions 58 and 56 are located in the first well region 52 and the second well region 54, gate conductor layer 60 is located on the surface of the substrate 84, the channel 62 is located in the base diffusion region 84 is covered by the gate conductor layer 60 and located portion 52 and the first well region above the second well region 54, gate oxide layer 86 is located between the gate conductor layer 60 and the surface of the substrate 84 and a shallow trench isolation 82 is located in the substrate 84 to isolate the source diffusion region 56, a drain diffusion region 58 and the channel diffusion region 62. 如图4所示,导体栅极层60的突出区域64具有窗口68以暴露出部分栅极氧化层86。 4, the projection region of the gate conductor 64 layer 60 has a window 68 to expose a portion of gate oxide layer 86. 其中,导体栅极层60覆盖于基底84中的通道扩散区62上方,且基底84中包括浅沟隔离82以形成隔离。 Above 62 wherein the gate conductor layer 60 covering the substrate 84 in the channel diffusion region 84 and the substrate 82 including a shallow trench isolation to form isolated. 相较于现有技术,由于本发明于导体栅极层两侧突出的区域形成二窗而能抑制寄生电流的产生,并能保有现有高压元件结构的长通道扩散区可避免通道扩散区的角落产生漏电流现象的优点,因此本发明非常有利于小尺寸的高压元件的制作。 Compared to the prior art, since the present invention is formed of two windows on both sides of the protruding region of the conductor layers of the gate parasitic current can be suppressed, and to maintain the existing long channel diffusion region to avoid the high pressure passage member structure may be diffusion region corner leak current phenomenon to advantage, the present invention is thus very beneficial to production of small-sized high-voltage components. 以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,皆应属本发明的涵盖范围。 The above are only preferred embodiments of the present invention, all modifications and alterations made under this invention as claimed in claim, also belong to the scope of the present invention.

Claims (16)

  1. 1. 一种高压元件结构,该高压元件结构设于一第一导电类型的一基底中,且该高压元件结构包括: 位于该基底中的具有一第二导电类型的一第一阱区及一第二阱区; 分别位于该第一阱区及该第二阱区中的具有一第一长度的一源极扩散区及一漏极扩散区; 位于该基底表面的具有一第二长度的一导体栅极层,其中该第二长度大于该第一长度,以于该导体栅极层两侧形成二突出区域; 一通道扩散区,位于被该导体栅极层所覆盖的该基底中;以及二窗口,分别位于这些突出区域的该导体栅极层中, 其中该导体栅极层所覆盖的该基底表面还包括一栅极氧化层,且所述窗口暴露出部分该栅极氧化层。 1. A high voltage element structure, the high pressure element structure disposed on a substrate of a first conductivity type, and the high voltage structure element comprising: a substrate located in the first well region having a second conductivity type and a the second well regions, respectively; a source diffusion region is located, and a drain diffusion region having a first length of the first well region and the second well region; located on a surface of the substrate having a second length the gate conductor layer, wherein the second length is greater than the first length, to both sides of the conductive gate layer to form two projecting regions; a channel diffusion region located in the substrate is covered by the gate conductor layer; and two windows, the conductive gate layer located region of these projections, wherein the surface of the conductor substrate covered gate layer further comprises a gate oxide layer, and said window exposing a portion of the gate oxide layer.
  2. 2. 如权利要求1所述的高压元件结构,其中该第一导电类型具有P 型掺杂,该第二导电类型具有N型掺杂。 High voltage element structure of claim 1 as claimed in claim 2, wherein the first conductivity type having a P-type dopant, the second conductive type having N-type dopant.
  3. 3. 如权利要求1所述的高压元件结构,其中该第一导电类型具有N 型掺杂,该第二导电类型具有P型掺杂。 Said high-voltage element structure as claimed in claim 1, wherein the first conductivity type having an N type dopant, the second conductive type having a P-type dopant.
  4. 4. 如权利要求1所述的高压元件结构,其中该导体栅极层为多晶硅所构成。 A high voltage device structure according to claim 1, wherein the conductive layer is a polysilicon gate configuration.
  5. 5. 如权利要求1所述的高压元件结构,其中该通道扩散区位于部分该第一阱区及该第二阱区上方。 A high voltage device structure according to claim 1, wherein the channel portion of the first diffusion region is located well above the second region and the well region.
  6. 6. 如权利要求1所述的高压元件结构,还包括一接触插塞,位于这些突出区域上方。 Said high-voltage element structure as claimed in claim 1, further comprising a contact plug, which is located above the protruding region.
  7. 7. 如权利要求1所述的高压元件结构,还包括至少一接触插塞,位于该源极扩散区上方。 7. The high-voltage device structure according to claim 1, further comprising at least one contact plug, which is located above the source diffusion region.
  8. 8. 如权利要求1所述的高压元件结构,还包括至少一接触插塞,位于该漏极扩散区上方。 8. The structure of the high-pressure device as claimed in claim 1, further comprising at least one contact plug, located above the drain diffusion region.
  9. 9. 如权利要求1所述的高压元件结构,还包括位于该基底中的至少一浅沟隔离,以隔离该源极扩散区、该漏极扩散区及该通道扩散区。 9. The structure of the high-pressure device according to claim 1, further comprising at least one substrate of the shallow trench isolation to isolate the source diffusion region, the drain diffusion region and the channel diffusion region.
  10. 10. —种高压元件结构,该高压元件结构设于一第一导电类型的一基底中,且该高压元件结构包括:位于该基底中的具有一第二导电类型的一第一阱区及一第二阱区;分别位于该第一阱区及该第二阱区中的具有一第一长度的一源极扩散区及一漏极扩散区;位于该基底表面的具有一第二长度的一导体栅极层,其中该第二长度大于该第一长度,于该导体栅极层两侧形成二突出区域;一栅极氧化层,位于该导体栅极层所覆盖的该基底表面;一通道扩散区,位于被该导体栅极层所覆盖的该基底中,并位于部分该第一阱区及该第二阱区上方;位于该基底中的至少一浅沟隔离,以隔离该源极扩散区、该漏极扩散区及该通道扩散区;以及二窗口,分别位于这些突出区域的该导体栅极层中,且这些窗口分别暴露出部分该栅极氧化层。 10. - High Pressure element structure types, structure of the high-voltage components provided on a substrate of a first conductivity type, and the high voltage structure element comprising: a substrate located in the first well region having a second conductivity type and a the second well regions, respectively; a source diffusion region is located, and a drain diffusion region having a first length of the first well region and the second well region; located on a surface of the substrate having a second length the gate conductor layer, wherein the second length is greater than the first length, forming two projecting regions on both sides of the gate conductor layer; a gate oxide layer, located on the substrate surface of the conductor layer covering the gate; and a passage diffusion region of the substrate is located covered by the gate conductive layer, and the portion located above the first well region and said second well region; located in the substrate at least one shallow trench isolation to isolate the source diffusion region, the drain diffusion region and the channel diffusion region; and two windows, which are located in the gate layer conductor protruding region, and these windows are portions of the gate oxide layer is exposed.
  11. 11. 如权利要求IO所述的高压元件结构,其中该第一导电类型具有P型掺杂,该第二导电类型具有N型掺杂。 11. The high-pressure IO claim element structure, wherein the first conductivity type having a P-type dopant, the second conductive type having N-type dopant.
  12. 12. 如权利要求IO所述的高压元件结构,其中该第一导电类型具有N型掺杂,该第二导电类型具有P型掺杂。 IO 12. The high-voltage device structure of claim, wherein the first conductivity type having an N type dopant, the second conductive type having a P-type dopant.
  13. 13. 如权利要求IO所述的高压元件结构,其中该导体栅极层为多晶硅所构成。 13. The high-voltage device structure IO claim, wherein the conductive layer is a polysilicon gate configuration.
  14. 14. 如权利要求IO所述的高压元件结构,还包括一接触插塞,位于这些突出区域上方。 IO 14. The high pressure of the element structure claim, further comprising a contact plug, which is located above the protruding region.
  15. 15. 如权利要求IO所述的高压元件结构,还包括至少一接触插塞,位于该源极扩散区上方。 IO 15. The high-voltage element structure claim, further comprising at least one contact plug, which is located above the source diffusion region.
  16. 16. 如权利要求IO所述的高压元件结构,还包括至少一接触插塞,位于该漏极扩散区上方。 IO 16. The high-voltage element structure claim, further comprising at least one contact plug, located above the drain diffusion region.
CN 200510054315 2005-03-08 2005-03-08 High-tension element structure CN100403551C (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5973362A (en) 1997-04-21 1999-10-26 Lg Semicon, Co., Ltd. Semiconductor device and method for fabricating the same
US6228663B1 (en) 1997-12-19 2001-05-08 Advanced Micro Devices, Inc. Method of forming semiconductor devices using gate insulator thickness and channel length for controlling drive current strength
US6369422B1 (en) 2001-05-01 2002-04-09 Atmel Corporation Eeprom cell with asymmetric thin window

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5973362A (en) 1997-04-21 1999-10-26 Lg Semicon, Co., Ltd. Semiconductor device and method for fabricating the same
US6228663B1 (en) 1997-12-19 2001-05-08 Advanced Micro Devices, Inc. Method of forming semiconductor devices using gate insulator thickness and channel length for controlling drive current strength
US6369422B1 (en) 2001-05-01 2002-04-09 Atmel Corporation Eeprom cell with asymmetric thin window

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