CN100392613C - Device and method for testing communication interface card slot - Google Patents
Device and method for testing communication interface card slot Download PDFInfo
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- CN100392613C CN100392613C CNB991064976A CN99106497A CN100392613C CN 100392613 C CN100392613 C CN 100392613C CN B991064976 A CNB991064976 A CN B991064976A CN 99106497 A CN99106497 A CN 99106497A CN 100392613 C CN100392613 C CN 100392613C
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Abstract
The present invention relates to a device and a method for testing communicating interface card slots to test whether the open circuit, the short circuit and the data transmission of each pin of the communicating interface card slots (such as PCMCIA card slots) normally work or not. Bit length and the bit number of data to be tested or test data with equivalent address bit number are respectively written into memories (such as a common memory, an attribute memory and an input/output area) selected by a micro controller in a Walk0' mode and a Walk1' mode, and are read out to be compared with the written date to judge the open circuit state and the short circuit state of the pins. Thus, a purpose for testing the operating states of the pins of the communicating interface card slots is achieved.
Description
Technical field
The present invention relates to a kind of proving installation and method of communication interface card slot, whether the pin that is applied to the interface draw-in groove of computer detects, normal with the duty of judging each pin.
Background technology
Communication interface card slot is the expansion link slot of present computer indispensability, with the pcmcia card groove of notebook computer be example it have 68 branch connecting pins in order to settle one big little the same with credit card, the function expansion board sheet that thickness is bigger (as: network interface card, FAX/MODEM card, MPEG card or the like) strengthens the function of notebook computer; Present function expansion board sheet can be divided into: I type, II type, three kinds of specifications of III type, the function expansion board sheet of these three kinds of specifications all has and the corresponding position that is connected of 68 branch connecting pins of pcmcia card groove, in order to after 68 branch connecting pins of pcmcia card groove are connected, carry out the transmission of data between notebook computer and function expansion board sheet; But so notebook computer whether the whether working properly of each pin of functions of use extension card, pcmcia card groove will be the place of key to the issue.Detect the computer interface cark mode at present employing Sycard is arranged, it is the test interface card that inserts a special use in the communication interface card slot of computer, cooperate the testing software that is installed in the computer, test interface is sticked into writing and reading of line data, and wherein the inner structure of test interface card includes: one in order to confirm input/output signal and determine the pattern of special pin mistake and the microcontroller of gap, a storer, one in order to the A/D converter and of metered voltage in order to the digital source of sound device of 1kHz audio frequency to be provided; Be that test with whole draw-in groove is divided into the different functional test of array during execution, for example: the unlatching of power supply, data pattern, same bit (Parity) ... or the like, and every employed method of functional test commonly used following dual mode arranged.
1) by the variation of data whether 55AA method: be exactly respectively with " 55h ", " AAh " test data is delivered to test card and is read through identical pin through pin to be measured, with, judge the duty of pin to be measured.
2) enumerative technique: be exactly that each possible data mode test once for instance, if will estimate eight pins simultaneously, then estimating the possible state of data just has 2
8=256 kinds; If simultaneously ten six roots of sensation pins are tested, then the state that test data is possible just has 2
16=65536 kinds.
So when every group of functional test, the accuracy that data (or signal) are transmitted between notebook computer and test card, will be to judge whether each pin in the draw-in groove is the foundation of open circuit or short circuit, that is to say when desire is understood each branch connecting pin whether working properly, just must can judge that this branch connecting pin produces fault after through the test formality more than at least one.Yet the complex structure of above-mentioned proving installation, cost an arm and a leg, it is also comparatively loaded down with trivial details and unsound to estimate method; For example: when even number pin and the short circuit of odd number pin, with the method for " 55AA ", just can't measure, " enumerative technique " then is to make and to cause expending of test duration by the redundant huge of data along with pin count purpose to be measured increases.
Summary of the invention
Fundamental purpose of the present invention be to provide a kind of can be directly to the open circuit of each pin of communication interface card slot, the apparatus and method that short-circuit condition is tested, in order to simplifying complicated proving installation of tradition and loaded down with trivial details test procedure, and cost-saved.
The present invention by to one with pick-up unit that communication interface card slot is connected on the read/write operation of storage unit, judge open circuit, the short circuit condition of each pin of communication interface card slot.Include: a monitoring module and connects the test interface card that the position is formed by generic array logic, a storage unit; Wherein generic array logic produces chip select signal according to a truth table, in order to select common memory, attributes store, the analog input/output region district in the storage unit for use and to simulate special pin memory, so that when each pin of test communications interface draw-in groove, as the read/write of data and the usefulness of user mode judgement.Aspect test data, test data is sent into pick-up unit through communication interface card slot, will read in its self-test device again in the mode of Walk0 ' and Walk 1 '; Whether consistent by the data relatively sent with the data of reading in, judge open circuit, the short-circuit condition of pin.
Realized following favourable effect by apparatus and method of the present invention:
1. by the mode of Walk 0 ' and Walk 1 ', can detect the open circuit short-circuit condition of each pin in the estimating of communication interface card slot immediately.
2. the test duration that reduces test data and shorten communication interface card slot, can improve the work efficiency in the production.
Description of drawings
Relevant detailed content of the present invention and technology, existing accompanying drawings is as follows:
Fig. 1 is the structural representation of detection communication interface card slot of the present invention.
Fig. 2 is the function block schematic diagram of communication interface card groove detection apparatus of the present invention.
Fig. 3 is the structural representation of communication interface card groove detection apparatus of the present invention.
Fig. 4 is the mapping synoptic diagram of communication interface card slot memory areas of the present invention.
Fig. 5 is a notebook data pin test flow chart.
Fig. 6 is an address of the present invention pin test flow chart.
Embodiment
Below the embodiment of Xiang Xishuominging is a notebook computer pcmcia card groove, this for the ease of after explanation, earlier hereinafter mentioned noun, the definition of symbol are explained as follows:
Walk 0 ': be a kind of two data layout, least significant bit (LSB) (LSB) from this two bit data, the output of each data only is set as " 0 " with a position, all the other positions are set as " 1 ", the highest significant position (MSB) of accomplishing these two bits data successively ends, so seem to just look like that one " 0 " moves on to highest significant position from least significant bit (LSB).
Walk 1 ': be a kind of two data layout, least significant bit (LSB) (LSB) from this two bit data, the output of each data only is set as " 1 " with a position, all the other positions are set as " 0 ", the highest significant position (MSB) of accomplishing these two bits data successively ends, and seems to just look like that one " 1 " moves on to highest significant position from least significant bit (LSB).
#: being one of the pin of element and mark of signal wire, is electronegative potential in order to the effective action voltage of representing this pin and signal wire.
D0-D15: be the sign symbol of 16 data pins on the pcmcia card groove, numbering from the 0th number to the ten No. five only, be the data of sixteen bit in order to transmission word string length.
A0-A25: be the sign symbol of 26 address pins on the pcmcia card groove, numbering from the 0th number to the 20 No. five only, in order to the access address of setting data on the function expansion board sheet.
Xxxxxxb: being a data word string, is the scale-of-two word string in order to represent this word string.
Xxxxxxh: being a data word string, is the sexadecimal word string in order to represent this word string.
In the embodiment in figure 1 with a pick-up unit 20 that is inserted in the pcmcia card groove 101 of notebook computer 10, the collocation one detection monitoring module 102 that is installed in the notebook computer 10 carries out the test of each pin on the pcmcia card groove 101, wherein detect monitoring module 102 and be in order in the test process of each pin of pcmcia card groove 101, the program of control pin test, and test data writes/reads the setting of state, and in the display that the results are shown in notebook computer 10 after will testing, or be stored in the memory storage.
Fig. 2 and Fig. 3 are the function block schematic diagram of communication interface card groove detection apparatus of the present invention, with the hardware configuration synoptic diagram, it includes: a draw-in groove linkage unit 11, an attributes store 12, a common memory 13, one analog input/output area 14 and the special pin memory 15 of a simulation; 68 required when wherein draw-in groove linkage unit 11 is formed test by first, second row's pin 111,112 connection runners are formed; Attributes store 12, common memory 13 and 14 of analog input/output areas are to be made of 161,162,163 of three storeies, and these three storeies 161～163 then are the storeies that can heavily cover Writing/Reading for static random-access memory (RAM) and so on; In addition also by the generic array logic (GAL on the circuit board of pick-up unit 20; 17, according to table one and the listed truth table of table two, set the duty of its control pin, produce a chip select signal, in order to the storer 161～163 of when testing, selecting desire to use, so that can carry out writing/reading of test data to attributes store 12, common memory 13 and analog input/output area 14 respectively, the buffer (simulating special pin memory 15) in the generic array logic 17 wherein, the usefulness that writes/read when detecting the specific function pin; Certainly, above-mentioned generic array logic 17 can also be implemented by a micro-control unit (as: dice).
The access in table one, storage space and I/O space selects to set table
Table is set in the selection of table two, shared storage and attributes store
In order to verify to the open circuit short circuit condition of data pin D0-D15 on the communication interface card slot and address pin A0-A25, consulting Fig. 3, is that data pin D0-D7 and address pin A0-A12 in first, second parent form row pin 111,112 are connected in the storer 161,162; Data pin D8-D15 then is to be connected with storer 163 with address pin A13-A25; See also Fig. 4, this line design mode will make the whole memory configurations in the pick-up unit 20 become storeies between the 000h-2000h of address for continuously, and be effective (part of figure bend) in the part of the data word string low level group 201 of each address only; From address 2000h, every interval 2000h has only the high hyte in position 202 effective, that is to say that in address 000h-2000h interval data pin D0-D7 on each address can have the variation on the current potential; From address 2000h, has only the variation on the current potential of having of a data pin D8-D25 on the address every the address of 2000h.
Fig. 5 is a data pin test flow chart of the present invention.During data pin D0-D15 on test pcmcia card groove 101, be divided into two test groups, as follows:
1) to the test of data pin D0-D7:
In the time will testing to data pin D0-D7, between the 0000h-2000h of address, specify an address, and the mode of Walk 0 ' and Walk 1 ' produces the test data (step 31) of test usefulness, wherein test data is " 11111110b "～" 01111111b ", and " 00000001b "～" 10000000b "; Prior to data pin D0-D7 test data " 11111110b " is write on the proving installation 20 interior pairing storage addresss (step 32) during test, and then the data of reading in the proving installation 20 are verified (step 33), if do not occur the variation (data consistent that promptly writes and read) of data exception between the data that write and read, represent that then data pin D0 is for normal; Otherwise as if what occur writing is " 11111110b ", and the result who reads is " 11111111b ", just represents that data pin D 0 is open circuit (step 34); That also also may occur writing be " 11111110b ", the result who reads is " 11110110b " (step 35), so just represent that short-circuit state (step 36) appears in these two data pins of D0 and D3, just unusual pin mark can be got up so detect monitoring module 102; Can judge whether further that then all data pins all tested (step 37) by test data, can not import the test (step 38) that the next record test data continues to do pin again if having; So as long as all have Walk 0 ' and Walk 1 ' to verify one time successively, and note the pin that open circuit or short circuit take place to data pin D0-D7, just can find the state of data pin D0-D7.
2) to the test of data pin D8-D15:
When data pin D8-D15 is tested, employed method is with similar to the test of data pin D0-D7, it also is the mode of adopting Walk 0 ' and Walk 1 ' test data, flow process according to Fig. 5, one by one each data pin is done the checking of open circuit or short circuit, only in the selection of address must in address 2000h, 4000h ..., select one among 1000000h, the 2000000h, and must verify with the test data of sixteen bit, can test high hyte (being data pin D8-D15).
Certainly, after detecting monitoring module 20 and knowing that all data pin D0-D15 all test, just the test result of data pin D0-D15 can be presented on the display screen of notebook computer 10 (step 39); In addition, in above data pin D0-D15 test process, why will be Walk 0 ' and be Walk 1 ' again, its Consideration has following 2 points:
1) when the pin state on the pcmcia card groove 101 is suspension joint, the signal of the pin of flowing through might be a noble potential, also may be electronegative potential; When noble potential, just can measure the state of opening a way in the circuit with Walk 0 ' and whether exist, just must just can measure the state of opening a way in the circuit during electronegative potential with Walk 1 '.
2) when circuit has short circuit phenomenon to exist, and occur in a noble potential data pin and the short circuit of an electronegative potential data pin, so just can't predict test result can be noble potential or electronegative potential (deciding on the signal intensity in the data pin), but the output state of two data pins of this short circuit certainly must be the same, in that is to say at one time, its output is not to be noble potential, is exactly electronegative potential; So, just can judge the circuit of short circuit from the result of output as long as finishing Walk 0 ' and Walk 1 ' afterwards.
Fig. 6 is an address of the present invention pin test flow chart.As the test of data pin D0-D15, during address pin A0-A25 on test computer interface draw-in groove 101, it is as follows also to be divided into two test groups:
1) to the test of address pin A0-A12:
Make address pin A0-A12 have only an address pin with the method for Walk 1 ' is noble potential at every turn, produce the address sequence (step 51) of test institute palpus, as: 0001h, 0002h, 0004h, ..., 1000h, then earlier all addresses are made as " Oxffh ", and in above-mentioned first address (0001h), " 0x00h " write in the proving installation 20 on the pairing storage address (step 52), and then read stored data in the same address (0001h), whether (step 53) conforms to the data that before write (" 0x00h ") with checking, if not representing that then this address pin (being made as noble potential) is open circuit (step 54), detect monitoring module 102 emblems this moment and write down the unusual pin of appearance; And then check one by one whether the data of reading from other address are " 0x00h " (step 55), if there is the phenomenon that address pin short circuit is necessarily arranged between the different addresses that can read " 0x00h " that is to say to take place, so just can read identical data (step 56), and detect monitoring module 102 and it can be noted in different addresses.And then repeat the step of Fig. 6 with the method for Walk 0 ', make that earlier have only an address pin among the pin A0-A12 of address is electronegative potential at every turn, produce test address Offffffeh, Offffffdh, Offffffbh, ..., Offefffh, similarly earlier all addresses being made as " 0x00h " writes on the proving installation 20 interior pairing storage addresss (step 52), again from this storage address with it in stored data read, with checking whether with the data that write earlier (" 0x00h ") conform to (step 53), if not representing that then this address pin (being made as electronegative potential) is open circuit (step 54); And then detect whether the data of reading from other address are " 0x00h " (step 55), if have between the different addresses that to read " 0x00h " that is to say, necessarily there is the phenomenon of address pin short circuit to take place, so just can read identical data (step 56).
2) to the test of address pin A13-A25:
The test mode of address pin A13-A25 is with similar to the test mode of address pin A0-A13, just the address sequence that produces is: 2000h, 4000h, 8000h ..., 1000000h, 2000000h, and must carry out access test with the data of sixteen bit, can be in high hyte (D8-D15) state of address acquisition pin A13-A25, this is that only the data in high hyte (D8-D15) are effective because after the 2000h of address.
Same after testing the address pin, detect monitoring module 20 and just the test result of data pin A0-A25 can be presented on the display screen (step 59) of notebook computer 10.Be that the specific function pin is detected at last, and the specific function pin of pcmcia card groove 101 mentioned herein is meant to include aforementioned data pin D0-D15 and address pin A0-A25 each signal (or power supply) pin in addition:
CD1#, CD2#: card detects, and is used for the measuring ability extension card whether to insert draw-in groove 101.
CS1#, VS2#: voltage sensor is used for the voltage that the measuring ability extension card supported.
BVD1, BVD2: battery voltage detection, whether the battery that is used on the measuring ability extension card is normal.
VPP1#, VPP2#: be used to provide program voltage.
RESET: the reset signal that the function expansion board sheet is provided.
... or the like.In the register of generic array logic 17, all have and the corresponding bit space of these specific function pins, writing/reading of data can be provided when detecting; But because of voltage that VPP1, VPP2 provided up to 12 volts, (IC is as TTL) receivable voltage so earlier with resistance 21～24 voltage is reduced to integrated circuit respectively.When testing via the data pin D0 (or D1) that is connected with generic array logic 17, set the state (wherein the setting of specific function pin state can be undertaken by the mode of coding) of specific function pin, again by data pin D0 (or D1) being read again the specific function pin state in the register that leaves generic array logic 17 in, afterwards by comparing setting value and read value, have not bad with checking specific function pin, so after having detected all specific function pins, just test result is shown on the display screen of notebook computer 10.
Though the present invention discloses as above with embodiment, so it is not in order to limiting the present invention, anyly knows this technology, does not break away from the spirit and scope of the present invention, change and modify can do some, so this protection domain should be looked accompanying claim and defines and be as the criterion.
List of numerals
10 notebook computers, 101 draw-in grooves
102 module of detecting and controllings, 11 draw-in groove linkage units
111 first parent forms row pin, 112 second parent forms row pin
12 attributes store, 13 common memories
14 analog inputs/special the pin memory of output area 15 simulations
161 memories, 162 memories
163 memories, 17 GALs
20 pick-up units, 201 low hytes
202 high hyte 21 resistance
22 resistance, 23 resistance
30 beginnings of 24 resistance
31 set the address of test usefulness and with 32 input test data
The mode of Walk 0 ' and Walk 1 ' produces
Test data
It is whether the data of opening a way out conform to that 33 each data pin of detection write with reading 34 these data pins
Whether 35 other address pins of detection are read has short circuit that identical data take place between 36 data pins
37 whether all data pins all surveyed 38 input next record test datas and tried
39 show test results 40 finishes
50 beginnings 51 are with Walk 0 ' and Walk 1 '
The address to be measured that the mode initialization is all
52 in address to be measured input one test several 53 detect and to write and to read
Whether conform to according to data
54 these address pins detect other address pin for open circuit 55
Whether read identical data
There is short circuit that whether all 57 address pins take place between 56 address pins
All tested
The next address 59 to be measured of 58 tests shows test results
60 finish
Claims (16)
1. the method for testing of a communication interface card slot in order to detect several data pins in the computer interface draw-in groove, the steps include:
A. specify a memory address;
B. specify a test data, this test data produces in the mode of Walk 0 ' or in the mode of Walk 1 ';
C. this test data is written into this memory address of a memory storage;
D. obtain the active data that is stored on this memory address; And
E. judge whether this obtained in this test data and steps d active data conforms to, and determines open circuit, the short-circuit condition of pin according to the result of above-mentioned judgement, thereby finds out unusual data pin, and it is recorded in the recording medium that a computer-readable writes.
2. the method for testing of communication interface card slot according to claim 1 is characterized in that the address of this appointment is corresponding to a memory storage.
3. as the method for testing of communication interface card slot as described in the claim 2, wherein, this memory storage includes: an attributes store, a shared storer and one analog input/output area.
4. the method for testing of communication interface card slot according to claim 1, wherein, the recording medium of this computer-readable/write is hard disk.
5. the method for testing of a communication interface card slot, in order to detect several address pins in the communication interface card slot, its step comprises:
A. specify one group of test data;
B. specify several memory addresss, these several memory addresss produce the content on these several memory addresss of initialization subsequently in the mode of Walk 0 ' or in the mode of Walk 1 ';
C. this test data is written into respectively on this memory address;
D. obtain the active data that is stored on this memory address respectively;
E. judge whether this obtained in this test data and steps d active data conforms to, and determines open circuit, the short-circuit condition of pin according to the result of above-mentioned judgement, thereby finds out unusual address pin, and it is recorded in the recording medium that a computer-readable writes.
6. as the method for testing of communication interface card slot as described in the claim 5, wherein, the address of this appointment is corresponding to a memory storage.
7. as the method for testing of communication interface card slot as described in the claim 6, wherein, this memory storage includes: an attributes store, a shared storer and one analog input/output area.
8. as the method for testing of communication interface card slot as described in the claim 5, wherein, this is readable/recording medium be hard disk.
9. the proving installation of a communication interface card slot is installed in this communication interface card slot, and with so that one in the notebook computer detects the action that supervising device can be done data and writes/read this proving installation, this proving installation includes:
One I/O unit is in order to be connected with this computer interface draw-in groove;
One storage unit has an attributes store, a common memory and one analog input/output area, can store the data from this I/O unit;
One generic array logic can produce a wafer and select signal, selects to use a wherein district of this storage unit according to the data of I/O; And
The special pin memory of one simulation is located in this generic array logic, in order to storage and corresponding these data of the special pin of this communication interface card slot.
10. as the proving installation of communication interface card slot as described in the claim 9, wherein, this storage unit is the storer that EEPROM can heavily cover Writing/Reading.
11. as the proving installation of communication interface card slot as described in the claim 9, wherein, these data are an address word string.
12. as the proving installation of communication interface card slot as described in the claim 11, wherein, this address word string system produces in the mode of Walk 0 '.
13. as the proving installation of communication interface card slot as described in the claim 11, wherein, this address word string produces in the mode of Walk 1 '.
14. as the proving installation of communication interface card slot as described in the claim 9, wherein, these data are a test data.
15. as the proving installation of communication interface card slot as described in the claim 14, wherein, this test data produces in the mode of Walk 0 '.
16. as the proving installation of communication interface card slot as described in the claim 14, wherein, this test data system produces in the mode of Walk 1 '.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB991064976A CN100392613C (en) | 1999-05-14 | 1999-05-14 | Device and method for testing communication interface card slot |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB991064976A CN100392613C (en) | 1999-05-14 | 1999-05-14 | Device and method for testing communication interface card slot |
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| Publication Number | Publication Date |
|---|---|
| CN1274115A CN1274115A (en) | 2000-11-22 |
| CN100392613C true CN100392613C (en) | 2008-06-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB991064976A Expired - Fee Related CN100392613C (en) | 1999-05-14 | 1999-05-14 | Device and method for testing communication interface card slot |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100388223C (en) * | 2002-08-29 | 2008-05-14 | 中兴通讯股份有限公司 | Internal storage detecting method |
| DE10344877B3 (en) * | 2003-09-26 | 2004-12-30 | Infineon Technologies Ag | Testing and monitoring circuit with interface card for data storage module has motherboard carrying storage module, microcontroller EEPROM, timing generator and interface card voltage source |
| CN100401084C (en) * | 2004-06-22 | 2008-07-09 | 大唐移动通信设备有限公司 | Inserted card tester |
| CN1330135C (en) * | 2004-07-01 | 2007-08-01 | 华为技术有限公司 | Detector |
| CN104932958B (en) * | 2014-03-18 | 2018-11-06 | 神讯电脑(昆山)有限公司 | Computer card class equipment interface function automatic detection method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996007968A1 (en) * | 1994-09-02 | 1996-03-14 | Telefonaktiebolaget Lm Ericsson | A method and a system for testing an interface |
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1999
- 1999-05-14 CN CNB991064976A patent/CN100392613C/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996007968A1 (en) * | 1994-09-02 | 1996-03-14 | Telefonaktiebolaget Lm Ericsson | A method and a system for testing an interface |
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| CN1274115A (en) | 2000-11-22 |
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