CN100388389C - Method for providing high external voltage for flash stoving & delate - Google Patents
Method for providing high external voltage for flash stoving & delate Download PDFInfo
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- CN100388389C CN100388389C CNB001362399A CN00136239A CN100388389C CN 100388389 C CN100388389 C CN 100388389C CN B001362399 A CNB001362399 A CN B001362399A CN 00136239 A CN00136239 A CN 00136239A CN 100388389 C CN100388389 C CN 100388389C
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- voltage
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- positive voltage
- deletion
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Abstract
In the present invention, an external high voltage is connected to a unit to be deleted in a chip comprising a flash memory. When an external voltage is used, an internal voltage exciting circuit is cut off. The external voltage, a high negative voltage and a high positive voltage are respectively connected to a grid electrode and a source electrode of a selected unit to be deleted through a voltage control module, wherein the external voltage efficiently execute the function of deletion during programming/deletion in the manufacture. After a flash memory unit is assembled onto a circuit board by a user, an internal high voltage exciting circuit is used for deleting the flash memory unit. Part of the voltage control module is formed by two level switching circuits, and voltage is added to the flash memory unit by a voltage switching circuit which also provides selection voltage and unselection voltage for unit deletion.
Description
Technical field
The present invention relates to semiconductor memory, particularly relate to flash memory (flash memory) and provide voltage for deletion action.
Background technology
In existing flash memory, the data of deletion flash cell need high negative voltage and high positive voltage.High negative voltage is added to the grid of flash cell, and high positive voltage is added to source electrode.It is unsettled usually to drain.If flash cell will be deleted after assembling like this; Just positive voltage exciting circuit and negative voltage exciting circuit need be set in flash chip.When opposite polarity two exciting circuits are present in same chip, there are several problems just must solve.Except improving chip power, need suitable holding circuit and quarantine measures to isolate exciting circuit and to avoid the device collapse.
The deletion action of using the internal motivation circuit to carry out flash cell is a relatively slow process, and this is because need certain hour to reach required voltage after exciting circuit is activated.Therefore it is favourable providing high negative voltage and high positive voltage from the outside to chip in the programming of manufacture process and deletion, and this can quicken programmed process.In the manufacturing of flash cell, provide high forward voltage by known a period of time; But owing to handle all difficulties of high negative voltage; Provide high negative voltage not use as yet at present from the outside.By outside added high negative voltage and outside added high positive voltage are provided to the chip that comprises flash memory, can shorten deletion/programming, reduce power consumption and faster production.
Summary of the invention
The invention discloses a kind of Method and circuits; It can allow from the outside to the chip that comprises or do not comprise high negative voltage exciting circuit and high positive voltage exciting circuit that comprises flash cell, increases negative voltage and high positive voltage and gives the wherein flash cell of desire row deletion.High negative voltage and high positive voltage are connected to chip by chip pin and are used in manufacture process chip deletion and programming.If after assembling, do not need flash cell is deleted and programmed, high positive voltage exciting circuit and high negative voltage exciting circuit are not set on chip, then high negative voltage pin and high positive voltage pin are the unique voltage sources that carries out the flash memory deletion.
Have high negative voltage exciting circuit and high positive voltage exciting circuit if comprise the chip of flash cell, this chip can be deleted by the user/programme after assembling.In this case, the output terminal that outside high negative voltage and high positive voltage are connected to corresponding exciting circuit concurrently, this exciting circuit Be Controlled is ended when using external high voltage.Use external high voltage to shorten the deletion/programming time when before assembling, making, reduce power consumption and make output with improving.If there is not external voltage to be connected to high negative voltage pin and high positive voltage pin, then the user deletes/programmes flash cell and must use the internal motivation circuit after assembling.
A high negative voltage level switching circuit, its use are arranged in a P type trap nmos pass transistor of the on-chip dark N type trap of a P type, provide the biasing of flash cell grid to select or remove choosing.For avoiding when the negative voltage of increasing give to be desired the grid of delete cells forward bias, for nmos pass transistor has used three well structures that comprise a P type trap that is arranged in the on-chip dark N type trap of a P type to PN junction.The grid that this negative voltage level switching circuit is carried out the flash cell of deletion to desire provides a high negative voltage and provides a moderate positive voltage to the flash cell that desire is not carried out deletion.
High negative voltage level switching circuit constitutes a part that is positioned at a voltage control module on the chip that comprises flash memory.The control signal that is connected to control module provides the instruction of the output state that instructs high negative voltage level switching circuit, make its switch in a high negative voltage with the flash cell of selecting the deletion of desire row and a moderate positive voltage to remove the flash cell that selects the deletion state.Level switching circuit comprises the N channel transistor of pair of cross coupling, and two kinds of modes of operation are provided.A voltage selecting circuit that comprises two p channel transistors is connected to the N channel transistor that this pair of cross is coupled through a biasing buffer circuit, to select one between two kinds of modes of operation.Voltage selecting circuit is switched by two input voltages, these two input voltages make the N channel transistor of this pair of cross coupling switch between two states, and drive difference channel make its switch in a high negative voltage with the grid of the flash cell of selecting the deletion of desire row and a moderate positive voltage to remove the grid that the flash cell of state is being deleted in choosing.
Similar with high negative voltage level switching circuit, a high positive voltage level switching circuit provide a high positive voltage to the flash cell of desire row deletion source electrode and provide a moderate positive voltage to remove the source electrode of the flash cell of choosing from deletion action to desire.The high positive voltage level switching circuit uses the PMOS transistor be arranged in the on-chip N type of P type trap, for the source electrode of flash cell provides biasing to select and remove choosing.For avoiding forward bias PN junction when high positive voltage is added to the source electrode of unit of desire row deletion, p channel transistor is placed in the N type trap.This positive voltage level commutation circuit provide a high positive voltage to the flash cell of desire row deletion source electrode and provide a moderate positive voltage to the source electrode of the unit of desire row deletion not.
The high positive voltage level switching circuit constitutes a part that is positioned at the voltage control module on the chip that comprises flash memory.The control signal that is connected to control module provides the instruction of the output state that instructs the high positive voltage level switching circuit, make its switch in a high positive voltage with the flash cell of selecting the deletion of desire row and a moderate positive voltage to remove the flash cell that selects the deletion state.Level switching circuit comprises the p channel transistor of pair of cross coupling, and two kinds of modes of operation are provided.A voltage selecting circuit that comprises two N channel transistors is connected to the p channel transistor that this pair of cross is coupled through a biasing buffer circuit, to select one between two kinds of modes of operation.Voltage selecting circuit is switched by two input voltages, and these two input voltages make the p channel transistor of this pair of cross coupling switch between two states; And drive difference channel make its switch in a high positive voltage with the source electrode of the flash cell of selecting the deletion of desire row and a moderate positive voltage to remove the source electrode of the flash cell that selects the deletion state.
The delete function that needs an exciting circuit or an external chip pin and only use a voltage to offer flash cell also is possible.This can accomplish by voltage reversal, promptly adds a negative voltage and gives high postivie grid deletion voltage, and source electrode deletion voltage just becomes the chip forward bias voltage like this.Then adding this same negative voltage gives high negative-gate voltage and keeps unsettled semiconductor substrate for drain electrode.This voltage reversal has been eliminated the demand to high positive source voltage, and has eliminated the demand to the high positive voltage exciting circuit.
Description of drawings
Following the present invention is described in more detail with reference to accompanying drawing, wherein
Fig. 1 a shows the synoptic diagram of the flash cell of setovering for deletion action in the prior art;
Fig. 1 b shows the basic synoptic diagram of prior art chips voltage;
Fig. 2 shows the synoptic diagram of a flash chip voltage;
Fig. 3 shows connection side's block diagram of exciting circuit and an external voltage and a voltage control module on a flash chip;
Fig. 4 a shows the electrical schematic diagram of a level switching circuit, and it provides the grid of a high negative voltage to the flash cell of desire row deletion;
Fig. 4 b shows the electrical schematic diagram of a level switching circuit, and it provides the source electrode of a high positive voltage to the flash cell of desire row deletion; With
Fig. 5 shows the process flow diagram of the method for using external voltage deletion flash cell in the mill.
Embodiment
Fig. 1 a shows the example of the flash cell of desire row deletion in the prior art, and this flash cell uses a high negative voltage bias.The control utmost point (grid) G is biased to a high negative voltage Vnn.This negative voltage for example can be approximately-8.5v as shown in the figure.Source S is biased to a high positive voltage Vpp, and Vpp is higher than chip bias voltage Vdd.Vpp for example is approximately+5V as shown in the figure.Drain D is unsettled, and semiconductor substrate B is 0V.Be to satisfy voltage conditions as shown in Figure 1a, need be by the external chip pin or/and be positioned at builtin voltage exciting circuit on the flash chip, two high voltages are provided.Fig. 1 b shows the synoptic diagram of prior art chip substrate, and it connects external voltage and thinks the flash chip power supply.Vdd and Vss are the chip bias voltages, and Vpp is the source electrode that a high positive voltage offers the flash cell of desire row deletion.Vnn voltage shown in Fig. 1 b is produced by the internal motivation circuit that is positioned on the flash chip.
Fig. 2 shows the basic synoptic diagram that connects according to the external chip voltage of flash chip of the present invention.Except that general flash chip voltage Vdd and Vss, also have a high positive voltage Vpp and a high negative voltage Vnn one to be connected to this chip.Vnn and Vpp provide external voltage, to delete flash cell in programming in manufacture process and the deletion action expeditiously.Fig. 3 is a block scheme, shows being connected and inner exciting circuit 12 and 13 of outside Vpp chip pin 10 and Vnn chip pin 11.Positive external voltage Vpp is connected to chip pin 10 and further is connected to voltage control module 14 concurrently with the output of positive voltage exciting circuit 13.Negative external voltage Vnn is connected to chip pin 11 and further is connected to voltage control module 14 concurrently with the output of negative voltage exciting circuit 12.Chip bias voltage Vdd and Vss are negative voltage exciting circuit 12 and 13 power supplies of positive voltage exciting circuit.Chip bias voltage Vdd and Vss and be voltage module 14 power supply.One group selection signal S (0) is provided for voltage control module 14 to S (k), in order to the voltage of grid G, source S and the drain D of selecting to be connected to flash cell.
Still as shown in Figure 3, when flash cell was programmed in manufacture process or deletes, external voltage Vpp and Vnn were connected respectively to Vpp pin one 0 and Vnn pin one 1.When supplying with Vpp and Vnn from the outside, positive internal voltage exciting circuit 13 and negative internal voltage exciting circuit 12 end, and voltage control module 14 obtains high positive voltage and obtains high negative voltage from Vnn pin one 1 from Vpp pin one 0.When not having outside Vpp and Vnn voltage, negative internal voltage exciting circuit 12 provides Vnn to voltage control module 14 in deletion action, and positive internal voltage exciting circuit 13 provides Vpp to voltage control module 14.Select signal S (0) to control voltage control module the grid of voltage to each flash cell, source electrode and drain electrode are provided, to select or to remove and select deletion, programming and read operation to S (k).
Fig. 4 a shows a level switching circuit, and it is for producing the part of voltage control module 14 that Vout exports to the grid of the flash cell in the deletion action.The switching state that Vout depends on circuit can be Vnn or Vss.Vnn is that a high negative voltage is used to delete flash cell; Vss is that a chip bias voltage is used for selecting flash cell from deleting to remove.Input voltage vin can make output voltage V out switch between Vss and Vnn in switching between Vdd and the Vss.Input voltage vin is connected to selects circuit 20.Select circuit 20 to comprise two p channel transistor Q1 and Q2, their grid links together through a negative circuit Inv1, and Vin is connected to the grid of Q1.Select circuit 20 to drive pair of cross coupling N channel transistor 22 through a biasing buffer circuit 21.Biasing buffer circuit 21 provides some voltage drops between Vdd and the Vnn, to reduce potential crash issue.One difference channel is driven by cross-couplings circuit 22, depends on input voltage vin and produces level switching output Vout.N channel transistor Q3, Q4, Q5, Q6, Q7 and Q8 are formed at one and bias in the P type trap of Vnn.This P type trap is arranged in and is formed at the dark N type trap that a P type on-chip that biases to Vss biases to Vdd.
Still with reference to Fig. 4 a, when Vin=Vss, Vdd by selecting circuit 20 Q1 and the Q3 of voltage buffer circuit 21, be added to the drain electrode of Q5 of cross-couplings two-state circuit 22 and the grid of Q6.The Q6 conducting, Vnn is added to the drain electrode of Q6 and the grid of Q5 and Q8.Transistor Q5 ends, and Vdd is connected to the grid of Q7, and it produces output Vout=Vss.Transistor Q7 and Q8 constitute a difference channel 23, and it produces the output of level switching circuit.When Vin=Vdd, Vdd by selecting circuit 20 Q2 and the Q4 of voltage buffer circuit 21, be added to the drain electrode of Q6 of cross-couplings two-state circuit 22 and the grid of Q5.The Q5 conducting, Vnn is added to the drain electrode of Q5 and the grid of Q6 and Q7.Transistor Q6 ends, and Vdd is connected to the grid of Q8, and it produces output Vout=Vnn.
Fig. 4 b shows a level switching circuit, it is for producing the part of voltage control module 14 that Vout exports to the source electrode of the flash cell in the deletion action, and its output Vout switches between Vdd and Vss along with input voltage river Vin and switches between a high positive voltage Vpp and Vdd.The circuit of the circuit of Fig. 4 b and Fig. 4 a is similar, and just voltage is different with transistor types.Input voltage vin is connected to one and selects circuit 30.Select circuit 30 to comprise two N channel transistor Q11 and Q12, their grid links together through a negative circuit Inv2, and Vin is connected to the grid of Q11.Select circuit 30 to drive pair of cross coupling p channel transistor 32 through a biasing buffer circuit 31.Biasing buffer circuit 31 provides some voltage drops between Vss and the Vpp, to reduce potential crash issue.One difference channel 33 is driven by cross-couplings circuit 32, depends on input voltage vin and produces level switching output Vout.P channel transistor Q13, Q14, Q15, Q16, Q17 and Q18 are formed at one and bias in the N type trap of Vpp.This N type trap is formed at one and biases on the P type substrate of Vss.
Continuation is with reference to Fig. 4 b, when Vin=Vss, Vss by selecting circuit 30 Q12 and the Q14 of voltage buffer circuit 31, be added to the drain electrode of Q16 of cross-couplings two-state circuit 32 and the grid of Q15.The Q15 conducting, Vpp is added to the drain electrode of Q15 and the grid of Q16 and Q17.Transistor Q16 ends, and Vss is connected to the grid of Q18, and it produces output Vout=Vpp.Transistor Q17 and Q18 constitute a difference channel 33, and it produces the output of level switching circuit.When Vin=Vdd, Vss by selecting circuit 30 Q11 and the Q13 of voltage buffer circuit 31, be added to the drain electrode of Q15 of cross-couplings two-state circuit 32 and the grid of Q16.The Q16 conducting, Vpp is added to the drain electrode of Q16 and the grid of Q15 and Q18.Transistor Q15 ends, and Vss is connected to the grid of Q17, and it produces output Vout=Vdd.
Fig. 5 shows the method for using external voltage deletion flash cell in the mill.In step 40, inner high negative voltage and inner high positive voltage are cut off.Then a high negative voltage is connected to high negative voltage chip pin, i.e. Vnn pin in step 41.In step 42, a high positive voltage is connected to the high positive voltage chip pin, i.e. the Vpp pin.In step 43, voltage control module 14 is connected to high negative voltage selection the grid of the flash cell of desire row deletion.In step 44, voltage control module 14 is connected to the high positive voltage selection source electrode of the flash cell of desire row deletion.The drain electrode of selected flash cell is unsettled in deletion action.In step 45, selected flash cell is deleted by Fu Le-Nuo Dehan tunneling method (Fowler-Nordheim Tunneling method).
Although the present invention is had been described in detail and explains with reference to above embodiment, institute it should be understood that and can change and do not break away from the spirit and scope of the present invention form of the present invention and details that it all should be included among the claim scope of the present invention.
Claims (15)
1. circuit that flash cell biasing is provided in deletion action comprises:
A) a negative voltage exciting circuit produces high negative voltage and is connected to a voltage control module;
B) a positive voltage exciting circuit produces high positive voltage and is connected to described voltage control module;
C) another provides first voltage source of described high negative voltage to be connected to described voltage control module from the outside by one first chip pin;
D) another provides second voltage source of described high positive voltage to be connected to described voltage control module from the outside by one second chip pin;
E) described voltage control module provides the biasing of grid, drain electrode and source electrode in the deletion action of flash cell; Wherein, described voltage control module comprises the first level handover module and the second level handover module;
The described first level handover module is used for providing gate bias in the flash memory deletion, and the described first level handover module selects circuit, the first biasing buffer circuit, the first cross-couplings circuit and first difference channel to form by first;
Described second level switching circuit is used for providing source electrode and drain bias in the flash memory deletion, and described second level switching circuit selects circuit, the second biasing buffer circuit, the second cross-couplings circuit and second difference channel to form by second.
2. circuit as claimed in claim 1 is characterized in that wherein said voltage control module provides the biasing of flash cell grid, drain electrode and source electrode, to select or to remove the unit of a collection of selected materials journey, deletion and read operation.
3. circuit as claimed in claim 1, it is characterized in that, wherein when described high negative voltage and described high positive voltage were connected to the described voltage control module of flash chip from the outside, described negative voltage exciting circuit and described positive voltage exciting circuit Be Controlled were ended.
4. circuit as claimed in claim 1 is characterized in that, wherein when programming occurs over just in the factory to flash chip, need not described positive voltage exciting circuit and described negative voltage exciting circuit.
5. circuit as claimed in claim 1 is characterized in that, wherein outside high positive voltage and the high negative voltage that connects provides the programming of acceleration to flash chip.
6. circuit as claimed in claim 1 is characterized in that, wherein more is not higher than in the voltage of flash cell in deletion under the situation of positive voltage of chip biasing, need not the high positive voltage that described positive voltage exciting circuit is connected with described outside.
7. level switching circuit, it provides gate bias in the flash memory deletion, comprise: a) pair of cross coupling N channel transistor constitutes a bifurcation circuit;
B) one select circuit, be connected to described pair of cross coupling N channel transistor by a biasing buffer circuit, described selection circuit comprises two p channel transistors, and the grid of two p channel transistors connects by a negative circuit;
C) difference channel, described difference channel are connected to described pair of cross coupling N channel transistor, and wherein difference channel is made of two N channel transistors;
D), control the state of described pair of cross coupling N channel transistor, to select the output voltage of described difference channel to the input of described selection circuit;
E) described difference channel, be used for providing the gate bias of flash cell in deletion action, two N channel transistors of described difference channel and described biasing buffer circuit and pair of cross coupling N channel transistor form in the P type trap that is offset in a P type on-chip one dark N type trap.
8. level switching circuit as claimed in claim 7 is characterized in that, the output of wherein said difference channel along with the switching of input between two kinds of input voltages to described selection circuit, and switches between a high negative voltage and the positive voltage.
9. level switching circuit as claimed in claim 7, it is characterized in that, wherein when described difference channel is switched king's selection mode by described selection circuit, described difference channel provides the grid of a high negative voltage to the flash cell of desire row deletion, remove when selecting state when described difference channel is switched to by described selection circuit, described difference channel provides the grid of a positive voltage to the flash cell of not deleting.
10. level switching circuit, it provides source-biased in the flash memory deletion, comprise: a) pair of cross coupling p channel transistor constitutes a bifurcation circuit;
B) one select circuit, connect inferior described pair of cross coupling p channel transistor by a biasing buffer circuit;
C) difference channel, the described described pair of cross coupling p channel transistor that is connected to, wherein said difference channel is made of two p channel transistors;
D) to the elm A of described selection circuit, control the state of described pair of cross coupling p channel transistor, to select the output voltage of described difference channel, wherein, described selection circuit comprises two N channel transistors, and the grid of two N channel transistors connects by a negative circuit.；
E) described difference channel provides the source-biased of flash cell in deletion action, and two p channel transistors of described difference channel and described biasing buffer circuit and pair of cross coupling p channel transistor are formed at one and bias in the on-chip N type trap of a P type.
11. level switching circuit as claimed in claim 10 is characterized in that, the output of wherein said difference channel along with the switching of input between two kinds of input voltages to described selection circuit, and switches between one first positive voltage and one first positive voltage.
12. level switching circuit as claimed in claim 10, it is characterized in that, wherein when described difference channel is switched to selection mode by described selection circuit, described difference channel provides the source electrode of one first positive voltage to the flash cell of desire row deletion, when described difference channel is switched to when removing fan's state by described selection circuit, described difference channel provides the source electrode of one first positive voltage to the flash cell of not deleting.
13. the method that external voltage is provided in the deletion action to flash cell comprises: a) by inner high negative voltage exciting circuit;
B) by inner high positive voltage exciting circuit;
C) connect the outside high negative voltage chip pin of a high negative voltage to;
D) connect the outside high positive voltage chip pin of a high positive voltage to;
E) draw the grid of selecting the high negative voltage in described outside to be connected to the flash cell of desire row deletion;
F) select described outside high positive voltage to be connected to the source electrode of the flash cell of desire row deletion;
G) use Fu Le-Nuo Dehan tunneling method to gather around and remove selected flash cell.
14. method as claimed in claim 13 is characterized in that, wherein connecting described high negative voltage and described high positive voltage to described chip pin is to carry out in the mill, to delete described flash cell.
15. method as claimed in claim 13 is characterized in that, wherein deletes flash cell and only carries out in the mill, has eliminated the needs to high negative voltage exciting circuit in described inside and described inner high positive voltage exciting circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001362399A CN100388389C (en) | 2000-12-25 | 2000-12-25 | Method for providing high external voltage for flash stoving & delate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001362399A CN100388389C (en) | 2000-12-25 | 2000-12-25 | Method for providing high external voltage for flash stoving & delate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1361536A CN1361536A (en) | 2002-07-31 |
| CN100388389C true CN100388389C (en) | 2008-05-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001362399A Expired - Lifetime CN100388389C (en) | 2000-12-25 | 2000-12-25 | Method for providing high external voltage for flash stoving & delate |
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| Country | Link |
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| CN (1) | CN100388389C (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1100823A (en) * | 1993-07-13 | 1995-03-29 | 株式会社日立制作所 | A flash memory and a microcomputer |
| US5455794A (en) * | 1993-09-10 | 1995-10-03 | Intel Corporation | Method and apparatus for controlling the output current provided by a charge pump circuit |
| US5483486A (en) * | 1994-10-19 | 1996-01-09 | Intel Corporation | Charge pump circuit for providing multiple output voltages for flash memory |
-
2000
- 2000-12-25 CN CNB001362399A patent/CN100388389C/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1100823A (en) * | 1993-07-13 | 1995-03-29 | 株式会社日立制作所 | A flash memory and a microcomputer |
| US5455794A (en) * | 1993-09-10 | 1995-10-03 | Intel Corporation | Method and apparatus for controlling the output current provided by a charge pump circuit |
| US5483486A (en) * | 1994-10-19 | 1996-01-09 | Intel Corporation | Charge pump circuit for providing multiple output voltages for flash memory |
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| Publication number | Publication date |
|---|---|
| CN1361536A (en) | 2002-07-31 |
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