CN100383754C - Method and apparatus for qualifying collection of performance monitoring events by types of interrupt when interrupt occurs - Google Patents

Method and apparatus for qualifying collection of performance monitoring events by types of interrupt when interrupt occurs Download PDF

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Publication number
CN100383754C
CN100383754C CNB2005100046186A CN200510004618A CN100383754C CN 100383754 C CN100383754 C CN 100383754C CN B2005100046186 A CNB2005100046186 A CN B2005100046186A CN 200510004618 A CN200510004618 A CN 200510004618A CN 100383754 C CN100383754 C CN 100383754C
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China
Prior art keywords
interrupt
performance monitoring
incident
system
interruption
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CNB2005100046186A
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Chinese (zh)
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CN1648871A (en
Inventor
小吉米·E·德威特
弗兰克·E·莱文
克里斯托弗·M·理查森
罗伯特·J·厄克特
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国际商业机器公司
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Priority to US10/757,186 priority Critical patent/US7895382B2/en
Priority to US10/757,186 priority
Application filed by 国际商业机器公司 filed Critical 国际商业机器公司
Publication of CN1648871A publication Critical patent/CN1648871A/en
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Publication of CN100383754C publication Critical patent/CN100383754C/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466Performance evaluation by tracing or monitoring
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466Performance evaluation by tracing or monitoring
    • G06F11/348Circuit details, i.e. tracer hardware
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/86Event-based monitoring
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/88Monitoring involving counting
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/885Monitoring specific for caches

Abstract

A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring unit (PMU) is used to program hardware counters that collect events associated with a type of interrupt, including nested interrupts. The performance monitoring unit may also count events that occur while servicing interrupt requests based upon the state of interrupt processing. Events that are known to the performance monitoring unit such as instruction retired, TLB misses, may be counted at the same time using a number of performance monitoring counters in the performance monitoring unit.

Description

Press the method and apparatus of its type-restriction collection of performance monitoring events when taking place to interrupt

Technical field

Usually, the present invention relates to a kind of improved data handling system, specifically, relate to a kind of in data handling system when take place interrupting the method and system of monitoring processor performance.More particularly, the present invention relates to a kind of method, device and computer instruction, be used for when taking place to interrupt, limiting (qualify) collection the monitoring events performance by interrupt type.

Background technology

Typical data handling system utilizes processor to carry out one group of instruction to carry out particular task, for example reads specific character from primary memory.Yet along with the number of tasks purpose that needs processor to carry out increases, for the slip-stick artist who wishes optimization system, processor becomes key factor to the efficient of the access module of storer and the characteristic of this type of visit.

Current, prior art comprise can the enumeration data disposal system in the frequency of software alternative (for example cache miss, performed instruction, I/O data transmission requests), and the mechanism of carrying out the given needed time of process.A kind of this type of mechanism is performance monitor.Performance monitor carries out the supervision to selected characteristic, thereby helps systematic analysis by the machine state of determining special time.This analysis provides following information: when how execution command the time uses processor, and when storing data the reciprocation of processor and primary memory.In addition, performance monitor can provide in the disposal system institute's elapsed time amount between the incident.The event count that performance monitor provides the slip-stick artist can be used for analyzing system performance.This analysis may cause that application code changes, and for example possible redistributes branch instruction and memory access, with further optimization system performance.In addition, performance monitor can be collected relevant the processor how one-level of visit data disposal system and the data of second level cache and primary memory, to find the performance bottleneck specific to hardware or software environment.

Aforesaid performance monitor does not provide following function: further limit the interruption event for particular type.For example when initiating look-at-me, interrupt, incident has taken place with notification processor such as equipment such as mouse or keyboards.When processor was accepted interrupt request, processor was finished its present instruction, and sent control to interrupt handling routine (handler).Interrupt handling routine is carried out the Interrupt Service Routine that is associated with this interruption.Interrupt also may causing, for example the product of Motorola Inc.---68000 TRAP by particular machine language manipulation code.In this case, do not expect that such as division by 0 etc. software condition makes processor storage current state, store the identification information of relevant specific interruption, and control sent to handle this and do not expect the interrupt handling routine of software condition.

Below be useful: have a kind of improved method, device and computer instruction, be used for limiting the counting of event, interrupt according to the interrupt type services request that has taken place simultaneously.

Summary of the invention

The invention provides a kind of method, device and computer instruction, when taking place to interrupt in the processor in data handling system, it limits incident by pressing interrupt type, comes the performance of monitoring data disposal system.Performance monitoring unit of the present invention is programmed the incident that limits based on the interrupt type that has taken place of counting.When performance monitoring unit detected the interruption of particular type, performance monitoring unit was collected this interrupt type event.Result's event information is presented to the user later on to carry out performance evaluation.

Description of drawings

Listed the distinctive novel feature of the present invention in the claims.To understand the present invention self better, preferably use pattern and further purpose and advantage by reference accompanying drawing and following detailed description exemplary embodiment, wherein:

Fig. 1 is for realizing the exemplary block diagram of data handling system of the present invention;

Fig. 2 is the exemplary block diagram of the processor system of disposal system according to the preferred embodiment of the present invention;

The exemplary illustration of Fig. 3 for showing according to the preferred embodiment of the present invention, pressing the assembly of interrupt type counting event when central broken hair is given birth to;

Fig. 4 for show according to the preferred embodiment of the present invention, the exemplary illustration of the assembly of performance monitoring unit and interrupt location;

Fig. 5 is for summarize showing according to the preferred embodiment of the present invention, limiting process flow diagram to the example procedure of the counting of incident based on interrupt type when central broken hair is given birth to.

Embodiment

The performance of preferred implementation of the present invention monitoring data disposal system when executive routine on data handling system.In one embodiment, performance monitoring unit is programmed, with counting event (for example cache miss, clock period or other events in execution of interrupting and processing procedure), and the state that the interrupt type by incident takes place in its process and (in some embodiments), the interruption of incident took place in its process limits the incident that those are counted.The information of collecting in System and method for of the present invention can be presented to software or user to analyze.

In a preferred embodiment, the present invention is implemented in the computer system.For example, this computer system can be client or the server under the client-server environment of network.Referring now to Fig. 1, shown the exemplary block diagram that wherein can realize data handling system of the present invention.Client 100 is the example of computing machine, wherein can place the code or the instruction that realize processing of the present invention.Client 100 adopts periphery component interconnection (PCI) local bus architecture.Though shown example adopts pci bus, can use other bus architectures, for example Accelerated Graphics Port (AGP) and ISA(Industry Standard Architecture).Processor 102 is connected to PCI local bus 106 with primary memory 104 by PCI bridge 108.PCI bridge 108 can also comprise the high-speed cache of processor 102 and integrated Memory Controller.By direct assembly interconnect or by inserting plate, can proceed to other connections of PCI local bus 106.In the example shown, Local Area Network adapter 110, small computer system interface SCSI host bus adaptor 112 and expansion bus interface 114 are connected to PCI local bus 106 by direct assembly interconnect.Different therewith, audio frequency adapter 116, graphics adapter 118 and audio/video adapter 119 are connected to PCI local bus 106 by the insertion plate that inserts in the expansion slot.Expansion bus interface 114 is provided for being connected of keyboard and mouse adapter 120, modulator-demodular unit 122 and annex memory 124.SCSI host bus adaptor 112 is provided for the connection of hard disk drive 126, tape drive 128 and CD-ROM drive 130.Typical PCI local bus is realized supporting three or four pci expansion slots or is inserted connector.

Operating system and is used for coordinating and provides control for various assemblies in the data handling system 100 of Fig. 1 on processor 102.Operating system can be the operating system that can buy on the market, Windows XP for example, and it can obtain from Microsoft.Such as Object oriented programming systems such as Java can with the operating system cooperation, and provide the application program or java applet the calling of carrying out from client 100 to operating system." Java " is the trade mark of Sun Microsystems company.The instruction of operating system, Object oriented programming system and application program or program is positioned on the memory device, for example on the hard disk drive 126, and can be loaded in the primary memory 104, to be carried out by processor 102.

Those skilled in the art should understand that: the hardware among Fig. 1 may change according to realization.Except that hardware shown in Figure 1, perhaps substitute these hardware ground, can use other internal hardwares or peripherals, for example the nonvolatile memory of flash ROM (ROM), equivalence or CD drive or the like.In addition, processing of the present invention can be applied to multi-processor data process system.

For example, if client 100 is configured to network computer alternatively, then can not comprise SCSI host bus adaptor 112, hard disk drive 126, tape drive 128 and CD-ROM 130.In this case, this computing machine correctly should be called client computer, comprises certain type network communication interface, for example lan adapter 110, modulator-demodular unit 122 or the like.As another example, client 100 can be a system independently, and it is configured to guidable, and does not rely on certain type network communication interface, and no matter whether client 100 comprises certain type network communication interface.As another example, client 100 can be a PDA(Personal Digital Assistant), and it is equipped with ROM and/or flash rom, so that nonvolatile memory to be provided, is used for the data that storage operating system file and/or user generate.Example shown in Fig. 1 and above-mentioned example are not the restriction that is used for inferring to architecture.

Processing of the present invention is carried out by processor 102 instruction that realizes that uses a computer, and these instructions may be arranged in storer, and for example primary memory 104, storer 124 perhaps are arranged in one or more peripherals 126-130.

Forward Fig. 2 to, shown to be used for the exemplary block diagram of processor system of process information according to the preferred embodiment of the present invention.Processor 210 can be implemented as the processor 102 among Fig. 1.

In a preferred embodiment, processor 210 is single integrated circuit superscalar microprocessor.Correspondingly, discussed in more detail below, processor 210 comprises various unit, register, impact damper, storer and other parts, and all these is formed by integrated circuit.In addition, in a preferred embodiment, processor 210 is according to reduced instruction set computer (" RISC ") technical operation.As shown in Figure 2, system bus 211 is connected to the Bus Interface Unit (" BIU ") 212 of processor 210.The transmission of information between BIU 212 processor controls 210 and the system bus 211.

BIU 212 is connected to the instruction cache 214 and data cache 216 of processor 210.Instruction cache 214 output orders are to sequencing unit 218.In response to from instruction cache 214 these the instruction, sequencing unit 218 optionally output order to other executive circuits of processor 210.

Except that sequencing unit 218, in a preferred embodiment, the executive circuit of processor 210 also comprises a plurality of performance elements, i.e. branch units 220, fixed point unit A (" FXUA ") 222, fixed point unit B (" FXUB ") 224, complicated fixed point unit (" CFXU ") 226, load/store unit (" LSU ") 228 and floating point unit (" FPU ") 230.FXUA 222, FXUB 224, CFXU 226 and LSU 228 are from general system register (" GPR ") 232 and fixed point rename impact damper 234 its source operand information of input.In addition, FXUA 222 imports " carry digit " with FXUB 224 from carry digit (" CA ") register 239.FXUA 222, FXUB 224, CFXU 226 and LSU 228 output its operation results (destination operand information) are with selected place's storage in fixed point rename impact damper 234.In addition, CFXU 226 from/to special register processing unit (" SPR unit ") 237 input and output source operand information and destination operand information.

FPU 230 is from floating-point system register (" FPR ") 236 and floating-point rename impact damper 238 its source operand information of input.FPU 230 output its operation results (destination operand information) are with selected place's storage in floating-point rename impact damper 238.

In response to load instructions, LSU 228 is from data cache 216 input informations, and with this information copy selected in rename impact damper 234 and 238.If this information is not stored in the data cache 216, then data cache 216 is imported these information (by BIU 212 and system bus 211) from the system storage 260 that is connected to system bus 211.In addition, data cache 216 can be from data cache 216 output informations to the system storage 260 that is connected to system bus 211 (by BIU 212 and system bus 211).In response to storage instruction, LSU 228 is from GPR 232 selected input information with FPR236, and with this information copy to data cache 216.

Sequencing unit 218 from/to GPR 232 and FPR 236 input and output informations.From sequencing unit 218, the instruction and the signal of branch units 220 input instruction processorunits 210 current states.In response to these instructions and signal, branch units 220 (to sequencing unit 218) output indication storage is by the signal of the suitable storage address of the instruction sequence of processor 210 execution.In response to these signals from branch units 220, sequencing unit 218 is from the indicated instruction sequence of instruction cache 214 inputs.If one or more instruction sequence is not stored in the instruction cache 214, then instruction cache 214 system storage 260 these instructions of input (by BIU 212 and system bus 211) from being connected to system bus 211.

In response to the instruction from instruction cache 214 inputs, sequencing unit 218 optionally divides the performance element 220,222,224,226,228 and 230 that sends instructions to selected.Each performance element is carried out one or many instructions of specific instruction classification.For example, 224 pairs of source operands of FXUA 222 and FXUB are carried out the fixed-point arithmetic computing of first category, for example addition, subtraction, with or and XOR.CFXU226 carries out the fixed-point arithmetic of second classification, for example fixed-point multiplication and division to source operand.230 pairs of source operands of FPU are carried out floating-point operation, for example floating-point multiplication and division.

When information stores during at rename impact damper 234 selected, the specified memory location of this information and the instruction of the rename impact damper of selecting for its distribution be associated (for example among the GPR 232 or carry digit (CA) register 242).In response to the signal from sequencing unit 218, canned data is copied into (perhaps the CA register 242) that it is associated among the GPR 232 at the selected item place of rename impact damper 234.Generate this information instruction in response to " finishing ", sequencing unit 218 commanders are to the described copy at 234 selected places of rename impact damper canned data.This copy is called " writing back ".

When information stores during at rename impact damper 238 selected, one among this information and the FPR 236 is associated.In response to the signal from sequencing unit 218, canned data is copied into one that it is associated among the FPR 236 at the selected item place of rename impact damper 238.Generate this information instruction in response to " finishing ", sequencing unit 218 commanders are to the described copy at 238 selected places of rename impact damper canned data.

By handling many instructions simultaneously at each performance element 220,222,224,226,228 and 230 places, processor 210 reaches high-performance.Correspondingly, every instruction is taken as a series of phase process, each stage all can with the stage executed in parallel of other instructions.This technology is called " streamline ".According to an importance of illustrated embodiment, instruction generally is treated to six stages, promptly obtains, decodes, distributes, carries out, finishes and write back.

In the stage of obtaining, sequencing unit 218 (from instruction cache 214) is optionally imported one or many instructions from one or more storage address, and described storage address has been stored top conjugate branch unit 210 and the sequencing unit 218 further instruction sequences of discussing.

At decode phase, sequencing unit 218 nearly four instructions of being obtained of decoding.

In distribution phase, after the result's (destination operand information) who is the instruction of being distributed had kept the rename buffer entries, sequencing unit 218 (in response to the decoding of decode phase) was optionally distributed nearly four and is decodedly instructed several in the selected performance element 220,222,224,226,228 and 230.In distribution phase, operand information is provided for the selected performance element for the instruction of being distributed.Processor 210 sends instructions by its programmed sequence branch.

In the execute phase, performance element is carried out its instruction of distributing, and exports its operation result (destination operand information), with selected place's storage in rename impact damper 234 and rename impact damper 238, as mentioned above.In this way, processor 210 can execute instruction out of sequence with respect to its programmed sequence.

In the stage of finishing, sequencing unit 218 indicators are " finishing ".Processor 210 " is finished " instruction by its programmed sequence.

Writing back the stage, sequencing unit 218 commanders distinguish copy information to GRP 232 and FPR 236 from rename impact damper 234 and 238.Sequencing unit 218 commanders are to the described copy at selected rename impact damper place canned data.Similarly, in the stage that writes back of specific instruction, in response to specific instruction, processor 210 upgrades its system status.Processor 210 " writes back " stage by each of its programmed sequence processing instruction.Preferably, under particular cases, the stage of finishing of processor 210 merge commands with write back the stage.

In illustrated embodiment, every instruction all requires a machine cycle to finish each stage of instruction process.Yet some instruction (for example complexity fixed point instruction of being carried out by CFXU 226) may require more than one-period.Therefore, in response to finishing the previous instruction variation of required time, in the execution of specific instruction and finish between the stage variable delay may take place.

In sequencing unit 218, be equipped with and finish impact damper 248, be used for following the tracks of the performance of many instructions of in performance element, carrying out.When an instruction or one group of instruction have successfully been finished in indication,, finish impact damper 248 and can be used to start these results that finished instruction of transmission to the general-purpose register that is associated according to the specified sequencing of application program.

In addition, processor 210 also comprises performance monitoring unit 240, and this unit is connected to other unit in instruction cache 214 and the processor 210.Utilize performance monitoring unit 240, operation that can monitoring processor 210, in illustrated embodiment, performance monitoring unit 240 is a software-accessible mechanism, it can provide a description the details of utilizing situation and storage control that resource is carried out in instruction.Though in Fig. 2, do not show, but performance monitoring unit 240 is coupled to each functional unit of processor 210, to allow all aspects of monitoring processor 210 operations, including (for example) the relation between the reconstruction incident, sign erroneous trigger, sign performance bottleneck, monitor flows pipeline stall, monitor idle processor cycle, determine distribution efficient, determine branch's efficient, determine the misaligned data visit performance loss, frequency that the sign serialized instructions is carried out, identify forbidden interruption and determinacy energy efficiency.Interested incident also comprises the time of (for example) instruction decoding, execution, branch's incident, cache miss and the cache hit of instruction.

Performance monitoring unit 240 comprises the counter 214-242 of the number (for example 2-8) that depends on realization, is labeled as PMC1 and PMC2, and it is used for counting the frequency of selected incident.Performance monitoring unit 240 also comprises at least one MONITOR MODE control register (MMCR).In this example, there are two control registers, MMCR 243 and 244, it specifies the function of counter 241-242.Preferably, counter 241-242 and MMCR 243-244 are embodied as the SPR that can read or write visit by MFSPR (moving from SPR) that is carried out by CFXU 226 and MTSPR (moving to SPR).Yet, replacing in the embodiment one, counter 241-242 and MMCR 243-244 can be implemented as the address in the input/output space simply.Replace in the embodiment at another, control register and counter can be visited indirectly by indexed registers.This embodiment is implemented in the IA-64 architecture in the processor of Intel company.

In addition, processor 210 also comprises interrupt location 250, and it is connected to instruction cache 214.In addition, although do not show in Fig. 2, interrupt location 250 is connected to other functional units in the processor 210.Interrupt location 250 can receive the signal from other functional units, and starts action, for example begins fault processing or trap process.In these examples, interrupt location 250 usefulness generate the exception and the interruption that may take place in program process.In addition,, corresponding interrupt location control register (IUCR) is arranged all for wait each performance monitoring counter such as PMC1 241, for example can be by the IUCR2 252 of interrupt location 250 visits.In this example, IUCR1 252 is corresponding to PMC1 241.IUCR2252 is corresponding to PMC2 242.Which interrupts generating signal for IUCR1 252 and IUCR2 254 signs, thereby PMC1 241 can count the incident that is associated with this interruption with PMC2 242.

The invention provides a kind of method, device and computer instruction, be used for when taking place to interrupt in the processor in data handling system, limit incident, monitor such as data handling system performances such as clients among Fig. 1 100 by pressing interrupt type.The processor of this data handling system can be implemented as the processor 210 of Fig. 2.

In a preferred embodiment, the invention provides performance monitoring unit (PMU), the performance monitoring unit among Fig. 2 240 for example, it can utilize such as MMCR 243 and the programming of MMCR 244 counter control registers such as grade (CCR), with counting event in interrupting implementation.The incident of being counted can be limited by the interrupt type that this incident takes place in its process.These incidents are current to be known for performance monitoring unit, and the instruction of for example returning, TLB error, second level cache is lost or clock period or the like.In a preferred embodiment, performance monitoring unit of the present invention allows the user to limit incident or condition, preferably hardware counter and the register by utilizing performance monitoring unit by interrupt type.When sending look-at-me, look-at-me is used to identify counter mechanism of the present invention and whether is programmed next intercourse counting event in the type.

Counter control register (CCR) in can the scalability monitor unit is to comprise interrupt location (IU) track field, interrupt location (IU) mode field and interrupt location (IU) state mask field.IU track field allows the user by enabling or forbidding that track following controls counting.The IU mode field is represented the current state of Interrupt Process, for example break, interrupt with picked, interrupt to be identified and to interrupt the pass.The state of the Interrupt Process of track following will take place in the indication of IU state mask field during it.These field do as one likes can be used by monitor unit, with counting event during the various states that interrupt, and press the state analysis counting.Result's data can be read by user or track application program, for example from performance monitoring unit, read, and carrying out performance evaluation afterwards, thus optimization system better.

In addition, utilize a plurality of performance monitoring counters, performance monitoring unit can be counted a plurality of incidents simultaneously.Mechanism of the present invention allows performance monitoring unit to programme each counter with the counting particular event.For example, counter 1 can be programmed the cache miss of counting for interrupt vector 1, and counter 2 can be programmed count cycle of counting for interrupt vector 2 or the like.Preferred implementation of the present invention does not limit the qualification for counter.According to the hardware that the user can use, counter can be programmed a plurality of incidents of counting.

In addition, the incident of performance monitoring unit support counting nested interrupt.When another interruption took place in an interrupt enable, nested interrupt promptly took place.Performance monitoring unit of the present invention makes the performance monitoring counter counting can be only limited in the state that opens or closes of Interrupt Process.Study the efficient of Interrupt Process self for the slip-stick artist, this mechanism comes in handy.

Then forward Fig. 3 to,, shown when broken hair is given birth in the middle of being used for exemplary plot by the assembly of interrupt type counting event according to preferred implementation of the present invention.As shown in Figure 3, in a preferred embodiment, CPU (central processing unit) (CPU) 302 can be implemented as the processor 210 among Fig. 2.When central broken hair was given birth to, CPU (central processing unit) (CPU) 302 sent a signal to interrupt location 304, with the look-at-me of request interrupt location 304 generations for the specific interruption type.

According to the number of performance monitoring counter in the performance monitoring unit 306, interrupt location 304 can comprise a plurality of interrupt location control registers (IUCR), and they can be by interrupt location 304 visits.Between IUCR and performance monitoring counter, has one-one relationship.In this example, have two IUCR, corresponding to the IUCR1 308 of performance monitoring counter PMC1 312, and corresponding to the IUCR2 310 of performance monitoring counter PMC2 314.Such as the IUCR containing type field of IUCR1 308, which kind of interrupt type is this field indicate generate the performance monitoring counter signals.Whether, to watch it be interested interrupt type, promptly whether want counting event in interrupting implementation if being checked by interrupt location 304 after the type field among the IUCR.If the interrupt type signal is interested interrupt type, then interrupt location 304 sends track following ON/OFF signal to performance monitoring unit 306, to enable or to forbid counting.

In addition, as shown in Figure 3, performance monitoring unit 306 comprises the hardware counter of the number that depends on realization, and for example hardware counter 312 and 314 is also referred to as the performance monitoring counter herein.PMC1 312 and PMC2 314 counting events during the particular state of Interrupt Process.Performance monitoring unit 306 comprises also that such as a plurality of counter control registers (CCR) such as CCR1 316 and CCR2 318 it can be implemented as MCCR1 233 and MCCR2 234 among Fig. 2.When receiving from interrupt location 304, CCR1 316 and CCR2 318 enable or when forbidding the signal of the incident of track following interrupt type during Interrupt Process and state variation, by storage current state of interrupting and the state for the treatment of the interruption of track following, CCR1 316 and the counting of CCR2 318 control performances supervision counter PMC1 312 with PMC2 314, thereby when enabling track following, performance monitoring counter PMC1 312 and PMC2 314 can count the incident of specific interruption state.The track data of event memory then, and the time is collected result's track data from performance monitoring counter 312 and 314 afterwards.

With reference to Fig. 4,, shown the exemplary plot of the assembly of display performance monitor unit and interrupt location according to preferred implementation of the present invention.As shown in Figure 4, in a preferred embodiment, performance monitoring unit can comprise a plurality of counter control registers (CCR), and it can be implemented as memory mode register (MMCR), for example MMCR1 among Fig. 2 233 and MMCR2 234.The counter control register control performance monitors the function of counter.Counter control register 402 can comprise 3 fields: interrupt location (IU) track field 404, interrupt location (IU) mode field 406 and interrupt location (IU) state mask field 408.In this example, IU track field 404 is a bit field, by position 0 expression; IU mode field 406 is two bit fields, by position 1 and 2 expressions; IU state mask field 408 is three bit fields, by position 3 to 5 expressions.

As shown in Figure 4, track 410 is the example of IU track field 404.When this position was 0, the track following of performance monitoring counter was for closing or being under an embargo.When this position was 1, the track following of performance monitoring counter was for opening or being enabled.Track 410 is provided with by track following ON/OFF signal, in case interrupt location checks that interrupt location control register (IUCR) is to determine whether interrupt type is interested, and this track following ON/OFF signal is sent by interrupt location.For example, the look-at-me of input can with handle interruption set appointment, storage for counting relatively.

Then, state 416 expression IU mode fields 406 examples.416 do as one likes of state can read by monitor unit, and are used for storing the current state of interruption.When the interruption state when breaking 418, the position in the state 310 is set to 01.Picked 420 the time for interrupting when the interruption state, the position in the state 410 is set to 10.When the interruption state was identified 422 for interruption, the position in the state 410 was set to 11.When the interruption state closed 424 for interruption, the position in the state 410 was set to 00.

Last field in the counter control register is an IU state mask field 408.The example of state mask 426 expression IU state mask field 408.IU state mask field 426 indications counting event during which interruption status.When the state of during it, counting when breaking 428, state masked bits 426 is set to 001.Picked 430 the time for interrupting when the state of counting during it, state masked bits 426 is set to 010.When the state of counting during it was identified for interruption, state masked bits 426 was set to 100.

At last, in Fig. 4, shown interrupt location control register (IUCR) 440.IUCR can be visited by interrupt location.IUCR 440 comprises the type field 442 that size is a byte (8).Type field 442 which kind of interrupt type of expression will generate the track following ON/OFF signal to performance monitoring unit.

Preferred implementation of the present invention can be used for coming counting event based on the type that the interruption of incident takes place during it.At IUCR field record interrupt type, the interrupt type that this field indication monitors incident during it will take place.When central broken hair was given birth to, the item among interrupt type and the IUCR compared, and if the item among the interrupt match IUCR that is taken place, then count in this intercourse event.Send signal to open track following to PMU, this makes PMU CCR be set to the state of the interruption of generation this moment.When central cracked ends was crossed its state, PMU continued indication and interrupts being in which kind of state, thereby can analyze the incident of counting at this intercourse according to the interruption status that incident takes place during it.

Forward Fig. 5 to, according to preferred implementation according to the present invention show summarize in the middle of broken hair limit general flowchart based on interrupt type when giving birth to the exemplary process of the counting of incident.As shown in Figure 5, when support software (for example performance monitoring software) and hardware interface when starting Interrupt Process (step 502), begin this processing.The performance monitoring counter is set to monitor some incident (step 504), for example cache miss or clock period by support software then.Support software also is provided with interrupt location control register (IUCR) type field, monitors which kind of interrupt type (step 506) with indication, promptly wants counting event during which interrupt type.Then, the support software setting is corresponding to being used for interrupt location (IU) the track field (step 508) the performance monitoring counter, counter control register (CCR) of counting event.Step 508 enables the track following to incident.

Certain hour after step 508 is provided with IU track field, execution will monitor the application code (step 510) of the application program of its performance.When interrupting (step 512) when at code the term of execution, interrupt location is checked IUCR type field (step 514).Judge that to this interruption is whether identical with the IUCR type IUCR type is an interested interrupt type (step 516).If this interrupt type is different from the IUCR type, then this process is returned step 512, interrupts taking place to wait for next.If this interrupt type is identical with the IUCR type, then interrupt location sends track following ON/OFF signal, and this signal is sent to performance monitoring unit (step 518), with beginning track following interrupt event.In case receive this signal, performance monitoring unit is 01 by the status word section that counter control register is set just, and the mode field of counter control register is set to break (step 520).

Then, interruption status become interrupt picked, interrupt location and then send state-change, and this signal is sent to performance monitoring unit (step 522).Subsequently, performance monitoring unit is 10 by the status word section that counter control register is set, and the mode field that counter control register is set is for interrupting picked (step 524).Another interruption status changes makes interrupt location send state-change, and this signal is sent to performance monitoring unit (step 526).Similarly, performance monitoring unit is 11 by the status word section that counter control register is set, and the mode field that counter control register is set is for interrupting being identified (step 524).When the interruption handling procedure was finished the execution Interrupt Service Routine, it sent IRET (interruption is returned) signal (step 530) to interrupt location.Interrupt location sends track following ON/OFF signal, and this signal is sent to performance monitoring unit, to stop the incident (step 532) that track following interrupts.(note: embodiments of the present invention can be crossed over one or more interruption status and be carried out track following, as mentioned above.) final, performance monitoring unit receives this signal, and is set to 00 by counter control register status word section, and the counter control register mode field is set to interrupt closing (step 534).Thus, this is handled and ends.

Thus, the invention provides a kind of performance monitoring unit, it allows the user to use one or more hardware counter to limit event by interrupt type.Hardware counter is collected event when interrupt request, so that the user can monitor the system performance when handling the particular type interruption.By utilizing a plurality of hardware counter of the present invention, the user can limit the different event of different interrupt types.

Performance monitoring unit also makes the user limit event according to the state of Interrupt Process, thereby the user can further be collected in event during the specific interruption state.In addition, performance monitoring unit provides following support: by utilizing the counter that is associated with nested interrupt, make the user can limit event when nested interrupt takes place.In addition, performance monitoring unit can also be counted under the specific interruption state condition such as specific interruption types such as clock period.

Though be noted that and described the present invention at the situation of global function data handling system, but those skilled in the art should understand that process of the present invention can distribute with the form and the various forms of computer-readable medium of instruction, and no matter the particular type of the actual signal bearing medium that is used for carrying out this distribution why, is suitable for the present invention equally.But the example of computer-readable medium comprises the record type medium, for example floppy disk, hard disk drive, RAM, CD-ROM, DVD-ROM and transmission type medium, for example numeral and analog communication links are used the wired or wireless communication link such as delivery forms such as radio frequency and light wave transmission.Computer-readable medium can adopt the form of coded format, and described coded format is decoded when reality is used in the particular data disposal system.

The description of this invention is for displaying and description purpose, rather than the present invention limit or that be limited to disclosed form.For those skilled in the art, obviously there are many modifications and variation.Select with the embodiment of describing so that explain principle of the present invention and practical application best, and make those skilled in the art understand the various embodiments that the present invention has the various modifications that are suitable for contemplated practical application.

Claims (12)

1. be used for the system of monitor performance when broken hair is given birth in the middle of one kind, comprise:
Performance monitoring unit;
One or more is positioned at the hardware counter of performance monitoring unit;
Wherein said one or more hardware counter is according to the frequency of counting at the interrupt type of intercourse generation incident in the incident of the intercourse of selecting interrupt type.
2. the system as claimed in claim 1, the state of wherein said interruption comprises: receive look-at-me, start the interrupt handling routine routine of interrupting, finish the interrupt handling routine routine and interrupt returning.
3. the system as claimed in claim 1 is wherein counted polytype incident at intercourse.
4. the system as claimed in claim 1, wherein said incident comprises clock period and cache miss.
5. the system as claimed in claim 1, wherein second interrupts first and interrupts, and wherein said hardware counter is counted discretely in first intercourse and the second intercourse event.
6. one kind is used for the method for monitor system performance in interrupt procedure, comprises following steps:
Microprocessor place in this system receives the signal that starts interruption, and wherein this interruption comprises a plurality of states; And
For the selected state in a plurality of states of this interruption, count at least one incident during it according to the interrupt type that incident takes place.
7. method as claimed in claim 6, wherein said counting step comprise at least one incident of each Count of Status for a plurality of states that interrupt.
8. method as claimed in claim 6, wherein said a plurality of states comprise: receive look-at-me, start the interrupt handling routine routine of interrupting, finish the interrupt handling routine routine and interrupt returning.
9. method as claimed in claim 6, wherein said incident comprises clock period and cache miss.
10. method as claimed in claim 6, wherein said counting step comprises: for the equal state of interrupting, count polytype incident.
11. method as claimed in claim 6, wherein said counting step is undertaken by one or more hardware counter.
12. method as claimed in claim 6, wherein first interrupts by second interruption, and wherein hardware counter is counted discretely in first intercourse and the second intercourse event.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102576327A (en) * 2009-09-29 2012-07-11 国际商业机器公司 Enhanced monitor facility

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7373637B2 (en) 2003-09-30 2008-05-13 International Business Machines Corporation Method and apparatus for counting instruction and memory location ranges
US7395527B2 (en) 2003-09-30 2008-07-01 International Business Machines Corporation Method and apparatus for counting instruction execution and data accesses
US7421681B2 (en) 2003-10-09 2008-09-02 International Business Machines Corporation Method and system for autonomic monitoring of semaphore operation in an application
US8381037B2 (en) 2003-10-09 2013-02-19 International Business Machines Corporation Method and system for autonomic execution path selection in an application
US7895382B2 (en) 2004-01-14 2011-02-22 International Business Machines Corporation Method and apparatus for qualifying collection of performance monitoring events by types of interrupt when interrupt occurs
US7526757B2 (en) 2004-01-14 2009-04-28 International Business Machines Corporation Method and apparatus for maintaining performance monitoring structures in a page table for use in monitoring performance of a computer program
US7415705B2 (en) 2004-01-14 2008-08-19 International Business Machines Corporation Autonomic method and apparatus for hardware assist for patching code
US7421684B2 (en) 2004-03-22 2008-09-02 International Business Machines Corporation Method and apparatus for autonomic test case feedback using hardware assistance for data coverage
US7720670B2 (en) * 2005-05-16 2010-05-18 Texas Instruments Incorporated Saving resources by deducing the total prediction events
US20070174717A1 (en) * 2006-01-10 2007-07-26 Sun Microsystems, Inc. Approach for testing instruction TLB using user/application level techniques
US7617421B2 (en) * 2006-07-27 2009-11-10 Sun Microsystems, Inc. Method and apparatus for reporting failure conditions during transactional execution
US8656411B2 (en) * 2008-03-05 2014-02-18 Intel Corporation Technique for monitoring activity within an integrated circuit
JP5119994B2 (en) * 2008-03-14 2013-01-16 富士通株式会社 Performance monitoring program, performance monitoring method, performance monitoring device
TWI400618B (en) * 2009-05-26 2013-07-01
JP5423232B2 (en) * 2009-08-17 2014-02-19 富士通株式会社 Process state detection program, information processing apparatus, and process state detection method
JP5310819B2 (en) * 2010-11-29 2013-10-09 株式会社デンソー Microcomputer
US9720744B2 (en) 2011-12-28 2017-08-01 Intel Corporation Performance monitoring of shared processing resources
US9971603B2 (en) 2011-12-29 2018-05-15 Intel Corporation Causing an interrupt based on event count
US9575766B2 (en) 2011-12-29 2017-02-21 Intel Corporation Causing an interrupt based on event count
US9003236B2 (en) * 2012-09-28 2015-04-07 Intel Corporation System and method for correct execution of software based on baseline and real time information
US9075639B1 (en) * 2012-10-23 2015-07-07 Altera Corporation Systems and methods for handling interrupts during software design simulation
US9292288B2 (en) 2013-04-11 2016-03-22 Intel Corporation Systems and methods for flag tracking in move elimination operations
US9298651B2 (en) * 2013-06-24 2016-03-29 International Business Machines Corporation Continuous in-memory accumulation of hardware performance counter data
CN104239183B (en) * 2014-09-22 2017-10-27 北京国双科技有限公司 The method and device of monitoring system performance
US10282326B1 (en) * 2014-10-29 2019-05-07 Xilinx, Inc. Active interrupt handler performance monitoring in microprocessors
US9916161B2 (en) * 2015-06-25 2018-03-13 Intel Corporation Instruction and logic for tracking fetch performance bottlenecks
CN105550091A (en) * 2015-09-03 2016-05-04 刘晓建 Monitoring card for PCI (Peripheral Component Interface)/PCIe (Peripheral Component Interface Express) device status and Gigabit network card link monitoring method
CN105487958B (en) * 2015-11-24 2018-04-10 无锡江南计算技术研究所 Processor internal act monitoring method
US10185692B2 (en) 2016-08-22 2019-01-22 International Business Machines Corporation Monitoring use of specialized hardware components (SHC) of processors in heterogeneous environments by storing event counts during execution
CN108509255A (en) * 2017-02-24 2018-09-07 龙芯中科技术有限公司 The treating method and apparatus of hardware interrupts
JP2019096243A (en) * 2017-11-28 2019-06-20 ルネサスエレクトロニクス株式会社 Semiconductor device and method for detecting failures of the same
US10606971B2 (en) 2017-11-29 2020-03-31 International Business Machines Corporation Testing netlists based on singular independent signals

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5691920A (en) * 1995-10-02 1997-11-25 International Business Machines Corporation Method and system for performance monitoring of dispatch unit efficiency in a processing system
US6253338B1 (en) * 1998-12-21 2001-06-26 International Business Machines Corporation System for tracing hardware counters utilizing programmed performance monitor to generate trace interrupt after each branch instruction or at the end of each code basic block
US6356615B1 (en) * 1999-10-13 2002-03-12 Transmeta Corporation Programmable event counter system

Family Cites Families (395)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2112794A (en) 1935-06-15 1938-03-29 Underwood Elliott Fisher Co Typewriting machine
US3707725A (en) 1970-06-19 1972-12-26 Ibm Program execution tracing system improvements
FR2253420A5 (en) 1973-11-30 1975-06-27 Honeywell Bull Soc Ind
FR2253418A5 (en) 1973-11-30 1975-06-27 Honeywell Bull Soc Ind
FR2253423A5 (en) 1973-11-30 1975-06-27 Honeywell Bull Soc Ind
US4034353A (en) * 1975-09-15 1977-07-05 Burroughs Corporation Computer system performance indicator
US4145735A (en) 1977-02-02 1979-03-20 Nippon Steel Corporation Monitor for priority level of task in information processing system
US4291371A (en) 1979-01-02 1981-09-22 Honeywell Information Systems Inc. I/O Request interrupt mechanism
FR2471631B1 (en) 1979-12-11 1986-02-21 Cii Honeywell Bull Device for synchronizing and allocating processes between several processors in an information processing system
JPH036545B2 (en) 1983-01-18 1991-01-30 Mitsubishi Electric Corp
US4598364A (en) 1983-06-29 1986-07-01 International Business Machines Corporation Efficient trace method adaptable to multiprocessors
US4558413A (en) 1983-11-21 1985-12-10 Xerox Corporation Software version management system
US5103394A (en) 1984-04-30 1992-04-07 Hewlett-Packard Company Software performance analyzer
US4794472A (en) 1985-07-30 1988-12-27 Matsushita Electric Industrial Co., Ltd. Video tape reproducing apparatus with a processor that time-shares different operations
US4682283A (en) 1986-02-06 1987-07-21 Rockwell International Corporation Address range comparison system using multiplexer for detection of range identifier bits stored in dedicated RAM's
US5051944A (en) 1986-04-17 1991-09-24 Ncr Corporation Computer address analyzer having a counter and memory locations each storing count value indicating occurrence of corresponding memory address
US4821178A (en) * 1986-08-15 1989-04-11 International Business Machines Corporation Internal performance monitoring by event sampling
GB2200483B (en) 1987-01-22 1991-10-16 Nat Semiconductor Corp Memory referencing in a high performance microprocessor
US5822578A (en) 1987-12-22 1998-10-13 Sun Microsystems, Inc. System for inserting instructions into processor instruction stream in order to perform interrupt processing
US4798472A (en) * 1988-01-14 1989-01-17 Harry Chan Extruder screw with balanced flights of different functional sections
US6569679B1 (en) 1988-03-21 2003-05-27 Chiron Corporation Producer cell that generates adenoviral vectors encoding a cytokine and a conditionally lethal gene
US4912623A (en) 1988-04-11 1990-03-27 Square D Company Multiple processor communications system
US5032982A (en) * 1988-05-18 1991-07-16 Zilog, Inc. Device for timing interrupt acknowledge cycles
US5113507A (en) 1988-10-20 1992-05-12 Universities Space Research Association Method and apparatus for a sparse distributed memory system
US4928222A (en) 1988-10-31 1990-05-22 International Business Machines Corporation Enhanced semaphore architecture
US5142634A (en) 1989-02-03 1992-08-25 Digital Equipment Corporation Branch prediction
US5142635A (en) 1989-04-07 1992-08-25 Intel Corporation Method and circuitry for performing multiple stack operations in succession in a pipelined digital computer
US5257358A (en) 1989-04-18 1993-10-26 Nec Electronics, Inc. Method for counting the number of program instruction completed by a microprocessor
US5256775A (en) 1989-06-05 1993-10-26 Gilead Sciences, Inc. Exonuclease-resistant oligonucleotides
US5150349A (en) 1989-10-19 1992-09-22 Clarion Co., Ltd. Disc loading structure
US6083220A (en) 1990-03-13 2000-07-04 The Regents Of The University Of California Endovascular electrolytically detachable wire and tip for the formation of thrombus in arteries, veins, aneurysms, vascular malformations and arteriovenous fistulas
EP0458495A3 (en) 1990-05-21 1993-04-14 Texas Instruments Incorporated Apparatus and method for managing versions and configurations of persistent and transient objects
US5212794A (en) 1990-06-01 1993-05-18 Hewlett-Packard Company Method for optimizing computer code to provide more efficient execution on computers having cache memories
EP0463965B1 (en) 1990-06-29 1998-09-09 Digital Equipment Corporation Branch prediction unit for high-performance processor
US5276833A (en) 1990-07-02 1994-01-04 Chips And Technologies, Inc. Data cache management system with test mode using index registers and CAS disable and posted write disable
US5151981A (en) * 1990-07-13 1992-09-29 International Business Machines Corporation Instruction sampling instrumentation
JPH04248483A (en) 1991-02-01 1992-09-03 Nec Corp Semiconductor integrated circuit
EP0501613A3 (en) 1991-02-28 1993-09-01 Hewlett-Packard Company Heterogeneous software configuration management apparatus
JP2777496B2 (en) 1991-02-28 1998-07-16 インターナショナル・ビジネス・マシーンズ・コーポレイション Uses when profiling multi-processes in computer systems
US5297282A (en) 1991-05-29 1994-03-22 Toshiba America Information Systems, Inc. Resume processing function for the OS/2 operating system
JPH0774984B2 (en) 1991-06-10 1995-08-09 インターナショナル・ビジネス・マシーンズ・コーポレイション System resource utilization measurement method and data processing system
US5193180A (en) 1991-06-21 1993-03-09 Pure Software Inc. System for modifying relocatable object code files to monitor accesses to dynamically allocated memory
US5644692A (en) 1991-12-06 1997-07-01 Lucent Technologies Inc. Information display apparatus and methods
US5574872A (en) * 1991-12-10 1996-11-12 Intel Corporation Method and apparatus for controlling the saving of pipelines in pipelined processors during trap handling
US5414827A (en) 1991-12-19 1995-05-09 Opti, Inc. Automatic cache flush
US5548762A (en) 1992-01-30 1996-08-20 Digital Equipment Corporation Implementation efficient interrupt select mechanism
US5537572A (en) 1992-03-31 1996-07-16 Vlsi Technology, Inc. Cache controller and method for dumping contents of a cache directory and cache data random access memory (RAM)
JP3544214B2 (en) * 1992-04-29 2004-07-21 サン・マイクロシステムズ・インコーポレイテッドSun Microsystems, Inc. Method and system for monitoring processor status
US5657253A (en) 1992-05-15 1997-08-12 Intel Corporation Apparatus for monitoring the performance of a microprocessor
US5581778A (en) 1992-08-05 1996-12-03 David Sarnoff Researach Center Advanced massively parallel computer using a field of the instruction to selectively enable the profiling counter to increase its value in response to the system clock
US5450349A (en) 1992-10-27 1995-09-12 Digital Equipment Corporation Computer system performance evaluation system and method
US5479633A (en) 1992-10-30 1995-12-26 Intel Corporation Method of controlling clean-up of a solid state memory disk storing floating sector data
US5404500A (en) 1992-12-17 1995-04-04 International Business Machines Corporation Storage control system with improved system and technique for destaging data from nonvolatile memory
JPH09501517A (en) 1993-02-08 1997-02-10 アクション・テクノロジーズ・インコーポレーテッド Method and apparatus for managing business processes
US5544342A (en) 1993-06-30 1996-08-06 International Business Machines Corporation System and method for prefetching information in a processing system
US5751942A (en) 1993-06-30 1998-05-12 Intel Corporation Trace event detection during trace enable transitions
JP3639927B2 (en) 1993-10-04 2005-04-20 株式会社ルネサステクノロジ Data processing device
JP3242508B2 (en) 1993-11-05 2001-12-25 松下電器産業株式会社 Microcomputer
DE4423559A1 (en) 1993-11-09 1995-05-11 Hewlett Packard Co Data connection method and apparatus for multiprocessor computer systems with shared memory
US5581981A (en) 1993-11-12 1996-12-10 Thiele Engineering Company Method of packaging toothbrushes
US5745770A (en) 1993-12-27 1998-04-28 Intel Corporation Method and apparatus for servicing simultaneous I/O trap and debug traps in a microprocessor
US5666507A (en) 1993-12-29 1997-09-09 Unisys Corporation Pipelined microinstruction apparatus and methods with branch prediction and speculative state changing
US5603004A (en) 1994-02-14 1997-02-11 Hewlett-Packard Company Method for decreasing time penalty resulting from a cache miss in a multi-level cache system
US5966539A (en) 1994-03-01 1999-10-12 Digital Equipment Corporation Link time optimization with translation to intermediate program and following optimization techniques including program analysis code motion live variable set generation order analysis, dead code elimination and load invariant analysis
US5581482A (en) * 1994-04-26 1996-12-03 Unisys Corporation Performance monitor for digital computer system
US5590352A (en) 1994-04-26 1996-12-31 Advanced Micro Devices, Inc. Dependency checking and forwarding of variable width operands
WO1995031782A1 (en) 1994-05-12 1995-11-23 Ast Research, Inc. Cpu activity monitoring through cache watching
US5652858A (en) 1994-06-06 1997-07-29 Hitachi, Ltd. Method for prefetching pointer-type data structure and information processing apparatus therefor
EP0689141A3 (en) 1994-06-20 1997-10-15 At & T Corp Interrupt-based hardware support for profiling system performance
US5627981A (en) 1994-07-01 1997-05-06 Digital Equipment Corporation Software mechanism for accurately handling exceptions generated by instructions scheduled speculatively due to branch elimination
US5689712A (en) 1994-07-27 1997-11-18 International Business Machines Corporation Profile-based optimizing postprocessors for data references
US6006033A (en) 1994-08-15 1999-12-21 International Business Machines Corporation Method and system for reordering the instructions of a computer program to optimize its execution
US5537541A (en) 1994-08-16 1996-07-16 Digital Equipment Corporation System independent interface for performance counters
US5555432A (en) 1994-08-19 1996-09-10 Intel Corporation Circuit and method for scheduling instructions by predicting future availability of resources required for execution
US5557548A (en) 1994-12-09 1996-09-17 International Business Machines Corporation Method and system for performance monitoring within a data processing system
US5694540A (en) 1994-12-15 1997-12-02 Lucent Technologies Inc. Automated software regression test and compilation system
JP2908739B2 (en) 1994-12-16 1999-06-21 インターナショナル・ビジネス・マシーンズ・コーポレイション System and method for monitoring a CPU in a multiprocessor system
WO1996024991A1 (en) 1995-02-08 1996-08-15 Actual Radio Measurement Remote listenership monitoring system
US5794052A (en) 1995-02-27 1998-08-11 Ast Research, Inc. Method of software installation and setup
US5761103A (en) 1995-03-08 1998-06-02 Texas Instruments Incorporated Left and right justification of single precision mantissa in a double precision rounding unit
US5675802A (en) 1995-03-31 1997-10-07 Pure Atria Corporation Version control system for geographically distributed software development
US5727167A (en) 1995-04-14 1998-03-10 International Business Machines Corporation Thresholding support in performance monitoring
US6148321A (en) 1995-05-05 2000-11-14 Intel Corporation Processor event recognition
GB9509987D0 (en) 1995-05-17 1995-07-12 Sgs Thomson Microelectronics Manipulation of data
US5659679A (en) 1995-05-30 1997-08-19 Intel Corporation Method and apparatus for providing breakpoints on taken jumps and for providing software profiling in a computer system
US5671920A (en) 1995-06-01 1997-09-30 Xerox Corporation High speed printed sheet stacking and registration system
US6408386B1 (en) 1995-06-07 2002-06-18 Intel Corporation Method and apparatus for providing event handling functionality in a computer system
US5684030A (en) 1995-06-07 1997-11-04 American Home Products Corporation 2-substituted benzimidazole derivatives
US5878255A (en) 1995-06-07 1999-03-02 Advanced Micro Devices, Inc. Update unit for providing a delayed update to a branch prediction array
US5740413A (en) 1995-06-19 1998-04-14 Intel Corporation Method and apparatus for providing address breakpoints, branch breakpoints, and single stepping
US5875294A (en) 1995-06-30 1999-02-23 International Business Machines Corporation Method and system for halting processor execution in response to an enumerated occurrence of a selected combination of internal states
JP3290567B2 (en) 1995-08-24 2002-06-10 富士通株式会社 Profile instrumentation method
US5754839A (en) 1995-08-28 1998-05-19 Motorola, Inc. Apparatus and method for implementing watchpoints and breakpoints in a data processing system
US6311327B1 (en) 1998-03-02 2001-10-30 Applied Microsystems Corp. Method and apparatus for analyzing software in a language-independent manner
US5748878A (en) 1995-09-11 1998-05-05 Applied Microsystems, Inc. Method and apparatus for analyzing software executed in embedded systems
US5752062A (en) 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring through monitoring an order of processor events during execution in a processing system
US5797019A (en) 1995-10-02 1998-08-18 International Business Machines Corporation Method and system for performance monitoring time lengths of disabled interrupts in a processing system
US5949971A (en) 1995-10-02 1999-09-07 International Business Machines Corporation Method and system for performance monitoring through identification of frequency and length of time of execution of serialization instructions in a processing system
US5787286A (en) 1995-10-10 1998-07-28 International Business Machines Corporation Method and system for tabulation of execution performance
US5815707A (en) 1995-10-19 1998-09-29 Hewlett-Packard Company Dynamic function replacement for streams framework
JP3717212B2 (en) 1995-10-27 2005-11-16 株式会社日立製作所 Information processing apparatus and information processing unit
US5875334A (en) 1995-10-27 1999-02-23 International Business Machines Corporation System, method, and program for extending a SQL compiler for handling control statements packaged with SQL query statements
US5774724A (en) 1995-11-20 1998-06-30 International Business Machines Coporation System and method for acquiring high granularity performance data in a computer system
US5758061A (en) 1995-12-15 1998-05-26 Plum; Thomas S. Computer software testing method and apparatus
US5805879A (en) 1996-02-23 1998-09-08 Cyrix Corporation In a pipelined processor, setting a segment access indicator during execution stage using exception handling
JP3650460B2 (en) 1996-03-06 2005-05-18 株式会社アドバンテスト Driver circuit with temperature compensation
US5758187A (en) 1996-03-15 1998-05-26 Adaptec, Inc. Method for enhancing performance of a RAID 1 read operation using a pair of I/O command blocks in a chain structure
US5909573A (en) 1996-03-28 1999-06-01 Intel Corporation Method of branch prediction using loop counters
US5758168A (en) * 1996-04-18 1998-05-26 International Business Machines Corporation Interrupt vectoring for optionally architected facilities in computer systems
US5822763A (en) 1996-04-19 1998-10-13 Ibm Corporation Cache coherence protocol for reducing the effects of false sharing in non-bus-based shared-memory multiprocessors
DE69728081T2 (en) 1996-05-30 2004-08-19 Matsushita Electric Industrial Co., Ltd., Kadoma Method and circuit for controlling delayed branch instructions
US5772322A (en) 1996-05-31 1998-06-30 Honeywell Inc. Resonant microbeam temperature sensor
US5775825A (en) 1996-07-22 1998-07-07 Hewlett-Packard Company Integrated shell-and-chasis construction for a desktop image-related device
US6025924A (en) 1996-09-05 2000-02-15 Ricoh Company, Ltd. Image forming system including a first printer connected to a host computer and a second printer connected to the host computer via a switching device provided in the first printer
US5794028A (en) 1996-10-17 1998-08-11 Advanced Micro Devices, Inc. Shared branch prediction structure
US5835702A (en) 1996-10-21 1998-11-10 International Business Machines Corporation Performance monitor
US5937437A (en) 1996-10-28 1999-08-10 International Business Machines Corporation Method and apparatus for monitoring address translation performance
US6278064B1 (en) 1996-10-30 2001-08-21 Square D Company Conductive joint formed by electron beam welding and method thereof
US5926640A (en) 1996-11-01 1999-07-20 Digital Equipment Corporation Skipping clock interrupts during system inactivity to reduce power consumption
US6128711A (en) * 1996-11-12 2000-10-03 Compaq Computer Corporation Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writes
US5862381A (en) 1996-11-26 1999-01-19 International Business Machines Corporation Visualization tool for graphically displaying trace data
US5896538A (en) 1996-11-26 1999-04-20 International Business Machines Corporation System and method for multi-phased performance profiling of single-processor and multi-processor systems
US5887159A (en) 1996-12-11 1999-03-23 Digital Equipment Corporation Dynamically determining instruction hint fields
US5913925A (en) 1996-12-16 1999-06-22 International Business Machines Corporation Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order
US5889947A (en) 1996-12-16 1999-03-30 International Business Machines Corporation Apparatus and method for executing instructions that select a storage location for output values in response to an operation count
US5870576A (en) 1996-12-16 1999-02-09 Hewlett-Packard Company Method and apparatus for storing and expanding variable-length program instructions upon detection of a miss condition within an instruction cache containing pointers to compressed instructions for wide instruction word processor architectures
US5938760A (en) 1996-12-17 1999-08-17 International Business Machines Corporation System and method for performance monitoring of instructions in a re-order buffer
US6189072B1 (en) 1996-12-17 2001-02-13 International Business Machines Corporation Performance monitoring of cache misses and instructions completed for instruction parallelism analysis
US20030061471A1 (en) 1999-07-23 2003-03-27 Masahito Matsuo Data processor
US5822790A (en) 1997-02-07 1998-10-13 Sun Microsystems, Inc. Voting data prefetch engine
SE520343C2 (en) 1997-02-12 2003-07-01 Ericsson Telefon Ab L M Method, system, and computer branch prediction
ES2234042T3 (en) 1997-02-17 2005-06-16 E.G.O. Elektro-Geratebau Gmbh Circuit set for a sensor element.
US5872913A (en) 1997-03-07 1999-02-16 International Business Machines Corporation System and method for low overhead, high precision performance measurements using state transistions
US6112317A (en) 1997-03-10 2000-08-29 Digital Equipment Corporation Processor performance counter for sampling the execution frequency of individual instructions
US5857097A (en) 1997-03-10 1999-01-05 Digital Equipment Corporation Method for identifying reasons for dynamic stall cycles during the execution of a program
US5796939A (en) 1997-03-10 1998-08-18 Digital Equipment Corporation High frequency sampling of processor performance counters
US5950009A (en) 1997-03-10 1999-09-07 International Business Machines Coporation Method and apparatus for profile-based reordering of program portions in a computer program
US5970439A (en) 1997-03-13 1999-10-19 International Business Machines Corporation Performance monitoring in a data processing system
EP0864969A1 (en) 1997-03-14 1998-09-16 Alcatel Alsthom Compagnie Generale D'electricite A method to provide a software package and a provider station and a user station realising the method
US5928334A (en) 1997-03-28 1999-07-27 International Business Machines Corporation Hardware verification tool for multiprocessors
US6149318A (en) 1997-04-15 2000-11-21 Samuel C. Kendall Link-time and run-time error detection, and program instrumentation
US6026235A (en) 1997-05-20 2000-02-15 Inprise Corporation System and methods for monitoring functions in natively compiled software programs
US5966537A (en) 1997-05-28 1999-10-12 Sun Microsystems, Inc. Method and apparatus for dynamically optimizing an executable computer program using input data
US5920721A (en) 1997-06-11 1999-07-06 Digital Equipment Corporation Compiler generating functionally-alike code sequences in an executable program intended for execution in different run-time environments
US6094709A (en) 1997-07-01 2000-07-25 International Business Machines Corporation Cache coherence for lazy entry consistency in lockup-free caches
US5991708A (en) 1997-07-07 1999-11-23 International Business Machines Corporation Performance monitor and method for performance monitoring within a data processing system
US5987598A (en) 1997-07-07 1999-11-16 International Business Machines Corporation Method and system for tracking instruction progress within a data processing system
US5802678A (en) 1997-07-16 1998-09-08 Puente; Joe A. Non-penetrating tie restraining device
US6425118B1 (en) 1997-07-18 2002-07-23 Compaq Computer Corporation System for automatically generating tests to ensure binary compatibility between software components produced by a source-to-source computer language translator
US5926176A (en) 1997-07-31 1999-07-20 Think & Do Software, Inc. Control program tracking and display system
US6202199B1 (en) 1997-07-31 2001-03-13 Mutek Solutions, Ltd. System and method for remotely analyzing the execution of computer programs
US5987250A (en) 1997-08-21 1999-11-16 Hewlett-Packard Company Transparent instrumentation for computer program behavior analysis
JPH1185515A (en) 1997-09-10 1999-03-30 Ricoh Co Ltd Microprocessor
US5940618A (en) 1997-09-22 1999-08-17 International Business Machines Corporation Code instrumentation system with non intrusive means and cache memory optimization for dynamic monitoring of code segments
US5991908A (en) 1997-09-29 1999-11-23 Xilinx, Inc. Boundary scan chain with dedicated programmable routing
US5995754A (en) 1997-10-06 1999-11-30 Sun Microsystems, Inc. Method and apparatus for dynamically optimizing byte-coded programs
US6256771B1 (en) 1997-10-16 2001-07-03 At&T Corp. Method and apparatus for providing a dynamic service composition software architecture
US6101524A (en) 1997-10-23 2000-08-08 International Business Machines Corporation Deterministic replay of multithreaded applications
US6105051A (en) 1997-10-23 2000-08-15 International Business Machines Corporation Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor
US5966538A (en) 1997-10-31 1999-10-12 Hewlett-Packard Company Method and apparatus for automatically determining which compiler options should be used when compiling a computer program
US5938778A (en) 1997-11-10 1999-08-17 International Business Machines Corporation System and method for tracing instructions in an information handling system without changing the system source code
US6199154B1 (en) 1997-11-17 2001-03-06 Advanced Micro Devices, Inc. Selecting cache to fetch in multi-level cache system based on fetch address source and pre-fetching additional data to the cache for future access
US6119075A (en) 1997-11-26 2000-09-12 Digital Equipment Corporation Method for estimating statistics of properties of interactions processed by a processor pipeline
US6442585B1 (en) 1997-11-26 2002-08-27 Compaq Computer Corporation Method for scheduling contexts based on statistics of memory system interactions in a computer system
US6549930B1 (en) 1997-11-26 2003-04-15 Compaq Computer Corporation Method for scheduling threads in a multithreaded processor
US6163840A (en) 1997-11-26 2000-12-19 Compaq Computer Corporation Method and apparatus for sampling multiple potentially concurrent instructions in a processor pipeline
US6070009A (en) 1997-11-26 2000-05-30 Digital Equipment Corporation Method for estimating execution rates of program execution paths
US6256775B1 (en) 1997-12-11 2001-07-03 International Business Machines Corporation Facilities for detailed software performance analysis in a multithreaded processor
US6349406B1 (en) 1997-12-12 2002-02-19 International Business Machines Coporation Method and system for compensating for instrumentation overhead in trace data by computing average minimum event times
FR2772547B1 (en) 1997-12-12 2000-01-21 Soudure Autogene Francaise Electrode body / electrode holder assembly for plasma torch
US6182210B1 (en) 1997-12-16 2001-01-30 Intel Corporation Processor having multiple program counters and trace buffers outside an execution pipeline
US6098169A (en) 1997-12-23 2000-08-01 Intel Corporation Thread performance analysis by monitoring processor performance event registers at thread switch
US6195765B1 (en) 1998-01-05 2001-02-27 Electronic Data Systems Corporation System and method for testing an application program
US6631514B1 (en) 1998-01-06 2003-10-07 Hewlett-Packard Development, L.P. Emulation system that uses dynamic binary translation and permits the safe speculation of trapping operations
JPH11194957A (en) 1998-01-07 1999-07-21 Matsushita Electric Ind Co Ltd Debug supporting device, parallel execution information generation device and recording medium for recording program applied to the same
US6374364B1 (en) 1998-01-20 2002-04-16 Honeywell International, Inc. Fault tolerant computing system using instruction counting
GB2333864B (en) 1998-01-28 2003-05-07 Ibm Distribution of software updates via a computer network
US6202207B1 (en) 1998-01-28 2001-03-13 International Business Machines Corporation Method and a mechanism for synchronized updating of interoperating software
JP3881763B2 (en) 1998-02-09 2007-02-14 株式会社ルネサステクノロジ Data processing device
US6105129A (en) 1998-02-18 2000-08-15 Advanced Micro Devices, Inc. Converting register data from a first format type to a second format type if a second type instruction consumes data produced by a first type instruction
GB9805485D0 (en) 1998-03-13 1998-05-13 Sgs Thomson Microelectronics Microcomputer
US6237019B1 (en) 1998-03-18 2001-05-22 International Business Machines Corporation Method and apparatus for performing a semaphore operation
US6185671B1 (en) 1998-03-31 2001-02-06 Intel Corporation Checking data type of operands specified by an instruction using attributes in a tagged array architecture
US6067644A (en) 1998-04-15 2000-05-23 International Business Machines Corporation System and method monitoring instruction progress within a processor
US6134676A (en) 1998-04-30 2000-10-17 International Business Machines Corporation Programmable hardware event monitoring method
US6189141B1 (en) 1998-05-04 2001-02-13 Hewlett-Packard Company Control path evaluating trace designator with dynamically adjustable thresholds for activation of tracing for high (hot) activity and low (cold) activity of flow control
US6247113B1 (en) 1998-05-27 2001-06-12 Arm Limited Coprocessor opcode division by data type
US6735757B1 (en) 1998-06-04 2004-05-11 Gateway, Inc. Apparatus and method for checking component compatibility in a build to order computer system
US6317820B1 (en) 1998-06-05 2001-11-13 Texas Instruments Incorporated Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism
US6145123A (en) 1998-07-01 2000-11-07 Advanced Micro Devices, Inc. Trace on/off with breakpoint register
US6286584B1 (en) 1998-07-15 2001-09-11 James A. Frields Quick-change mechanism for a tie bar
US6243804B1 (en) 1998-07-22 2001-06-05 Scenix Semiconductor, Inc. Single cycle transition pipeline processing using shadow registers
US6073215A (en) 1998-08-03 2000-06-06 Motorola, Inc. Data processing system having a data prefetch mechanism and method therefor
US6240510B1 (en) 1998-08-06 2001-05-29 Intel Corporation System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructions
US6275893B1 (en) 1998-09-14 2001-08-14 Compaq Computer Corporation Method and apparatus for providing seamless hooking and intercepting of selected kernel and HAL exported entry points in an operating system
US6212675B1 (en) 1998-09-16 2001-04-03 International Business Machines Corporation Presentation of visual program test coverage information
US6189142B1 (en) 1998-09-16 2001-02-13 International Business Machines Corporation Visual program runtime performance analysis
US6324689B1 (en) 1998-09-30 2001-11-27 Compaq Computer Corporation Mechanism for re-writing an executable having mixed code and data
US6223338B1 (en) 1998-09-30 2001-04-24 International Business Machines Corporation Method and system for software instruction level tracing in a data processing system
JP3123047B2 (en) 1998-10-02 2001-01-09 日本電気株式会社 Microprocessor
JP3551353B2 (en) 1998-10-02 2004-08-04 株式会社日立製作所 Data relocation method
US6192513B1 (en) 1998-11-02 2001-02-20 Hewlett-Packard Company Mechanism for finding spare registers in binary code
US6185652B1 (en) 1998-11-03 2001-02-06 International Business Machin Es Corporation Interrupt mechanism on NorthBay
US6351844B1 (en) 1998-11-05 2002-02-26 Hewlett-Packard Company Method for selecting active code traces for translation in a caching dynamic translator
US6826749B2 (en) 1998-12-08 2004-11-30 Nazomi Communications, Inc. Java hardware accelerator using thread manager
US6654781B1 (en) 1998-12-11 2003-11-25 International Business Machines Corporation Enhanced thread processing
US6636950B1 (en) 1998-12-17 2003-10-21 Massachusetts Institute Of Technology Computer architecture for shared memory access
US6230313B1 (en) 1998-12-23 2001-05-08 Cray Inc. Parallelism performance analysis based on execution trace information
US6446019B1 (en) 1998-12-29 2002-09-03 Intel Corporation Method and apparatus for calibrating analog sensor measurement
US6404500B1 (en) 1999-01-25 2002-06-11 Aqua Check Systems, Inc Colorimeter apparatus and related process
US7254806B1 (en) 1999-08-30 2007-08-07 Ati International Srl Detecting reordered side-effects
US6484315B1 (en) 1999-02-01 2002-11-19 Cisco Technology, Inc. Method and system for dynamically distributing updates in a network
US6378066B1 (en) 1999-02-04 2002-04-23 Sun Microsystems, Inc. Method, apparatus, and article of manufacture for developing and executing data flow programs, and optimizing user input specifications
US6330662B1 (en) 1999-02-23 2001-12-11 Sun Microsystems, Inc. Apparatus including a fetch unit to include branch history information to increase performance of multi-cylce pipelined branch prediction structures
US6430741B1 (en) 1999-02-26 2002-08-06 Hewlett-Packard Company System and method for data coverage analysis of a computer program
US6526571B1 (en) 1999-03-16 2003-02-25 International Business Machines Corporation Method for identifying calls in java packages whose targets are guaranteed to belong to the same package
US6647301B1 (en) 1999-04-22 2003-11-11 Dow Global Technologies Inc. Process control system with integrated safety control system
US7086035B1 (en) 1999-05-13 2006-08-01 International Business Machines Corporation Method and system for counting non-speculative events in a speculative processor
US6562858B2 (en) 1999-05-17 2003-05-13 St. Elizabeth's Medical Center Of Boston, Inc. Method for treating depression
US6460693B1 (en) 1999-05-19 2002-10-08 Valley Design, Inc. Child resistant blister pack container with compound action release mechanism
US6339818B1 (en) 1999-06-24 2002-01-15 International Business Machines Corporation Method and system for dynamically locating frequently accessed memory regions or locations
US6477703B1 (en) 1999-06-29 2002-11-05 Hewlett-Packard Company Software patch selection tool
US6501995B1 (en) 1999-06-30 2002-12-31 The Foxboro Company Process control system and method with improved distribution, installation and validation of components
US6446029B1 (en) 1999-06-30 2002-09-03 International Business Machines Corporation Method and system for providing temporal threshold support during performance monitoring of a pipelined processor
US6453468B1 (en) 1999-06-30 2002-09-17 B-Hub, Inc. Methods for improving reliability while upgrading software programs in a clustered computer system
US20030040955A1 (en) 1999-07-02 2003-02-27 The Nasdaq Stock Market, Inc., A Delaware Corporation Market monitoring architecture for detecting alert conditions
US6206235B1 (en) 1999-07-07 2001-03-27 Daniel Green Candy dispenser
US6459998B1 (en) 1999-07-24 2002-10-01 Gary R. Hoffman Sensing downed power lines
US7430670B1 (en) 1999-07-29 2008-09-30 Intertrust Technologies Corp. Software self-defense systems and methods
US6601233B1 (en) 1999-07-30 2003-07-29 Accenture Llp Business components framework
US6457170B1 (en) 1999-08-13 2002-09-24 Intrinsity, Inc. Software system build method and apparatus that supports multiple users in a software development environment
US6438743B1 (en) 1999-08-13 2002-08-20 Intrinsity, Inc. Method and apparatus for object cache registration and maintenance in a networked software development environment
US6406135B1 (en) 1999-08-23 2002-06-18 Canon Kabushiki Kaisha Ink jet recording head and recording apparatus using the same
US6542985B1 (en) 1999-09-23 2003-04-01 Unisys Corporation Event counter
US6594820B1 (en) 1999-09-28 2003-07-15 Sun Microsystems, Inc. Method and apparatus for testing a process in a computer system
US6298521B1 (en) 1999-10-18 2001-10-09 Gary Butterfield Door knob sanitizing device
US6557096B1 (en) 1999-10-25 2003-04-29 Intel Corporation Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types
US6550002B1 (en) 1999-11-04 2003-04-15 International Business Machines Corporation Method and system for detecting a flush of an instruction without a flush indicator
US6574727B1 (en) 1999-11-04 2003-06-03 International Business Machines Corporation Method and apparatus for instruction sampling for performance monitoring and debug
US6973417B1 (en) 1999-11-05 2005-12-06 Metrowerks Corporation Method and system for simulating execution of a target program in a simulated target system
US6718543B2 (en) 1999-11-08 2004-04-06 Hewlett-Packard Development Company, L.P. Method and apparatus for optimization of the performance of an application program in a computer system while preserving the system behavior
US6530042B1 (en) 1999-11-08 2003-03-04 International Business Machines Corporation Method and apparatus for monitoring the performance of internal queues in a microprocessor
US6871298B1 (en) 1999-11-12 2005-03-22 Obsidian Software, Inc. Method and apparatus that simulates the execution of paralled instructions in processor functional verification testing
US6513045B1 (en) 1999-11-17 2003-01-28 International Business Machines Corporation Method and an apparatus for providing cross product automated user assistance in the planning, configuration, and management of information systems
US6681387B1 (en) 1999-12-01 2004-01-20 Board Of Trustees Of The University Of Illinois Method and apparatus for instruction execution hot spot detection and monitoring in a data processing unit
US6480966B1 (en) * 1999-12-07 2002-11-12 International Business Machines Corporation Performance monitor synchronization in a multiprocessor system
JP3600095B2 (en) 1999-12-07 2004-12-08 松下電器産業株式会社 Interrupt management device and interrupt management method
US6560693B1 (en) 1999-12-10 2003-05-06 International Business Machines Corporation Branch history guided instruction/data prefetching
US6598153B1 (en) 1999-12-10 2003-07-22 International Business Machines Corporation Processor and method that accelerate evaluation of pairs of condition-setting and branch instructions
JP3946397B2 (en) 1999-12-24 2007-07-18 三菱電機株式会社 In-vehicle information processing equipment
JP3575593B2 (en) 1999-12-27 2004-10-13 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Object lock management method and apparatus
US6848029B2 (en) 2000-01-03 2005-01-25 Dirk Coldewey Method and apparatus for prefetching recursive data structures
US6549998B1 (en) 2000-01-14 2003-04-15 Agere Systems Inc. Address generator for interleaving data
US6772322B1 (en) * 2000-01-21 2004-08-03 Intel Corporation Method and apparatus to monitor the performance of a processor
JP2001202270A (en) 2000-01-21 2001-07-27 Mitsubishi Electric Corp Processor with internal bus tracing function
TW457432B (en) 2000-02-11 2001-10-01 Via Tech Inc Method to resolve the interrupt problem of data stream and the device thereof
US6721875B1 (en) 2000-02-22 2004-04-13 Hewlett-Packard Development Company, L.P. Method and apparatus for implementing a single-syllable IP-relative branch instruction and a long IP-relative branch instruction in a processor which fetches instructions in bundle form
US6735666B1 (en) 2000-02-22 2004-05-11 Wind River Systems, Inc. Method of providing direct user task access to operating system data structures
US6865663B2 (en) 2000-02-24 2005-03-08 Pts Corporation Control processor dynamically loading shadow instruction register associated with memory entry of coprocessor in flexible coupling mode
JP2001265609A (en) 2000-03-16 2001-09-28 Omron Corp Arithmetic processor
US6862729B1 (en) 2000-04-04 2005-03-01 Microsoft Corporation Profile-driven data layout optimization
US6687807B1 (en) 2000-04-18 2004-02-03 Sun Microystems, Inc. Method for apparatus for prefetching linked data structures
JP2001312374A (en) 2000-04-28 2001-11-09 Fujitsu Ltd Storage device and access control method
EP1150213B1 (en) 2000-04-28 2012-01-25 TELEFONAKTIEBOLAGET LM ERICSSON (publ) Data processing system and method
US7024668B2 (en) 2000-05-15 2006-04-04 Matsushita Electric Industrial Co., Ltd. Application execution apparatus and method
US6725457B1 (en) 2000-05-17 2004-04-20 Nvidia Corporation Semaphore enhancement to improve system performance
US6951018B2 (en) 2000-05-30 2005-09-27 Sun Microsystems, Inc. Method and apparatus for efficiently tracking monitors
DE10028500A1 (en) 2000-06-08 2002-01-03 Deutsche Telekom Ag Process for installing software in hardware
US6678755B1 (en) 2000-06-30 2004-01-13 Micron Technology, Inc. Method and apparatus for appending memory commands during a direct memory access operation
US6557083B1 (en) 2000-06-30 2003-04-29 Intel Corporation Memory system for multiple data types
US6658416B1 (en) 2000-07-10 2003-12-02 International Business Machines Corporation Apparatus and method for creating an indexed database of symbolic data for use with trace data of a computer program
US6973542B1 (en) 2000-07-18 2005-12-06 International Business Machines Corporation Detecting when to prefetch inodes and then prefetching inodes in parallel
JP2002110537A (en) 2000-07-19 2002-04-12 Nikon Corp Electron beam exposure aligner for drawing mask
US6918106B1 (en) 2000-07-31 2005-07-12 Sun Microsystems, Inc. Method and apparatus for collocating dynamically loaded program files
US6928521B1 (en) 2000-08-01 2005-08-09 International Business Machines Corporation Method, system, and data structures for using metadata in updating data in a storage device
US6757771B2 (en) 2000-08-09 2004-06-29 Advanced Micro Devices, Inc. Stack switching mechanism in a computer system
US6961681B1 (en) 2000-09-12 2005-11-01 Microsoft Corporation System and method providing virtual applications architecture
US6948059B1 (en) 2000-09-28 2005-09-20 Rockwell Automation Technologies, Inc. Component loader for industrial control device providing resource search capabilities
US6782454B1 (en) 2000-09-29 2004-08-24 Sun Microsystems, Inc. System and method for pre-fetching for pointer linked data structures
US6775825B1 (en) 2000-10-31 2004-08-10 Hewlett-Packard Development Company, L.P. Common software application definition for resource management
US6971091B1 (en) 2000-11-01 2005-11-29 International Business Machines Corporation System and method for adaptively optimizing program execution by sampling at selected program points
FI117143B (en) 2000-11-30 2006-06-30 Metso Automation Oy Method and equipment for cleaning the boiler for soda
US20020073406A1 (en) 2000-12-12 2002-06-13 Darryl Gove Using performance counter profiling to drive compiler optimization
US6480938B2 (en) 2000-12-15 2002-11-12 Hewlett-Packard Company Efficient I-cache structure to support instructions crossing line boundaries
US6857083B2 (en) 2000-12-18 2005-02-15 International Business Machines Corporation Method and system for triggering a debugging unit
US7448025B2 (en) 2000-12-29 2008-11-04 Intel Corporation Qualification of event detection by thread ID and thread privilege level
US6665776B2 (en) 2001-01-04 2003-12-16 Hewlett-Packard Development Company L.P. Apparatus and method for speculative prefetching after data cache misses
US6785844B2 (en) 2001-01-26 2004-08-31 Dell Products L.P. Automated test system and method for computer factory install environment
US7093236B2 (en) 2001-02-01 2006-08-15 Arm Limited Tracing out-of-order data
US6865667B2 (en) 2001-03-05 2005-03-08 Freescale Semiconductors, Inc. Data processing system having redirecting circuitry and method therefor
US6519310B2 (en) 2001-03-28 2003-02-11 Intel Corporation Hardware event based flow control of counters
US6966057B2 (en) 2001-03-30 2005-11-15 Intel Corporation Static compilation of instrumentation code for debugging support
US20030066055A1 (en) 2001-04-26 2003-04-03 Spivey John Michael Profiling computer programs
US20020169738A1 (en) 2001-05-10 2002-11-14 Giel Peter Van Method and system for auditing an enterprise configuration
JP4445160B2 (en) 2001-05-18 2010-04-07 富士通株式会社 Event measurement device and method, event measurement program, computer-readable recording medium containing the program, and processor system
WO2002095601A1 (en) 2001-05-22 2002-11-28 Koninklijke Philips Electronics N.V. Method and system for accelerated access to a memory
US20020199179A1 (en) 2001-06-21 2002-12-26 Lavery Daniel M. Method and apparatus for compiler-generated triggering of auxiliary codes
US6988186B2 (en) 2001-06-28 2006-01-17 International Business Machines Corporation Shared resource queue for simultaneous multithreading processing wherein entries allocated to different threads are capable of being interspersed among each other and a head pointer for one thread is capable of wrapping around its own tail in order to access a free entry
US20030005422A1 (en) 2001-07-02 2003-01-02 Nicolai Kosche Technique for improving the prediction rate of dynamically unpredictable branches
US6742179B2 (en) 2001-07-12 2004-05-25 International Business Machines Corporation Restructuring of executable computer code and large data sets
US6848030B2 (en) 2001-07-20 2005-01-25 Freescale Semiconductor, Inc. Method and apparatus for filling lines in a cache
GB2379039B (en) 2001-08-22 2005-03-23 Ibm Transaction processing in a distributed data processing system
US6687794B2 (en) 2001-10-18 2004-02-03 International Business Machines Corporation Prefetching mechanism for data caches
US6430938B1 (en) 2001-10-18 2002-08-13 Praxair Technology, Inc. Cryogenic vessel system with pulse tube refrigeration
US20030131343A1 (en) 2001-10-19 2003-07-10 French Ronan J. Framework for system monitoring
CA2359862A1 (en) 2001-10-24 2003-04-24 Ibm Canada Limited - Ibm Canada Limitee Using identifiers and counters for controlled optimization compilation
US7093154B2 (en) 2001-10-25 2006-08-15 International Business Machines Corporation Critical adapter local error handling
US6775728B2 (en) 2001-11-15 2004-08-10 Intel Corporation Method and system for concurrent handler execution in an SMI and PMI-based dispatch-execution framework
US20030126590A1 (en) 2001-12-28 2003-07-03 Michael Burrows System and method for dynamic data-type checking
US6928582B2 (en) 2002-01-04 2005-08-09 Intel Corporation Method for fast exception handling
US20030135720A1 (en) * 2002-01-14 2003-07-17 International Business Machines Corporation Method and system using hardware assistance for instruction tracing with secondary set of interruption resources
US20030135719A1 (en) 2002-01-14 2003-07-17 International Business Machines Corporation Method and system using hardware assistance for tracing instruction disposition information
US7035996B2 (en) 2002-01-17 2006-04-25 Raytheon Company Generating data type token value error in stream computer
US7168067B2 (en) 2002-02-08 2007-01-23 Agere Systems Inc. Multiprocessor system with cache-based software breakpoints
US7069541B2 (en) 2002-03-01 2006-06-27 Bellsouth Intellectual Property Corporation System and method for a web-based application development and deployment tracking tool
US7131115B2 (en) 2002-03-25 2006-10-31 Hewlett-Packard Development Company, L.P. Unwinding instrumented program code
US7089535B2 (en) 2002-03-28 2006-08-08 International Business Machines Corporation Code coverage with an integrated development environment
US6832296B2 (en) 2002-04-09 2004-12-14 Ip-First, Llc Microprocessor with repeat prefetch instruction
US6732354B2 (en) 2002-04-23 2004-05-04 Quicksilver Technology, Inc. Method, system and software for programming reconfigurable hardware
US7577951B2 (en) 2002-05-30 2009-08-18 Hewlett-Packard Development Company, L.P. Performance of computer programs while they are running
WO2004001584A2 (en) 2002-06-24 2003-12-31 Ante Vista Gmbh A method for executing structured symbolic machine code on a microprocessor
JP4077252B2 (en) 2002-06-28 2008-04-16 富士通株式会社 Compiler program and compile processing method
KR100481854B1 (en) 2002-07-29 2005-04-11 삼성전자주식회사 Integrated circuit with on-chip termination
US6970999B2 (en) 2002-07-31 2005-11-29 International Business Machines Corporation Counting latencies of an instruction table flush, refill and instruction execution using a plurality of assigned counters
US9003376B2 (en) 2002-08-09 2015-04-07 Texas Instruments Incorporated Software breakpoints with tailoring for multiple processor shared memory or multiple thread systems
US6840829B2 (en) 2002-08-30 2005-01-11 Kawasaki Jukogyo Kabushiki Kaisha Jet-propulsion watercraft
US7296259B2 (en) 2002-09-11 2007-11-13 Agere Systems Inc. Processor system with cache-based software breakpoints
US6774724B2 (en) 2002-11-21 2004-08-10 Motorola, Inc. Radio frequency power amplifier active self-bias compensation circuit
AT504446T (en) 2002-12-02 2011-04-15 Silverbrook Res Pty Ltd Totdüsenausgleich
US7155575B2 (en) 2002-12-18 2006-12-26 Intel Corporation Adaptive prefetch for irregular access patterns
US7237242B2 (en) 2002-12-31 2007-06-26 International Business Machines Corporation Dynamic thread pool tuning techniques
US20040128651A1 (en) 2002-12-31 2004-07-01 Michael Lau Method and system for testing provisioning and interoperability of computer system services
US7207043B2 (en) 2002-12-31 2007-04-17 International Business Machines Corporation Programmatic response-time based workload distribution techniques
US6948032B2 (en) 2003-01-29 2005-09-20 Sun Microsystems, Inc. Method and apparatus for reducing the effects of hot spots in cache memories
US7114150B2 (en) 2003-02-13 2006-09-26 International Business Machines Corporation Apparatus and method for dynamic instrumenting of code to minimize system perturbation
US7290254B2 (en) 2003-03-25 2007-10-30 Intel Corporation Combining compilation and instruction set translation
JP3955285B2 (en) 2003-03-27 2007-08-08 松下電器産業株式会社 Inverter control device for motor drive and air conditioner
US6944722B2 (en) 2003-04-14 2005-09-13 Sun Microsystems, Inc. Method and system for postmortem identification of falsely shared memory objects
US6981128B2 (en) 2003-04-24 2005-12-27 International Business Machines Corporation Atomic quad word storage in a simultaneous multithreaded system
US7469407B2 (en) 2003-04-24 2008-12-23 International Business Machines Corporation Method for resource balancing using dispatch flush in a simultaneous multithread processor
US7181723B2 (en) 2003-05-27 2007-02-20 Intel Corporation Methods and apparatus for stride profiling a software application
US7194732B2 (en) 2003-06-26 2007-03-20 Hewlett-Packard Development Company, L.P. System and method for facilitating profiling an application
US7415699B2 (en) 2003-06-27 2008-08-19 Hewlett-Packard Development Company, L.P. Method and apparatus for controlling execution of a child process generated by a modified parent process
US7594219B2 (en) 2003-07-24 2009-09-22 International Business Machines Corporation Method and apparatus for monitoring compatibility of software combinations
US6918606B2 (en) 2003-08-11 2005-07-19 Radio Flyer Inc. Tricycle push handle arrangement
US20050071612A1 (en) 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus for generating interrupts upon execution of marked instructions and upon access to marked memory locations
US20050071611A1 (en) 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus for counting data accesses and instruction executions that exceed a threshold
US20050071816A1 (en) 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus to autonomically count instruction execution for applications
US20050071821A1 (en) 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus to autonomically select instructions for selective counting
US20050071608A1 (en) 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus for selectively counting instructions and data accesses
US20050071516A1 (en) 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus to autonomically profile applications
US7937691B2 (en) 2003-09-30 2011-05-03 International Business Machines Corporation Method and apparatus for counting execution of specific instructions and accesses to specific data locations
US7373637B2 (en) 2003-09-30 2008-05-13 International Business Machines Corporation Method and apparatus for counting instruction and memory location ranges
US20050071609A1 (en) 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus to autonomically take an exception on specified instructions
US7395527B2 (en) 2003-09-30 2008-07-01 International Business Machines Corporation Method and apparatus for counting instruction execution and data accesses
US20050071610A1 (en) 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus for debug support for individual instructions and memory locations
TWI258078B (en) 2003-10-07 2006-07-11 Via Tech Inc Pre-fetch controller and method thereof
US8381037B2 (en) 2003-10-09 2013-02-19 International Business Machines Corporation Method and system for autonomic execution path selection in an application
US7225309B2 (en) 2003-10-09 2007-05-29 International Business Machines Corporation Method and system for autonomic performance improvements in an application via memory relocation
US7421681B2 (en) 2003-10-09 2008-09-02 International Business Machines Corporation Method and system for autonomic monitoring of semaphore operation in an application
US6925424B2 (en) 2003-10-16 2005-08-02 International Business Machines Corporation Method, apparatus and computer program product for efficient per thread performance information
US20050091456A1 (en) 2003-10-23 2005-04-28 Huck Jerome C. Determining an arrangement of data in a memory for cache efficiency
US7257657B2 (en) 2003-11-06 2007-08-14 International Business Machines Corporation Method and apparatus for counting instruction execution and data accesses for specific types of instructions
US7458078B2 (en) 2003-11-06 2008-11-25 International Business Machines Corporation Apparatus and method for autonomic hardware assisted thread stack tracking
US7162594B2 (en) 2003-11-19 2007-01-09 Buffalo Inc. Memory module indicator device
US7082486B2 (en) 2004-01-14 2006-07-25 International Business Machines Corporation Method and apparatus for counting interrupts by type
US20050155022A1 (en) 2004-01-14 2005-07-14 International Business Machines Corporation Method and apparatus for counting instruction execution and data accesses to identify hot spots
US20050155018A1 (en) 2004-01-14 2005-07-14 International Business Machines Corporation Method and apparatus for generating interrupts based on arithmetic combinations of performance counter values
US7114036B2 (en) 2004-01-14 2006-09-26 International Business Machines Corporation Method and apparatus for autonomically moving cache entries to dedicated storage when false cache line sharing is detected
US7526757B2 (en) 2004-01-14 2009-04-28 International Business Machines Corporation Method and apparatus for maintaining performance monitoring structures in a page table for use in monitoring performance of a computer program
US7392370B2 (en) 2004-01-14 2008-06-24 International Business Machines Corporation Method and apparatus for autonomically initiating measurement of secondary metrics based on hardware counter values for primary metrics
US7293164B2 (en) 2004-01-14 2007-11-06 International Business Machines Corporation Autonomic method and apparatus for counting branch instructions to generate branch statistics meant to improve branch predictions
US7093081B2 (en) 2004-01-14 2006-08-15 International Business Machines Corporation Method and apparatus for identifying false cache line sharing
US7290255B2 (en) 2004-01-14 2007-10-30 International Business Machines Corporation Autonomic method and apparatus for local program code reorganization using branch count per instruction hardware
US7496908B2 (en) 2004-01-14 2009-02-24 International Business Machines Corporation Method and apparatus for optimizing code execution using annotated trace information having performance indicator and counter information
US7197586B2 (en) 2004-01-14 2007-03-27 International Business Machines Corporation Method and system for recording events of an interrupt using pre-interrupt handler and post-interrupt handler
US7415705B2 (en) 2004-01-14 2008-08-19 International Business Machines Corporation Autonomic method and apparatus for hardware assist for patching code
US7895382B2 (en) 2004-01-14 2011-02-22 International Business Machines Corporation Method and apparatus for qualifying collection of performance monitoring events by types of interrupt when interrupt occurs
US7181599B2 (en) 2004-01-14 2007-02-20 International Business Machines Corporation Method and apparatus for autonomic detection of cache “chase tail” conditions and storage of instructions/data in “chase tail” data structure
CA2494000C (en) 2004-01-23 2014-12-02 Kevin Mckenzie Remotely activated tank hatch system
US7987453B2 (en) 2004-03-18 2011-07-26 International Business Machines Corporation Method and apparatus for determining computer program flows autonomically using hardware assisted thread stack tracking and cataloged symbolic data
US7421684B2 (en) 2004-03-22 2008-09-02 International Business Machines Corporation Method and apparatus for autonomic test case feedback using hardware assistance for data coverage
US7299319B2 (en) 2004-03-22 2007-11-20 International Business Machines Corporation Method and apparatus for providing hardware assistance for code coverage
US20050210450A1 (en) 2004-03-22 2005-09-22 Dimpsey Robert T Method and appartus for hardware assistance for data access coverage
US8135915B2 (en) 2004-03-22 2012-03-13 International Business Machines Corporation Method and apparatus for hardware assistance for prefetching a pointer to a data structure identified by a prefetch indicator
US7480899B2 (en) 2004-03-22 2009-01-20 International Business Machines Corporation Method and apparatus for autonomic test case feedback using hardware assistance for code coverage
US7296130B2 (en) 2004-03-22 2007-11-13 International Business Machines Corporation Method and apparatus for providing hardware assistance for data access coverage on dynamically allocated data
US7526616B2 (en) 2004-03-22 2009-04-28 International Business Machines Corporation Method and apparatus for prefetching data from a data structure
US7895473B2 (en) 2004-04-29 2011-02-22 International Business Machines Corporation Method and apparatus for identifying access states for variables
CA2594754A1 (en) 2005-01-13 2006-07-20 Hsbc North America Holdings Inc. Computer software implemented framework for configuration and release management of group systems software, and method for same
US20080088609A1 (en) 2006-10-16 2008-04-17 King I Tech Corporation Control system with a display interface for a fitness equipment meter
JP5103127B2 (en) 2007-10-05 2012-12-19 株式会社日立製作所 RFID tag
US20090287729A1 (en) 2008-05-16 2009-11-19 Microsoft Corporation Source code coverage testing
US20090300587A1 (en) 2008-05-27 2009-12-03 Microsoft Corporation Determining domain data coverage in testing database applications
US20110105970A1 (en) 2009-11-02 2011-05-05 Gainer Jr James V Anatomical support braces and methods

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5691920A (en) * 1995-10-02 1997-11-25 International Business Machines Corporation Method and system for performance monitoring of dispatch unit efficiency in a processing system
US6253338B1 (en) * 1998-12-21 2001-06-26 International Business Machines Corporation System for tracing hardware counters utilizing programmed performance monitor to generate trace interrupt after each branch instruction or at the end of each code basic block
US6356615B1 (en) * 1999-10-13 2002-03-12 Transmeta Corporation Programmable event counter system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102576327A (en) * 2009-09-29 2012-07-11 国际商业机器公司 Enhanced monitor facility
CN102576327B (en) * 2009-09-29 2014-12-17 国际商业机器公司 Method and system for monitoring computing environment

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