CN100362710C - Nitride semiconductor device and fabrication method thereof, and method for forming nitride semiconductor substrate - Google Patents
Nitride semiconductor device and fabrication method thereof, and method for forming nitride semiconductor substrate Download PDFInfo
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- CN100362710C CN100362710C CNB2004800021820A CN200480002182A CN100362710C CN 100362710 C CN100362710 C CN 100362710C CN B2004800021820 A CNB2004800021820 A CN B2004800021820A CN 200480002182 A CN200480002182 A CN 200480002182A CN 100362710 C CN100362710 C CN 100362710C
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Abstract
A nitride semiconductor device comprising a substrate (101) having trenches (102b) each formed of a cavity and peaks (102a) formed from a group III nitride on the surface thereof; a nitride semiconductor layer (106) formed on the substrate (101); and a nitride semiconductor multilayered structure that is formed on the nitride semiconductor layer (106) and has an active layer, wherein the lattice constant of the substrate (101) is different from that of the group III nitride substance (102a), the substrate (101) has a mask (104a) formed from a dielectric (104), the mask (104a) is formed only on the side surfaces of the peaks (102a), the upper surfaces of the peaks (102a) are exposed and the substrate (101) is exposed in the trenches (102b), a height L1 of the mask (104a) is not less than 50 nm and not more than 5000 nm, a width L2 of the trench (102b) is not less than 5000 nm and not more than 50000 nm, and an aspect ratio L1/L2 of the trenches (102b) is not less than 0.001 and not more than 1.0. This structure enhances the reliability of the nitride semiconductor devices.
Description
Technical field
The present invention relates to the semiconductor element of semiconductor laser or semiconductor light-emitting apparatus etc. and the manufacture method of manufacture method and nitride semiconductor base plate thereof.
Background technology
Nitride-based semiconductor is expected to material as the short-wave long light-emitting element according to the size of its band gap width, waits in expectation in the application of aspects such as optical information processing field.Wherein, the research of gallium nitride compound semiconductor (for example GaN based semiconductor of GaN, AlGaN, GaInN, AlGaInN etc.) is being carried out energetically, blue LED (LED) and green LED be practicability.In addition, for the high capacity of optical disc apparatus, need have the semiconductor laser of oscillation wavelength at the 400nm band, noticeable is to be the semiconductor laser of material with the GaN based semiconductor, now, has reached practical level.
As the substrate that nitride semiconductor crystal is grown up, preferably use nitride-based semiconductor the volume substrate (bulk substrate: the block substrate), still because the price height is difficult to buy, so, typically use sapphire substrate or SiC substrate etc.Yet these substrates and nitride semiconductor crystal lattice do not match, so, in the GaN layer that on sapphire substrate for example, forms with about 1 * 10
9Cm
-2Dislocation density have dislocation.This dislocation is the reason that the reliability of the semiconductor element of manufacturing reduces, so, all reduce dislocation density in research in the past.Particularly, now known by between substrate and nitride semiconductor layer, forming the method that space part ground crystalline growth reduces dislocation density.
For example, open in the 2001-274093 communique the spy, disclose the manufacture method that is become the semiconductor substrate of space part on the crystalline growth face of substrate by the crystallization that the concavo-convex GaN of making based compound semiconductor etc. is set from the upper portion of protuberance along laterally carrying out crystalline growth by the recess that semiconductor layer covered.
In addition, open in the 2001-168042 communique, disclose concave surface setting by on the crystalline growth face, having concavo-convex substrate by SiO the spy
2Deng the mask that constitutes and become the manufacture method of the semiconductor substrate of space part with the upper portion of protuberance as starting point along laterally carrying out crystalline growth by the recess that semiconductor layer covered.
In addition, open in the 2002-9004 communique the spy, disclose by in the GaN layer that on substrate, forms protuberance formed striated and after the bottom surface of recess and sidewall form mask above protuberance the edge laterally carry out crystalline growth and become the manufacture method of the semiconductor substrate of space part by the recess that semiconductor layer covered.
Particularly, as shown in figure 10, at first, on sapphire substrate 1001, supply with TMG and NH down at 500 ℃
3, pile up after the GaN resilient coating (not shown), make substrate temperature be warmed up to 1020 ℃, supply with TMG and NH
3, pile up GaN layer 1002.Then, as shown in figure 11, utilize photoetching technique to form the resist 1003 of striated on the surface of GaN layer 1002, by with of the dry ecthing of this resist 1003, the Surface Machining of GaN layer 1002 is become groove shape (concavity) as mask.Secondly, as shown in figure 12, use the ECR sputtering method on whole surface, to pile up the dielectric 1004 that constitutes by silicon nitride film.And, as shown in figure 13, remove the dielectric 1004 of resist 1003 and top thereof by separating treatment (liftoff).Then, when the selection of using the MOVPE method that the exposed portions serve above the protuberance in the GaN layer 1002 is carried out GaN as kind of crystallization is laterally grown up, laterally be integrated between the adjacent GaN that grows up, as shown in figure 14, at the GaN layer 1005 of surface formation as smooth continuous film.As a result, below GaN layer 1005, just form space part 1006.
The manufacture method of the disclosed semiconductor substrate of above-mentioned each communique, all be by with near above the protuberance on the substrate as starting point make nitride semiconductor crystal grow up and with recess as space part, but, as the spy open the 2001-274093 communique disclosed when substrate surface is not provided with mask, or when opening the 2001-168042 communique and only mask being set disclosed, all have the problem that may below semiconductor layer, can not form space part in the recess bottom surface of substrate as special.
In addition, the manufacture method that the spy opens the disclosed semiconductor substrate of 2002-9004 communique is to form mask in the bottom surface and the side of substrate recess, compares with the manufacture method of the above-mentioned semiconductor substrate that has earlier, and the formation of space part is easy.Yet because the formation of mask utilizes sputtering method to carry out, so the spreadability of concavo-convex step is bad, the spreadability of substrate recess side is insufficient easily.Therefore between substrate and semiconductor layer, form reliably space part aspect also have the leeway of improvement.In addition, owing to utilize partition method to carry out removing of resist figure above the protuberance and silicon nitride film, so, be difficult to remove equably the resist figure above the protuberance, thereby residual a part of resist figure might hinder crystalline growth above the protuberance.
List of references
The spy opens the 2001-274093 communique
The spy opens the 2001-168042 communique
The spy opens 2002-9004 communique (content that discloses No. 1104031 communique with European patent is identical)
The spy opens the 2001-176813 communique
The spy opens 2001-342100 communique (paragraph 0022)
International No. 01/84608 Fact Book (content that discloses No. 1278233 communique with European patent is identical) that disclose
Summary of the invention
The present invention is motion in order to address the above problem, and purpose aims to provide the manufacture method of the employed nitride semiconductor base plate of manufacturing of reliability is high by form space part reliably between substrate and nitride semiconductor layer nitride semiconductor device and manufacture method thereof and such nitride semiconductor device.
Above-mentioned purpose of the present invention, utilize the manufacture method of the nitride semiconductor device of the following stated to reach, the manufacture method of this nitride semiconductor device is characterised in that: order comprises: be formed with the recess that constitutes by the space from the teeth outwards and the substrate of the protuberance that constitutes by the III group-III nitride on, by making the crystallization of III group-III nitride form the horizontal growth operation of nitride semiconductor layer as kind of crystallization the top of raised part along laterally growing up; Form the duplexer formation operation that the nitride semiconductor layer with active layer is folded body with surface at above-mentioned nitride semiconductor layer, the lattice constant of aforesaid substrate is different with the lattice constant of above-mentioned III group-III nitride, aforesaid substrate has the mask that is made of dielectric, the crystallization of above-mentioned III group-III nitride is grown up along horizontal in the temperature more than 900 ℃, aforementioned mask only forms in the side of raised part, expose above the raised part, and expose substrate at above-mentioned recess, the height L1 of aforementioned mask is below the above 5000nm of 50nm, the width L2 of above-mentioned recess is below the above 50000nm of 5000nm, and the depth-width ratio L1/L2 of above-mentioned recess is more than 0.001 below 1.0.
In addition, above-mentioned purpose of the present invention, utilize the nitride semiconductor device of the following stated to reach, this nitride semiconductor device is characterised in that: the substrate with the protuberance that is formed with the recess that is made of the space on the surface and is made of the III group-III nitride, at nitride semiconductor layer that forms on the aforesaid substrate and the folded body of the nitride semiconductor layer that on above-mentioned nitride semiconductor layer, forms with active layer, the lattice constant of aforesaid substrate is different with the lattice constant of above-mentioned III group-III nitride, aforesaid substrate has the mask that is made of dielectric, aforementioned mask only forms in the side of raised part, expose above the raised part, and expose substrate at above-mentioned recess, the height L1 of aforementioned mask is below the above 5000nm of 50nm, the width L2 of above-mentioned recess is below the above 50000nm of 5000nm, and the depth-width ratio L1/L2 of above-mentioned recess is more than 0.001 below 1.0.
In addition, above-mentioned purpose of the present invention, utilize the manufacture method of the nitride semiconductor base plate of the following stated to reach, the manufacture method of this nitride semiconductor base plate is characterised in that: order comprises: be formed with the recess that constitutes by the space from the teeth outwards and the substrate of the protuberance that constitutes by the III group-III nitride on, the horizontal growth operation that forms nitride semiconductor layer along laterally growing up by the top crystallization that makes the III group-III nitride for kind of crystallization with raised part with by above-mentioned nitride semiconductor layer is separated the separation circuit that obtains the nitride semiconductor base plate that constitutes by above-mentioned nitride semiconductor layer with aforesaid substrate, the lattice constant of aforesaid substrate is different with the lattice constant of above-mentioned III group-III nitride, aforesaid substrate has the mask that is made of dielectric, the crystallization of above-mentioned III group-III nitride is grown up along horizontal in the temperature more than 900 ℃, aforementioned mask only forms in the side of raised part, expose above the raised part, and expose substrate at above-mentioned recess, the height L1 of aforementioned mask is below the above 5000nm of 50nm, the width L2 of above-mentioned recess is below the above 50000nm of 5000nm, and the depth-width ratio L1/L2 of above-mentioned recess is more than 0.001 below 1.0.
Description of drawings
Fig. 1～Fig. 8 is the operation sectional view of manufacture method that is used to illustrate the nitride semiconductor base plate of embodiments of the present invention.The details of Fig. 1～Fig. 8 is as follows.
The lamella that Fig. 1 represents to make the crystal seed layer 102 that is made of the III group-III nitride to grow up on substrate 101 forms operation.
The surface sediment protuberance that Fig. 2 is illustrated in crystal seed layer 102 forms the mask layer accumulation operation of using mask layer 103.
Fig. 3 is illustrated in protuberance and forms with the mask layer patterns chemical industry preface that forms figure on the mask layer 103.
Fig. 4 represents patterned protuberance is formed with the lamella etching work procedure of mask layer 103 as mask etching crystal seed layer 102.
Fig. 5 represents to remove operation with mask layer 103 formation by crystal seed layer 102 protuberance 102a that constitutes and the mask layer that exposes the recess 102b of substrate 101 by removing protuberance formation.
The dielectric that the surface that Fig. 6 is illustrated in the substrate 101 that comprises protuberance 102a forms the dielectric 104 of stratiform forms operation.
Fig. 7 represent by dielectric 104 is carried out anisotropic etching remove the top dielectric 104 of protuberance 102a and recess 102b the bottom surface dielectric 104 and only the mask of the residual mask 104a that is made of dielectric 104 forms operation in the side of protuberance 102a.
Fig. 8 be illustrated in that the surface is formed with the recess 102b that is made of the space and the substrate 101 of the protuberance 102a that constitutes by the III group-III nitride on form the horizontal growth operation of nitride semiconductor layer 106 by the crystallization that makes the III group-III nitride along laterally growing up as kind of crystallization with the top of protuberance 102a.
The duplexer that the surface that Fig. 9 is illustrated in nitride semiconductor layer 106 forms the folded body of nitride semiconductor layer with active layer forms operation, also is the sectional view of the semiconductor element of the embodiments of the present invention made of the nitride semiconductor base plate that utilizes the manufacture method by above-mentioned nitride semiconductor base plate to obtain.
Figure 10～Figure 14 is the operation sectional view that is used to illustrate the manufacture method of the nitride semiconductor base plate that has earlier.
Embodiment
Below, with reference to the description of drawings embodiments of the present invention.Fig. 1～Fig. 8 is the operation sectional view of manufacture method that is used to illustrate the nitride semiconductor base plate of embodiments of the present invention.
At first, as shown in Figure 1, on substrate 101, supply with TMG and NH down at 500 ℃
3, pile up after the resilient coating (not shown) that constitutes by GaN, be warmed up to 1020 ℃, supply with TMG and NH
3, pile up the crystal seed layer 102 that constitutes by the III group-III nitride that with GaN is representative.Then, as shown in Figure 2, utilize plasma CVD method to pile up by SiO
2The protuberance that constitutes forms with mask layer 103.As the material of crystal seed layer 102, in the present embodiment, adopt GaN, still, also can be the GaN based material that comprises In or Al, in addition, also can be other III group-III nitrides.In addition, in the present embodiment, as substrate 101, having used sapphire substrate, still, also can be other substrates of the material different with III group-III nitride lattice constant such as SiC substrate.
Secondly, utilize photoetching to form the resist figure (not shown) that forms striated with the surface of mask layer 103 at protuberance.The size of resist figure is that for example wide 3 microns, the repetition period of figure is 15 microns.And, be that mask use fluorine is that gas carries out reactive ion etching with above-mentioned resist figure, as shown in Figure 3, protuberance is formed realize graphical with mask layer 103.
In addition, after removing resist, forming with mask layer 103 with patterned protuberance is that mask utilization use chlorine is the reactive ion etching of gas, and as shown in Figure 4, it is graphical that crystal seed layer 102 is realized, thereby the part of substrate 101 is exposed.
Then, utilize the fluoric acid (buffered hydrofluoric acid) of buffering to carry out wet etching, remove protuberance and form with mask layer 103.As a result, as shown in Figure 5, form a plurality of protuberance 102a that constitute by crystal seed layer 102, between each protuberance 102a, form the recess 102b that exposes substrate 101 on the surface of substrate 101.This recess 102b constitutes the space.The side of protuberance 102a is in order to form easily the described mask in back, preferably with the surperficial approximate vertical of substrate 101.Therefore, form the material of using mask layer 103, preferably use and to guarantee that to crystal seed layer 102 (being GaN in the present embodiment) material of bigger etching selectivity (is SiO in the present embodiment as protuberance
2).
Secondly, as shown in Figure 6, (Low Pressure Chemical VaporDeposition: the low-pressure chemical vapor phase deposition method) method covers the substrate surface that comprises protuberance 102a and recess 102b and all piles up the dielectric 104 that is made of for example silicon nitride film of the about 300nm of thickness to utilize LPCVD.The formation of dielectric 104, the method for the concavo-convex coverage property that preferred utilization can obtain coordinating is carried out, and except above-mentioned LPCVD method, also can utilize plasma CVD method, atmospheric pressure cvd method, optical cvd method etc.In addition, dielectric 104 also can use silicon oxide film, silicon oxynitride film, pellumina, aluminum oxynitride film, oxidation titanium film, zirconium oxide film, niobium oxide film etc. except silicon nitride film, perhaps, also can be their duplexers more than 2 kinds.The thickness of the dielectric 104 that the covered substrate surface is all is by the decisions such as height of protuberance 102a, and still, below the preferred above 5000nm of 10nm, and the above 500nm of 50nm is with more preferably next.
Then, substrate surface being used fluorine is the reactive ion etching of gas.In reactive ion etching, remove the dielectric 104 of the bottom surface that covers the top of protuberance 102a and recess 102b, on the other hand, the monitoring by luminescence of plasma intensity etc., control etching thickness keeps the dielectric 104 that forms in the side of protuberance 102a.One example of etching condition is that importing gas is CF
4(20sccm), etching period is that 300 seconds, chamber pressure are that 6.7Pa, power are 80w.
As shown in Figure 7, utilize such anisotropic etching, expose substrate 101, on protuberance 102a, only form the mask 104a that constitutes by dielectric 104 in the side in the bottom surface of recess 102b, and protuberance 102a above become the state that exposes.
Secondly, (Metal-Organic Chemical Vapor Deposition: metal/organic-matter chemical gas-phase depositing) method forms semiconductor layer at substrate surface to use MOCVD.As the material of semiconductor layer, the same with crystal seed layer 102, can use the III group-III nitride, particularly the GaN based material is more preferably.In the present embodiment, (trimethyl gallium: trimethylgallium), V family raw material adopts NH to III family raw material employing TMG
3(ammonia).V group element is preferably 3000～5000 with the material flow of III family element than (V/III ratio), and pressure is preferably 1.3 * 10
4～4.0 * 10
4Pa, temperature is preferably 900～1100 ℃.
Such being chosen under the elongate member, with the protuberance 102a that exposes is kind of crystallization when laterally carrying out crystalline growth, the crystalline phase of growing up between adjacent protuberance 102a links, and as shown in Figure 8, is to form the semiconductor layer 106 that is made of GaN under the state of space part at recess 102b.
In the crystalline growth condition that forms semiconductor layer 106, the temperature conditions particular importance.When the crystalline growth temperature is too low, bottom at recess 102b will generate crystallization, thereby space part might be eliminated, on the other hand, when temperature is too high, the flatness of the crystallization side in laterally growing up might incur loss, so, as mentioned above, must be more than 900 ℃, preferably in the temperature range below 1100 ℃, and more than 950 ℃ 1080 ℃ with more preferably next.In addition, according to the described reason in back, must be more than 900 ℃.
Manufacture method according to the nitride semiconductor device of present embodiment, utilize the CVD method all to form dielectric 104 having concavo-convex substrate surface, by this dielectric layer is carried out anisotropic etching, the mask 104a that is made of dielectric 104 is kept reliably in the side of protuberance 102a.As a result, when crystalline growth is laterally carried out in the edge directly over protuberance 102a, prevent from recess 102b is buried by semiconductor layer 106, thereby can below semiconductor layer 106, form space part reliably.
The protuberance 102a that is made of GaN forms on the substrate 101 that is made of sapphire, so, owing to matching, lattice do not have crystal defect.This crystal defect when semiconductor layer 106 is grown up to directly over to growth, the result near the protuberance 102a of semiconductor layer 106, becomes dislocation density and is about 1 * 10
9Cm
-2The high dislocation density zone.In contrast, the area just above of the recess 102b of semiconductor layer 106, be with protuberance 102a be kind of crystallization along the zone of laterally carrying out crystalline growth, so, become dislocation density and be about 1 * 10
7Cm
-2The low-dislocation-density zone.Therefore, in order to obtain the low-dislocation-density zone nitride semiconductor base plate relatively bigger, preferably increase the width of recess 102b as far as possible than high dislocation density zone.But, when the width of recess 102b is too big, will be difficult to keep space part owing to the height of mask 104a between substrate 101 and the semiconductor layer 106.
Promptly, in Fig. 7, when the height L1 of mask 104a was too big, the thickness of crystal seed layer 102 was just too big, thereby needed etch quantity surplus, on the other hand, too hour, be difficult to form space part, so, must be below the above 5000nm of 50nm, below the preferred above 2000nm of 500nm, and the above 1200nm of 800nm is with more preferably next.
In addition, the width of recess 102b (between the side of adjacent protuberance 102a) is when L2 is too big, be difficult to form space part, on the other hand, too hour, can not obtain abundant low-dislocation-density zone, so, must be below the above 50000nm of 5000nm, below the preferred above 20000nm of 8000nm, and the above 15000nm of 10000nm is with more preferably next.
In addition, when the depth-width ratio of recess 102b (L1/L2) is too big, be used for the etching work procedure surplus of the formation of protuberance 102a, on the other hand, too hour, be difficult to form space part, so, must be more than 0.001 below 1.0, preferred more than 0.01 below 0.5, and more than 0.05 0.15 with more preferably next.
By changing L1 and L2, and the results are shown in table 1 to what the semiconductor substrate of various depth-width ratios was estimated.As shown in table 1, confirmed that by experiment depth-width ratio (L1/L2) is being good below 1.0 more than 0.001.
Table 1
| Depth-width ratio | L1 (nm) | L2 (nm) | The result | |
| 0.0008 | 50 | 60000 | × | Do not form space part |
| 0.001 | 50 | 50000 | ○ | Confirm the formation in low-dislocation-density zone |
| 0.05 | 1000 | 20000 | ○ | ↑ |
| 0.08 | 1000 | 12000 | ○ | ↑ |
| 1.0 | 5000 | 5000 | ○ | ↑ |
| 1.2 | 5000 | 4200 | × | Can not guarantee sufficient low-dislocation-density zone |
In the present embodiment, getting L1 is 1000nm, and L2 is 12000nm, and depth-width ratio (L1/L2) is about 0.08.
In addition, in Fig. 7, when the width L3 of mask 104a is too big, the thickness surplus of needed dielectric 104, on the other hand, too hour, the process allowance of the anisotropic etching operation of dielectric 104 diminishes, so, below the preferred above 1000nm of 10nm, more preferably below the above 500nm of 50nm, and the above 300nm of 100nm is with more preferably next.But, L3＜L2/2.In the present embodiment, getting L3 is 200nm.
In addition, when the width L4 of protuberance 102a is too big, the low-dislocation-density zone of semiconductor layer 106 compares less, on the other hand, too hour, be difficult to form kind of a crystallization, so, below the preferred above 10000nm of 500nm, more preferably below the above 5000nm of 1000nm, below the above 4000nm of 2000nm on then more preferably.In the present embodiment, getting L4 is 3000nm.
Here, can think that the do not grow up reason of crystallization is roughly as follows on sapphire substrate 101.
Usually supply with TMG or NH to sapphire substrate
3During etc. unstrpped gas, the crystallization that on sapphire substrate, will grow up and constitute by GaN.
But, under the atmosphere of the high temperature more than 900 ℃, arrive sapphire substrate 101 surfaces based on the raw material of Ga and N and than the crystal lattice of GaN and spacing of lattice from the not combination of sapphire that departs from about 14%, on the surface of sapphire substrate 101, repel mutually.For the substrate (that is, comparing spacing of lattice from the substrate that departs from) beyond the GaN substrates such as SiC substrate too with the crystal lattice of GaN.
On the other hand, in the present invention, the height L1 of mask 104a is below the above 5000nm of 50nm, the width L2 of recess 102b is below the above 50000nm of 5000nm, the depth-width ratio L1/L2 of recess 102b is more than 0.001 below 1.0, so near the surface of sapphire substrate 101, existing with GaN is the protuberance 102 that is made of the III group-III nitride of representative.Arrive the top raw material of this protuberance 102 based on Ga and N and since be the spacing of lattice that has of the lattice of protuberance 102 from substantially the same, so, serve as that crystalline growth is carried out in a kind crystallization with protuberance 102.
Like this, thereby after the tabular III group-III nitride body that formation semiconductor layer 106 shown in Figure 8 obtains being made of this semiconductor layer 106 and substrate 101, as shown in Figure 9, utilize well-known method, by sequential cascade n type nitride semiconductor layer, by active layer and p type nitride semiconductor layer that multiple quantum trap structure constitutes, can obtain nitride semiconductor device.These n type nitride semiconductor layers, active layer and p type nitride semiconductor layer are generically and collectively referred to as the folded body of nitride semiconductor layer.
Particularly, after the superficial layer of nitride semiconductor base plate 100 formed n-GaN layer 106a, order was piled up n-Al
0.07Ga
0.93Coating layer 107, n-GaN photoconductive layer 108, multiple quantum trap (MQW) active layer 109, p-GaN photoconductive layer 110, p-Al
0.07Ga
0.93N coating layer 111 and p-GaN layer 112.And, with p-GaN layer 112 and p-Al
0.07Ga
0.93N coating layer 111 is processed into the about 2 microns ridged shape of stripes of width, is covered by the both sides of dielectric film 113 with the R of spine, forms the current injection area territory.The R of spine is formed on as the low-dislocation-density zone on the recess 112b of space part.In addition, the part on the surface of the dielectric film 113 that comprises p-GaN layer 112 is provided with p electrode 114, simultaneously, on the n-GaN layer 106 that exposes a part by etching n electrode 115 is set.
The semiconductor laser that obtains like this, by voltage being added between p electrode 114 and the n electrode 115, respectively from p electrode 114 to MQW active layer 109 injected holes, inject electronics from n electrode 115 to MQW active layer 109, cause laser vibration (wavelength 404nm) by obtaining gain at MQW active layer 109.According to this semiconductor laser, form the semiconductor multilayer body that comprises active layer on the surface of the nitride semiconductor base plate of present embodiment, so, reliability can be improved, thereby qualification rate can be improved as element.
After forming semiconductor layer 106, in order to obtain nitride semiconductor base plate, from the rear side of substrate 101 to the protuberance 102a of the kind crystallization that becomes semiconductor layer 106 irradiation ultraviolet radiation laser UL (Nd:YAG laser alignment 3 high frequency waves (wavelength 355nm)).Like this, the GaN of protuberance 102a is because photochemical effect and deterioration, thereby substrate 101 separates with semiconductor layer 106.Like this, just, can make nitride semiconductor base plate with the semiconductor layer 106 that constitutes by GaN.
The wavelength that shines the ultraviolet laser on the substrate 101 is preferably in the scope of 150nm～400nm.In addition, the focal position of the laser beam of irradiation is set in protuberance 102a, and beam waist is preferably less than the width of protuberance 102a.
Scan method as laser beam mainly contains the combination, (3) of the combination, (2) mirror polygon (polygonmirror) of (1) automatically controlled beam flying mirror (galvanomirror) and f-θ lens and f-θ lens 3 methods that move based on the x-y workbench.In order correctly to keep the beams focusing position, preferably use the method for the mobile x-y workbench of (3) to scan.Here, the direction of scanning is the direction of striped preferably, promptly GaN＜1-100 direction.
In addition, in order more effectively to carry out separating of substrate 101 and semiconductor layer 106, before the irradiation of ultraviolet laser, the substrate after can forming semiconductor layer 106 is being to carry out about 6 hours thermal anneal process with about 1000 ℃ under the atmosphere of inert gases of representative under the nitrogen atmosphere.At this moment, in order not to be subjected to the damage that nitrogen-atoms is separated out etc. from the GaN of protuberance 102a, annealing temperature preferably maintains below 1200 ℃.
In addition, when protuberance 102a is made of InGaN, compare with GaN, big with the lattice degree of not matching of substrate 101, the crystallinity of InGaN reduces owing to be separated, thereby a lot of defectives and space take place.The InGaN that is separated is easily because heat energy or luminous energy and deterioration utilizes thermal annealing and laser radiation only to remove InGaN selectively, so, can be easy to substrate 101 is separated with GaN based semiconductor layer 106.
Industrial utilizability
As mentioned above, according to the present invention, by between substrate and nitride semiconductor layer, forming reliably space part, can provide the manufacture method of the employed nitride semiconductor base plate of manufacturing of the high nitride semiconductor device of reliability and manufacture method thereof and such nitride semiconductor device.
Claims (28)
1. the manufacture method of a nitride semiconductor device is characterized in that, this method comprises in proper order:
On the substrate of the protuberance that is formed with the recess that forms by the space from the teeth outwards and constitutes by the III group-III nitride, by making the crystallization of III group-III nitride form the horizontal growth operation of nitride semiconductor layer as kind of crystallization the top of described protuberance along laterally growing up; With
On the surface of described nitride semiconductor layer, the duplexer that forms the folded body of nitride semiconductor layer with active layer forms operation,
The lattice constant of described substrate is different with the lattice constant of described III group-III nitride,
Described substrate has the mask that is made of dielectric,
The crystallization of described III group-III nitride is grown up along horizontal in the temperature more than 900 ℃,
Described mask only forms in the side of described protuberance, and expose above the described protuberance, and expose substrate at described recess,
The height L1 of described mask below the above 5000nm of 50nm,
The width L2 of described recess below the above 50000nm of 5000nm,
The depth-width ratio L1/L2 of described recess is more than 0.001 below 1.0.
2. the manufacture method of nitride semiconductor device as claimed in claim 1 is characterized in that, described horizontal growth operation comprises:
The crystal seed layer of the crystal seed layer that is made of the III group-III nitride of growing up on described substrate forms operation;
Surface sediment protuberance at described crystal seed layer forms the mask layer accumulation operation of using mask layer;
Described protuberance is formed the mask layer patterns chemical industry preface of carrying out graphical treatment with mask layer;
Patterned described protuberance formation is carried out etched crystal seed layer etching work procedure as mask to described crystal seed layer with mask layer;
Form the mask layer that forms the protuberance that constitutes by described crystal seed layer and expose the recess of described substrate with mask layer and remove operation by removing described protuberance;
The dielectric dielectric that forms stratiform on the surface of the described substrate that comprises described protuberance forms operation; With
By described dielectric is carried out anisotropic etching remove the top dielectric of described protuberance and described recess the bottom surface dielectric and the mask that only keeps the mask that is made of described dielectric in the side of described protuberance forms operation.
3. the manufacture method of nitride semiconductor device as claimed in claim 1 is characterized in that:
Described nitride semiconductor layer is by forming carrying out crystalline growth below 1100 ℃.
4. the manufacture method of nitride semiconductor device as claimed in claim 1 is characterized in that:
Described III group-III nitride is the GaN based material.
5. the manufacture method of nitride semiconductor device as claimed in claim 1 is characterized in that:
Described substrate is a sapphire substrate.
6. the manufacture method of nitride semiconductor device as claimed in claim 1 is characterized in that:
The width L3 of described mask is below the above 1000nm of 10nm.
7. the manufacture method of nitride semiconductor device as claimed in claim 1 is characterized in that:
The width L4 of described protuberance is below the above 10000nm of 500nm.
8. the manufacture method of nitride semiconductor device as claimed in claim 1 is characterized in that:
Described nitride semiconductor layer by pressure 1.3 * 10
4Pa above 4.0 * 10
4Carry out crystalline growth below the Pa and form.
9. the manufacture method of nitride semiconductor device as claimed in claim 1 is characterized in that:
The material flow of described nitride semiconductor layer by V group element and III family element forms carrying out crystalline growth more than 3000 below 5000 than (V/III than).
10. nitride semiconductor device is characterized in that having:
The substrate of the protuberance that is formed with the recess that forms by the space on the surface and constitutes by the III group-III nitride;
The nitride semiconductor layer that on described substrate, forms; With
The nitride semiconductor layer that forms on described nitride semiconductor layer, have active layer is folded body,
The lattice constant of described substrate is different with the lattice constant of described III group-III nitride,
Described substrate has the mask that is made of dielectric,
Described mask only forms in the side of described protuberance, and expose above the described protuberance, and expose substrate at described recess,
The height L1 of described mask below the above 5000nm of 50nm,
The width L2 of described recess below the above 50000nm of 5000nm,
The depth-width ratio L1/L2 of described recess is more than 0.001 below 1.0.
11. nitride semiconductor device as claimed in claim 10 is characterized in that:
Described III group-III nitride is the GaN based material.
12. nitride semiconductor device as claimed in claim 10 is characterized in that:
Described substrate is a sapphire substrate.
13. nitride semiconductor device as claimed in claim 10 is characterized in that:
The width L3 of described mask is below the above 1000nm of 10nm.
14. nitride semiconductor device as claimed in claim 10 is characterized in that:
The width L4 of described protuberance is below the above 10000nm of 500nm.
15. the manufacture method of a nitride semiconductor base plate is characterized in that, this method comprises in proper order:
On the substrate of the protuberance that is formed with the recess that forms by the space from the teeth outwards and constitutes by the III group-III nitride, by making the crystallization of III group-III nitride form the horizontal growth operation of nitride semiconductor layer for kind of crystallization along laterally growing up with the top of described protuberance; With
By described nitride semiconductor layer being separated the separation circuit that obtains the nitride semiconductor base plate that constitutes by described nitride semiconductor layer with described substrate,
The described substrate that is formed with described recess and described protuberance with the surface is as first substrate, with the described nitride semiconductor base plate that constitutes by described nitride semiconductor layer as second substrate,
The lattice constant of described first substrate is different with the lattice constant of described III group-III nitride,
Described first substrate has the mask that is made of dielectric,
The crystallization of described III group-III nitride is grown up along horizontal in the temperature more than 900 ℃,
Described mask only forms in the side of described protuberance, and expose above the described protuberance, and expose first substrate at described recess,
The height L1 of described mask below the above 5000nm of 50nm,
The width L2 of described recess below the above 50000nm of 5000nm,
The depth-width ratio L1/L2 of described recess is more than 0.001 below 1.0.
16. the manufacture method of nitride semiconductor base plate as claimed in claim 15 is characterized in that:
In described separation circuit, by described nitride semiconductor layer being separated with described first substrate to described protuberance irradiating laser.
17. the manufacture method of nitride semiconductor base plate as claimed in claim 15 is characterized in that, described horizontal growth operation comprises:
The crystal seed layer of the crystal seed layer that is made of the III group-III nitride of growing up on described first substrate forms operation;
Surface sediment protuberance at described crystal seed layer forms the mask layer accumulation operation of using mask layer;
Described protuberance is formed the mask layer patterns chemical industry preface of carrying out graphical treatment with mask layer;
Patterned described protuberance formation is carried out etched crystal seed layer etching work procedure as mask to described crystal seed layer with mask layer;
Form the mask layer that forms the protuberance that constitutes by described crystal seed layer and expose the recess of described first substrate with mask layer and remove operation by removing described protuberance;
The dielectric dielectric that forms stratiform on the surface of described first substrate that comprises described protuberance forms operation; With
By described dielectric is carried out anisotropic etching remove the top dielectric of described protuberance and described recess the bottom surface dielectric and the mask that only keeps the mask that is made of described dielectric in the side of described protuberance forms operation.
18. the manufacture method of nitride semiconductor base plate as claimed in claim 15 is characterized in that:
Described nitride semiconductor layer is by forming carrying out crystalline growth below 1100 ℃.
19. the manufacture method of nitride semiconductor base plate as claimed in claim 15 is characterized in that:
Described III group-III nitride is the GaN based material.
20. the manufacture method of nitride semiconductor base plate as claimed in claim 15 is characterized in that:
Described first substrate is a sapphire substrate.
21. the manufacture method of nitride semiconductor base plate as claimed in claim 15 is characterized in that:
The width L3 of described mask is below the above 1000nm of 10nm.
22. the manufacture method of nitride semiconductor base plate as claimed in claim 15 is characterized in that:
The width L4 of described protuberance is below the above 10000nm of 500nm.
23. the manufacture method of nitride semiconductor base plate as claimed in claim 15 is characterized in that:
Described nitride semiconductor layer is by being 1.3 * 10 at pressure
4Pa above 4.0 * 10
4Carry out crystalline growth below the Pa and form.
24. the manufacture method of nitride semiconductor base plate as claimed in claim 15 is characterized in that:
The material flow of described nitride semiconductor layer by V group element and III family element carries out crystalline growth than (V/III than) and forms under the condition below 5000 more than 3000.
25. the manufacture method of nitride semiconductor base plate as claimed in claim 15 is characterized in that:
Described protuberance is made of InGaN.
26. the manufacture method of nitride semiconductor base plate as claimed in claim 15 is characterized in that:
Between described horizontal growth operation and described separation circuit, described first substrate is heat-treated under the non-active gas atmosphere.
27. the manufacture method of a tabular III group-III nitride body is characterized in that, this method comprises:
Be formed with on the surface on the substrate of recess that forms by the space and the protuberance that constitutes by the III group-III nitride, top by with described protuberance for kind of crystallization forms the horizontal growth operation of nitride semiconductor layer in the horizontal crystallization of growth III group-III nitride,
The lattice constant of described substrate is different with the lattice constant of described III group-III nitride,
Described substrate has the mask that is made of dielectric,
The crystallization of described III group-III nitride is laterally grown up in the temperature more than 900 ℃,
Described mask only forms in the side of described protuberance, and expose above the described protuberance, and expose substrate at described recess,
The height L1 of described mask below the above 5000nm of 50nm,
The width L2 of described recess below the above 50000nm of 5000nm,
The depth-width ratio L1/L2 of described recess is more than 0.001 below 1.0.
28. a tabular III group-III nitride body is characterized in that, comprising:
The substrate of the protuberance that is formed with the recess that forms by the space on the surface and constitutes by the III group-III nitride; With
The nitride semiconductor layer that on described substrate, forms,
The lattice constant of described substrate is different with the lattice constant of described III group-III nitride,
Described substrate has the mask that is made of dielectric,
Described mask only forms in the side of described protuberance, and expose above the described protuberance, and expose substrate at described recess,
The height L1 of described mask below the above 5000nm of 50nm,
The width L2 of described recess below the above 50000nm of 5000nm,
The depth-width ratio L1/L2 of described recess is more than 0.001 below 1.0.
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| TWI489016B (en) * | 2010-03-05 | 2015-06-21 | Namiki Precision Jewel Co Ltd | Single crystal substrate, single crystal substrate manufacturing method, multi-layer single-crystal substrate manufacturing method and component manufacturing method |
| KR101761309B1 (en) * | 2011-04-19 | 2017-07-25 | 삼성전자주식회사 | GaN film structure, method of fabricating the same and semiconductor device including the same |
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| EP1104031A2 (en) * | 1999-11-15 | 2001-05-30 | Matsushita Electric Industrial Co., Ltd. | Nitride semiconductor, nitride semiconductor device, semiconductor light emiting device and method of fabricating the same |
| JP2001176813A (en) * | 1999-12-15 | 2001-06-29 | Nichia Chem Ind Ltd | Method for manufacturing nitride semiconductor substrate |
| JP2001217503A (en) * | 2000-02-03 | 2001-08-10 | Matsushita Electric Ind Co Ltd | Gallium nitride based semiconductor light emitting element and its manufacturing method |
| EP1184897A1 (en) * | 1999-03-17 | 2002-03-06 | Mitsubishi Cable Industries, Ltd. | Semiconductor base and its manufacturing method, and semiconductor crystal manufacturing method |
| JP2002110569A (en) * | 2000-10-04 | 2002-04-12 | Matsushita Electric Ind Co Ltd | Method for manufacturing semiconductor device, semiconductor device and method of manufacturing semiconductor substrate |
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| EP1184897A1 (en) * | 1999-03-17 | 2002-03-06 | Mitsubishi Cable Industries, Ltd. | Semiconductor base and its manufacturing method, and semiconductor crystal manufacturing method |
| EP1104031A2 (en) * | 1999-11-15 | 2001-05-30 | Matsushita Electric Industrial Co., Ltd. | Nitride semiconductor, nitride semiconductor device, semiconductor light emiting device and method of fabricating the same |
| JP2001176813A (en) * | 1999-12-15 | 2001-06-29 | Nichia Chem Ind Ltd | Method for manufacturing nitride semiconductor substrate |
| JP2001217503A (en) * | 2000-02-03 | 2001-08-10 | Matsushita Electric Ind Co Ltd | Gallium nitride based semiconductor light emitting element and its manufacturing method |
| JP2002110569A (en) * | 2000-10-04 | 2002-04-12 | Matsushita Electric Ind Co Ltd | Method for manufacturing semiconductor device, semiconductor device and method of manufacturing semiconductor substrate |
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