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半导体装置及其制造方法

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CN100334723C
CN100334723C CN 200410038457 CN200410038457A CN100334723C CN 100334723 C CN100334723 C CN 100334723C CN 200410038457 CN200410038457 CN 200410038457 CN 200410038457 A CN200410038457 A CN 200410038457A CN 100334723 C CN100334723 C CN 100334723C
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CN 200410038457
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CN1551347A (zh )
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野间崇
铃木彰
篠木裕之
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三洋电机株式会社
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Abstract

一种半导体装置及其制造方法,不使用昂贵的装置,以低的制造成本制造层积型MCM。介由绝缘膜2在第一半导体装置100a的半导体芯片1的表面形成第一配线3A及第二配线3B。在形成有这些第一配线3A及第二配线3B的半导体芯片1的表面粘接具有露出第二配线3B的开口部12的玻璃衬底4。另外,第三配线9自半导体芯片1的背面介由绝缘膜7向半导体芯片1的侧面延伸,连接到第一配线3A上。然后,介由开口部12将另一半导体装置100b的导电端子11B连接到第二配线3B。

Description

半导体装置及其制造方法

技术领域

本发明涉及半导体装置及其制造方法,特别是涉及半导体芯片的封装技术。

背景技术

近年来,作为新的封装技术,引起人们关注的有MCM(Multi ChipModule:多片模制)。所谓MCM,是通过在一个封装中组入多个半导体芯片来实现高性能的模块的技术。MCM根据半导体芯片的配置方法有许多种类。其中,最近特别引人关注的是层积多个半导体芯片形成的“层积型MCM”。

图14显示了该层积型MCM结构的一例。该层积型MCM200是层积多个半导体芯片204的结构。通过激光加工形成贯通半导体芯片204的通孔205,并在该通孔205侧面利用喷溅法或CVD法形成势垒金属202。然后,通过镀铜将导电材料埋入所述通孔205内,形成连接上下邻接配置的半导体芯片204、204的配线。

半导体芯片204间的绝缘通过插入热塑性薄膜203保持。可通过反复进行这样的制造工序层积多个半导体芯片204。在最下方的半导体芯片204上通过安装的导电端子206和外部电路进行连接。

可利用以上的制造工序制造层积型MCM200。专利文献1中开示有所述的层积型MCM。

专利文献1特开平9-232503号公报发明内容为制造所述的层积型MCM200,必须形成直径数十um程度、具有深度的通孔并向通孔内埋入导电材料。其结果,需要在现有的半导体封装中未使用的昂贵的装置,如通孔加工用激光加工机、势垒金属成膜用势垒CVD装置、用于进行通孔的埋入的镀铜装置等,存在成本增高的问题。

在本发明的半导体装置中,介由第一绝缘膜在半导体芯片表面形成第一配线及第二配线。在形成这些第一配线及第二配线的半导体芯片表面上粘接具有使两配线露出的开口部的支撑体。另外,第三配线自半导体芯片的侧面的端部露出而连接到第一配线。

附图说明

图1是本发明实施例的半导体装置制造方法的剖面图;图2是本发明实施例的半导体装置制造方法的剖面图;图3是本发明实施例的半导体装置制造方法的剖面图;图4是本发明实施例的半导体装置制造方法的剖面图;图5是本发明实施例的半导体装置制造方法的剖面图;图6是本发明实施例的半导体装置制造方法的剖面图;图7是本发明实施例的半导体装置制造方法的剖面图;图8是本发明实施例的半导体装置制造方法的剖面图;图9是本发明实施例的半导体装置制造方法的剖面图;图10是本发明实施例的半导体装置制造方法的剖面图;图11是本发明实施例的半导体装置制造方法的剖面图;图12是本发明实施例的半导体装置制造方法的剖面图;图13是本发明实施例的半导体装置制造方法的剖面图;图14是现有的MCM型半导体装置剖面的示意图。

具体实施方式

其次,参照图1~图13说明本发明实施例的半导体装置及其制造方法。

首先,如图1所示,准备半导体晶片1a。该半导体晶片1a在后述的工序中被切断,分离为多个半导体芯片1。这些半导体芯片1是例如CCD图像传感器或半导体存储器的芯片,其通过半导体的晶片加工形成。介由绝缘膜2在该半导体晶片1a表面同时形成多个第一配线3A、多个第二配线3B。夹着用于将半导体晶片1a切断分离为多个半导体芯片1的边界S,使其两侧具有规定的间隙而形成第一配线3A。边界S被称为切割线或划线。

在此,第一配线3A是自半导体芯片1的通常的接合焊盘位置扩张至边界S附近的焊盘。另外,多个第二配线3B是在以后的工序中和层积在半导体芯片1上的与另一半导体装置的导电端子电连接的导电焊盘。

然后,在形成第一配线3A及第二配线3B的半导体晶片1a表面使用作为粘接剂的环氧树脂层5粘接作为支撑体的玻璃衬底4。在此,作为支撑体使用玻璃衬底,作为粘接剂使用玻璃树脂层。但除硅衬底或塑料板外也可以使用带或片状物质作为支撑体,是,粘接剂只要选择适于这些支撑体的粘接材料即可。

其次,如图2所示,将所述半导体晶片1a的未粘接玻璃衬底4的面,也就是其背面反向研磨加工,将半导体晶片1a的厚度变薄。反向研磨后的半导体晶片1a背面产生划痕,形成宽度、深度数um程度的凹凸。为了减小这些,使用相对于作为半导体晶片1a的材料的硅(以下称Si),比作为绝缘膜2材料的硅氧化膜(以下称SiO2)具有更高的选择比的硅蚀刻液进行湿蚀刻。作为这样的硅蚀刻液,理想的是例如氟化氢酸2.5%、硝酸50%、醋酸10%及水37.5%的混合溶液。

其次,如图3所示,对所述半导体晶片1a的背面,以沿边界S设有开口部的未图示的抗蚀图案为掩膜,进行各向同性蚀刻。由此,在边界S的局部形成槽,形成绝缘膜2部分地露出的状态。另外,该蚀刻可以由干蚀刻、湿蚀刻的任意一种进行。通过该蚀刻,半导体晶片1a被切断为多个半导体芯片1,但利用玻璃衬底4支撑,维持半导体晶片1a的形态。

在被蚀刻的半导体晶片1a的背面存在有凹凸、残渣、异物,且形成图3中虚线园a、b所示的角部。因此,如图4所示,为了除去残渣或异物,并将角部变园,而进行湿蚀刻。由此,图3虚线园a、b所示的角部形成如图4中虚线园a、b所示的圆滑形状。

其次,如图5所示,在多个半导体芯片1的背面及它们的被蚀刻的侧面被覆绝缘膜7。绝缘膜7是例如硅烷基的氧化膜。

其次,如图6所示,在半导体芯片背面涂敷未图示的抗蚀剂,并进行图案制作。将该抗蚀剂膜作为掩膜,蚀刻绝缘膜7、绝缘膜2,使第一配线3A的端部露出。

然后,在和以后形成导电端子11的位置重合的位置形成具有柔软性的缓冲部件8。另外,缓冲部件8吸收施加在导电端子11上的力,其具有缓和导电端子11接合时的应力的功能,但这并非必须的。其次,形成绝缘膜7、缓冲部件8、覆盖第一配线3A的露出部分的第三配线9。由此,将第一配线3A和第三配线9电连接。

其次,如图7所示,在半导体芯片1的背面侧涂敷未图示的抗蚀剂,使沿该抗蚀剂边界线S的部分开口,进行图案的形成。而后,将该抗蚀剂作为掩膜,进行蚀刻,除去边界S附近的第三配线9。另外,虽然未图示,但也可以在形成第三配线9后,进行无电解镀敷处理,在第三配线9的表面实施Ni-Au的镀敷。

其次,在半导体芯片1的背面侧形成保护膜10。为了形成保护膜10,将半导体芯片1的背面侧朝上,自上方向下滴下热硬性有机类树脂,使具有多个半导体芯片1且粘接了玻璃衬底4的半导体晶片1a旋转。利用该旋转产生的离心力将有机类树脂在半导体晶片1a的面上扩散。由此,可在第三配线9的表面形成保护膜10。

其次,如图8所示,将形成导电端子11的部分的保护膜10利用使用抗蚀剂掩膜的蚀刻选择地除去,使第三配线9露出,形成与该露出的第三配线9接触的导电端子11。导电端子11可利用例如焊锡补片或金补片这样的突起电极端子形成。导电端子11的厚度在使用焊锡补片时为160um,而在使用金补片时,可减少至数um~数十um。导电端子11可以以相同的结构在半导体芯片1的背面设置多个,构成球栅阵列(Ball Grid Array).

其次,通过削去玻璃衬底4的表面将其厚度变薄。由此,可缩短后述的用于在玻璃衬底4上形成开口部的加工时间。理想的玻璃衬底厚度为50um~100um。作为使玻璃衬底4变薄的方法,列举如下方法:(1)由反向研磨装置研削玻璃衬底4的方法;(2)由CMP装置研削玻璃衬底4的方法;(3)如抗蚀剂涂敷那样,向玻璃衬底4上滴蚀刻液,通过使粘接玻璃衬底4的半导体晶片1a旋转,使蚀刻液遍布玻璃衬底4的整体,蚀刻玻璃衬底4的方法;(4)利用干蚀法蚀刻玻璃衬底4的方法。另外,在本发明中具有使玻璃衬底4变薄的工序,但是,最初就使用规定厚度的板材、带或片状的物质构成的支撑体的使用并不受限制。

其次,如图10所示,利用蚀刻等除去第二配线3B的一部分上的玻璃衬底4和树脂层5,形成使第二配线3B的表面露出的开口部12。相反的,在形成开口部12后,将玻璃衬底4削薄也可以,但是,用于形成开口部12的加工时间变长。然后,在通过开口部12露出的第二配线3B的表面形成镀层13。镀层13构成第二配线3B的一部分。例如层积Ni镀层和Au镀层形成镀层13。

其次,如图12所示,使用切割装置沿边界S切断半导体晶片1a,并分离为多个半导体芯片1a。此时,沿边界S切断玻璃衬底4、树脂层5、保护层10。由此,组装了半导体芯片1a的BGA型半导体装置100完成。根据该BGA型半导体装置100,由于仅将一片支撑半导体芯片1的玻璃衬底4粘接到半导体芯片1上,且将该玻璃衬底4加工薄,故可将封装整体变薄。由于在玻璃衬底4上形成露出半导体芯片1的第二配线3B的开口部12,故可通过该开口部12实现和外部电子电路的必要的电连接。

图13是作为这种电连接结构的一例显示层积型MCM结构的剖面图。该层积型MCM层积第一半导体装置100a和第二半导体装置100b。第一半导体装置100a和第二半导体装置100b具有和所述的半导体装置100相同的结构。将第二半导体装置100B的导电端子11B通过开口部2电及机械地连接到第一半导体装置100a的第二配线3B上。当其连接强度不足时,也可以补助地使用底部填充等的有机类粘接剂。另外,层积的半导体装置的数量可根据需要进行选择。

根据本发明,可不使用昂贵的装置,以低的制造成本制造层积型MCM。

Claims (16)

1.一种半导体装置,其特征在于,包括:第一配线及第二配线,所述第一配线及第二配线介由绝缘膜形成在半导体芯片的表面;支撑体,其被粘接在形成所述第一及第二配线的所述半导体芯片的表面,且具有露出所述第二配线的开口部;第三配线,其自所述半导体芯片的侧面的端部露出,与所述第一配线连接。
2.一种半导体装置,其特征在于,包括第一半导体装置和配置在该第一半导体装置上的第二半导体装置,其中,所述第一半导体装置包括:第一配线及第二配线,所述第一配线及第二配线在第一半导体芯片的表面形成;支撑体,其被粘接在形成所述第一及第二配线的所述半导体芯片的表面,且具有露出所述第二配线的开口部;第三配线,其自所述半导体芯片的侧面的端部露出,与所述第一配线连接,所述第二半导体装置包括:第二半导体芯片;形成在该第二半导体芯片背面的导电端子,所述第二半导体装置的所述导电端子介由所述第一半导体装置的开口部被连接至所述第二配线。
3.如权利要求1或2所述的半导体装置,其特征在于,具有覆盖所述第三配线的保护膜。
4.如权利要求1或2所述的半导体装置,其特征在于,具有形成在所述第三配线上的导电端子。
5.如权利要求4所述的半导体装置,其特征在于,所述导电端子是突起电极端子。
6.如权利要求5所述的半导体装置,其特征在于,所述突起电极端子是焊锡补片或金补片。
7.如权利要求1或2所述的半导体装置,其特征在于,所述第三配线与自所述半导体芯片的侧面的端部露出的所述第一配线的背面连接。
8.一种半导体装置的制造方法,其特征在于,包括:准备具有介由第一绝缘膜形成第一配线及第二配线的多个半导体芯片的半导体晶片,在形成所述第一及第二配线的所述半导体芯片的表面粘接支撑体的工序;对所述半导体芯片的背面进行蚀刻而形成半导体芯片的侧面,并在该侧面和背面形成第二绝缘膜,进而形成从该背面介由第二绝缘膜向所述半导体芯片的侧面延伸并连接在从其端部露出的所述第一配线上的第三配线的工序;以及在所述支撑体上形成使所述第二配线露出的开口部的工序。
9.如权利要求8所述的半导体装置的制造方法,其特征在于,还包括形成覆盖所述第三配线的保护膜的工序。
10.如权利要求8所述的半导体装置的制造方法,其特征在于,所述第三配线与自所述半导体芯片的侧面的端部露出的所述第一配线的背面连接。
11.如权利要求8所述的半导体装置的制造方法,其特征在于,包括削去所述支撑体表面的工序。
12.如权利要求11所述的半导体装置的制造方法,其特征在于,削去所述支撑体表面的工序是向所述支撑体表面滴蚀刻液并使所述支撑体旋转的工序。
13.如权利要求8所述的半导体装置的制造方法,其特征在于,包括将所述半导体晶片切断分离为多个半导体芯片的工序。
14.如权利要求8所述的半导体装置的制造方法,其特征在于,包括在所述第三配线上形成导电端子的工序。
15.如权利要求8所述的半导体装置的制造方法,其特征在于,包括在所述支撑体上形成使第二配线露出的开口部的工序后,在所述第二配线上形成镀层的工序。
16.如权利要求13所述的半导体装置的制造方法,其特征在于,包括在所述第二配线上介由所述开口部连接其它半导体装置的导电端子的工序。
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