CN100334562C - Correlation method for operating clock pulse of dynamically regulative microprocessor simulator - Google Patents

Correlation method for operating clock pulse of dynamically regulative microprocessor simulator Download PDF

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CN100334562C
CN100334562C CN 03147453 CN03147453A CN100334562C CN 100334562 C CN100334562 C CN 100334562C CN 03147453 CN03147453 CN 03147453 CN 03147453 A CN03147453 A CN 03147453A CN 100334562 C CN100334562 C CN 100334562C
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microprocessor
memory
buffer
control means
operation
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CN 03147453
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CN1567243A (en
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杜立群
郭弘政
陈炳盛
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联发科技股份有限公司
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Abstract

本发明提供一种用来动态调整一微处理器模拟装置(MicroprocessorEmulator)的操作时钟脉冲(Operating Clock)的方法。 The present invention provides a method for dynamically adjusting a microprocessor simulation apparatus (MicroprocessorEmulator) operation clock pulses (Operating Clock) of. 该微处理器模拟装置是电连于一微处理器系统(Microprocessor System),该微处理器系统包含一缓冲控制装置,该方法包含有(a)使用该微处理器模拟装置发送一存取地址(Access Address)至该缓冲控制装置;(b)在步骤(a)中,当该存取地址位于该缓冲控制装置中时,使用该缓冲控制装置输出该操作时钟脉冲至该微处理器模拟装置,以操作该微处理器模拟装置;以及(c)在步骤(a)中,当该存取地址不是位于该缓冲控制装置中时,使用该缓冲控制装置停止输出该操作时钟脉冲至该微处理器模拟装置,以暂停操作该微处理器模拟装置。 The microprocessor is electrically connected to the simulation apparatus is a microprocessor system (Microprocessor System), the microprocessor system comprises a buffering control device, the method comprising (a) transmitting an access address using the simulation device microprocessor (access address) to the buffer control means; (b) in step (a), when the access address control means located in the buffer, the buffer using the control means outputs the operation clock to the microprocessor simulation device to simulate operation of the microprocessor means; and (c) in step (a), when the access address is not in the buffer control device, using the buffer operation control means stops outputting the clock pulse to the microprocessor modeling means, to suspend operation of the microprocessor simulation device.

Description

动态调整微处理器模拟装置的操作时钟脉冲的相关方法 Dynamically adjusting operation of the simulation apparatus the microprocessor clock associated methods

技术领域 FIELD

本发明提供一种可动态调整一微处理器模拟装置(MicroprocessorEmulator)的操作时钟脉冲(Operating Clock)的方法,尤指一种将此微处理器模拟装置电连于一缓冲控制装置,以动态调整此微处理器模拟装置的操作时钟脉冲,用来模拟一微处理器存取至少一个存储器的方法。 The present invention provides a method of dynamically adjusting a microprocessor simulation apparatus (MicroprocessorEmulator) operation clock pulses (Operating Clock), and particularly to a microprocessor this simulation apparatus is electrically connected to a buffer control means to dynamically adjust the microprocessor operation clock pulses simulation apparatus, a simulation method for accessing at least one memory of the microprocessor.

背景技术 Background technique

随着数字时代的演进,为满足使用者的需求激增,数字数据的提取、传输、存储、运用、与显示的速度及正确性必须不断随之增强,而其中与信息系统的效能关系最剧烈的,即是处理器与相关存储器的存取运作。 With the evolution of the digital age, in order to meet the needs of users surge in digital data extraction, transmission, storage, use, and display of speed and accuracy must continue to increase as well, and the effectiveness of the relationship among the information systems of the most dramatic , that is, the access processor and associated memory operating. 在现有技术中,当一微处理器(Micro-processor)向一程序存储器要求提出数据(程序码)时,也就是微处理器要存取程序存储器时,必须发出对应于所需数据(程序码)的存取位置及其他控制信号,而程序存储器(如只读存储器ROM、快闪存储器Flash等等)必须在收到微处理器所发出的存取位置及相关控制信号后的一定时间内,让所需的程序码由微处理器读走。 In the prior art, when a microprocessor (Micro-processor) present data (program code) to a program memory requirements, i.e. when the microprocessor program memory to be accessed, must be issued corresponding to the desired data (program code) and the position of the other access control signal, and a program memory (e.g., read only memory ROM, flash memory, Flash, etc.) must be within a certain time after receipt of an access position and associated control signals issued by the microprocessor , so that the program code required to go read by the microprocessor. 请参阅图1,图1为现有一微处理器10存取一程序存储器12的架构示意图。 Please refer to FIG. 1, FIG. 1 a schematic architecture of the program memory 12 is a conventional microprocessor 10 access. 在图1中,微处理器10对程序存储器12发出一存取地址(Access Address)以及一控制信号,而程序存储器12在收到此存取地址及控制信号后,传回对应的一数字数据(程序码)至微处理器10。 In Figure 1, microprocessor 10 program 12 issues a memory access address (Access Address) and a control signal, and the program memory 12 upon receipt of this access address and control signals, return digital data corresponding to a (program code) to the microprocessor 10.

在评估一个存储器的效能时,最重要的便是其存取的时间与速度。 In assessing the effectiveness of a memory, the most important is its access time and speed. 从微处理器发布存取地址及相关指令,存储器取得存取地址数据,至存储器传回对应的数字数据给微处理器,最后到微处理器确实接收到所需的数字数据并完成数据分析为止,整个程序所花的时间可称为该存储器的完整的一读取周期,假设存储器的读取周期是60ns(毫微秒),这便意味着完成上述的程序所需的时间是60ns。 Release from the microprocessor and associated instruction access address, access address data acquisition memory, returned to the memory corresponding to the digital data to the microprocessor, the microprocessor does receive finally desired and complete the digital data until the data analysis , the entire process may be referred to the time it takes to complete a read cycle of the memory, assuming the memory read cycle is 60ns (nanoseconds), which would mean that the time required to complete the procedure is 60ns. 请继续参阅图1的现有实施例,若微处理器10与程序存储器12之间一个完整的读取动作包含有四个操作步骤:a.微处理器10发出存取地址、b.等待程序码由程序存储器12回传、c.程序码分析、d.由微处理器10发出新的存取地址,以现行一个具有时钟脉冲频率33MHz的8051系列的芯片(IC)为例,若设计四个时钟脉冲周期(30ns*4=120ns)为一个读取周期,即,程序存储器12必须在120ns的时间内完成一个完整的读取动作,包括上述a.至d.四个操作步骤,若程序存储器12无法在一个读取周期内完成上述所有步骤,则可能发生数据流失、阻塞、程序码无法正常执行等不良效应。 Please refer to the prior embodiment of Figure 1, if the microprocessor 10 and the program memory 12 between a full reading operation includes four steps:. A microprocessor 10 access address issued, b wait for the program. code from the program memory 12 return, c. analysis program codes, d. a new access address issued by the microprocessor 10 to a current clock frequency of 33MHz 8051 chip (IC) having an example, if the design four clock cycles (30ns * 4 = 120ns) of a read cycle, i.e., a program memory 12 must be completed within a 120ns time to complete the read operation, comprising a. above to d. four steps, when the program 12 can not complete all the steps in a memory read cycle, data loss may occur, blocking, the program code can not be executed like a normal adverse effects.

因此,程序存储器12的速度必须要达到一定要求,才能让微处理器10顺利存取并执行程序存储器12中的程序码。 Therefore, the speed of the program memory 12 must meet certain requirements in order to allow smooth access and microprocessor 10 executes the program code in the program memory 12. 如此一来,存取速度不快但可因此省却引脚数(Pin Count)的使用及占有较少系统资源的存储器,如串行式快闪存储器(Serial Flash)等,则在上述现有技术的架构下,无法应用于现今高速的微处理器系统中。 Thus, the access speed is not fast, but use may therefore save pin count (Pin Count) and occupies less memory of system resources, such as the serial flash memory (Serial Flash), etc., in the above-described prior art under architecture, it can not be applied to today's high-speed microprocessor-based systems. 再者,以一动态随机存取存储器(DRAM)而言,在多工的模式下在时序的控制上也必须要精准,才能确保存取时的数据的完整和正确性。 Further, in terms of a dynamic random access memory (DRAM), in multiplex mode on the control timing must be precise in order to ensure the integrity and accuracy of the data access time. 若能将这些成本低廉、架构简易的存储器与现今愈加高速的微处理器系统加以配合运用,对于系统资源的节省与产品的价格竞争力必有显著的提升。 If it could be these low-cost, simple architecture of today's increasingly high-speed memory and microprocessor systems with the use of them for the price competitiveness save system resources and products must be significantly improved.

事实上,微处理器系统的运作与模拟其实是同一回事,一个典型的模拟程序应该要能真实反映原本的系统设计,借由模拟找出实际操作时可能会遇到的问题并加以除错。 In fact, the operation of the microprocessor system simulation is actually the same thing, a typical simulation program should be able to truly reflect the original design of the system, by means of simulation to identify problems that may be encountered during actual operation and make debugging . 因此,在一个完整的微处理器系统的发展成型的过程中,一内嵌式处理器模拟器(In-Circuit Emulator)的加入是极为重要的一环。 Thus, during the development of a complete microprocessor system forming was added an embedded processor simulator (In-Circuit Emulator) is an extremely important part. 简单来说,内嵌式处理器模拟器ICE是一个用来模拟微处理器电路的硬件设备,外接于原有的微处理器系统,可作为一些未设置有除错线路的微处理器的扩充,以便让系统开发商或是程序设计师可以对微处理器系统的软/硬件做模拟除错的动作。 Briefly, the Embedded ICE emulator processor is a hardware device used to simulate the microprocessor circuit is, in the original external microprocessor system, the microprocessor can be expanded as a number of lines is not provided with debug in order to allow system developers or designers can do a simulation program of action for debugging microprocessor systems hardware / software. 请参阅图2,图2为现有技术利用一内嵌式处理器模拟器24模拟一微处理器系统20的示意图。 Please refer to FIG. 2, FIG. 2 a schematic view of a simulator 24 simulated embedded processor 20 is a microprocessor system utilizing the prior art. 图2中包含了芯片20(微处理器系统)、内嵌式处理器模拟器24、一程序存储器22、以及一外接式(External)时钟脉冲产生器26。 In FIG. 2 contains 20 (microprocessor system) chip, embedded processor simulator 24, a program memory 22, and an external (External) clock generator 26. 请回头对照图1,此时内嵌式处理器模拟器24即取代原本芯片20中微处理器的功能,模拟芯片20(其中包含有图1中的微处理器10)在实际操作时的情形。 Refer back to FIG. 1 controls, when the embedded processor 24 that is substituted emulator chip original function of the microprocessor 20, an analog chip 20 (which includes a microprocessor 10 in FIG. 1) in the case of actual operation . 在实际实施时,目前一般的内嵌式处理器模拟器24的引脚设计会与其要模拟的微处理器一样,方便把内嵌式处理器模拟器24直接插在原来的微处理器插槽上,再利用软件的配合以控制整个内嵌式处理器模拟器24的运作。 As in actual practice, the general design of the embedded processor simulator pin 24 will therewith be simulated microprocessor, embedded processor to facilitate the simulator 24 is directly inserted in the original microprocessor socket on the re-use with the software to control the operation of the entire embedded processor 24 of the simulator. 在本现有实施例中,内嵌式处理器模拟器24的操作时钟脉冲是由外接式时钟脉冲产生器26提供,与被测试的芯片(微处理器系统20)无关。 In the present conventional embodiment, embedded processor simulator operation clock 24 is generated by the external clock 26 provides a chip (microprocessor system 20) and is independent of the test. 程序存储器22提供内嵌式处理器模拟器24运作所需的指令(Instruction),内嵌式处理器模拟器24对被测的芯片提供存取地址以及相关的控制信号等,而被测试的芯片则依据存取地址以及相关控制信号,传回对应的数字数据至内嵌式处理器模拟器24。 The program memory 22 to provide the desired operation of the embedded processor 24 emulator instruction (Instruction), embedded processor chip under test simulator 24 provides access to address and associated control signals, a chip is tested based on the access address and associated control signals, return digital data corresponding to the embedded processor emulator 24. 借由上述概略的运作,即可例用内嵌式处理器模拟器24控制被测芯片的运作。 By means of the operation of the above schematic, the embodiment can be embedded with a processor simulator 24 controls the operation of the chip under test.

然而,无论是使用内嵌式处理器模拟器24,或者是通过现行的一些模拟软件,有时仍无法模拟出微处理器系统20真实的状态。 However, whether using the embedded processor simulator 24, or by some of the current simulation software, sometimes still can not simulate the real state of the microprocessor system 20. 例如在动态即时(Real-Time)反应的工作情形下,时钟脉冲的变动、中断(Interruption)、或暂停(Suspension)是时常可能发生的情况,而若要如上面所述,将成本低廉、架构简易的慢速存储器(例如串行式快闪存储器)与高速的微处理器系统20配合运用,时钟脉冲变动、中断或暂停运作等的程序更是需要纳入考虑。 For example, in the case of dynamic real-time work (Real-Time) reactions, changes in clock pulses, interrupt (Interruption), or suspend (Suspension) is a situation that may occur from time to time, but as to the above, the low cost, architecture easy slow memory (such as serial flash memory) and a high-speed microprocessor system 20 with the use of the clock pulse change, break or suspend the operation of such programs is the need to be taken into account. 现有技术的困窘之处在于,一般的(外接式)时钟脉冲产生器26很难模拟这些动态的运作情形,在无从模拟许多真实情况的处境下,更是遑论将慢速存储器与高速的微处理器系统20配合运用的可能性。 The embarrassment of the prior art is that, in general (external) clock generator 26 are difficult to simulate the operation of these dynamic situation, in no way to simulate the situation in many real situations, but not to mention the slow memory with high-speed micro- 20-processor system with the possibility of the use of.

发明内容 SUMMARY

因此本发明的主要目的在于提供一种动态调整一微处理器模拟装置的操作时钟脉冲的方法,用来模拟利用一缓冲控制装置使一微处理器存取至少一个存储器的运作情形,以解决上述问题。 The main object of the present invention is therefore to provide a method for dynamically adjusting operation of a microprocessor clock pulses simulation apparatus for simulating a buffer control device using a microprocessor to access the at least one operational situation of the memory, in order to solve the above problem.

在本发明所揭露的方法及架构中,我们在一微处理器系统中设置一缓冲控制装置,输出一操作时钟脉冲至微处理器,并由存储器中连续不间断的读取一定数量的数据(程序码)。 In the disclosed method and structure of the present invention, we provided a microprocessor system, a buffering control device, outputs a clock to operate the microprocessor, a data memory by a certain number of uninterrupted reading ( program code). 当微处理器需要数据时,检查缓冲控制装置中是否存有微处理器所需的程序码,若有,微处理器则直接从缓冲控制装置中存取,若没有,缓冲控制装置会将操作时钟脉冲掩盖(mark)掉,而微处理器会因为操作时钟脉冲的消失,而暂时停止运作,并保留其现有的状态。 When the microprocessor needs data, the control apparatus checks whether there buffer required microprocessor program code, if so, the microprocessor directly from the buffer access control means, if not, the buffer control means will operate clock hide (mark) away, and the microprocessor will disappear because the operating clock pulse, and suspend their operations and retain its existing state. 在程序存储器搜寻到并回传微处理器所需的程序码后,缓冲控制装置再恢复操作时钟脉冲的输出。 After the program memory and return to find the required microprocessor program code, the output buffer control means then resume operation clock pulses. 如此一来,即可达成动态控制操作时钟脉冲,以大幅降低程序存储器所须的存取速度。 Thus, to achieve dynamic operation clock control pulses, to substantially reduce the access speed required by the program memory.

在本发明中,我们还提出一种可动态调整一微处理器模拟装置的操作时钟脉冲的技术特征,其是利用将此微处理器模拟装置电连于一缓冲控制装置,而缓冲控制装置输出操作时钟脉冲至微处理器模拟装置,以操作此微处理器模拟装置。 In the present invention, we propose a technique to dynamically adjust the operating characteristics of a microprocessor clock simulation apparatus, which is the use of this simulation apparatus is electrically connected to the microprocessor a buffering control device, and the buffer output control means microprocessor operation clock pulses to the simulation device, the simulation device to operate the microprocessor. 如此一来,该缓冲控制装置可经由判断微处理器模拟装置所发送的存取地址是否位于缓冲控制装置中,来动态调整操作时钟脉冲,以模拟本发明利用缓冲控制装置使一微处理器存取一慢速的存储器的情形。 Thus, the buffer control means may be via a microprocessor simulation apparatus determines the access address transmitted is located in the buffer control means to dynamically adjust an operating clock pulses to simulate the present invention by the buffer memory control means so that a microprocessor take the case of a slow memory. 如此一来,即使在不同的跳跃状态(Jump Condition),或在可变动的操作时钟脉冲下,微处理器模拟装置都可正确地模拟出微处理器的效能。 Thus, even in different skip state (Jump Condition), or in an operating variable of the clock pulse, the microprocessor means can be simulated accurately simulate the performance of the microprocessor.

本发明的目的是提供一种利用一缓冲控制装置使一微处理器存取至少一个存储器的方法,该存储器存储有多笔数字数据,该方法包含有:(a)使用该缓冲控制装置输出一操作时钟脉冲至该微处理器,以操作该微处理器;(b)使用该缓冲控制装置读取存储于该存储器中的预定数目笔数字数据;(c)使用该微处理器由该缓冲控制装置中读取所需的至少一个数字数据;(d)在步骤(c)中,当该微处理器所需的该数字数据位于该缓冲控制装置中时,使用该微处理器读取位于该缓冲控制装置中的该数字数据,并继续使用该缓冲控制装置输出该操作时钟脉冲至该微处理器;(e)在步骤(c)中,当该微处理器所需的该数字数据不是位于该缓冲控制装置中时,使用该缓冲控制装置停止输出该操作时钟脉冲,以暂停该微处理器的操作;以及(f)在进行步骤(e)后,将该微处理器所需的该 Object of the present invention is to provide a method for using a buffer control means causes a microprocessor to access the at least one memory, the memory storing a plurality of digital data values, the method comprising: (a) using the buffer control means outputs a operation clock pulses to the microprocessor to operate the microprocessor; (b) using the buffer a predetermined number of digital data in the memory control means reads the stored; (c) the use of the buffer is controlled by microprocessor at least one digital data required reading means; (d) in step (c), when the digital data required by the microprocessor control means located in the buffer, the microprocessor reads located using buffer control means of the digital data, and continue to use the buffer control means outputs the operation clock to the microprocessor; (e) in step (c), when the digital data required by the microprocessor is not located when the buffer control device, using the buffer control means stops outputting the operation clock to suspend operation of the microprocessor; and (f) after performing step (E), the microprocessor required for the 字数据由该存储器传送至该缓冲控制装置以及该微处理器,并使用该缓冲控制装置恢复输出该操作时钟脉冲,以使该微处理器读取该数字数据。 Transmitted by the data word to the buffer memory control device and the microprocessor, using the buffer control means outputs the operation clock recovery, so that the microprocessor reads the digital data.

本发明的另一目的是提供一种用来动态调整一微处理器模拟装置的操作时钟脉冲的方法,该微处理器模拟装置是电连于一微处理器系统(Microprocessor System),该微处理器系统包含一缓冲控制装置,该方法包含有:(a)使用该微处理器模拟装置发送一存取地址至该缓冲控制装置;(b)在步骤(a)中,当该存取地址位于该缓冲控制装置中时,使用该缓冲控制装置输出该操作时钟脉冲至该微处理器模拟装置,以操作该微处理器模拟装置;以及(c)在步骤(a)中,当该存取地址不是位于该缓冲控制装置中时,使用该缓冲控制装置停止输出该操作时钟脉冲至该微处理器模拟装置,以暂停操作该微处理器模拟装置。 Another object of the present invention is to provide a method for dynamically adjusting operation of a microprocessor clock pulses simulation apparatus, the microprocessor is electrically connected to the simulation apparatus is a microprocessor system (Microprocessor System), the microprocessor a buffer system comprising a control device, the method comprising: (a) transmitting an access control address to the buffer means using the microprocessor simulation apparatus; (b) in step (a), when the access address is located when the buffer control device, using the buffer control means outputs the operation clock to the microprocessor simulation device, a microprocessor to operate the simulation device; and (c) in step (a), when the access address when the control device is not located in the buffer, the buffer using the control means stops outputting the clock pulse to the microprocessor operation simulation device, a microprocessor to halt operation of the simulation apparatus.

附图说明 BRIEF DESCRIPTION

图1为现有一微处理器存取一程序存储器的架构的示意图。 FIG 1 is a schematic diagram of the architecture of the program memory access is a conventional microprocessor.

图2为现有一内嵌式处理器模拟器模拟一微处理器系统的示意图。 2 is a diagram of a conventional microprocessor system in a simulated embedded processor simulator.

图3为本发明的一微处理器通过一缓冲控制装置存取一存储器的架构的示意图。 Figure 3 is a schematic diagram of a microprocessor control device of the invention accesses a memory through a buffer architecture.

图4为图3的一详细实施例的示意图。 4 is a schematic view of a detail of the embodiment of FIG.

图5为一屏蔽信号、一操作时钟脉冲、存取地址、及程序码的时序图。 FIG 5 is a masking signal, a clock operation, the access address, and a timing diagram of the program code.

图6为本发明一方法实施例的流程图。 6 a flowchart of a method embodiment of the present invention.

图7为本发明一微处理器模拟装置利用一缓冲控制装置模拟一微处理器系统的示意图。 Figure 7 a schematic diagram of a microprocessor system microprocessor analog simulation means using a buffer control means of the present invention.

图8为图7的一详细实施例的示意图。 FIG 8 is a schematic diagram of a detailed embodiment of FIG.

附图的符号说明10、30微处理器12、22、32、52(程序)存储器20、50微处理器系统 24内嵌式处理器模拟器26外接式时钟脉冲产生器38、59缓冲控制装置 53第二存储器54微处理器模拟装置具体实施方式请参阅图3,图3为本发明的一实施例的示意图。 DESCRIPTION OF THE DRAWINGS symbol microprocessor 10, 30, 12,22,32,52 (program) memory systems 20, 50, 24 embedded microprocessor emulator processor 26 external clock generator buffering control means 38,59 the second microprocessor 53 memory 54 analog device DETAILED DESCRIPTION Referring to FIG. 3, FIG. 3 of the present invention, a schematic of an embodiment. 图3的架构包含:一缓冲控制装置38、一微处理器(Micro-processor)30,一存储器32,存储器32中存储有多笔数字数据。 The architecture of FIG. 3 comprises: a buffer controller 38, a microprocessor (Micro-processor) 30, a memory 32, the memory 32 stores a plurality of digital data values. 与图1现有实施例对照可知,本发明的基本架构仍是利用微处理器30存取存储器32,但在存取的过程中,由于本发明的存储器32是期以一慢速存储器(例如串行式快闪存储器)完成,而在微处理器30仍为高速运作的情形下,为避免数据在传输时逸失或阻塞,我们在本实施例中让微处理器30通过缓冲控制装置38来间接存取存储器32,并配合上本发明所揭露的方法技术特征,以确保微处理器30正确无误地存取较慢速的存储器32。 1 and the conventional embodiment of FIG control understood, the basic architecture of the present invention is the use of a microprocessor 30 still access memory 32, but in the process of access, since the memory 32 of the present invention in a slow memory (e.g. serial flash memory) is completed, the microprocessor 30 remains in the case of high-speed operation, in order to avoid data escaping transmission or blocked, in the present embodiment, we allow the microprocessor 30 through the buffer 38 to the control means indirect access memory 32, and with the methods disclosed in the technical features of the present invention, the microprocessor 30 to ensure the correct access to the slower memory 32.

在本实施例中,微处理器30不直接由存储器32索取所需的数字数据,而是预先由缓冲控制装置38连续读取位于存储器32中多笔数字数据,将此多笔数字数据存放入缓冲控制装置38中,当微处理器30需要数字数据时,发送一要求消息至缓冲控制装置38,直接从缓冲控制装置38中存取。 In the present embodiment, the microprocessor 30 is not required to be obtained directly from the digital data memory 32, but the control means 38 in advance by the buffer 32 reads in the continuous multi-digital data located in a memory, this digital data is stored into the multiple buffer control means 38, the microprocessor 30 when the digital data is needed, sending a message to the required buffering control device 38, from the buffer control unit 38 directly accessed. 由于本实施例中,缓冲控制装置38与微处理器30之间所具有的数据存取速率大于存储器32与缓冲控制装置38之间的数据存取速率,因此,只要缓冲控制装置38的存取速度能符合微处理器30对数据存取速度的要求,存储器32则可以用较慢速的存储器32完成。 Since the present embodiment, the buffering control device 38 and between the microprocessor 30 has access to data greater than the data rate between the access rate of the buffer memory 32. The control device 38, therefore, the access control device 38 as long as the buffer speed can meet the access speed of the data to claim 30 of a microprocessor, memory 32 may be 32 accomplished by the slower memory. 以承袭前述8051系列的微处理器30为例,若其读取周期设计为四个时钟脉冲周期(120ns=30ns*4),也即微处理器30以四个时钟脉冲周期完成一个完整的读取动作,若完整的读取动作仍包含四个操作步骤,其中一个步骤为存储器32的存取,其余三个步骤是关于数字数据的处理(如程序码分析等),也就是说,其中一个时钟脉冲为相关于存取存储器32的操作,另外三个时钟脉冲用来处理数字数据。 In inherited the 8051 series microprocessor 30 as an example, the read cycle if it is designed to four clock cycles (120ns = 30ns * 4), i.e., the microprocessor 30 to four clock cycles to complete a full read take action, if the reading operation is still full operation includes four steps, a step wherein access memory 32, the remaining three steps of the processing on the digital data (e.g. program code analysis, etc.), that is to say, where a clock pulse 32 associated with the memory access operation, the other three clock pulses for processing digital data. 所以在一个读取周期内,当微处理器30在处理所接收到的数字数据时,存储器32其实会有部分时间空置。 Therefore, in one read cycle, when the microprocessor 30 in processing the received digital data, the memory 32 is actually part of the time there will be empty. 因此,借由缓冲控制装置38的设置与运作,可使用存取速度为原来的四分之一的存储器32来存放数字数据。 Thus, the buffer provided by means of the operation of the control device 38, using a quarter of the original access speed memory 32 to store digital data. 若存储器32的存取速度大于原来的四分之一,甚至可以缓慢地填满缓冲控制装置38,而无需担心数据壅塞的情况。 If the memory access speed is greater than a quarter of the original 32, and even slowly filling the buffer control unit 38, without worrying about data congestion situation. 因此,本发明加入缓冲控制装置38的技术特征,可使所需要的存储器32的存取速度大幅下降。 Thus, the technical features of the apparatus 38 of the present invention was added buffer control, can require a substantial decline in memory access speed of 32.

请继续参阅图3,缓冲控制装置38输出一操作时钟脉冲(OperatingClock)至微处理器30,以控制微处理器30的运作,即,当操作时钟脉冲停止时,微处理器30的运作也会随之暂停。 Please refer to FIG. 3, a buffer control means 38 outputs the operation clock (OperatingClock) to microprocessor 30 to control the operation of the microprocessor 30, i.e., when the operating clock is stopped, the operation of the microprocessor 30 will subsequently suspended. 在实际运作时,由于微处理器30的程序中常有跳跃(jump)的动作,造成缓冲控制装置38中不一定存有所需的数字数据,此时就需要利用缓冲控制装置38动态调整此操作时钟脉冲,以动态控制微处理器30的运作。 In actual operation, since the program of the microprocessor 30 often jump (Jump) operation, the control unit 38 causes the buffer there is not necessarily required for the digital data, it is necessary at this time by the buffer control means to dynamically adjust the operation 38 clock, to dynamically control the operation of the microprocessor 30. 请参阅图4,图4为图3的一详细实施例的示意图。 Please refer to FIG. 4, FIG. 4 is a schematic view of a detail of the embodiment of FIG. 对应于图3实施例,本实施例中的存储器32是一慢速的程序存储器32,而存储于该存储器32中的多笔数字数据为多笔程序码(Programming Code)。 3 corresponds to FIG embodiment, the memory in the embodiment of the present embodiment 32 is a slow program memory 32, and multiple digital data stored in the memory 32 as a multi-pen program code (Programming Code). 缓冲控制装置38为一先进先出式(FIFO)存储架构,而缓冲控制装置38是在一起始地址(Starting Address)处,由存储器32中连续不间断地读取预定数目笔程序码。 Buffer control means 38 is a FIFO memory architecture of Formula (the FIFO), the control device 38 and the buffer start address is together (Starting Address), the predetermined number of uninterrupted reading the program code from the pen memory 32. 当微处理器30需要程序码而直接从缓冲控制装置38中存取时,微处理器30会先发送对应于该程序码的一存取地址至缓冲控制装置38,以使缓冲控制装置38判断微处理器30所送出的存取地址是否位于其中。 When the microprocessor 30 and the program code required to access the device 38 directly from the buffer control, the microprocessor 30 will first send an access address corresponding to the program code to the buffer control means 38 to the buffer control means 38 determines the microprocessor 30 sends the access address is located. 若缓冲控制装置38已存有微处理器30要求的程序码,则微处理器30直接由缓冲控制装置38发送该所需的程序码;若缓冲控制装置38中没有微处理器30要求的程序码(如微处理器30正执行含有跳跃状态(Jump Condition)的运作),则缓冲控制装置38会停止输出操作时钟脉冲,同时微处理器30会因为操作时钟脉冲的消失,而暂时停止运作并保留现有状态。 When the buffering control device 38 requires the microprocessor 30 has been stored program code, program code, the microprocessor 30 by the buffer control unit 38 directly transmits the required; if the buffering control device 38 is not required microprocessor program 30 code (e.g., microprocessor 30 is executing the operating state including the jump (jump Condition)), the buffering control device 38 stops the output operation of the clock pulse, while the microprocessor 30 will disappear since the operation clock pulse, the operation is temporarily stopped and preserve the existing state. 在同一时刻,微处理器30将对应程序码的存取地址传送到程序存储器32,在程序存储器32接收到存取地址后,会搜寻并回传搜寻到的程序码,将该程序码填入缓冲控制装置38并传给微处理器30,此时缓冲控制装置38再将微处理器30的操作时钟脉冲释放,让微处理器30读取程序码。 At the same time, the microprocessor 30 to access the address corresponding to the program code is transferred to the program memory 32, a program memory 32 after receiving the access address, and the search will return to search for the program code, the program code is filled buffer control means 38 and transmitted to the microprocessor 30, this time buffering control device 38 then releases the microprocessor operation clock pulses is 30, so that the microprocessor 30 reads the program codes. 借由本实施例中的架构及方法,微处理器30可在与慢速的程序存储器32配合运用时,执行含有跳跃状态的程序,再者,经由此可动态控制的操作时钟脉冲,程序存储器32甚至可以使用速度更慢的传统存储器32完成,如串行式存储器(Serial Memory)。 By structure and by the method in the embodiment, when the microprocessor 30 may be with the use of slow program memory 32 containing program execution jumps state, furthermore, by operation of clock pulses whereby dynamic control of the program memory 32 even slower using conventional memory 32 is completed, such as a serial memory (serial memory).

在本发明的技术特征中,让缓冲控制装置38停止输出操作时钟脉冲的方法是采用将操作时钟脉冲掩盖(Mark)的方式,并在缓冲控制装置38中设置一屏蔽信号来达成。 In the technical features of the present invention, so that the buffer control means 38 stops the output operation of the clock pulse method is to use a clock masking operation mode (Mark), and the buffer control means 38 is provided to achieve a mask signal. 请参阅图5,图5为屏蔽信号、并同图4中的操作时钟脉冲、存取地址、及程序码的时序图。 Refer to FIG. 5, FIG. 5 is a mask signal, and the same operation clock pulses in FIG. 4, the access address, and a timing diagram of the program code. 请见图5,当微处理器30所需的存取地址A2(对应于程序码C2)不位于缓冲控制装置38中时,将屏蔽信号提升至一预设的电位,以掩盖掉此操作时钟脉冲,此时微处理器30保留其现有状态(存取地址A2)。 See Figure 5, when the microprocessor 30 to access the desired address A2 (corresponding to the program code C2) is not located in the buffer control means 38, the mask signal raised to a predetermined potential, to mask out this operation clock pulse, then the microprocessor 30 remains in its current state (access address A2). 当微处理器30所需的程序码C2由程序存储器32回传至缓冲控制装置38及微处理器30时,屏蔽信号会回复至一原先预设的电位,以恢复操作时钟脉冲的输出,使微处理器30继续运作。 When the microprocessor 30 program code C2 required by the program memory 32 back to the buffering control device 38 and a microprocessor 30, a mask signal will be recovered to the original predetermined potential, to the output of the clock pulse recovery operation, so that The microprocessor 30 continues to operate. 由前述可知,屏蔽信号的电位跃起前代表了微处理器30所需的存取地址(与对应的程序码)并未位于缓冲控制装置38中,而屏蔽信号的电位落下后的时点,则代表了微处理器30所需的存取地址(与对应的程序码)已在程序存储器32中找到并回传的时刻。 From the foregoing, the potential before the mask signal leaps represents the required access address 30 (corresponding to the program code) is not located in the buffer the microprocessor control unit 38, and the shielding potential of the signal point after the fall, 30 represents the required access address (program code corresponding to) the microprocessor found in the program memory 32 and the time of return. 因此,再次强调,借由本发明“缓冲控制装置38合并动态调整操作时钟脉冲的方法”的技术特征,可以顺利的存取较慢速的程序存储器32,例如串行式快闪存储器,而对于频宽并不保证随时足够的动态随机存取存储器(DRAM)或只读存储器(ROM),也可以用同样的机制加以存取,确保微处理器30所得到的数据的正确性。 Thus, once again emphasized that the technical features of the present invention by means of a "buffer control means dynamically adjusting operation of the clock pulse 38 merge" can successfully access the slower the program memory 32, for example, serial flash memory, and for frequency does not always guarantee a sufficiently wide dynamic random access memory (DRAM) or read only memory (ROM), it may also be accessed with the same mechanisms to ensure the correctness of the resulting data to the microprocessor 30.

综上所述,本发明利用一缓冲控制装置,动态调整一微处理器的操作时钟脉冲,以使微处理器存取一存储器的方法可参阅图6,图6为本发明一方法实施例的流程图,包含有下列步骤:步骤100:开始;步骤102:使用缓冲控制装置输出操作时钟脉冲至微处理器,以控制微处理器的操作;步骤104:使用缓冲控制装置读取存储于存储器中的预定数目笔数字数据,在图5实施例中,缓冲控制装置会在一起始地址处,由存储器中连续读取该预定数目笔程序码数据;步骤106:使用微处理器由缓冲控制装置中读取所需的至少一个数字数据,并由缓冲控制装置判断微处理器所需的数字数据(对应的存取地址)是否位于缓冲控制装置中,若是,则进行至步骤112;若微处理器正执行含有跳跃状态(Jump Condition)的运作,使得缓冲控制装置中没有微处理器所需的数字数据(对应的存取 In summary, the present invention uses a buffer control means to dynamically adjust the operating clock of a microprocessor, the microprocessor so that the method of accessing a memory can be found in FIG. 6, FIG. 6 of the present invention, a method of an embodiment flowchart includes the following steps: step 100: start; step 102: using a buffer control means outputs the operation clock to the microprocessor to control the operation of the microprocessor; step 104: using a buffer control means for reading stored in memory apparatus using a microprocessor controlled by the buffer: step 106; a predetermined number of digital data, in the FIG. 5 embodiment, the buffer address control means will start with, the program reads the predetermined number of strokes from the code data memory successively embodiment reading at least one digital data required by the buffer control means determines a desired digital data, a microprocessor (corresponding to the access address) is located in the buffering control device, and if yes, proceeds to step 112; if the microprocessor operation is being executed state including the jump (jump Condition) such that the buffer control means is not required for the microprocessor digital data (corresponding to the access 地址),则进行步骤108。 Address), step 108 is performed.

步骤108:使用缓冲控制装置停止输出操作时钟脉冲,以暂停该处理器的操作(将一屏蔽信号提升至一预设的高电位)并保留现有状态。 Step 108: using a buffer control means stops the output operation of the clock pulses to suspend operation of the processor (lifting a mask signal to a predetermined high voltage) and to retain the existing state. 同时,微处理器将对应于所需的数字数据的相关消息(对应程序码数据的存取地址)传送到存储器;步骤110:在存储器接收到数字数据的相关消息(对应程序码数据的存取地址)后,会搜寻并回传搜寻到的数字数据(程序码)。 Meanwhile, the microprocessor corresponding to the desired digital data related message (program code corresponding to the access address data) to the memory; Step 110: after receiving the digital data in the memory related messages (program code corresponding to the access data address), the search will search for and return to digital data (program code). 将该数字数据(程序码)填入缓冲控制装置及微处理器,此时缓冲控制装置再将微处理器的操作时钟脉冲释放(将屏蔽信号回复至原先预设的低电位),让微处理器继续运作;步骤112:继续进行正常的数据读取,也就是使用微处理器继续由缓冲控制装置中读取所需的数字数据(程序码),并递回至步骤106作其余每笔数据的判断。 The digital data (program codes) filled in the buffer control means and a microprocessor, controls the operation of the clock at this time the buffer and then release means of the microprocessor (the mask signal is returned to the original preset low potential), so that the microprocessor operation continues; step 112: proceed with normal data read, the microprocessor proceeds apparatus used is required to read in a digital data (program code) controlled by the buffer, and handed back to step 106 for the remainder of each data judgment.

接下来,我们必须考虑的是,在本发明上述所揭露的方法及架构下,如何完成包含本发明技术特征的微处理器的模拟运作。 Next, we must consider that, in the present invention, the above-described method and architecture disclosed, how to complete the simulation operating features of the invention comprising a microprocessor. 由于微处理器的运作与模拟是一体的两面,在微处理器系统发展成型的阶段,如何利用外加的一微处理器模拟装置真实模拟出原本的系统设计在实际操作时可能会遇到的问题,也包含于本发明主要的技术特征。 Since the operation and simulation is one of the sides of the microprocessor, the microprocessor system forming stage of development, how to use a microprocessor simulator to simulate the real plus of the original system design problems may be encountered in actual operation also included in the main technical features of the present invention. 请回头参照图2,现有实施例及图3、图4的本发明实施例,本发明的架构为了能存取慢速的程序存储器,在微处理器30及程序存储器32之间额外设置一缓冲控制装置38,且利用此缓冲控制装置38输出的操作时钟脉冲动态控制微处理器30,当缓冲控制装置38内没有微处理器30所需要的程序码数据时,将微处理器30暂停,并等待程序存储器32提供所需的程序码数据。 Please Referring back to FIG. 2, FIG. 3 and the conventional embodiment, the present invention is the embodiment of FIG. 4, the architecture of the present invention in order to slow memory access procedure, the microprocessor 30 and the program memory 32 is additionally provided between a buffer control means 38, and use this clock buffer 38 outputs the operation control means dynamically control microprocessor 30, when the buffer control means is not required to program code data 38 of the microprocessor 30, the microprocessor 30 will be suspended, and waiting for the program memory 32 to provide data required for the program code. 如此一来,由于微处理器30所接收的操作时钟脉冲是(动态的)时有时无,如图2现有技术中的微处理器20模拟装置无法模拟出这种动态情形,也无法模拟出本发明中缓冲控制装置38(以一先进先出式存储架构FIFO完成)配合一慢速存储器32(如一串行式快闪存储器)运作时的情况。 Thus, since the operation clock pulses received by the microprocessor 30 is sometimes no (dynamic), the prior art 2 as shown by the microprocessor 20 simulation apparatus can not simulate this dynamic situation, can not simulate the buffer control means of the present invention, 38 (a FIFO type memory architectures to completion FIFO) when the fit (such as a serial type flash memory) 32 a slow operating memory.

请参阅图7,图7为本发明另一实施例的示意图。 Please refer to FIG. 7, FIG. 7 is a schematic of another embodiment of the present invention. 图7中包含了一缓冲控制装置58以及一微处理器模拟装置54,缓冲控制装置58是设置在一微处理器系统50中,而缓冲控制装置58与微处理器模拟装置54相互电连。 FIG 7 includes a buffering control device 58 and a microprocessor simulation means 54, buffer control means 58 is provided in a microprocessor system 50, and the buffer 54 are electrically connected to the microprocessor means 58 controlling the simulation device. 实际上,若与本发明前述图3及图4实施例相对照,微处理器模拟装置54即对应于图3、图4中的微处理器30,具备相近的功能。 Indeed, if the previous embodiment in contrast embodiment of the present invention, FIG. 3 and FIG. 4, i.e., the microprocessor simulation apparatus 54 corresponding to Figure 3, the microprocessor 30 in FIG. 4, have a similar function. 为使微处理器模拟装置54能模拟测试出具有本发明技术特征的微处理器系统50,缓冲控制装置58是提供一操作时钟脉冲至该微处理器模拟装置54,以控制该微处理器模拟装置54的运作。 Simulation means for the microprocessor 54 can simulate a microprocessor system having features of the invention a test 50, the buffer control means 58 to provide a clock to the microprocessor operation simulation device 54, a microprocessor for controlling the analog the operating device 54. 无论在缓冲控制装置58中是否原先即存储有一定数量的地址(Address)数据,在执行模拟的运作时,微处理器模拟装置54会发送一存取地址至此缓冲控制装置58,若此存取地址位于缓冲控制装置58中时,缓冲控制装置58会继续输出操作时钟脉冲至微处理器模拟装置54,以维持微处理器模拟装置54的运作,而当此存取地址并非位于缓冲控制装置58中时,缓冲控制装置58就会停止输出操作时钟脉冲至微处理器模拟装置54,以暂停操作微处理器模拟装置54。 No matter whether the buffer control that is previously stored a certain number of address (Address) data unit 58, when performing the simulation operation, simulation apparatus the microprocessor 54 sends an access point address buffer control means 58, if this access when the address is in the buffer control means 58, the buffer control unit 58 continues to output the operating clock to the microprocessor simulation apparatus 54 to maintain the operation of the simulation apparatus 54 of the microprocessor, and when the buffer control means accessing this address is not at 58 when the buffer control means 58 stops the output operation of the analog clock to the microprocessor 54 to suspend operation of the microprocessor 54 simulation apparatus. 如此一来,利用缓冲控制装置58提供可动态调整的操作时钟脉冲给微处理器模拟装置54,即可动态控制微处理器模拟装置54的运作,正确模拟出具有本发明技术特征的微处理器系统50。 Thus, by the buffer control means 58 provides the operating clock to the microprocessor can dynamically adjust the simulation apparatus 54, to control the operation of dynamic simulation device 54 of the microprocessor, the microprocessor having correctly simulate the technical features of the present invention system 50.

在模拟的过程中,可将本实施例设计为当缓冲控制装置58停止输出操作时钟脉冲以暂停微处理器模拟装置54之后,经过一预定数目的操作时钟脉冲周期后,缓冲控制装置58就会自动恢复输出操作时钟脉冲至微处理器模拟装置54,恢复微处理器模拟装置54的操作。 In the simulation process, the present embodiment can be designed as the embodiment when the buffering control device 58 stops the output operation of the microprocessor clock to pause simulation apparatus 54, after a predetermined number of clock cycles of operation, buffer control means 58 will auto-recovery operation of the output clock pulses to a microprocessor simulation apparatus 54, the recovery operation of the microprocessor 54 of the simulation device. 此时,由于是纯粹模拟测试的过程,缓冲控制装置58是否连接有一存储器并不重要,倘若缓冲控制装置58电连至一存储有多笔数字数据的慢速存储器,则其架构就几乎等同于本发明图3及图4的实施例。 At this time, since the process is a pure simulation tests, buffer control means 58 is connected with a memory is not important, if the buffer control device 58 connected electrically to a slow memory storing a plurality of digital data, which is almost equivalent to the schema embodiment of the invention FIG 3 and 4. 请参阅图8,图8为图7的一详细实施例的示意图。 Refer to FIG. 8, FIG. 8 a schematic view of a detail of the embodiment of FIG. 7. 缓冲控制装置58是一先进先出式存储架构,并电连至一较慢速的存储器52,此存储器52可为一串行式快闪存储器、一动态随机存取存储器52、或者一只读存储器52等等,而微处理器模拟装置54是一内嵌式处理器模拟器24(In-Circuit Emulator)。 Buffer control means 58 is a FIFO type memory architecture, and is electrically connected to a slower speed memory 52, the memory 52 may be a serial flash memory, a dynamic random access memory 52, a read-only or etc. the memory 52, the microprocessor means 54 is a simulated embedded processor simulator 24 (In-Circuit emulator). 缓冲控制装置58会由一起始地址处,从存储器52中连续读取预定数目笔数字数据及其对应的存取地址,预先存于缓冲控制装置58中,当微处理器模拟装置54所传送的该存取地址位于缓冲控制装置58中时,即使用该缓冲控制装置58传送对应于此存取地址的数字数据至微处理器模拟装置54,若该存取地址并非位于缓冲控制装置58中时(可模拟微处理器30执行含有跳跃状态(Jump Condition)的运作状况),存储器52会搜寻并回传对应于该存取地址的数字数据至缓冲控制装置58,缓冲控制装置58再传送搜寻到的数字数据至微处理器模拟装置54,同时恢复输出操作时钟脉冲。 Buffer control means 58 will be initiated by a start address, read from the memory 52 a predetermined number of successive digital data and corresponding access address, previously stored in the buffering control device 58, when the simulation apparatus 54 is transmitted microprocessor when the address is in the access control device 58 in the buffer, i.e. using the buffer control means 58 transmits the access address corresponding to this digital data to a microprocessor simulation apparatus 54, if the access address is not located in the buffering control device 58 (to simulate the operating conditions the microprocessor 30 executes a skip state comprising (jump condition)), the memory 52 will search for and return the access address corresponding to the digital data to the buffer control means 58, the re-transmission buffer control unit 58 to search digital data to the simulation apparatus the microprocessor 54, while the recovery operation of the output clock pulses. 当然,若微处理器模拟装置54也电连于存储器52,存储器52在搜寻到对应于此存取地址的数字数据后,可直接回传数字数据至微处理器模拟装置54,而无需通过缓冲控制装置58。 Of course, if the microprocessor simulation apparatus 54 is also electrically connected to the memory 52, the memory 52 after searching the digital data corresponding to the address of this access, the digital data can be transmitted directly back to the simulation apparatus the microprocessor 54 without passing through the buffer The control device 58.

请注意,在本实施例中,缓冲控制装置58仍可采用将操作时钟脉冲掩盖(Mark)的方式以停止输出操作时钟脉冲,此时,在缓冲控制装置58中必须设置一屏蔽信号来达成。 Note that in the present embodiment, the buffer control means 58 by way of the operation can still be masked clock (Mark) to stop the output operation of the clock pulse, this time must be set in a mask signal buffer control means 58 to achieve. 如同图4及图5中所描述的技术特征,当微处理器模拟装置54所需的存取地址不位于缓冲控制装置58中时,缓冲控制装置58内部会将屏蔽信号提升至一预定的电位,以掩盖掉操作时钟脉冲。 And technical characteristics as described in FIG. 5 to FIG. 4, when the microprocessor 54 to access the desired address is not located in the buffer simulator control means 58, 58 will be internal mask signal buffer control means to a predetermined potential upgrade to mask off the clock operation. 当经过预定数目的时钟脉冲周期后,或者数字数据开始由存储器52回传至缓冲控制装置58及微处理器模拟装置54后,屏蔽信号才会回复至一原先预设的(低)电位,以恢复操作时钟脉冲的输出,使微处理器模拟装置54继续运作。 When after a predetermined number of clock cycles, or digital data transmitted from the start means 52 back to the memory buffer 58 and the microprocessor 54 controls the simulation apparatus, a mask signal will return to the original predetermined (low) potential to the output clock pulse recovery operation, causing the microprocessor 54 to continue operation of the simulation device.

此外,在本发明的实施例中,缓冲控制装置58与微处理器模拟装置54之间所具有的数据存取速率仍大于存储器52与缓冲控制装置58之间的数据存取速率,用来模拟在慢速的存储器52设置下,高速的微处理器30与缓冲控制装置58的配合运用。 Further, in the embodiment of the present invention, the buffer control means between the microprocessor 58 and the simulation device 54 having a data access rate of the buffer memory 52 is still greater than the data rate between the access control device 58 to simulate the memory 52 is provided at a slow, high-speed microprocessor 30 and buffer control means 58 with the use of. 请继续参阅图8,微处理器模拟装置54电连至另一第二存储器53,其是一程序存储器,可使用一静态随机存取存储器(static random access memory,SRAM)或是ROM完成,在第二存储器53中存储有微处理器模拟装置54运作所需的多个指令。 Please refer to FIG. 8, a microprocessor, an analog device 54 is electrically connected to the other second memory 53, which is a program memory, may use a static random access memory (static random access memory, SRAM) or ROM is complete, the second memory 53 stores a plurality of instructions of a microprocessor simulation apparatus 54 required for operation. 当缓冲控制装置58输出操作时钟脉冲至微处理器模拟装置54时,此第二存储器53会传送相关的指令至微处理器模拟装置54,而当缓冲控制装置58暂停输出操作时钟脉冲至该微处理器模拟装置54时,由于此时微处理器模拟装置54停止运作,无法接收由第二存储器53传送来的任何指令。 When the simulation device 54 to the microprocessor, the second memory 53 sends instructions related to the simulation apparatus the microprocessor 54, the buffer 58 outputs the operation control means and when the clock pulse means 58 to suspend operation of the output buffer control clock pulses to the micro- processor simulation apparatus 54, since then the microprocessor 54 stops the operation of the simulation device, can not be received by the second memory 53 of any transfer instruction. 上述的程序及方法即非常近似于前述本发明图4的实施例。 I.e., the above-described procedures and methods very similar to the embodiment of the present invention in FIG. 4. 此外,该缓冲控制装置58所提供的操作时钟脉冲的频率是可视实际情况调整变动的,或者利用电连至一外接式时钟脉冲产生器56加以调整。 In addition, the frequency of operation of the buffer clock pulses supplied from the control means 58 is adjusted to actual situation changes, or using an adjusted electrically connected to the external clock pulse generator 56. 综合以上所述可知,具有本发明技术特征的微处理器模拟装置54可以正确模拟出,具有本发明技术特征的微处理器系统50在应用慢速存储器52并在不同的跳跃状态(Jump Condition)下,动态调整的操作时钟脉冲对微处理器系统50效能的影响。 Based on the above the known, microprocessor simulation device 54 having features of the invention may be correctly simulated, having features of the invention a microprocessor system 50 and memory 52 apply slow different skip state (Jump Condition) in under the influence of dynamic adjustment of the operation clock of the microprocessor system 50 performance.

在本发明中,我们首先提出一种新型的方法即架构,利用设置一缓冲控制装置在一微处理器与一存储器之间,依据检查在缓冲控制装置中是否存有微处理器所需的数据,输出一可动态调整的操作时钟脉冲至微处理器以控制该微处理器的存取运作,使得此较高速的微处理器30能与具有较低存取速度的存储器(如一串行式快闪存储器(Serial Flash))配合运用,节省引脚的使用、节省系统数据、并提升相关产品的价格竞争力。 In the present invention, we first propose a novel method i.e. architecture, using a buffer control means is provided between a microprocessor and a memory, according to the control apparatus checks whether the buffer contains data required for the microprocessor , a dynamically adjustable output operation clock pulses to the microprocessor to control the access operation of the microprocessor, such that this higher speed microprocessors and memory 30 can have a lower access speed (such as a fast serial type Flash memory (Serial Flash)) with the use of savings pins, saving system data, and improve the price competitiveness of related products. 同时,我们另提出了包含有此缓冲控制装置以动态调整一微处理器模拟装置的操作时钟脉冲的方法,以准确模拟出本发明中当微处理器、缓冲控制装置、与慢速存储器共同运作时的各种情况。 At the same time, we have made further comprising buffer control means for this to dynamically adjust a method of operating a microprocessor simulation device clock pulses to accurately simulate the present invention when the microprocessor, the buffer control means, co-operating with slow memory various situations when.

以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,皆应属本发明专利的涵盖范围。 The above are only preferred embodiments of the present invention, all modifications and alterations made under this invention as claimed in claim, also belong to the scope of the present invention patent.

Claims (20)

1.一种利用一缓冲控制装置使一微处理器存取至少一个存储器的方法,该存储器存储有多笔数字数据,该方法包含有:(a)使用该缓冲控制装置输出一操作时钟脉冲至该微处理器,以控制该微处理器的操作;(b)使用该缓冲控制装置读取存储于该存储器中的预定数目笔数字数据;(c)使用该微处理器由该缓冲控制装置中读取所需的至少一个数字数据;(d)在步骤(c)中,当该微处理器所需的该数字数据位于该缓冲控制装置中时,使用该微处理器读取位于该缓冲控制装置中的该数字数据,并继续使用该缓冲控制装置输出该操作时钟脉冲至该微处理器;(e)在步骤(c)中,当该微处理器所需的该数字数据不是位于该缓冲控制装置中时,使用该缓冲控制装置停止输出该操作时钟脉冲,以暂停该微处理器的操作;以及(f)在进行步骤(e)后,将该微处理器所需的该数字数据由 A buffering control device using a microprocessor to make a method for accessing at least one memory, the memory storing a plurality of digital data values, the method comprising: (a) using the buffer control means outputs an operation clock to the microprocessor to control the operation of the microprocessor; (b) using the buffer a predetermined number of digital data in the memory control means reads the stored; (c) the use of the buffer is controlled by the microprocessor means reading at least one digital data required; (d) in step (c), when the digital data required by the microprocessor control means located in the buffer, the microprocessor reads located using the buffer control the digital data device, and continue to use the buffer control means outputs the operation clock to the microprocessor; (e) in step (c), when the digital data is not required by the microprocessor located in the buffer control means using the buffer operation control means stops outputting the clock to suspend operation of the microprocessor; and after (f) performing step (E), the digital data required by the microprocessor 存储器传送至该缓冲控制装置以及该微处理器,并使用该缓冲控制装置恢复输出该操作时钟脉冲,以使该微处理器读取该数字数据。 To the buffer memory transfer control device and the microprocessor, using the buffer control means outputs the operation clock recovery, so that the microprocessor reads the digital data.
2.如权利要求1所述的方法,其还包含有:(g)在步骤(b)中,使用该缓冲控制装置在该存储器的一起始地址处连续读取该预定数目笔数字数据;以及(h)在步骤(c)、(d)、及(e)中,使用该微处理器发送对应于该数字数据的一存取地址至该缓冲控制装置,以使该缓冲控制装置判断该微处理器所需的该数字数据是否位于该缓冲控制装置中。 2. The method according to claim 1, further comprising: (g) in step (b) using the buffer control means reads the predetermined number of successive digital data at a start address of the memory; and (h) in step (c), (d), and (e) using the microprocessor sends the digital data corresponding to an access address to the buffer control means, so that the buffer control means determines that the micro- whether or not the digital data required by the processor is located in the buffer control means.
3.如权利要求1所述的方法,其中该缓冲控制装置包含一屏蔽信号,该方法还包含有:(i)在步骤(e)中,当该微处理器所需的该数字数据不是位于该缓冲控制装置中时,将该屏蔽信号提升至一预设的电位,以停止该操作时钟脉冲的输出;以及(j)在步骤(f)中,当该微处理器所需的该数字数据由该存储器传送至该缓冲控制装置及该微处理器时,将该屏蔽信号回复至另一预设的电位,以恢复该操作时钟脉冲的输出。 3. The method according to claim 1, wherein the buffer control means comprises a masking signal, the method further comprising: (i) in step (e), when the digital data required by the microprocessor is not located when the buffer control apparatus, the mask signal is raised to a predetermined level, to stop the operation of the output clock pulses; and (j) in step (f), when the digital data required for the microprocessor when transmitted by the buffer memory to the control device and the microprocessor, the mask signal is returned to the another predetermined potential, the output of the operation to recover the clock pulses.
4.如权利要求1所述的方法,其中该存储器是一慢速的程序存储器,且存储于该存储器中的这些数字数据是多笔程序码。 4. The method according to claim 1, wherein the memory is a slow program memory, and the digital data stored in the memory of the program code is a multi-pen.
5.如权利要求4所述的方法,其中该存储器是一串行式快闪存储器、一动态随机存取存储器、或一只读存储器等。 5. The method according to claim 4, wherein the memory is a serial flash memory, a dynamic random access memory, a read only memory, or the like.
6.如权利要求4所述的方法,其中该缓冲控制装置与该微处理器之间具有一第一数据存取速率,该存储器与该缓冲控制装置之间具有一第二数据存取速率,其中该第一数据存取速率高于或等于该第二数据存取速率。 6. The method according to claim 4, wherein the buffer control means between the first microprocessor having a data access rate, the memory and the buffer having a second data rate between the access control device, wherein the first data access rate is higher than or equal to the second data access rate.
7.如权利要求4所述的方法,其中该缓冲控制装置是一先进先出式存储架构。 7. The method according to claim 4, wherein the buffer control means is a FIFO type memory architectures.
8.一种用来动态调整一微处理器模拟装置的一操作时钟脉冲的方法,该微处理器模拟装置是电连于一微处理器系统,该微处理器系统包含一缓冲控制装置,该方法包含有:(a)使用该微处理器模拟装置发送一存取地址至该缓冲控制装置;(b)在步骤(a)中,当该存取地址位于该缓冲控制装置中时,使用该缓冲控制装置输出该操作时钟脉冲至该微处理器模拟装置,以操作该微处理器模拟装置;以及(c)在步骤(a)中,当该存取地址不是位于该缓冲控制装置中时,使用该缓冲控制装置停止输出该操作时钟脉冲至该微处理器模拟装置,以暂停操作该微处理器模拟装置。 A method for dynamically adjusting a simulation apparatus of a microprocessor operation clock pulses, the microprocessor is electrically connected to the simulation apparatus is a microprocessor system, the microprocessor system comprises a buffering control device, which the method comprises: (a) transmitting an access control address to the buffer means using the microprocessor simulation apparatus; (b) in step (a), when the access address control means located in the buffer using the buffer control means outputs the operation clock to the microprocessor simulation device, a microprocessor to operate the simulation device; and (c) in step (a), when the access address is not in the buffer when the control device, using the buffer control means stops outputting the clock pulse to the microprocessor operation simulation device, a microprocessor to halt operation of the simulation apparatus.
9.如权利要求8所述的方法,其还包含有:(d)在进行步骤(c)后,在一预定数目的时钟脉冲周期后,使用该缓冲控制装置恢复输出该操作时钟脉冲至该微处理器模拟装置,以恢复该微处理器模拟装置的操作。 9. The method according to claim 8, further comprising: (d) after performing step (C), after a predetermined number of clock cycles, the buffer control means using the output of the restore operation to the clock simulation microprocessor means to resume operation of the microprocessor simulation device.
10.如权利要求9所述的方法,其中该缓冲控制装置包含一屏蔽信号,该方法还包含有:(e)在步骤(c)中,当该存取地址不是位于该缓冲控制装置中时,将该屏蔽信号提升至一预设的电位,以停止该操作时钟脉冲的输出;以及(f)在步骤(d)中,在该预定数目的时钟脉冲周期后,将该屏蔽信号回复至另一预设的电位,以恢复该操作时钟脉冲的输出。 10. The method according to claim 9, wherein the buffer control means comprises a masking signal, the method further comprising: (e) in step (c), when the access address is not in the buffer when the control means to enhance the mask signal to a predetermined level, to stop the operation of the output clock pulses; and (f) in step (d), after the predetermined number of clock cycles, the mask signal is returned to the other a predetermined potential, the output of the operation to recover the clock pulses.
11.如权利要求8所述的方法,其中该微处理器模拟装置是电连至一第一存储器,该方法还包含有:(h)当该缓冲控制装置输出该操作时钟脉冲至该微处理器模拟装置时,使用该第一存储器传送至少一个指令至该微处理器模拟装置;以及(i)当该缓冲控制装置暂停输出该操作时钟脉冲至该微处理器模拟装置时,该第一存储器不传送任一指令至该微处理器模拟装置。 (H) when the buffer control means outputs the operation clock to the microprocessor: 11. The method according to claim 8, wherein the analog means is a microprocessor electrically connected to a first memory, the method further comprises when the analog means, using the first memory transfer command to the microprocessor at least one simulator; and when (i) when the output buffer control means to suspend the operation of the analog clock to the microprocessor means, the first memory a command is not transmitted to the microprocessor to any analog means.
12.如权利要求11所述的方法,其中该第一存储器是一静态随机存取存储器或其他型式的存储器。 12. The method of claim 11, wherein the first memory is a static random access memory, or other types of memory.
13.如权利要求8所述的方法,其中该缓冲控制装置是电连至一第二存储器,该第二存储器存储有多笔数字数据,该方法还包含有:(j)使用该缓冲控制装置读取存储于该第二存储器中的预定数目笔数字数据;(k)在步骤(b)中,当该存取地址位于该缓冲控制装置中时,使用该缓冲控制装置传送对应于该存取地址的一数字数据至该微处理器模拟装置;以及(l)在进行步骤(c)后,将对应于该存取地址的该数字数据由该第二存储器传送至该缓冲控制装置以及该微处理器模拟装置,并使用该缓冲控制装置恢复输出该操作时钟脉冲。 13. The method according to claim 8, wherein the buffer control means is electrically connected to a second memory, the second memory storing a plurality of digital data values, the method further comprising: (j) using the buffer control means reading stored in the second memory the predetermined number of digital data; (K) in step (b), when the buffer address is the access control means, a means for transmitting the buffer corresponding to the access control a digital data to the microprocessor address simulation device; and the (l) performing step (c), the access address corresponding to the digital data transmitted from the second to the buffer memory and a micro control unit processor simulation device, using the buffer control means outputs the operation clock recovery.
14.如权利要求13所述的方法,其中在步骤(j)中,该缓冲控制装置是在一起始地址处,由该第二存储器中连续读取该预定数目笔数字数据。 14. The method according to claim 13, wherein in step (j), the buffer address control means is at the start together, reads the predetermined number of digital data from the second memory continuously.
15.如权利要求13所述的方法,其中该第二存储器是一慢速的程序存储器,且存储于该第二存储器中的这些数字数据是多笔程序码。 15. The method according to claim 13, wherein the second memory is a slow program memory, and the digital data stored in the second memory is a multi-pen program code.
16.如权利要求15所述的方法,其中该第二存储器是一串行式快闪存储器、一动态随机存取存储器、或一只读存储器等。 16. The method according to claim 15, wherein the second memory is a serial flash memory, a dynamic random access memory, a read only memory, or the like.
17.如权利要求15所述的方法,其中该缓冲控制装置与该微处理器模拟装置之间具有一第一数据存取速率,该第二存储器与该缓冲控制装置之间具有一第二数据存取速率,其中该第一数据存取速率高于或等于该第二数据存取速率。 17. The method of claim 15, wherein the buffer control means between said microprocessor means and having a first analog data access rate, the second memory having a second data control between the buffer means and access rate, wherein the first data access rate is higher than or equal to the second data access rate.
18.如权利要求8所述的方法,其中该操作时钟脉冲的频率是可利用一外接式时钟脉冲装置加以调整。 18. The method according to claim 8, wherein a frequency of the operation clock is a can be adjusted using the external clock device.
19.如权利要求8所述的方法,其中该缓冲控制装置是一先进先出式存储架构。 19. The method according to claim 8, wherein the buffer control means is a FIFO type memory architectures.
20.如权利要求8所述的方法,其中该微处理器模拟装置是一内嵌式处理器模拟器。 20. The method according to claim 8, wherein the analog means is a microprocessor embedded processor simulator.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN86106826A (en) * 1985-09-12 1987-06-10 菲利蒲光灯制造公司 Data processing apparatus
EP0287301B1 (en) * 1987-04-17 1995-02-01 Tandem Computers Incorporated Input/output system for multiprocessors

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN86106826A (en) * 1985-09-12 1987-06-10 菲利蒲光灯制造公司 Data processing apparatus
EP0287301B1 (en) * 1987-04-17 1995-02-01 Tandem Computers Incorporated Input/output system for multiprocessors

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