CH653505A5 - Telegraphic receiver for serial impulse telegrams. - Google Patents

Telegraphic receiver for serial impulse telegrams. Download PDF

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Publication number
CH653505A5
CH653505A5 CH305381A CH305381A CH653505A5 CH 653505 A5 CH653505 A5 CH 653505A5 CH 305381 A CH305381 A CH 305381A CH 305381 A CH305381 A CH 305381A CH 653505 A5 CH653505 A5 CH 653505A5
Authority
CH
Switzerland
Prior art keywords
telegram
signal
detection
circuit
memory
Prior art date
Application number
CH305381A
Other languages
German (de)
Inventor
Reto Klein
Original Assignee
Bbc Brown Boveri & Cie
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bbc Brown Boveri & Cie filed Critical Bbc Brown Boveri & Cie
Priority to CH305381A priority Critical patent/CH653505A5/en
Publication of CH653505A5 publication Critical patent/CH653505A5/en

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/06Dc level restoring means; Bias distortion correction decision circuits providing symbol by symbol detection
    • H04L25/068Dc level restoring means; Bias distortion correction decision circuits providing symbol by symbol detection by sampling faster than the nominal bit rate
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/20Repeater circuits; Relay circuits
    • H04L25/24Relay circuits using discharge tubes or semiconductor devices
    • H04L25/242Relay circuits using discharge tubes or semiconductor devices with retiming
    • H04L25/245Relay circuits using discharge tubes or semiconductor devices with retiming for start-stop signals

Description

The present invention relates to a telegraph receiver for serial pulse telegrams, the telegram head of which has a start character, comprising a receiving circuit which can be set to at least two predefined baud numbers, and a clock generator which generates at least two clock sequences with clock repetition frequencies proportional to these baud numbers.

Telegraphy receivers of the type described are used in particular in telecontrol technology and are connected to an assigned transmitter via a transmission channel. The pulse telegrams usually contain technical information, such as operating status messages, measured values or limit value signals, which are sent from a remote outside part to a control center, or switching commands, manipulated variables and steering commands, which are transmitted in the opposite direction. For the transmission of a lot of information, a high transmission speed with a high pulse repetition frequency corresponding to a large baud number is aimed for, the highest possible transmission speed and the corresponding baud number being dependent on the available transmission channel and the selected transmission type. The customary transmitters and receivers are therefore set up for sending or receiving pulse telegrams with several predefined baud numbers and are permanently set to one of the predefined baud numbers when connected to a transmission channel.

Modern semiconductor technology enables telegraph transmitters and receivers to be designed as integrated circuits, the components of which are arranged on a single chip. Each chip contains as many external connections as are required for signal input and output, for connecting the supply voltage and for setting the baud rate. For miniaturized components, these external connections have at least two disadvantages: they are relatively large, which hinders miniaturization, and they are less reliable than the integrated circuit itself, which impairs the reliability of the entire component.

The present invention is therefore based on the object of providing a receiver for serial pulse telegrams which is designed as an integrated circuit and which automatically adjusts itself to the baud rate of the incoming telegrams, so that the external connections for setting the baud rate can be dispensed with.

According to the invention, this object is achieved with a telegraphic receiver of the type mentioned at the outset, which is characterized by at least two detection circuits, each of which is assigned one of the clock sequences and each of which contains at least one memory in which the structure of a telegram header is stored, and at least one shift register, through which a signal sequence corresponding to the telegram header of each received telegram with the assigned clock repetition frequency is pushed, and at least one comparator circuit which compares the content of the at least one shift register with the content of the at least one memory for each clock cycle

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circuit-specific detection signal generates, if the two contents match, which detection signal the receiving circuit sets to the baud rate corresponding to the repetition frequency of the shift clock.

The additional detection circuits required for generating the detection signal and setting the receiving circuit to the corresponding baud number can be formed as part of the integrated circuit of the receiver without any significant additional outlay. These detection circuits advantageously replace the external connections previously required for setting the receiver to the baud number of the incoming telegram, as a result of which the external dimensions can be reduced and the reliability of the entire module can be improved.

A preferred embodiment of the new telegraph receiver is described below with the aid of the figures. Show it:

1 shows the structure of a telegram common in telecontrol technology,

2 the end one and the beginning of the subsequent telegram transmitted in synchronous operation,

3 shows the block diagram of a simplified embodiment of the new receiver,

4 shows the block diagram of a detection circuit in the receiver according to FIG. 2,

5 shows the end of one and the beginning of the subsequent telegram corresponding to FIG. 2 with the detection clocks which read the signal sequence and the successive edges of the signal sequence into a signal or edge shift register, and the signal and edge sequence corresponding to a truth table for detection of a telegram header.

The new receiver is described below using the example of a telecontrol system, without being limited to this use.

In telecontrol systems, it is common to transmit the telegrams with the technical information or commands in synchronous operation. In this mode of operation, telegrams are transmitted continuously, regardless of whether they contain different or the same information, commands or addresses. A typical telegram structure is shown in FIG. 1, for example. The telegram 10 contains a header 11, an information and / or address part 12, a check character 13 and a stop character 14. The header consists of a start character 16 corresponding to binary 1, which is separated by a separator 17 corresponding to binary 0 from the following information and / or address part is separated. In the selected example, this information and / or address part contains 24 = 16 data bits (DI5 to DO) which, in accordance with the information and / or address to be transmitted, are designed as binary 1 or binary 0 (and therefore shown in broken lines in FIG. 1) are. The check character 13 can also be binary 0 or binary 1 depending on the bits in the information and / or address part, while the stop character 14 is always binary 0. The duration of the separator 17, the data bits D15 to DO, the check character 13 and the stop character 14 is the same and is t s, corresponding to a baud rate 1 / t s ~ '. The duration of the start character 16 in the selected example is 1.5 t in order to clearly distinguish the start character from the uninterrupted character string in synchronous operation and to prevent a signal sequence corresponding to the telegram header from being recognized as a telegram header in the information and / or address part.

2 shows the end of a telegram Tn and the beginning of the following telegram Tn + |. As the figure shows, in the selected telegram structure, the start character 16 'designed as binary 1 is enclosed by the stop character 14' of the telegram Tn represented by binary 0 and the similar separator 17 'of the subsequent telegram Tn + i. This telegram structure enables the stop sign of the previous telegram to be included in the head recognition and the baud rate determination and thus to increase the security of the correct recognition and determination.

FIG. 3 shows the block diagram of a simplified embodiment of the new receiver with three detection circuits, which are provided for detecting three different baud rates. The telegram input terminal 20 of the receiver is connected to the telegram input of a receiving circuit 22 by means of a feed line 21 and to the telegram input of each of the three detection circuits 23, 24, 25 by means of a further branched line 21 '. The receiving circuit 22 includes a shift register 27 which interacts with an activatable output circuit 28, the outputs of which are connected to the data output terminals 29. The receiver also contains a clock generator 31 which has at least as many outputs as detection circuits are provided. The outputs of the clock generator are connected by means of lines 32, 33, 34 to a second input on each of the detection circuits and, via assigned coasters 36, to corresponding clock inputs of the reception circuit. Lines 37, 38, 39 lead from the signal outputs of the detection circuits at which different detection signals associated with the respective detection circuit appear to a multi-part detection signal memory 41, the outputs of which correspond to the different detection signals are connected to detection signal inputs of the reception circuit by means of lines 42, 43, 44. The detection signal memory interacts with a “one-out-of-n control circuit” 46. Finally, a tail unit 47 is also provided, the inputs of which are connected via a line 48 to the output of the “one-of-n control circuit” and by means of at least two lines 49, 50 with outputs of the receiving circuit and the outputs of which are connected to the reset inputs by means of a branched line 52 each of the three detection circuits and a line 53 are connected to the activation signal input of the output circuit 28. Preferably, the tail contains a counter 54, the operation of which will be described.

4, the detailed block diagram of a preferred embodiment of the detection circuit is shown. This detection circuit contains a first input terminal 60 for the received telegrams, which is connected via a branched line 61 to the one input of a signal shift register 62 and the one input of an edge detector 63. A buffer 64 is connected downstream of the edge detector, from the output of which a line 65 leads to the one input of an edge shift register 66. A second input terminal 68 for the detection clocks is connected via a branched line 69 to the other input of the signal and edge shift registers 62 and 66, respectively. A third input terminal 71 for reset signals from the tail unit is connected by means of a line 72 to the other input of the edge detector. The detection circuit also contains a read-only memory 74 and a signal and an edge comparator circuit 75 and 76, respectively, which interact with the memory and the signal or edge shift register. The outputs of the comparator circuits are connected to an AND gate 77, the output of which is led to the output terminal 78 of the detection circuit.

As already mentioned in the introduction, a telecontrol system contains a plurality of transmitter-receiver connections,

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each of these connections usually having a different transmission frequency and the telegrams being assigned a corresponding baud rate. Similar receivers can be used for all connections, which automatically adjust to the baud number of the telegrams, provided that the number of detection circuits provided in the receiver is at least as large as the number of baud numbers used in the system and that the baud numbers recognizable by the receiver are included correspond to the baud rates used for the telecontrol connection.

To describe the operation of the new receiver, it is assumed that the received telegrams have the structure shown in Fig. 1, i.e. contain a telegram header with a start and a delimiter and a stop sign after the information and / or address part and the test sign. The duration of the bits including the separator and the stop character is t s, that of the start character 1.51 s. It is also assumed that the system works in synchronous operation, i.e. an uninterrupted sequence of telegrams is transmitted, the transition from one telegram to the following telegram having the structure shown in FIG. 2.

Furthermore, it is assumed that the receiver contains three detection circuits and is connected to a system that transmits telegrams with three different baud rates and that the clock generator generates a detection cycle sequence for each detection circuit that is proportional to one of the baud rates used for the transmission and, for example, four times this transmission baud rate is.

Finally, it is assumed that the registers in the detection circuit have at least so many memory locations that the stop sign of a previous and the header of the following message can be stored by the clocks of the detection clock sequence. With the numerical values given, for example: stop sign + telegram header = 3.5 transmission cycles and one transmission cycle = 4 detection cycles, then at least 14 memory locations are calculated for each register. The read-only memory contains at least as many memory locations as the two shift registers together, i.e. 28 in the selected example. The values stored in the two parts of the read-only memory correspond to the optimum or to be expected with a specified tolerance, generated by the stop sign of a telegram and the header of the subsequent telegram Signal sequence.

The telegrams sent to the input terminal 20 of the receiver are routed via the branched line 21, 21 'to the receiving circuit 22 and to the three detection circuits 23, 24, 25. The telegram bits arriving in accordance with their transmission clock are then read into the respective signal shift register 62 using the detection clock assigned to the detection circuit. For the signal shift register of that detection circuit, the detection clock of which is proportional to the transmission clock of the incoming telegram, after reading the stop sign 14 'of a telegram Tn and the header 11 of the following telegram Tn +, the optimal assignment of the continuous line drawn in FIG. 5 results Storage locations S00-Si5. The actual occupancy of the memory locations can deviate from this optimal occupancy because the clock generators in the transmitter and in the receiver have only a limited accuracy and the transmission conditions can also distort the signals. In the receivers used in practice, tolerances are therefore provided for the beginning and end of each character, which in the selected example can be up to ± 0.25 t. With this assumed tolerance it follows that after reading in the stop sign and telegram header, only the memory locations for the signals S6, S7, S8, S9 or S2, S3 and S12, S13 are occupied or not occupied.

The same signal sequence which is expected when the stop sign of a telegram Tn and the header of the subsequent telegram Tn + 1 are stored in the signal shift register is permanently stored in the memory locations of the read-only memory 74 assigned to the signal shift register 62. The signal comparator circuit 76 assigned to the signal shift register and the corresponding memory part compares the content of the register with the assigned memory part with each clock, the comparison expediently being limited to those memory locations which are occupied or not occupied, which is in line 80 the truth table shown in FIG. 5 is shown. Each time the signal comparator circuit detects correspondence between the signals in the signal shift register and the corresponding memory section, a detection signal is generated and sent to the AND gate 77.

The head detection circuit shown in FIG. 4 also contains an edge detector 63, the incoming telegrams of which are fed to an input via the branched line 61. Every time a signal change from binary 0 to binary 1 or vice versa takes place in the incoming telegram, the edge detector generates an output signal which is immediately read into the buffer memory 64 and at the subsequent clock pulse into the edge shift register 66. For the stop signal of a telegram Tn and the header of a subsequent telegram Tn + 1 with the signal form described above and the tolerances specified, the storage locations in the edge shift register shown in line 81 of the truth table according to FIG. 5 are then assigned signals in accordance with the possible appearance or the safe absence of an edge between successive bars. This signal sequence is permanently stored in the part of the read-only memory 74 assigned to the edge shift register 66. The edge comparator 76 compares the content of the edge shift register 66 with the content of the associated memory part with each detection clock, the comparison again being limited only to the edge signals that appear to be certain or are absent, and generates a detection signal, if matched, which is sent to the AND gate 77 becomes.

When a detection signal from the signal and edge comparators 62 and 66 arrives at the same time, the AND gate 77 generates an output signal assigned to the corresponding detection circuit, which is stored in the detection memory and forwarded to the receiver circuit 22 as a baud rate detection signal. The baud rate detection signal switches the receiver to the clock sequence supplied by the coaster, which is proportional to the assigned detection clock sequence.

The buffer memory 64 connected downstream of the edge detector is reset with each detection cycle and after its content has been read into the edge shift register 66 and is thus prepared for reading in a further edge signal.

As is clear from the above description, the function of the new receiver is relatively simple. Each incoming telegram is sent with different clock sequences, i.e. Clock sequences with different baud numbers, read into a shift register, the content of which is compared with a predetermined signal sequence for each clock. Only in the shift register of the detection circuit whose assigned detection clock sequence is proportional to the transmission clock sequence or baud number of the received telegrams does a signal sequence appear periodically that the previous one

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the same signal sequence in the read-only memory.

In order to ensure that the correct baud number is recognized during synchronous operation, the stop sign of the previous telegram can simply be evaluated together with the header of the subsequent telegram, as described for the preferred embodiment.

Another safeguard is the simultaneous evaluation of the signal sequence and the edge sequence, although it would suffice to evaluate only the signal or the edge sequence. Counter 54 is provided in the tail unit for even better protection. This counter is incremented by one unit each time a detection circuit delivers a detection signal and the reception circuit has recognized the subsequent telegram as good. Only when the counter has reached a predetermined counter reading is the output circuit 28 activated and the telegram passed on to the data output terminals 29. If one or both of the above conditions are not met, the counter is reset to zero and the output circuit is only activated again when so many consecutive telegrams that meet the two conditions have been counted into the counter that the counter reaches the specified counter reading.

It goes without saying that with this type of backup, some of the telegrams recognized as good are not output. Because experience has shown that a large number of successive telegrams contain the same information in synchronous operation, this disadvantage is of no practical importance.

In the previous description it was assumed that the telegrams are transmitted in an uninterrupted sequence. The new receiver with the detection circuits can, however, also be used advantageously for transmission in the start-stop mode. Because of this

Transmission pauses between the individual telegrams that characterize the operating mode, the stop sign of a previous telegram cannot be used to recognize and evaluate the probe of an incoming telegram 5. In order to increase the security when recognizing the telegram header and determining the baud number in start-stop operation, a telegram structure can be used, for example, which has two check bits after the information and / or address bit, at least one of which is binary 1 and which enable subsequent checking of the baud number recognized and set on the telegram header.

A practically tested embodiment of the new receiver is provided for receiving telegrams with seven different baud rates and contains seven detection circuits for this. The baud number of the seven identification clock sequences is 32 times larger than the intended telegram baud numbers and accordingly each shift register 98 and the read-only memory 196 contain 20 memory locations. Such receivers are particularly well suited for telecontrol transmissions in which several transmitters and receivers are connected to one another via the same line and, for example, in frequency division multiplex operation.

The 25 transmission bands used in particular in telecontrol technology and the baud numbers assigned to their frequency ranges are described in the literature and defined, for example, in the CCITT standards, which is why, for example, information is expressly omitted here.

The new receiver can be produced using the methods customary for the production of integrated circuits and known to any person skilled in the art, which is why this production is also not described.

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2 sheets of drawings

Claims (7)

653505 PATENT CLAIMS
1. Telegraphy receiver for serial pulse telegrams, the telegram header (11) has a start character (16), containing a receiving circuit (22) that can be set to at least two predefined baud rates, and a clock generator (31) that also has at least two clock sequences generated clock rate frequencies proportional to these baud numbers, characterized by at least two detection circuits (23, 24, 25), each of which is assigned one of the clock sequences and each contain at least one memory (74) in which the structure of a telegram header is stored, and at least one shift register (62,66), through which a signal sequence corresponding to the telegram header of each received telegram is pushed with the assigned clock repetition frequency, and at least one comparator circuit (75,76) which, for each clock, the content of the at least one shift register with the content of the at least compares a memory and generates a circuit-specific detection signal t, if the two contents match, which detection signal the receiving circuit sets to the baud rate corresponding to the repetition frequency of the shift clock.
2. Receiver according to claim 1, characterized in that each detection circuit (23, 24, 25) is assigned a detection signal memory (41), which stores a stored detection signal at least for the duration of the assigned telegram to the corresponding input (42, 43, 44). the receiving circuit (22) conducts, and the output of each detection circuit or signal latch is connected to a one-out-of-n control (46) which generates an error signal when more than one detection signal appears or is stored simultaneously.
3. Receiver according to claim 2, characterized in that a tail unit (47) is also provided, which resets the detection circuits (23, 24, 25) and the detection signal memory (41) when an error signal appears and blocks the telegram output circuit (28) and at If there is no error signal, the receiving circuit (22) adjusts to the baud rate corresponding to the stored detection signal and the telegram output circuit (28) is activated after each well received telegram
4. Receiver according to claim 1, characterized in that the structure of the telegram header stored in the at least one memory (74) of each detection circuit corresponds to its binary signal sequence [80 in FIG. 5] and the sequence of the binary signals forming the telegram into the signal shift register ( 62) can be read.
5. Receiver according to claim 1, characterized in that the structure of the telegram header stored in the at least one memory (74) of each detection circuit (23, 24, 25) is the same as the sequence of edges [81 in FIG. 5] between those forming the telegram header is binary signals and each detection circuit contains an edge detector (63), which is followed by a buffer (64), which stores each detected edge and reads into an edge shift register (66) at the next cycle.
6. Receiver according to claim 1, characterized in that the binary signal sequence and the sequence of the edges of the binary signals of a telegram header are stored in the at least one memory (74) of each detection circuit (23, 24, 25) and each detection circuit has a signal shift register (62 ) and an edge shift register (66) and for comparing the content of the memory with each of the two registers contains a signal and an edge comparator (75, 76), the outputs of which are connected to an AND gate (77).
7. Receiver according to claim 3, characterized in that the tail unit (47) contains a counter (54) by one
Unit switches on if the receiving circuit (22) recognizes the received telegram as good and the baud number corresponding to the recognition signal matches that of the previously received telegram or is reset to zero if at least one of the two conditions is not met and which counter is exceeded an activation signal for the telegram output circuit (28) generates a predetermined counter reading.
CH305381A 1981-05-12 1981-05-12 Telegraphic receiver for serial impulse telegrams. CH653505A5 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CH305381A CH653505A5 (en) 1981-05-12 1981-05-12 Telegraphic receiver for serial impulse telegrams.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH305381A CH653505A5 (en) 1981-05-12 1981-05-12 Telegraphic receiver for serial impulse telegrams.
DE19813124163 DE3124163A1 (en) 1981-05-12 1981-06-19 Telegraphy receiver for serial pulse telegrams

Publications (1)

Publication Number Publication Date
CH653505A5 true CH653505A5 (en) 1985-12-31

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Family Applications (1)

Application Number Title Priority Date Filing Date
CH305381A CH653505A5 (en) 1981-05-12 1981-05-12 Telegraphic receiver for serial impulse telegrams.

Country Status (2)

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CH (1) CH653505A5 (en)
DE (1) DE3124163A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3404790C2 (en) * 1984-02-10 1989-04-27 Siemens Ag, 1000 Berlin Und 8000 Muenchen, De
US4847703A (en) * 1985-06-03 1989-07-11 Canon Kabushiki Kaisha Data transmission and detection system
DE3537477C2 (en) * 1985-10-22 1991-04-25 Dr.Ing.H.C. F. Porsche Ag, 7000 Stuttgart, De

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001504A (en) * 1975-06-09 1977-01-04 International Business Machines Corporation Automatic terminal data rate selection
JPS6028424B2 (en) * 1977-04-25 1985-07-04 Kokusai Denshin Denwa Co Ltd

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DE3124163A1 (en) 1982-12-09

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