CH566079A5 - - Google Patents

Info

Publication number
CH566079A5
CH566079A5 CH1818873A CH1818873A CH566079A5 CH 566079 A5 CH566079 A5 CH 566079A5 CH 1818873 A CH1818873 A CH 1818873A CH 1818873 A CH1818873 A CH 1818873A CH 566079 A5 CH566079 A5 CH 566079A5
Authority
CH
Switzerland
Application number
CH1818873A
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of CH566079A5 publication Critical patent/CH566079A5/xx

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222Bipolar technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0821Combination of lateral and vertical transistors only
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/037Diffusion-deposition
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/085Isolated-integrated
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/117Oxidation, selective
CH1818873A 1972-12-29 1973-12-27 CH566079A5 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7217783.A NL161301C (nl) 1972-12-29 1972-12-29 Halfgeleiderinrichting en werkwijze voor de vervaar- diging daarvan.

Publications (1)

Publication Number Publication Date
CH566079A5 true CH566079A5 (es) 1975-08-29

Family

ID=19817648

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1818873A CH566079A5 (es) 1972-12-29 1973-12-27

Country Status (11)

Country Link
US (1) US3911471A (es)
JP (1) JPS524433B2 (es)
AT (1) AT356178B (es)
CA (1) CA1003577A (es)
CH (1) CH566079A5 (es)
DE (1) DE2361319C2 (es)
FR (1) FR2271666B1 (es)
GB (1) GB1456376A (es)
IT (1) IT1000635B (es)
NL (1) NL161301C (es)
SE (1) SE390852B (es)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3993513A (en) * 1974-10-29 1976-11-23 Fairchild Camera And Instrument Corporation Combined method for fabricating oxide-isolated vertical bipolar transistors and complementary oxide-isolated lateral bipolar transistors and the resulting structures
DE2510593C3 (de) * 1975-03-11 1982-03-18 Siemens AG, 1000 Berlin und 8000 München Integrierte Halbleiter-Schaltungsanordnung
GB1499845A (en) * 1975-03-26 1978-02-01 Mullard Ltd Thyristors
US4063272A (en) * 1975-11-26 1977-12-13 General Electric Company Semiconductor device and method of manufacture thereof
DE2708639A1 (de) * 1977-02-28 1978-08-31 Siemens Ag Transistoranordnung auf einem halbleiterplaettchen
JPS6055988B2 (ja) * 1979-01-26 1985-12-07 株式会社日立製作所 半導体装置の製法
JPS5599722A (en) * 1979-01-26 1980-07-30 Hitachi Ltd Preparation of semiconductor device
JPS55133569A (en) * 1979-04-06 1980-10-17 Hitachi Ltd Semiconductor device
JPS588139B2 (ja) * 1979-05-31 1983-02-14 富士通株式会社 半導体装置の製造方法
DE3071380D1 (en) * 1979-05-31 1986-03-13 Fujitsu Ltd Method of producing a semiconductor device
US4376664A (en) * 1979-05-31 1983-03-15 Fujitsu Limited Method of producing a semiconductor device
JPS5673446A (en) * 1979-11-21 1981-06-18 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
JPS5856434A (ja) * 1981-09-30 1983-04-04 Fujitsu Ltd 半導体装置の製造方法
US5248894A (en) * 1989-10-03 1993-09-28 Harris Corporation Self-aligned channel stop for trench-isolated island
US7981759B2 (en) * 2007-07-11 2011-07-19 Paratek Microwave, Inc. Local oxidation of silicon planarization for polysilicon layers under thin film structures

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE636317A (es) * 1962-08-23 1900-01-01
US3423650A (en) * 1966-07-01 1969-01-21 Rca Corp Monolithic semiconductor microcircuits with improved means for connecting points of common potential
US3502951A (en) * 1968-01-02 1970-03-24 Singer Co Monolithic complementary semiconductor device
NL169121C (nl) * 1970-07-10 1982-06-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een halfgeleiderlichaam, dat aan een oppervlak is voorzien van een althans ten dele in het halfgeleiderlichaam verzonken, door thermische oxydatie gevormd oxydepatroon.
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
NL173110C (nl) * 1971-03-17 1983-12-01 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een uit ten minste twee deellagen van verschillend materiaal samengestelde maskeringslaag wordt aangebracht.
NL7105000A (es) * 1971-04-14 1972-10-17
US3796613A (en) * 1971-06-18 1974-03-12 Ibm Method of forming dielectric isolation for high density pedestal semiconductor devices

Also Published As

Publication number Publication date
SE390852B (sv) 1977-01-24
GB1456376A (en) 1976-11-24
FR2271666B1 (es) 1976-11-19
FR2271666A1 (es) 1975-12-12
CA1003577A (en) 1977-01-11
AU6389573A (en) 1975-06-26
NL161301C (nl) 1980-01-15
US3911471A (en) 1975-10-07
JPS4999286A (es) 1974-09-19
JPS524433B2 (es) 1977-02-03
ATA1085073A (de) 1979-09-15
NL7217783A (es) 1974-07-02
DE2361319A1 (de) 1974-07-04
IT1000635B (it) 1976-04-10
DE2361319C2 (de) 1983-03-03
AT356178B (de) 1980-04-10
NL161301B (nl) 1979-08-15

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Legal Events

Date Code Title Description
PL Patent ceased