CH457921A - Einrichtung zur Addition mehrstelliger Operanden - Google Patents

Einrichtung zur Addition mehrstelliger Operanden

Info

Publication number
CH457921A
CH457921A CH1223067A CH1223067A CH457921A CH 457921 A CH457921 A CH 457921A CH 1223067 A CH1223067 A CH 1223067A CH 1223067 A CH1223067 A CH 1223067A CH 457921 A CH457921 A CH 457921A
Authority
CH
Switzerland
Prior art keywords
adding multi
digit operands
operands
digit
Prior art date
Application number
CH1223067A
Other languages
English (en)
Inventor
Elliott Goldschmidt Robert
John Litwiller Robert
Michaels Powers Don
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH457921A publication Critical patent/CH457921A/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3884—Pipelining

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
CH1223067A 1966-08-31 1967-08-31 Einrichtung zur Addition mehrstelliger Operanden CH457921A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US57640166A 1966-08-31 1966-08-31

Publications (1)

Publication Number Publication Date
CH457921A true CH457921A (de) 1968-06-15

Family

ID=24304268

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1223067A CH457921A (de) 1966-08-31 1967-08-31 Einrichtung zur Addition mehrstelliger Operanden

Country Status (9)

Country Link
US (1) US3515344A (de)
AT (1) AT268732B (de)
CH (1) CH457921A (de)
DE (1) DE1549477B1 (de)
DK (1) DK141182B (de)
ES (1) ES344566A1 (de)
FR (1) FR1529408A (de)
NL (1) NL6711951A (de)
SE (1) SE330277B (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3697734A (en) * 1970-07-28 1972-10-10 Singer Co Digital computer utilizing a plurality of parallel asynchronous arithmetic units
US3675001A (en) * 1970-12-10 1972-07-04 Ibm Fast adder for multi-number additions
PL106470B1 (pl) * 1977-02-01 1979-12-31 Inst Maszyn Matematycznych Uklad cyfrowy do obliczania wartosci zlozonych wyrazen arytmetycznych
US4110832A (en) * 1977-04-28 1978-08-29 International Business Machines Corporation Carry save adder
US4208722A (en) * 1978-01-23 1980-06-17 Data General Corporation Floating point data processing system
US4168530A (en) * 1978-02-13 1979-09-18 Burroughs Corporation Multiplication circuit using column compression
US4228520A (en) * 1979-05-04 1980-10-14 International Business Machines Corporation High speed multiplier using carry-save/propagate pipeline with sparse carries
US4399517A (en) * 1981-03-19 1983-08-16 Texas Instruments Incorporated Multiple-input binary adder
US4556948A (en) * 1982-12-15 1985-12-03 International Business Machines Corporation Multiplier speed improvement by skipping carry save adders
US4616330A (en) * 1983-08-25 1986-10-07 Honeywell Inc. Pipelined multiply-accumulate unit
JPH0640301B2 (ja) * 1983-09-22 1994-05-25 ソニー株式会社 並列乗算回路
JPS6068432A (ja) * 1983-09-22 1985-04-19 Hitachi Ltd キヤリセ−ブアダ−の符号生成方式
DE3524981A1 (de) * 1985-07-12 1987-01-22 Siemens Ag Anordnung mit einem saettigbaren carry-save-addierer
US4901270A (en) * 1988-09-23 1990-02-13 Intel Corporation Four-to-two adder cell for parallel multiplication
US5150321A (en) * 1990-12-24 1992-09-22 Allied-Signal Inc. Apparatus for performing serial binary multiplication
US5625582A (en) * 1995-03-23 1997-04-29 Intel Corporation Apparatus and method for optimizing address calculations
US5818743A (en) * 1995-04-21 1998-10-06 Texas Instruments Incorporated Low power multiplier
US5612911A (en) * 1995-05-18 1997-03-18 Intel Corporation Circuit and method for correction of a linear address during 16-bit addressing
US5973705A (en) * 1997-04-24 1999-10-26 International Business Machines Corporation Geometry pipeline implemented on a SIMD machine
JP3529622B2 (ja) * 1998-05-08 2004-05-24 株式会社東芝 演算回路
US6484193B1 (en) * 1999-07-30 2002-11-19 Advanced Micro Devices, Inc. Fully pipelined parallel multiplier with a fast clock cycle
GB2396708B (en) * 2002-12-05 2006-06-21 Micron Technology Inc Hybrid arithmetic logic unit
US8073892B2 (en) * 2005-12-30 2011-12-06 Intel Corporation Cryptographic system, method and multiplier
CN105512724B (zh) * 2015-12-01 2017-05-10 中国科学院计算技术研究所 加法器装置、数据累加方法及数据处理装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3253131A (en) * 1961-06-30 1966-05-24 Ibm Adder
US3115574A (en) * 1961-11-29 1963-12-24 Ibm High-speed multiplier
US3311739A (en) * 1963-01-10 1967-03-28 Ibm Accumulative multiplier
US3278732A (en) * 1963-10-29 1966-10-11 Ibm High speed multiplier circuit
US3340388A (en) * 1965-07-12 1967-09-05 Ibm Latched carry save adder circuit for multipliers

Also Published As

Publication number Publication date
NL6711951A (de) 1968-03-01
US3515344A (en) 1970-06-02
ES344566A1 (es) 1968-10-16
DK141182B (da) 1980-01-28
SE330277B (de) 1970-11-09
AT268732B (de) 1969-02-25
FR1529408A (fr) 1968-06-14
DE1549477B1 (de) 1971-03-25
DK141182C (de) 1980-06-23

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