CH312268A - Multiplication device of a purely digital electronic calculating machine. - Google Patents

Description

  

  Multiplication device of a purely digital electronic calculating machine. The subject of the present invention is a positive multiplication device for a purely digital electronic calculating machine to operate on numbers represented in binary notation by electrical signals.



  In binary numeration, especially when it is used for purely numerical calculating machines, we use both the so-called unsigned (or arithmetic) notation and the so-called si gnes (or algebraic) notation or else to complements. In arithmetic notation, the number is read by adding the values of all its digits; thus, for example, the binary number 1011 represents 1.23 + 0.22 + 1.21 + 1.20 that is: 8 + 2 + 1 = 11 (in decimal numeration). Only positive numbers can be represented in this way.

   In algebraic notation, the value of the leftmost digit, which represents the highest order units, is subtracted from the sum of the values of the other digits. This notation makes it possible to represent both positive and negative numbers. Thus, for example, in this notation, the binary number 01011 represents the decimal number 11, as before, while the binary number 1107.1 represents -16 + 8 + 2 + 1, that is: -5. Likewise, the decimal number -11 would be represented, in this notation, by 10101, i.e. -16 + 4 + 1.

   It will be noted that the conversion of a binary number into its complement is obtained by inverting the significant value of each digit after the first digit 1, starting from the order of the lowest units of the number.



  If it is necessary to extend an unsigned number in the direction of increasing unit orders from, for example, a number of five digits to obtain a number of ten digits, this operation can be carried out by adding the number of zeros needed to the left of the shadow. So, <B> 01011 </B> transformed into a ten-digit number becomes 0000001011. On the other hand, in the case of a number affected by a sign, it is necessary to repeat as many times as necessary the extreme left digit of the initial number. This is how 01011 becomes 0000001011, while 11011 becomes 1111111011.



  The use of such a notation with si gnes or in the form of complements allows, provided that the two numbers concerned by the operation have the same number of digits, to carry out the addition and the subtraction exactly by the same ones. methods for signed numbers only for unsigned numbers, if we neglect the units to be carried over or retained from the highest key units order. On the other hand, for multiplication, it is necessary to take into account the sign conventions of the factors.

      The table below gives an example of binary multiplication of two numbers without signing
EMI0002.0004
  
    1011 <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP> R <SEP> (11) <SEP> __ <SEP> h <SEP> = <SEP> 3 <SEP> dK.2x.R
 <tb> 0101 <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP> D <SEP> (5) <SEP> <i> <U> Y </U> </I> K <SEP> = <SEP> 0
 <tb> 00001011 <SEP> <I>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP> Rdo2o </I>
 <tb> <B> (0) 0000000 </B> <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP> Rdi2i
 <tb> (00) <SEP> 0010 <SEP> 11 <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP> Rd222
 <tb> (000) <SEP> 0000 <SEP> 0. <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP>:

    <SEP> Rd323
 <tb> (000) <SEP> 0011 <SEP> 0111 <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP> RD <SEP> (32 <SEP> + <SEP> 16 <SEP> + <SEP> 4 <SEP> + <SEP> 2 <SEP> + <SEP> 1 <SEP> = <SEP> 55) We can see that such an operation involves three processes, namely: 1 The factor R is multiplied separately by each digit di {of the factor D, 2 The products Rdx thus obtained are multiplied each by 2K then extended to the left.



  3 The RdK2K partial products are added to obtain the final product.



  The prolongation of each partial product RdK2K doubling the initial length of the num ber, that is to say transforming it into an eight-digit number, is carried out by adding zeros, since neither R nor D contains sign.

      In a multiplication involving signed numbers, it is necessary to extend each one. : partial products RdK2K by repeating the units digit of the highest order if the R factor is assigned a sign. In addition, if the factor D is assigned a sign, we must invert the sign of the last partial product Rd323, i.e. transform it into its complement before adding it, given that the digit. The highest order of units of the factor D has a negative value.



  The table below gives an example of binary multiplication of two algebraic numbers:
EMI0002.0029
  
     <B> 11011 </B> <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP> R. <SEP> (- <SEP> 5) <SEP> _ <SEP> K <SEP> = <SEP> 3 <SEP> (dK2K <SEP> - <SEP> d424) <SEP>. <SEP> R
 <tb> 10101 <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP> D <SEP> (-11) <SEP> - @ K <SEP> = <SEP> 0
 <tb> 11111 <SEP> 11011 <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP> Rd020
 <tb> 00000 <SEP> 0000 <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP> Rdi2i
 <tb> <B> 11111011 </B> <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP> <I> Rd222 </I>
 <tb> <B> 0000000 </B> <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP> Rd323
 <tb> <B> 000101 </B> <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP>. <SEP>.

    <SEP> - <SEP> Rd424
 <tb> (10) <SEP> <B> 00001 <SEP> 10111 </B> <SEP> ...:. <SEP> RD = (32 + 16 + 4 + 2 + 1 = 55) The object of the present invention is in particular to create a multiplication device capable of operating on factors whose total number of digits is greater than the number of digits of what is called a combination, that is, a series of digits which can be expressed in dynamic sequential form by a series of consecutive signals which occupy the duration of a cycle mi neur or time of the rhythm of operation for which the calculating machine is built.

   In a preferred embodiment, said device may be capable of operating, under the control of a suitable combination of sound-order, either on arithmetic numbers or on algebraic numbers.



  The multiplication device for my purely digital electronic calculating machine operating on numbers represented in binary notation by electrical signals according to the invention comprises a device for storing series of signals representing the multiplicand and the multiplier, and. a multiplication arrangement comprising a number X of distinct and parallel inputs each capable of being controlled by a signal representing one of the digits of the multiplicand represented by X digits and a single input intended to receive consecutive signals representing the digits of the multiplier.

   This device is characterized in that said storage device has a capacity allowing the storage of signals representing a multiplicand and a multiplier each comprising a number of digits greater than said number X of inputs that comprises said assembly- of -multi plication, and in that it comprises a selector and sampling device cooperating with said storage device, so as to be able to make a choice among the locations thereof in which signals are stored, and take these if general in the chosen locations,

   this positive selector and sampling device being arranged so that at least those of said stored signals which represent the multiplication can be taken in segments of signals each representing X digits, a control device capable of being actuated by an order signal single provided by the calculating machine and capable of extracting from the storage device the first of said signal slices representing digits of the multiplier, of applying this slice of signals to the control of said X inputs of the multiplica assembly - tion likely to be controlled by these signals,

   while the complete series of consecutive signals representing the multiplier is applied to said single input of the multiplication assembly intended to receive these consecutive signals, so that this assembly provides a first partial product represented by a series of signals, of then extract from the storage device the second of said slices of signals representing the digits of the multiplicand, to apply this second slice to the control of said X inputs of the multiplication assembly capable of being controlled by these signals while the complete series of consecutive signals.

   representing the multiplier is extracted from the storage device and applied again to the said single input of the multiplication assembly intended to receive these consecutive signals, so that this assembly provides a second: partial product represented by another sequence of si general, and a device capable of combining said series of signals representing respectively said first and second partial products in the form of a series of signals representing the product of the complete Multiplication and of the multiplier.



  The appended drawing represents, by way of example, an embodiment of the device which is the subject of the invention.



  Fig. 1 is a symbolic diagram of the main elements of the calculating machine which are intended to work during a multiplication operation.



       Figs. 2 to 9 represent graphic symbols used in the other figures with plps developed diagrams of equivalent assemblies of. these symbols. Figs. 10a, 10b and 10c together represent a detailed diagram of the multiplication device.



  FIGS: 11 and 12 each represent a series of curves showing different forms of electrical waves capable of being used in the machine and actuating the multiplier device, FIG. 12 comprising, in addition, a table indicating the positions in time of the: different phases of the process of a multiplication operation.



  Fig. 13 shows schematically the essential elements of a waveform generator WGU and machine insofar as these elements take part in the multiplication operation.



  Fig. 1.4 is a schematic view similar to FIG. 13 of the essential elements of a main dynamicostatic converter DIST1i insofar as these elements take part in the multiplication operation.



  Fig. 15 is a schematic view, similar to FIG. 13, essential elements of a control unit <I> CL </I> to the extent that these elements take part in the multiplication operation.



  Fig. 16 is a more detailed diagram of part of the device of FIG. 10a constituting a CCV complement converter.



  Fig. 17 is a more detailed diagram of part of the device & e in FIG. 10b constituting a number / complement converter CDV.



  Fig. 18 is a circuit diagram of the elements of vertical deflection waveform generators MYG and AYG of FIGS. 10a and 10c respectively.



  . Fig. 19 is a circuit diagram of a decoder tube intended to establish an electronic counter control potential; from a particular combination of digits identifying functions of a signal-order.



  Fig. 20 is a diagram showing a variant of the interconnections between a multi-element adder device of the multiplier device and an accumulator.



  The embodiment of the device shown in the drawing forms an integral part of a purely digital electronic calculating machine, and in order to allow a clear understanding of it, everything will be recalled: first briefly below the design and organization. general of such a cal culating machine.



  Fig. 1 represents, in the symbolic form of rectangles, the essential elements of the machine which take part in the multiplication operation. These elements are a main store 111S, which has the function of recording the electrical signals representing both the numbers to be multiplied and the combinations-orders;

      an accumulator A for storing an identifying signal of any number applied thereto and for performing an arithmetic operation, such as addition or subtraction, with this recorded signal and another signal corresponding to another number and which may be applied subsequently to said accumulator, the signal identifying the result of such an arithmetic operation then being recorded in the same accumulator replacing the initial signal;

   a command block <I> CL </I> which determines the cyclic operation of the machine by extracting command signals from the main store MS in the order of their use and by transmitting signals drawn from these command combinations to other parts of the machine to determine the initiation of operations involved in the order to be executed;

   said multiplier device D1 which receives signals representing the factors, that is to say a multiplicand D and a multiplier R (in the remainder of the present description, to avoid any confusion between the multiplier device and Pun of the factors .a multiplication operation which, in accordance with the usual mathematical terminology, is also designated under the name of multiplier, the said device will be designated under the name multiplier device 11 and the number under the name of multiplier R), to .

   starting from the main store DIS and after having produced the product of these two factors, transmits to the accumulator A a signal representing this product; finally, means for generating waveforms WGU and comprising a plurality of assemblies suitably connected to one another and capable of supplying a range of electrical waveforms serving to determine and control the operational rhythm of the machine.

        The machine uses binary numbers and combinations-orders, both represented by trains of electric pulses, examples of which are given respectively in figs. 11 (i) and 11 (j) and in which the presence of a negative pulse with respect to a reference potential, during a defined time interval, referred to as the digit period indicates the binary value 1 , while the absence of such a pulse within a given digit period represents the binary value 0.

   In what follows, for simplicity, we will simply denote by negative or positive pulses respectively. negative or positive with respect to a potential of. reference. The digit periods p0, Dl: to p23 have. each lasts ten microseconds, and as the machine is designed primarily to operate with binary numbers of twenty digits, a <B> suc- </B> Twenty digit intervals are needed to express a given number. The storage devices used in the machine are of the thodic AC beam tube type. as described by F. C. Williams and T. gilburn in Proceedings of the I. E.

   E., volume III, March 1949, pages 81 to 100 (article hereinafter referred to as reference A), and, given that these devices require an additional period equal to four digit periods between two operations carried out on two successive numbers, to ensure the sudden return movement to the initial position of the beam of the tube concerned, the expression in the form of a train of electrical pulses of a number or of a combination-order occupies at total twenty-four digit periods, or 240 microseconds. This 240 microsecond time period constitutes what is called the minor cycle - or time of the machine and, as discussed in detail by F. C.

   Williams and others in Proceedings of the I. E. E., Volume II; February 1951, pages 13 to 28 (article - hereinafter referred to as the reference B), the machine requires a minimum of four times to form a major cycle or measurement during which an elementary phase of a process of. any calculation is performed. Certain types of calculation process, such as those of multiplication, require a longer time than the above four minor cycles and, in this case, the duration of the major cycle; or measurement, is extended by the addition of overtime.



  During each time of twenty-four digit periods, the first four periods are those used for the jerk; return to its initial position of the bundle of the tube concerned, while the other periods numbered respectively p0, p1 ... p19 in fig: 11 are used for the actual signaling of the values of the digits.



  In any signal representing a number, the value in binary units (or powers of two) of each digit period increases progressively, the first digit period p0 representing the binary value 20, the second period p1, the binary value 21 , And so on.



  Command signals are identical to signals-numbers, but their respective digit periods do not have the same binary numerical meaning: On the contrary, certain digit periods, for example periods p0 to p5, are assigned to the selection of a particular storage line belonging to a set of sixty-four lines available in one of the storage cathode ray tubes.



  The corresponding digits of the combination-sequence are referred to as digits 1. Other digit periods, namely p6 to p9, are likewise assigned to the selection of a particular tube belonging to a set of sixteen different beam, cathodic tubes available in the store. These digits are referred to as e digits. Still other digits, such as p13 to p19, are used to control the function which is to be performed by the machine during a given measurement.

   They are referred to as numbers <B> f. </B> Finally, some other digit periods of a given .combination-sequence are used for other purposes, but, since these latter digits lie play no role in the multiplication operation described here, they will no longer be mentioned below.



  To avoid exaggerated complexity, the figures have used symbols representing a wide variety of different elements of apparatus or electronic assemblies, and, to facilitate the understanding of these symbols, typical examples of Practical arrangements are first described below for some of said symbols with reference to FIGS. 2 to 9.



  The symbol in fig. 2a represents a known moxitage, in the technique of calculating machines, under the name of electronic counter with coincidence, which will be simply de-signed below under the name of counter; this assembly requires the simultaneous presence of voltages on its signal input terminals such as 1, 2, 3 (in number at least equal to two) to provide an output energy that can be used on its output terminal 4.

   Fig. 2b represents an embodiment of such a window, in which the input terminals 1, 2, 3 are connected to the respective anodes of diodes D1, D2, D3, the cathodes of which are connected in parallel to the input of a cathode load stage 5 as well as to one of the terminals of a load resistor 6, the other terminal of which is connected to a source of negative potential of -150 volts. The output energy of the cathode load stage 5 feeds the output terminal 4 of the window.

   Such a device operates under the action of negative potentials, and it is only when all the input terminals 1, 2, 3 simultaneously receive a suitable negative voltage that a corresponding negative voltage appears on the output terminal. 4.



  As will be discussed later, most of the control waveforms acting in the machine have a positive reference potential of about 3 volts with respect to the earth potential - and a fairly strongly negative operating level, for example 20 volts or more with respect to the potential of the earth. A window of this type can consist of a number of diodes at least equal to two, and a larger number of these diodes is shown in FIG. 2b by diodes D4, D5 indicated in dotted lines.



  The symbol in fig. 3a represents an assembly known in the art of calculating machines under the name of electronic counter that with alternatives, or buffer assembly, designated. hereinafter, for simplicity, under the name of buffer, in which any input energy appearing on one or more of the input terminals 7, 8, 9 or even on these three terminals at the same time, is transmitted to the output terminal 10, whatever the condition of the other input circuits at the time considered and without any interaction on said other inputs.

   A typical assembly of such a buffer is shown in FIG. 3b; it comprises a plurality of diodes D6, D7, D8, the cathodes of which are connected respectively to the input terminals 7, 8, 9 and the anodes of which are connected in parallel to the input of a cathode load stage 11 as well as to one of the terminals of a load resistor 12, the other terminal of which is connected to a source of positive potential (from -I-200 volts). The output terminal of the cathode load stage 11 constitutes the output 10 of the buffer.

   With this assembly, which works like that of FIG. 2b under the action of negative voltages, the presence of such a voltage on any input terminal causes the transmission of an equivalent voltage to the output terminal 10. The effect on this output terminal is appreciably the even, regardless of the number of input terminals receiving energy at a given time.



  As with the assembly of fig. 2b, the number of input terminals can be increased at will as required.



  The symbol in fig. 4a shows the interposition on a conductor 15 of a differentiator network such as that of FIG. 4b, which has a capacitor 13 in series and a resistor 14 which is normally connected to a source of negative potential. The operation of such a differentiator assembly is well known.

   Together with the signals in the form of rectangular pulses normally used in the calculating machine, it ensures the production of a small sharp pulse, or negative top, on the leading edge of each rectangular pulse and of a positive top. on the trailing edge of the same pulse, or again, in the case of: certain inverted or paraphase waveforms which are also used in the. machine and whose pulses are positive, a positive top on the front flank and a negative top on the rear flank.



  The symbol in fig. 5a shows an electronic assembly with abrupt engagement and dis- engagement consisting of a multivibrator with two stability conditions and, for example, by a so-called Eccles-Jordan assembly, as shown in FIG. 5b. Such an assembly will be referred to below as the rocker none.

   This assembly comprises two electronic tubes 16-17, generally of the pentode type, the anode of each of these tubes being connected to the reject grid of the other by direct coupling connections comprising resistors 18-19, of so as to form a conventional flip-flop, in which one of the tubes is always at the cut-off voltage for its anode current, when the other tube is conducting.

   The condition of such an arrangement at any time can be reversed if a negative pulse is applied to the conductive cube at the time in question, for example by means of the latching input terminal 20 at the control gate of the tube 16, or alternatively, by means of the disengagement input terminal 21 to the control grid of the tube 17. The application of a negative pulse to any one of the two tubes, when this tube is at the cut-off voltage of its anode current, a. no effect.

   With the assembly elements described so far, the rocker can be brought to one of its conditions of stability, here referred to as latching, by an input pulse applied to terminal 20 and brought back. to its opposite condition of stability, here referred to as disengaging, by a pulse applied to terminal-21.

   Depending on the condition of the assembly, that is to say depending on whether one or the other of the two tubes is a conductor; the potentials of the discharge grids of the two tubes are at one level or another; these potentials can be collected in the form of output voltages at the output terminals 22-23, through cathode load stages 24-25. With the assembly shown, the application of a negative interlocking pulse to the.

   terminal 20 renders tube 16 non-conductive, so that the potential of its rejection gate drops to negative and the output energy at terminal 22 is also negative, while the output energy at The other terminal 23 is higher and appreciably above the potential of the earth. The change of -on dition of the assembly under the action of a deactivation pulse applied to the terminal 21 makes the tube 17 non-conductive, so that the reject grid of this tube is made more negative and the energy The output power at terminal 23 also becomes negative, meaning that the output energy at terminal 22 rises above the earth potential.



  Instead of switching the circuit first to one, then to the other of its two stability conditions, by means of individual switching on and off pulses applied to the respective input terminals 20 = 21, it is possible to provide, in such an assembly, a common reversal terminal, so that any negative impulse applied to this terminal causes the assembly to pass from the condition of stability in which it is at the moment considered to its other condition of stability. Such an inversion terminal is shown at 26, the terminal 26 being connected by means of diodes D9, D10 to the respective anodes of the two tubes 16-17.



  Referring to the equivalent symbol in fig. 5a, we will notice. the position of the respective interlocking 20 and interlocking keys 21, relative to the common reversing input terminal 26.

   A flip-flop of this type can comprise either individual switching on and off terminals, or a common reversing terminal, or even both of these two devices, and the presence or the absence of the corresponding input terminals on the üymbole will indicate the type of assembly used below.



  . The symbol in fig. 6a shows a phase inverter which produces, at its output terminal 28, a positive pulse waveform with negative reference potential in response to the application, to the input terminal 27, of a waveform negative pulse wave with reference potential immediately above the earth potential and vice versa. A practical embodiment of such an assembly is shown in FIG. 6b.

   Said assembly comprises an electronic amplifier tube 32, the control gate of which is connected to the input terminal 27 and. whose anode output energy collected by means of a potentiometric network of resistors 29-30 is applied to the input of a cathode load stage 31 of which the output terminal constitutes the terminal output 28 of the assembly.

   This symbol is also used to represent the roughly equivalent device used in machine technology to be calculated as a device for indicating the absence of pulses, hereinafter referred to as indication inverter by means of which an output pulse is obtained in any digit interval during which: no input pulse is applied, while conversely no output pulse is obtained when an input pulse is present.



  Fig. 7a represents the symbol of a positive delay device by means of which any signal arriving at input terminal 33 during any one of the digit periods of a group of periods p0 to p19 form a signal representing a number is delayed, so as to appear at the output terminal 34 only during the immediately following digit period of such a group. Thus, a pulse arriving during the digit period p0 comes out <B> - </B> of.

         mounting 'during the period p1, while:' an impulse arriving during the digit period. p19 will exit during period p0 from the immediately following group. The corresponding practical assembly (fig. 7b) comprises a first electronic tube 35, the control gate of which is supplied from the input terminal 33 via a differentiator comprising a capacitor 36, a resistor 37. and a diode D11, said control grid also being connected to the earthed cathode via a capacitor 38 and, on the other hand;

   via a diode <I> D12 </I> to a source of negative pulses (lines) [fig. 11 (a)] each appearing for a digit period. The anode of the tube 35 is coupled by a capacitor 39 and a diode D13 to the control grid of a second tube 40 which is arranged in a similar manner, a capacitor 41 being interposed between its control grid and its control grid. cathode, and its control grid being supplied, via a diode D14 and the.

   release terminal 44, from a source of positive pulses (pause) [fig. 11 (b)] which occur during each number period with the exception of periods p20 to p23. The anode output energy of the tube 40 is collected at the output terminal 34 through a potentiometric network of resistors 42-43.



  The operation of this assembly is as follows: The tube 35 is made conductive by the positive top of the rear flank of an input pulse applied to the assembly and remains in this condition, due to the fact that the capacitor 38 is charged, until that the falling leading edge of the line pulse of the next digit period, arriving via diode D12, again brings the tube to the cut-off voltage of its anode current.

   The potential rise which occurs on the anode of tube 35 at this instant is applied through diode D13 to tube 40 which it makes conductive, and this condition persists, due to capacitor 41 is charged, until the trailing edge of the pause pulse of the same digit period, applied through the diode D14, again brings the tube 40 to the cut-off voltage of its current d 'anode.



  Fig. 8a is the symbol of an adder device, while FIG. 8b schematically shows an embodiment of such an assembly. Such a device is well known, so that it does not seem necessary to describe it here in detail, given that its mode of operation can be easily understood from the description given above of the assemblies it comprises and which are shown in fig. 8b by symbols already defined.

   The adder device comprises two input terminals 45 and 46, an output terminal 47 as well as a disengagement terminal 48 intended to supply the pulses of the pause waveform necessary to supply the delay assembly that comprises. the device. By virtue of the incorporation of such a delay assembly controlled by pulses, the adder assembly is able to transfer the intermediate digit periods p20 to p23 between: two adjacent groups of digit periods each representing a number.



  Fig. 9a represents the symbol of a similar subtractor assembly. to the preceding one and comprising two input terminals 49-50, an output terminal 51 and a disengagement terminal 52. One embodiment of such a subtractor assembly is shown in FIG. 9b.



  Fig. 13 represents; schematically the generator block of waveforms hereinafter called WGÜ waves (fig. 1).

   The base digit period, the duration of which is ten microseconds, is determined by a pilot oscillator, or time center, at 100 kilocycles, C0, whose output energy is applied to a rectifier assembly of asymmetric pulses. , DWG, which provides the line wave [fig. 11 (a)] which comprises a negative impulse with respect to a reference potential situated immediately above the potential of the earth during the first six microseconds of each period number.

   An inverted version of - this wave, known as the pause wave [fig. 11 (b)], has a negative reference potential and rises above the earth's potential for the first six mi- .croseconds of each digit period. This wave is supplied by means of a phase inverter 53. The pause pulses during the digit periods p20 to p23 are suppressed by passing the output energy of the phase inverter 53 through a window. G20 which is controlled by an INV BO wave described later.

   The output energy @ from the DWG assembly <I> is </I> also applied to a generator assembly of tangular DTG pulses of the monostable multivibrator type which serves to supply the wave of points mentioned in the aforementioned references. The same output energy from the DWG assembly is further applied to another SPG rectangular pulse generator assembly which provides a strobe examination wave also mentioned in the aforementioned references.

   The output energy from the DWG assembly is further applied as switch-on energy to a PDV pulse number divider which is used to count the input pulses applied and gives an output pulse every twenty-four pulses. 'Entrance. This assembly can comprise, for example,: two dividers of the phantastron type mounted in series.

   Each of the õr tie pulses from the PDV divider assembly is applied as an initial switch-on pulse to a PPG pulse selector assembly which has a series of twenty-four combined PO-P23 counters and tumblers, the first stage in the chain being P20 and the last being P19.

   These counter-bascale stages comprise a counter - normally closed, but kept open for a limited time, after the application to the flip-flop of a starting pulse which precedes in time the application of a pulse subjected to the control window, the rocker being disengaged immediately after the passage of this last impulse.

   A device of this type is described in patent No. 280880 in the name of: National Research Development Corporation. Each rocker, with the exception of that: of P19, is connected to the. immediately following flip-flop and applies a starting pulse thereto and, moreover, each flip-flop, including P20, is also connected to the immediately preceding circuit to which it applies a deactivation pulse. In addition, the various counters are all supplied by the draft wave [fig. 11 (a)] from DWG assembly,

      so that the first stroke pulse which follows the arrival of a starting pulse from the PDV pulse number divider can pass through assembly P20 which then initiates assembly P21 and is then disengaged, from so that the P21 assembly allows the immediately following stroke pulse to pass to its output terminal and so on.

   In this way, each of the individual output connections of the PO assemblies P20 transmits only one stroke pulse, which always coincides in time with the same digit period: The first pulse p0, shown in fig. 11 '(d), thus coincides with the digit period p0, the, second pulse, pl, shown in fig. 11 (e), coincides with the second digit period pl, and so on. The last pulse in the series, p19, is shown in fig. 11 (f).



  The output pulses of stages P20 and PO of the PPG pulse selector assembly are used respectively as switching on and off pulses for a BOWG flip-flop which supplies the obfuscation wave BO of FIG. 11 (c), which has a negative pulse extending over the digit periods p20 to p23. An inverted version of this BO wave controls gate G20 controlling the previously mentioned pause wave. This BO wave thus effectively marks each beat of the rhythm of the machine and is therefore used for a number of other control operations as a function of time.

    



  The beginning of each active major cycle is determined by the transmission of a signal called bar of measurement [fig: 12 (a)], which is obtained either by manual control by means of a KifIP switch, when a single cycle of operation is necessary, either automatically, so that it immediately follows the end of the previous measure, regardless of the number of beats thereof.

   The measuring bar pulse generator devices include a G40 window which receives the BO wave and which is controlled by a flip-flop F1, so that it is open when this flip-flop is engaged, and by another 7S wave. which is at a negative active potential level. The differentiated falling edge of the BO wave thus forms, at each period p20, a measuring bar signal.

   The flip-flop F1 is deactivated at the start of each time by the application of the pulse p0, but it can be triggered again by a pulse p1 arriving via the gates G41 and G42 in series.

   The G41 counter is controlled by the INV waves <I> S1, </I> INV A1 and INV <I> S2 re- </I> shown respectively in fig. 12 (c), 12 (e) and 12 (g), the formation of which is described later, as well as by the combination of the INV A2 wave of FIG. 12 <i> (i) </I> and a 5 / 7B (5/7 beats) code signal wave derived from a machine order involving the prolongation of a measurement. Thus, in the normal four-beat rhythm, window G41 is only open during the time A2 of each measure.

   The counter G42 ′ is kept open permanently by the potential applied by means of the switch S1 from a flip-flop F2, when the latter is in the disengaged state. According to a variant, the gui chet G42 can be opened by a potential present when the switch KDIP is closed.

    Consequently, a pulse pl normally passes through the counters G41 and G42 to switch on the flip-flop F1 during the last time, A2, of a measurement, and this allows the immediately following pulse BO to determine the emission .d 'a measuring bar pulse and, consequently, to trigger a new active measurement.



  The times previously described (each measure is made up of it are defined separately by waves designated respectively by S1, <I> A1, S2, </I> A2 for a four-beat measure and by additional A3, S3 and B4 waves for extended five or seven-beat measures. These waves and their inverted counterparts are shown in FIGS. 12 (b) to 12 (o). These waves identifying the times are obtained as follows: Each bar signal is applied to a flip-flop F3 and switches it on at the beginning of a determined time and said flip-flop remains in this state until it or deactivated by the differentiated BO waveform at the end of the time considered.

   This then constitutes the first time of the measurement and the output energies of this latch constitute the waves Sl and INV <I> S1. </I> The negative trailing edge of the INV wave <I> S1 </I> is used, after differentiation, to engage a second flip-flop F4 which is likewise disengaged by the BO wave at the end of the second time following a bar pulse. This latch supplies the waves A1 and INV A1.

   In an analogous manner, a flip-flop F5 is engaged by the wave INV A1 and disengaged by the wave BO at the end of the third time after a bar pulse, to supply the waves S2 and INV <I> S2, </I> and a fourth F6 flip-flop is triggered by the INV wave <I> S2 </I> and released by the BO wave at the end of the fourth beat after a bar pulse, to supply the A2 and INV A2 waves.

   These four flip-flops are the only ones which are normally active in the four-stroke operation, but if it is necessary to use measures comprising a greater number of times, this prolongation is determined by the particular composition of the signal-order. This composition gives rise to the signal wave of code 5 / 7B (five or seven beat measurement) and opens the electronic window G50 which uses the INV A2 wave to engage a flip-flop F7. This is disengaged by the immediately following B0 wave at the end of the fifth beat after a bar pulse,

      so as to produce the A3 and INV A3 waves. As in the previous assemblies, the wave INV A3, whenever it is present, engages the flip-flop F8 which is disengaged by the BO wave at the end of the sixth beat after a bar pulse, to provide the waves <B> 83 </B> and INV <I> S3, </I> and the latter is then used to engage a flip-flop F9 which is disengaged by the following pulse BO at the end of the seventh beat after a bar signal,

   so as to provide the B4 and INV waves <I> B4. </I> The 5 / 7B code signal present at this time causes the. closing of the G41 window, so that the flip flop F1 does not receive the pulse p1 during the time A2, but remains disengaged. The generation of another bar signal is thus prevented until the fifth time A3 is completed, when the extraction of the command signal from a dynamicostatic converter element of the control system , extraction which determines the appearance of the signal 5 / 7B,

   again allows opening of the G41 window which can then let the following available pulse p1 pass to the flip-flop Fl. As will be understood later, the times S3 and B4 of a given measurement can overlap the times S1 and A1 of the immediately following measure, so that it is not essential to delay the appearance of the next bar pulse until the end of time B4.



  Apart from those described above, a number of additional control waves are used more specifically during the multiplication process. These waves will be described later.



  The main store <B> JUICE </B> uses a total of sixteen tube storage devices. cathode beams arranged and arranged in the manner described in the aforementioned reference A, while the general organization and the mode of operation of the whole of this store are as described in reference B; the selection of the desired tube is carried out by means of the numbers e <I> (p6 p9) </I> of the signal-order and the selection of the desired storage line of this tube being effected by means of the digits l (p0 p5) of said signal-order.

   Due to the full descriptions which have been given in the references in question, the main store will not be described in detail here. We will be satisfied with indicating that its reading terminal is connected to a conductor 200 of FIG. 10a.



  The command block <I> CL </I> is shown schematically in fig. 15. Its construction and mode of operation are very similar to those which have been described in reference B.

   It essentially comprises a storage device comprising a cathode-ray tube exploring two storage lines of twenty digits, each denoted respectively under the name of lines. <I> CI </I> and <I> PI, </I> under the command of a. vertical deflection potential provided by a wave generator 69, which is itself controlled by different waves including S2 and A1, as shown.

   The generator 69 can be considered as causing the exploration of the line CI permanently, except when it receives a negative control voltage, at which point it causes the exploration of the. line <I> PI. </I> Accordingly, the line <I> PI </I> is explored during times A1 and S2 of a given measurement and the line CI during the other times of this measurement.

   The XTB wave is applied in the usual way to the horizontal deflection plates, so as to produce a linear exploration movement of the beam on any chosen line in syn chronism with the time of the rhythm of the machine, the sudden return of the beam to its initial position occurring during the period of the pulse B0.



  The device comprises the signal pick-up plate 61 whose output energy is applied to an amplifier 62 which in turn transmits signals to a read element 63 of the conventional type, as described in references A and B aforementioned.

   The output energy of the reading element 63 supplies one of the input terminals 66 of an adder assembly 64: the other input terminal 67 of which is supplied by means of 'a counter G21 and a conductor 70, from the main store 1311S and further receives, via a counter G22, the pulse p0. Gate G21 is controlled by wave A1, so that it opens during time A1; Likewise, the G22 counter is open during the time <B> 81 </B> by the S1 wave.

    An output terminal 68 of the adder assembly 64 is connected to the input terminal of the registration element 65 of the storage device as well as a conductor 72 also connected to a main dynamicostatic converter DISTR ( fig. 14). Means comprising, in particular, the wave A1 are also intended to apply a negative erasure voltage to the reading element 63 during each time A1, so as to erase, on the line PI, all any previously recorded signals.



  The elements of the dynamico-static converter 1VISTR are shown in fig. 14. This device comprises a total of twenty F40-P59 flip flops.



  Flip-flops F40 F45, the function of which is to convert from dynamic form to static form the first six digits or digits 1 of a given signal-order, receive wind, via the conductor 72 and the G30 counter, - signals from the control unit <I> CL, </I> the input circuit of each of said flip-flops passing through one of the counters G60 to G65 which are respectively controlled by the pulses p0 to p5, so that each signal comprising a pulse corresponding to the number 1 present in the corresponding digit periods of a given command signal, brings the interested flip-flop to its engaged condition, i.e. during time S1,

   or during the time S2 of any measurement, when the window G30 is opened by the waveforms S1 and S2 which control it. When engaged, any flip-flop gives, on its left output terminal, a negative voltage which is used to control the vertical deflection wave generator which is part of the address selector means in the main store. <I> DIS </I> as described in detail in reference A.

   These six flip-flops have their right output terminal, or terminal <B> 4, </B> connected through a. differentiating assembly to the inversion terminal of the following latch, so that the whole constitutes a binary counting chain. The inversion terminal of the first flip-flop F40 receives the wave A3. Each time a measurement has a time A3, the indication of the counter chain at the time in question is automatically increased by one.

   Each of the flip-flops F40 to F45 is disengaged by the waves S1 or S2 combined in the buffer B75. Thus, the switching off takes place immediately before the flip-flops are actuated again by a command signal.



  The flip-flops F46 to F49 are supplied with the same signals arriving by the gui chet G30 via individual counters G66 to G69 respectively controlled by the pulses p6 to p9; these flip-flops operate in an analogous manner in response to the pulses present at the digit positions p6 to p9 of a command signal and establish a combination of output potentials which, by acting on the obscuration tube associated with each of the different storage tubes of the main store 111S in the manner described in reference B, ensures the darkening of all the tubes, except one, the selected tube, so that only this one is active during the time d active exploration next.

   These flip-flops are not mounted in a counting chain, but they are nevertheless disengaged by the waveforms S1 and S2.



  The flip-flops F50 to F52 operate in a general analogous manner, but as they do not concern the multiplication operation, they are not represented and will not be described here.



  The other flip-flops F53 to F59 are used to convert from dynamic form to static form the digits f of the PI command signal available during time S2 and are, in sequence, each supplied to this signal from the conductor 72 through the counter G31 and individual counters G73 to G79 controlled respectively by the pulse waves p13 to p19. Window 031 -is controlled by wave E2 alone, so that it opens only during time S2 of each measurement.

   Each of the flip-flops is disengaged by the decreasing edge of the INV wave <I> A1 </I> which always appears immediately before the instant the fixtures are about to be operated.



       The various rockers are mounted in the manner described in detail with regard to FIG. 15 of the. reference B and provide at least two variants of output potentials, one of which (called potential 1) is negative when the corresponding flip-flop is engaged. and to the earth potential when said assembly is disengaged, and the other of which (called the 0 potential) is negative when the assembly is disengaged and to the earth potential when it is engaged.

   A selection of these flip-flop output potentials is used to actuate counters or other arrangements directly or selectively to influence a decoder tube (fig. 19).



  Although the total number of signal-order combinations different from the digits f, p13 to p19 is very high, only the six orders directly concerned with the multiplication and which, to facilitate the multiplication, will be taken into consideration here. description, will be supposed to use the digits p13, p14, p15 and p16 of the signal-order.

   These six orders are: Order D, of which there are two variants: sD - (1.0.0.0.) Which indicates that the multiplication D is to be transferred from the main store MS to the multiplier assembly and that this number is present in the arithmetic form (without sign) and if.D - (1010) which also indicates a transfer of the number D, but this one being algebraic (that is to say affected by a sign).



  The order R, of which there are four variants: sR - (0100) which determines the transfer of the multiplier R from the main store 111S. To the multiplier assembly, then continues the process of multiplication by adding the resulting product in l accumulator A and indicates that the number R is in arithmetic form. st.R - (0110) which is identical to s. $, except that the number R is algebraic.



       -sR - (0101) which is identical to sR, except that the product must be subtracted from the existing content of accumulator A instead of being added to this content, and -si.R - (0111 ) which is identical to s1.R, except that a subtraction must be performed in accumulator A instead of an addition.



  We will now consider figs. 10a, 10b and 10c.



  Said multiplier device comprises a special storage tube 111T, of which a reading element lYIRU and a recording element MWU are interposed in the usual closed regeneration circuit between a signal pick-up plate 81 and a modulating electrode of beam 82.

   The MRU reading element is arranged so as to be able to be blocked by erase voltages applied to the input tube of this element, said erasure voltages comprising either a potential KIIl% drawn from a switch which can be actuated. by hand, used to erase all the contents of the machine and that it is not necessary to describe here in more detail, i.e. the output energy of a G114 window which receives, on the one hand, the waves A2 @ and A3 via buffer B1,

    and, on the other hand, a control signal coming from the dynamicostatic converter MSTR and which is active during and only during the duration of any code signal comprising the digits f of a combination-command and indicating an operation of multiplication and which., in the example shown, is preferably obtained by combining the output potentials (1) of the flip-flops F53 and F54 in a buffer, whereby, when any one of said flip-flops is engaged ,

   the necessary code signal is applied to the G114 counter. Thus, an erasure potential is always applied to the tube <I> MT </I> during times A2 and A3 of any active measure of a multiplication. The MT tube is arranged so as to be able to store on any one conch of four distinct and parallel lines each having a capacity of twenty digits, the,

   line active during a given time being determined by the vertical deflection wave applied to the vertical deflection plates of the tube from a MYG generator described in detail below with reference to the, fig. 18 and which is controlled by the setting of two flip-flops F31 and F32 mentioned later.

   As it emerged clearly from the description below, the 31T tube explores the four lines <I> d0, d1, r0 </I> and r1. In a variable order according to the indications of the time program in fig. 12 during the various successive times of the measures assigned to the execution either of the order D or of the order R of a multiplication operation.



  Entrance to the storage tube <I> MT </I> is carried out by a conductor 206 and is always obtained from the terminal: of output of the reading of the main store MS by the conductor 200 and the counter G113 which comprises two command input energies. One of the latter consists of the A2 -and A3 waves combined in the buffer B2 and the other consists of a code signal similar to that which is used for the gui chet 6114, said signal being active during the presence of any order involving a multiplication operation. This code signal can be drawn from the same source as that which is applied to the G114 gate.



  Two output circuits are possible from the storage tube <I> MT. </I> The first of these circuits passes through conductor 201 and crosses gate G115 which comprises only one control input energy, which is constituted by the S2 -and S5 waves combined in the buffer. B3: The signal present on the conductor 201 is applied to twenty identical counters GO to G19 which each comprise a single control input terminal, the terminals of said counters respectively receiving the pulse waveforms p0 to p19 , so that the counters are opened successively at the rate of one for each digit period of a given time.

   The output energy of the first GO gate constitutes a latching input signal, for the first of twenty identical bistable flip-flops WO to W19, the latching input terminals of the other nineteen flip-flops also receiving, respectively, the output energies of the associated counters G1 to G19.

   These flip-flops then constitute a second dynamicostatic converter which transforms the dynamic pulse train present on the conductor 201 into a series of static potentials identifying the pulses present in each of the digit periods of said train.

   This dynamic converter MTR of the multiplier assembly can, in practice, also be used as a converter for other functions in the.

   machine and, for example, those which deal with magnetic order combinations involved in transfers between the main ma gasin <B> 1118 </B> and an auxiliary storage magnet drum. Each of the flip-flops WO to W19 is disengaged by the output energy coming from the gate G117 (fig. 10c) which comprises two control input energies, one being the pulse wave p20 and the the other being the output energy of a buffer B4, which receives, on one of its input terminals, the wave S2 and, on its other input terminal,

   the output energy of an inverter assembly INV2 or the output energy of the G129 window combined in a buffer B5. The inverter INV2 receives the wave INV <I> S5 </I> and, in addition, via a buffer B6, the output energy of an inverter assembly INV3, itself supplied by an active code signal during each of the four orders R and which can, consequently, be constituted by the output potential (1) of the flip-flop F54 (fig. 14)

   of the main dynamic converter MSTR. The output energy of this inverter assembly INV3 constitutes the input energy for controlling the gui chet G129 to which the wave A2 is applied.



  The second output circuit of the storage tube lYIT is formed by the conductor 203 connected to the counter G137 which comprises a single control input energy coming from an INVI inverter assembly which receives its input energy. a buffer B8 itself having two input energies, one consisting of an INV 1VIG wave and the other by an MCd wave mentioned below.

    The output energy of the G137 gate is applied to the signal input terminal of a CCV complement converter, the arrangement of which is described in detail in connection with fig. 16.

   The operation of this complement converter is controlled by the output energy of a G127 window, which comprises three control input energies, one consisting of the potential drawn from the output terminal (1). flip-flop F55 of the main dynamicostatic converter 11′lSTR which processes the digit <B> f15, </B> the second constituted by the MG wave. [fig. 12 (q)

  j and the third consisting of the lllCd and HCm waves [fig. 12 <I> (r) </I> and 12 (s)] combined in a B9 buffer. In practice, the complement converter is normally at rest and passes the applied signals directly from its input terminal to its output terminal, without modifying their shape.

   When activated by the control potential coming from the G127 counter, this converter extends the input signal representing a forty-digit number and transforms it into an eighty-digit number by examining the digits of the units of the highest order of the input signal applied to it and reproducing forty times that digit (1 or 0 as appropriate) in all remaining digit periods of the number.



  The output energy from the CCV complement converter present on a conductor 205 is applied to twenty identical counters, G200 to G219 (fig. 10b), each comprising a single control input terminal, the terminals of the twenty. counters receiving respectively the output potentials (1)

   flip-flops WO to W19 of the second dynamicostatic converter 11ITR. The output energy of each of the counters G200 to G218 constitutes one of the input energies of one of the adding devices ADO to AD18, while the output energy of the gate 6219 is applied.

      at the input terminal of a positive device transforming a number into its complement, hereinafter referred to as the number / complement converter <I> 0D20 </I> described in more detail in connection with fig. 17.



  The output energy of the number / complement CDV converter is applied to a delay device <I> DL19 </I> described later with reference to fig. 7b. The output energy of this delay device <I> DL19 </I> constitutes the second input energy of the AD18 additive device. The output energy thereof is applied to a second delay device <I> DL18 </I> whose output energy is, in turn, applied to an adder device <I> AD17 </I> of which it constitutes the second input energy and so on,

   the output terminal of the first adder device ADO constituting the output terminal of the signals representing the sum towards the conductor 202. The disengagement signals necessary for the operation of the various delay and adder devices are supplied by the wave INV pause [fig. 11 <I> (b)] </I> applied through a wave controlled G80 gate <I>. Dl G. </I>



  The number / complement converter CDV is normally at rest, i.e. it passes the input signals applied to it to the output terminal, without modifying their shape, but, when it is made active by the presence on its control conductor 135 of a suitable positive potential, it transforms the signals representing a number which are applied into signals representing the complement of this number.

   The control potential present on the conductor 135 is obtained from a plurality of sources comprising the wave INV 31G and the output potential 0 of a flip-flop F34, that is to say the potential that is gets at the output of this flip-flop when it is disengaged. The flip-flop F34 is arranged in such a way that it is engaged by the output energy of a G130 gate and disengaged by that of a G131 gate.

   Each of these counters receives the A2 wave which constitutes one of their key command input energies, the second command input energy of gate G130 being a code signal resulting from the setting of the dynamieostatic converter IIISTR of the store. main by a function signal si.D and the G131 gate being controlled by the setting of said dynamicostatic converter by a function signal sD Another source of control signals for the number / complement converter <RTI

   ID = "0016.0039"> ment CDV is obtained from an inverter assembly INV4 receiving, via another inverter INV5, a code signal in response to the application of any one of the four R codes to the dynamico-static converter. lVSTR. Yet another source of control potential is obtained by means of the buffer B10 from the output terminal of a gate G202, which comprises five control input energies constituted respectively by the INV waves. <I> A2,

   </I> INV <I> A3, </I> INV <I> S3, </I> INV <I> B4, </I> INV <I> S5. </I>



  The control energies of the DIYG vertical deflection wave generator of the DIT storage tube are obtained from two flip-flops F31 and F32 which, one, supply the MCZ and MCin waves [fig. 12 (s)] -and the other, MCd waves [fig. 12 <I> (r)] </I> and! 1'10r. The flip-flop F31 permanently receives an inversion energy constituted by the wave B0,

   so that its state is always reversed at the end of each beat. This flip-flop receives, in addition, a switching input energy which can be constituted either by the wave S2, or by the output energy of a G121 gate, or even of that of a G118 gate. The G121 window receives the A2 wave and is controlled by the dynamicostatic converter DISTR, so that it is active, that is to say open,

   when the order concerned includes any s.R code signal. The G118 window also receives the A2 wave and is controlled by the dynamicostatic converter DISTR, so that it is active during any one of the D orders.



  The second flip-flop F32 permanently receives an inversion energy constituted by the output wave MCl differentiated from flip-flop F31 and, as switching means, either the S2 wave, or the output energy of the G118 window. , or again the wave S5 coming from the flip-flop F35. The same wave <B> 85 </B> is applied as disengagement input energy to flip-flop F31,

      while the output energy of the G121 gate constitutes a similar disengaging input energy for the F32 flip-flop.



  The F35 rocker gives rise to the S5 wave [fig. 12 (p)] and reviews, as a triggering means, the output energy of a G200 gate to which the INV wave is applied <I> B4 </I> and which comprises a single control input energy from the dynamic converter MSTR, said window being active whenever any signal of code R is contained in an order.

   This F35 flip-flop is disengaged by the differentiated BO wave. Another F33 flip-flop provides the IIIG and INV waves <I> MG. </I> The engagement input terminal of this flip-flop receives either a differentiated version of the INV S5 wave, or the output energy of a G201 gate which receives the A2 wave and of which the command input energy is active when an order present in the dynamicostatic converter MSTR includes any sR code.

   This latch is disengaged by the AYCm wave.



       Accumulator A comprises a cathode beam storage tube AT (fig. 10c) associated with a reading element ARU and an inscription element AWU as mounted between a signal pick-up plate 91 and a beam modulator electrode 92 of the tube. These reading and writing elements are incorporated into the closed regeneration circuit which can be used either through the G106 gate which provides a direct interconnection, or through an adder element AU, or even by the 'intermediary of a subtractor element SU.

   The selection between these three elements determines which of them is to establish the closed regeneration circuit and is controlled from the dynamic converter MSTR, according to the combination of particular function digits of the order concerned applied to that converter. The control potentials are supplied respectively through the conductors 93, 94 and 95.

   One of the input terminals of each of: two elements, AU adder and subtractor <I> SU, </I> is connected to conductor 202 coming from the store <I> MT </I> of the multiplier assembly, while a reading output conductor 96 and. a usual writing input conductor 97 are also fixed in the store of the accumulator with a view to the interconnection of this device with other parts of the machine which are neither shown nor described here.



  The accumulator tube receives the usual horizon tal scan time base waveform XTB for providing line scanning movement of the beam and is arranged to have four storage lines a0. , a1, a2 and a3 respectively receiving the four twenty-digit segments of a number <B> - </B> Eighty digits sorted by increasing values of unit orders.



  The beam deflection to selectively determine the exploration of either line is provided by a vertical deflection potential applied to the vertical deflection plates of the tube by firing an AYG generator which resembles to that which is shown in detail in FIG. 18 and which is controlled by the output potentials provided by two flip-flops AYCO and AYCL The AYCO flip-flop receives the BO waveform on its, inversion input terminal and, moreover, on its release terminal, the differentiated A2 waveform,

   its two output terminals supplying the AYCO and INV AYCO waves respectively. The AYC1 flip-flop receives, on its version input terminal, the differentiated AYCO INV wave and, on its disengagement terminal, the differentiated A2 wave.

   This flip-flop provides the AYC1 and INV AYCL waves on its respective output terminals. The operating mode of the assemblies described is as follows:

   The multiplication operation uses two distinct orders: the order <I> D, </I> in execution of which the multiplicand <I> D </I> which is a forty digit number is taken from the main store <I> DIS </I> and brought to the storage location assigned to it on lines d0 and d1 of the lhfT store of the multiplier device, and the order R,

      whereby the multiplier R which is also a forty-digit number is extracted in an analogous manner from the main store 11IS and brought to the storage location assigned to it on lines r0 and r1 of store 117T and is used to perform the multiplication operation.



  Fig. 12 indicates in the form of a table the different phases of each operation. Although this table indicates the order R as immediately following the order D, this arrangement is not essential and other operations can be carried out by the machine between these two orders.



  Order D is selected by the command block <I> CL </I> during the normal operating process of the machine, as described above as well as in the patent descriptions cited above and in the. reference B. The first step, S1,

   of an active measurement assigned to the order D causes the usual transformation of the command order signal <I> CI </I> stored on the line <I> CI </I> from the storage tube to the command block <I> CL </I> by transforming this signal into a new signal CI --I- 1 and applying this new signal to the sections <B> 10 </B> to <B> 15 </B> and e6 to e9 of the main dynamicostatic converter DISTR (fig. 14),

   so as to prepare this to take over control of the vertical deflection waveform generator which controls the address selector mechanism in the main store DIS during the following time A1, thereby determining the selection the storage location of this main store to which the D.

   During the following time A1, this order is extracted from the main store DIS by the driver 70 (fig. 15) and through the counter G21 to be applied to the line <I> PI </I> of the store of the control block from where it is transferred during the third time S2 by the driver 72 to the main dynamicostatic converter DISTR and determines a new setting of the address selection sections in the store main of this converter, so that it selects the storage location of the first half of the number D;

   at the same time, the order D regulates the control sections -defunction or f of the main dynamicostatic converter DISTR according to the particular operation D envisaged.



  During the fourth step, A2, of the measurement, the aforementioned number D is extracted from the main store DIS by the counter G113 (FIG. 10a) then opened by the presence of a code signal M and the simultaneous application of the wave A2, to be transmitted to the inscription element 111WU of the storage tube liIT of the multiplier assembly, so as to cause the inscription therein of the twenty digits thus extracted.

   This first segment of twenty digits of the number D is inscribed on line d0 belonging to the four storage lines available on the storage tube DIT, thanks to the excitation of the DIYG vertical deflection wave generator by the waves of output 111C1 and IZC'd coming respectively from the two control flip-flops F31 and F32 which, to cause the exploration of this line d0, are each triggered by the application of the wave A2 through the gate G7.18 opened by the presence is of the order sD,

      or of the order s1-D.



  The active measurement assigned to this order D is automatically extended, so as to include a fifth time A3 due to the existence of a time code 517 which opens the window G50 (fig. 13) and allows the operation of the flip-flop P7, so as to produce wave A3.

   During this fifth step, the setting of those of the sections (F40-P45) of the IISTR main dynamicostatic converter which control the address selector mechanism in the main magazine is automatically increased by one due to the application of wave A3 at the inversion input terminal of the first flip-flop F40 thus determining the selection of the address or location: of storage of the second segment of twenty digits of the number D.

   Said second slice of twenty digits is then extracted by the conductor 200 via: the counter G113 (which is still kept open, this time, by the wave A3) _ and applied to the writing element MWU of the storage tube 111T. Simultaneously, the pulse BO which appears at the beginning of time A3 has disengaged the first flip-flop I'31, so that the influence of this and of the second flip-flop F32 on the vertical deflection wave generator D1YG then initiates the exploration:

  of the second line d1 of the storage tube <I> MT; </I> the second half of the number D is then stored on said line d1.



  To ensure the erasure of any previous indication on the d0 or d1 lines of the storage tube <B> AIT, </B> waves A2 and A3 are applied simultaneously through the open G114 window in response to the application of any of the multiplication codes.



  Simultaneously, during the time A2 of this measurement assigned to the operations on D, the flip-flop F34 is set to one or the other of its two stability conditions depending on the nature of the order D to be executed. The purpose of this provision is to keep the indication of the nature of the number D (arithmetic or algebraic) with a view to its subsequent use during: the associated measurement assigned to operations on R.

   We have it. carries out by applying the wave A2 either through the open window G130 (fig. 10b) _ in the presence of an order si.D (indicating that it is an algebraic multiplication) to trigger the engagement flip-flop F34, or by applying the same wave A2 through gate G131 which is only open in the presence of an order sD (indicating that the multiplicand is arithmetical) to cause the,

  disengagement of rocker F34. This then supplies a selected control potential to the number / complement converter device CDV in a manner described below.



  During the subsequent R order (which does not necessarily immediately follow the D order), the active measure is extended and comprises a total of eleven consecutive beats, as shown in fig. 12. The last two beats of this measure may, if necessary, be confused with the first two beats of the immediately following active measure.



  During the first time, S1, of the active measurement assigned to the order R, the command block <I> CL </I> has its number <I> CI </I> automatically transformed in the usual way into <I> CI </I> -I- 1, and this number is applied to the converter.: Main dynamicostatic MSTR so as to set the address selection sections in the main store (F40 to F49) of said converter, so that they select the storage location of the next order <I> (PI) </I> which is the desired R order, This R order is taken from the main store.

    1118 and transmitted to the, line <I> PI </I> from the command block store over the next time, A1, then this command is transmitted; during the next time, 82, to the main dynamicostatic converter DISTR to adjust the select sections of addresses in the main store according to the address: of the desired number R in the main store. MS and to control the various function sections of this converter in response to any of the four R code signals.



  At the end of time S2, the main dynamicostatic converter DISTR is therefore adjusted: so as to select the desired number R in the main store <I> DIS </I> and to supply the necessary R code signal chosen from among the four possible codes, so as to control the various counters and similar devices.

   During the third step, S2, the G115 window (fig. 10a) is opened by the presence of the S2 wave, so that the application of the same S2 wave to each of the F31 and P32 flip-flops maintains them. in engaged condition, that is to say in:

  condition which regulates the generator 31YG so as to determine the exploration of the line d0 in the storage tube 31T, on which line has been previously recorded the first slice of twenty digits of the number D, so that at during this time S2, said first segment of twenty digits is extracted from the storage tube <I> MT </I> by conductor 201 to be applied to each of the twenty sections of the dynamicostatic converter MTR.



       Rockers W0, Wl ... W19 (fig. 10c) control the associated counters G200 ... G219 (fig. 10b) in such a way that each of these counters is open if the corresponding latch has been activated by the application of a signal corresponding to digit 1 and closed if the corresponding rocker has remained disengaged due to the presence of a signal corresponding to digit 0.

   So that the various sections of the dynamicostatic converter MTR are brought back to the rest position from any previous engagement condition in which they may be found, said sections are supplied in parallel, via the G117 switch (fig. 10c). ), by a certain number of disengaging energies which will be described later.

   We can, however, already indicate that one of these energies is the S2 wave passed through the G117 gate during the interval of the p20 pulse which occurs during the darkening period. , at the very beginning of time 82 and immediately before the application of the first portion of the number D, as described above.



  During the immediately following time, A2, the first twenty-digit slice of the number R is extracted from the main store MS through the intermediary of the conductor 200 and the counter G113, which is opened again as a result of the presence of a signal of code M and the simultaneous application of the wave A2, from there, this slice is applied to the inscription element IlIWU of the storage tube <I> MT </I> and, simultaneously, at counter G137.



  We will first consider the operation of the storage tube. <I> MT. </I> The flip-flop P31 is engaged and the flip-flop F32 is disengaged by the application of the waveform A2 to the gate G121 opened by the presence of any one of the four signals; code R.

   In this configuration of the two flip-flops, the third line, r0, of the tube @ d ', em- ma.gasina.ge 111T is explored during the time A2 and, consequently, the first slice of twenty digits applied of the number R is written on said store line.

   As in the previous operation D, the waveform A2 is also applied to the G114 window, which is opened by the presence of a code signal <B> 31 </B> to act as erase control energy preventing the operation of the reading element MRU and thus removing any number previously stored on said line r0 of the tube <I> MT. </I>



  The counter G137 (fig. 10a) is controlled by the intermediary of the inverter INV1 by the waves INV JIIG and ITTCd combined in the buffer B8 and, as these two waves are, at the instant considered, at their potential level. the highest, the output energy of the inverter INV1 is negative and determines the opening of the counter G137, so that the first twenty-digit slice of the number R, in folds of its inscription in the store <I> MT </I> of the multiplier set is,

   in addition., applied via the CCV complement converter to the input terminals of each of the counters. <B> G200 </B> to G219 (fig.10b).



  Depending on whether these latter counters are open or closed, as indicated above, that is to say depending on the nature of the. first slice of the number D, the whole of the first slice of twenty digits of the number R -is applied or not - to one of the inputs of each of the associated adder assemblies ADO, AD1 ...

   AD18 and the CDV number / complement transformer. As described in more detail in patent N 292118 in the name of the proprietor, this set of counters controlled by the values of the digits of the multiplicand, the associated additive assemblies and the delay devices of a unit which interconnect them, ensures the production on the conductor 202 of a signal expressed in the form of a sequential train of pulses and representing the product of the applied slices of the multiplicand D and of the multiplier R.

    At the end of time A2, the first twenty-digit segment of the multiplier R has been applied to each of the adder assemblies and the first twenty digits of the partial product have been transmitted from the adder assembly ADO to conductor 202.

   Another succession of twenty digit intervals is necessary to take into account the extension of the length of this partial product, since the .last digit of the first portion of the number R applied through the window G219 comes only, at the at the moment considered, to start traversing the chain and will not reach the conductor 202 until after twenty additional digit intervals.

   At the end of this time A2, the address selector mechanism of the main store <B> JUICE </B> is activated automatically as in the previous operation D, so that it selects the address: from the second twenty-digit range of the number R which is then in turn extracted from the main store <B> JUICE </B> by the G113 window which is still open to be applied to the MT tube and to the G137 gniichet.

   The tube <I> MT </I> is then set to explore the fourth line r1 as a result of the actuation of the. first rocker I'31 by pulse BO which takes place at the start of time A3, so that said second portion of twenty digits R is stored on said fourth line r1. At the same time, this second segment of twenty digits crosses, like the first, the counter G137 which is still open, and, from there, through the CCV supplement converter, it is applied to each of the counters G200 to G219. which have remained regulated according to the nature of the first twenty digits of the number D,

   since the configuration of the WO ... W19 flip-flops has not been changed. These twenty other digits take the continuation of the first twenty: digits of the number R by extending the operation of the multiplier assembly formed by the G200 counters ...

   G219, ADO ... AD18 adder stages and DL6 delay elements <I> ... </I> DL19, so that the resulting sequential pulse train which appears on conductor 202 represents the partial product of the set of forty digits of the number R by the first twenty digits of the number D.

    The train of sixty resulting digit pulses which represents the first sixty digits of the number constituting the final product, which will comprise eighty digits (since it is the result of the product of two numbers of forty digits) is applied by the conductor 202 to the sub-tractor unit <I> SU </I> (fig. 10c) and to the adding element AU of accumulator A.

   Only one of these elements is active at a given moment according to the type of order R being executed and, for the moment, we will assume hereafter that it is the adder element <I> AT </I> which is in use.



  Assuming, furthermore, that the accumulator store does not have any previous digital records, the sixty digits from the adder AU will be the same as those of the input train present on conductor 202 and arrive at the registration element AWU in such an order that the first twenty digits corresponding to the lowest unit orders occur during the time A2; the next twenty digits during the time following A3 and the remaining twenty digits representing the highest unit orders during the time immediately following S3.

    The inscription of these three sections of twenty digits on lines a0, a1 and a2, respectively,: of the storage tube <I> AT, </I> is ensured - as follows:

   Each of the flip-flops AYCO, AYCl is disengaged at the start of time A2 by the application of the differentiated leading edge of the waveform;

  12 and, in this disengaging condition, these rockers cause the exploration of the storage line at 0. At the end of time A2, after the first twenty digits of the partial product have been entered on line a0, the first AYCO flip-flop is reversed by the pulse p21, so that during the following time, A3, the AYC0 flip-flop is triggered, while the AYC1 flip-flop including the inversion input terminal.

   is powered by firing from the AYCO base-ale remains disengaged, given that it receives a reversing pulse from AYCO only when it is inverted from the engaged state to the starting state. triggered. Consequently, the vertical deflection wave generator AYG ensures the exploration of the second line A1 -in the storage tube AT of the accumulator during the time A3 so that this line receives the second slice of. twenty digits of the partial product,

   however, during the immediately salivating time, S3, the AYCO flip-flop is again inverted, that is to say disengaged, by the following pulse p21, and this time causes the inversion of the second AYC1 flip-flop, which is thus engaged. This state of affairs conditions the lagoon AYG generator which it ensures the exploration of the third line a2. Of the tube. <I> AT </I> during this time, so that it receives the third twenty-digit portion of the partial product.

    During the immediately following time, B4, a new inversion of the first AYCO flip-flop by the following pulse p21 takes place without modifying the state of the second AYCL flip-flop The result is that the AYG generator ensures, this time, the exploration of the fourth line a3 in the AT tube, which allows the possible recording of a carryover figure coming from the addition of the product of a number of forty digits by a number of twenty digits to a number already present in the accumulator and to allow to be, moreover,

   the recording of extension digits which may be necessary in the case of algebraic numbers. The end of the seventh step, B4, ends the first phase of the multiplication process, namely the formation: of the first partial product consisting of the product of the tranche corresponding to the lowest unit orders of factor D, by the whole number R. A new series of four additional times S5, <B> 86, </B> S7 and B8 then follow to allow a similar operation between the tranche corresponding to the highest unit orders of the factor D and the whole of the number R.

   This prolongation beyond the maximum of seven times that the normal rhythm of the machine described above includes is obtained by inhibiting the bar pulse, intended to determine the start of the. next active measurement, this inhibition continuing until the end of time S6 and being ensured by the wave 7S produced in its inverted form by window G202 and applied to window G41 (fig. 13) to determine the closure of this one.

   The G202 counter is controlled not only by the reverse versions of waves A2, A3, S3 and B4, but also by the reverse version of uncle S5 [fig. 12 <B> (p)]. </B> This last wave is produced by flip-flop F35 (fig. 10a) which normally dies in the disengaged condition by following the continuous application of BO pulses to its input terminal, to disengage - expensive. However,

   at the end of time B4, the decreasing trailing edge differentiated from the wave INV <I> B4 </I> which is applied to the G200 gate during any operation affecting R applies a pulse to the, flip-flop F35 and engages it until the arrival of the next BO pulse, at the end of the eighth time, so that a negative pulse is obtained, the duration of which embraces this eighth time S5.

       Since the bar signal is transmitted at the end of a time, the next bar pulse available is that which occurs at the end of the time <B> 86 </B> which follows time S5.



  During time S5, flip-flop F31 is disengaged and flip-flop F32 engaged by the leading edge of wave S5, so that the storage line d1 of the storage tube DIT is again explored and that, by after,

   the second slice of twenty digits of the number D previously stored on this line can be extracted at the read output terminal of the IIIT tube to be applied to the G115 window which is then opened again by the S5 wave then by the in intermediary of the conductor 201 to the various sections WO ...

       W19 of the DITR dynamic static converter. These dynamicostatic converter sections were disengaged at the beginning of time S5 by the application of the wave INV S5 through the intermediary of the inverter INV2 at the gate G117 (fig. 10c) which, at the time of its opening during the interval of the pulse p20 causes the disengagement of each rocker immediately before the arrival of the.

   second segment of twenty digits, of the number D on the conductor 201. As for the segment of previous twenty digits, the various flip-flops WO ... W19 are set during the time S5 according to the configuration of the associated digits of the second segment of twenty digits of the number D and these scales in turn control the counters G200 ... G219 according to the configuration of the second section of the number D.

   During the time S5, the gate G137 is kept closed, given that the waves INV DIG and l @ ICd are negative and give an inhibition energy preventing any output of energy from the inverter INV1.



  During the immediately following time, S6, the flip-flops F31 and F32 are actuated by one step by the pulse BO occurring at this moment, and the line. exploration of the tube IVIT is then r0 which contains the first twenty digits of the number R stored; this first segment of twenty digits of the number R is then available at the reading output terminal of the store.

   It is then applied through the G137 window which is again open due to the inversion of the INV IIIG waves <I> and </I> 111Cd to the CCV additional converter and, from there, to each of the G200 counters ...

   G219 of the .dispositif multiplier which, as before, .starts to give a second partial product resulting from the multiplication of the number R by the second half of the number D (the one which comprises the orders:

  highest units). As in the first operation of the multiplication, during the time immediately following, S7, the flip-flops F31 and F32 are again born of a step so that the storage tube swims <I> MT </I> explores line r1, so that during the time S7 in question, the. second portion of twenty digits of the number R which was previously stored on line r1 is transmitted to counter G137 which is still open and, from there, via the CCV complement converter, to counters G200 ...

   G219, so that during times S6, S7 and a final time B8, a sixty-digit sequential pulse train representing the product of the forty-digit number R by the second twenty-digit portion of the number D was centered on the conductor 202 with a view to its application to the accumulator A.



       Since this second sixty-digit partial product is, in fact, shifted by twenty orders of units towards the highest orders from the first partial product of sixty digits resulting from the first phase of the multiplication, it is necessary to adjust its connection with the partial product already contained in the AT tube of the accumulator by shifting it so that the number positions 0 to 59 of said second partial product coincide with the number positions 20 to 79 of the product already present in the accumulator store.



  This offset is obtained by forcing the storage tube <I> AT </I> of the accumulator to scan line a1 during time S6, line rat during time S7 and line a3 during time B8. This necessary operating sequence is obtained automatically by the step-by-step actuation of the two rockers mounted in series AYCO and AYC1 by each pulse B0, given that the line a3 has been explored during the time B4,

    and the intermediate time S5 during which the line a0 is automatically explored is not necessary for the reception of input energy into the accumulator; so that the time S6 which follows the time S5 finds the tube <I> AT </I> of the accumulator exploring line al in an order suitable for receiving the first twenty digits of the second partial product appearing on conductor 202.

   The combination in the additive element AU of the first partial product circulating around the closed regeneration circuit of the AT tube with the second. Partial product applied results in the recording of a number representing the final product on the four lines a0 ... a3 of accumulator A at the end of time B8 which marks the end of the multiplication process.



  The part of the operation which has been described so far does not take into account the nature (arithmetic or algebraic) of the numbers D and B concerned. However, as already explained, the flip-flop F34 (FIG. 10b) is conditioned according to the nature of the order D so that it is engaged only if the number D is algebraic.

   At all other times, it supplies a negative potential on conductor 135, which. prevents any transformation of number into its complement by the CDV converter which, consequently, lets pass directly to the retarder <I> DL19 </I> any R number that is applied to it without making it undergo any modification.

   If flip-flop F34 is set to indicate an algebraic number D, the previously described inhibition potential that was applied to the number / complement-CDV converter is deleted.



  * Although it is thus released from the inhibiting action of the flip-flop P34, said converter CDV must still be kept inoperative until times S6, S7 and S8 of the order R.

    This arrangement is achieved by also applying to said converter, -as command potentials, the wave INV <I> MG </I> which is negative all the time, except during times A2, A3, S3, <I> B4, </I> S6,

          S7 and B8 of an order R and the wave 7S which is drawn from the wave INV 7S previously indicated by the intermediary of the inverter INV4 from the output terminal of the multiple coincidence window G202.

       Since this 7S wave is negative during times A2, A3, S3 and B4, times during which the previously cited INV wave 112G would allow operation, the number / complement converter CDV can only operate during times <B> $ 6, </B> S7 and B8 of an R order, and this only if the previous D order indicated the use of a brick algebraic D multiplicand.

           When he. is thus released, the converter CDV transforms into its complement the number R (with its possible extension), which. can cross the counter G219 during the second transfer operation (that of the highest imitated orders) and, which, as indicated in the numerical example previously given, must be subtracted from the other partial products instead of their being added.



  When the order R indicated the use of a sign convention for the number R, it. is then necessary (as in the simple numerical example already given) to examine the digit of the order of the highest units of the number R and, depending on whether this digit is im 0 or a 1, to extend this number by qua rante digits into a number of eighty digits by forty successive repetitions of said digit.

   The existence of the sign convention is indicated by the presence of a digit fre 1 at the location of the digit f15 of the combination-order <I> PI </I> which, when applied to the main dynamicostatic converter Il1STR during time 82, causes an excitation of one of the output conductors of the corresponding section of this converter.

   The output voltage thus collected Ie is applied to the gate G127, which is, moreover, controlled by the wave 11 / G [fig. 12 (q)] and by the output energies HCd or JICm <I> of </I> flip-flops P31 and P32 [fig. 12 (r) and (s)], after combination in a buffer consisting of an electronic alternative counter.

   The resulting control wave intended to be applied to the CCV complement converter is shown in fig. 12 (t), where it can be seen that the CCV assembly is only active during times A3, S3 and B4 and during times S7 and B8, and this only in the presence of a command signal indicating that there is a sign convention.

   As is known in the converter assemblies of complements of this type, an uninterrupted succession of signals representing the digit 1 are emitted during the following times S3 and B4 or B8 if the fortieth digit was a 1; conversely, no signal is emitted, which indicates the value 0 if said fortieth digit was a 0. The resulting signal R thus applied to each of the counters G200 ... G219 is, therefore, an extended signal indicating the sign of the number R.



  As the R order may not immediately follow the D order and the fact that an order which has just been applied to the main dynamicostatic converter l @ ISTR is an R order does not appear evident until the end of the time S2, it is necessary to provide devices for the transfer of the first slice of the number D previously processed to the second dynamicostatic converter MTR during the time 82 of each measurement which follows the transfer of D, so that said con-. vertisseur is ready for use during times A2 and A3, if the order happens to require an operation on R.

   At the same time, if the order concerned does not include an operation on R, the same dynamicostatic converter can be used for other functions, and other devices consisting of an inverter INV3 and a G129 counter are available. intended to disengage each section of dynamicostatic converters WO ... W19 at the start of time A2, unless the order involves an operation on R.



  One embodiment of the CCV complement converter of FIG. 10a is shown schematically in FIG. 16. It comprises a flip-flop r20, the latching input terminal 88 of which receives the signals present on the input conductor 203 by means of a G82 gate and a phase inverter 87. The G82 window is controlled by the potential present on the conductor 86 and in the presence of the G127 window (fig. 10a) and by the pulse wave p19.

   Output energies 1 and 0: of the I'20 flip-flop control respectively counters G83 and G84. The G84 counter is mounted directly between the. input and output conductors 203, 205, while the gate G83 is interposed in a connection between the same input and output conductors, but comprising an indicating reversing device 84 which gives an output pulse at l 'absence of input pulses, -and vice versa. The input energy present on the conductor 86 is also applied by means of a phase inverter 85 to the release terminal 83 of the latch I'20.



  In operation, this flip-flop is normally kept @ disengaged, so that its output terminal 0 is held negative by the negative voltage coming from the phase inverter 85, when the control potential on the conductor 86 is. .at its highest value corresponding to 0. As a result, the G83 window is closed and the G84 window is opened and the input signals pass from the input conductor 203 to the output conductor 205 without being changed.



  The control potential present on conductor 86 is negative during times A3, <I> S3 </I> and B4 as well as during S7 and BS times of any. measure assigned to an order indicating the use of an algebraic number R. During the digit period p19 of each of these times, the window G82 is open and lets all the pulses of the signal present on the conductor 203 of this digit period pass to the inverter 37. However, only times A3 and S7 are active, since window G1.37 is closed during times S3, B4 and B8.

   When such a pulse 1 is present, it is phase-shifted into the inverter 87 and its decreasing rear flank - engages the latch 1F20, which causes the closing of the gate G84 and the opening of the gate G85, thanks to which the sign present on the conductor 203, which necessarily takes the form of a succession of pulses 0 (due to the closure of the G137 window) appears on the conductor 205 in the form of a succession of. 1 signals, which determines repeated reproduction of the last digit (p19) 1 of the original signal.

   If, on the other hand, the aforementioned period of digit p19 does not contain any pulse of 0, no input energy is applied to the flip-flop r20 and the state of the latter remains unchanged, so that the gate G84 remains open and no 1 pulse is emitted during the immediately following forty digit periods, the signal then being extended by the equivalent of forty 0 signals.



  When the control potential present on the conductor 86 is brought back to its normal level (that is to say the highest), the phase inverter 85 supplies a negative voltage which disengages the flip-flop F20 if it has been previously engaged.



  One embodiment of the number / complement converter CDp of FIG. 10b is shown schematically in FIG. 17. It comprises a flip-flop F21, the latching terminal 92 of which receives the input signals present on the conductor 205 by means of a G89 gate and of a phase inaer- sor 92 and of which the terminal trigger 93 receives the control potential present on conductor 135.

   The gui chet G89 is controlled by the inverted form of the control potential present on the conductor 135 and which, for its part, is applied via the phase inverter 91. The output terminal (1) of the flip-flop controls a gate G90 and the output terminal 0 of said flip-flop controls a second gate G91.

   The gate G91 is mounted directly between the input conductor 205 and the output conductor 207 which supplies the delay device DL19 (fig. 10b). The G90 counter constitutes a variant route between the two aforementioned conductors, this route comprising, in addition, an indication reversing device 90.



  The operation of this assembly is analogous from several points of view to that of the CCV complement converter. When the control potential present on the conductor 135 is at its normal level (that is to say negative), the number / complement converter does not act, since the latch is disengaged and the G89 gate is closed under the action of the phase inverter 91. Under these conditions, the G91 window is open and the G90 window closed, which allows direct transmission of the signals between the input conductor 205 and the output conductor tie 207, without these signals undergoing any modification.

   Each time the control potential present on the conductor 135 is brought to its upper level to actuate the number / complement converter, the window G89 opens under the action of the inverter 91, but the rocker switch remains in its previous state and maintains the counter <B> 091 </B> open and the counter G90 closed until the arrival of the first signal pulse on the input conductor 205.

   Said pulse is transmitted to the output conductor via the gui chet G91 and also passes through the gate G89 and the phase inverter 98, so that the falling rear edge of said pulse engages the flip-flop F21 immediately after said pulse has passed through the gui chet G91 to reach the output conductor 207. The reversal of the flip-flop F21 determines the closing of the counter G91 and the opening of the counter G90, whereby, during the remainder of the signal transmission period, the aforementioned variant route passing through the reversing indicating device 90 and the G90 window is used instead of the direct route through the G90 window.

   As a result, all the signals which follow the first digit 1 are inverted, ie all the signals 1 are transformed into signals 0 and vice versa. When the control potential present on the conductor 135 is lowered, the rocker is again disengaged and closes the window G90 while turning again. the G91 counter.



  An assembly that can be used for either of the DIYG and AYG vertical deflection wave generator devices (Figs. 10a and 10c) is shown in simplified form in Fig. 18.



  The: device shown comprises a tube 94 whose function and mode of operation are exactly identical to those of the vertical deflection tube of FIGS. 23 and 35 of the aforementioned reference A. Indeed, this positive dis controls the passage of current through a resistor R1 as a function of the value of the input current applied to its, control gate by the conductor 95-This is connected to the anodes of two diodes D10,

   D11, the cathodes of which are connected in parallel with the cathodes. Of the tubes 96-97 which are arranged in the manner of a cathode load arrangement with cathode load resistors R and R / 2 connected to a source of negative potential . The control gate of tube 96 is connected to a control input terminal 99 which is the terminal fed by wave 111C1 (or INV AYCO), while the control gate of the other tube 97 is connected. to a second control input terminal 100 which is the terminal supplied by the waveform 67Cd (or INV AYC1).



  The mode of operation of this assembly is exactly identical to that which was described in reference A, the two tubes 96 and 97 controlling the selective application of one or two units of current to the tube 94, which allows to vary the anode potential thereof by making it take one of four different values corresponding respectively to input currents of zero, one, two and three units. The effect of varying the anode potential of tube 94 acts on one of the vertical deflection plates of the associated cathode-ray tube and, through the intermediary of a phase-inverting amplifier <B> 98 </B> on the opposite vertical deflection plate of the same tube.



  The mounting of the output adder device ADO in cascade with the additive element AU or the subtractor element SU of the accumulator A can give rise to difficulties in obtaining a suitable operation of the element d. registration of the accumulator, due to the additional delay which may occur.

   As is already known in the art of cathode-ray tube magazines, the number 1 pulses have their leading edge slightly delayed from the corresponding true time at the start of the associated number interval of the rhythm. operation of the machine, due to the. the need to test the output pulse from the sensor plate of the tube by the stroboscopic examination wave, which itself is slightly delayed.

   -The signal arriving through the counter G200 comes from such a store and has, moreover, passed through the counter G137 and the complement converter <I> CC V </I> en route, which can only increase its delay. The new delay introduced in the ADO adder device (which cannot be compensated as in the other adder elements by a corresponding shortening of the late actions of the delay assemblies mounted downstream)

   can destroy the synchronism of the input energy of the adding or subtracting element of the accumulator A with respect to the rhythm of the machine which must be followed by the inscription element AyVU of the accumulator in a sufficient measure to introduce risks of error.

   Such a difficulty can be at least partially overcome by modifying the assembly of the elements shown in FIG. 20, where the output energy of the G200 gate is applied directly by the conductor 212 to one of the input terminals of the additor and subtractor elements AU, <I> SU </I> of the accumulator A, while the read output energy of the store of the accumulator is applied, as before,

   by the conductor 210 to the other input terminal of said elements AU-SU. The second input terminal of the ADO adder device. the multiplier chain is supplied, through the intermediary of the conductor 215, by the transfer output energy present on the conductors 213 and coming from that of the elements AU-SU which is then in service by the intermediary:

  a delay device <I> DL, </I> while the output energy of said ADO adder device is applied, through the conductor 216, to the input conductors, delayed transfer 214 of the elements <I> AU-SU. </I> The output energy of these latter elements is, in turn, applied, through the conductor 211, to the recording element of the accumulator in known manner. With this arrangement, one can compensate for the delays which occur in the ADO device by suitably adjusting the delaying action of the device. <I> DL. </I>

 

Claims (1)

CLAIM: Multiplication device of a purely digital electronic calculating machine intended to operate reliably numbers represented in binary notation by electric signals, comprising a device for storing series of signals representing the multiplicand and the multiplier, and a multiplication assembly comprising a number X of distinct and parallel inputs capable of being each controlled by a signal representing one of the digits of the multiplication represented by X digits and a single input intended to receive consecutive signals representing the digits of the multiplier, characterized in that said storage device has a capacity allowing the storage of signals representing a multiplicand and a multiplier each comprising a number of digits greater than said number X of inputs which said multiplication arrangement comprises, and in that it comprises a selector and sampling device cooperating with said device -d'emma gasinage, so as to be able to make a choice among the locations of the latter in which signals are stored and to collect these signals in the locations chosen. , this selector and sampling device being arranged so that at least those of said stored signals which represent the multiplicand can be sampled by slices of signals each representing X digits a control device capable of being actuated by a single command signal supplied by the calculating machine and capable of extracting from the storage device the first of said signal slices representing numbers of the multiplier, to apply this slice of signals to the control of said X inputs of the multiplication circuit capable of being controlled by these signals, while the complete series of consecutive signals representing the multiplier is applied to said single input of the multiplication circuit intended to receive these consecutive signals, so that this assembly provides a first partial product represented by a series of signals, then extract from the storage device the second of said slices of signals representing multiplicand digits, apply this second slice to the control of said X inputs of the multiplication assembly capable of being controlled by these signals while the complete series of consecutive signals representing the multiplier is extracted from the storage device and applied again to said single input of the multiplication assembly intended to receive these consecutive signals, so that this assembly provides a second partial product represented by another sequence of signals, and a device capable of combining said series of signals representing respectively said first and second partial products in the form of a series of signals representing the product of the complete multiplication and of the multiplier. SUB-CLAIMS 1. Multiplication device according to claim, characterized in that said positive control device is arranged so as to control said selector and sampling device, such that the first segment of signals representing X digits of the multiplicand which is extracted from the device 'storage includes the signals representing the group of digits of the multi plicand which corresponds to the lowest imitated orders, that the second portion of these signals which is extracted from the storage device comprises the signals representing the group of digits of the multiplication which corresponds to the orders of units immediately above those of the group of digits represented by the first slice, and that the series of consecutive signals representing the multiplier applied each time to the multiplication assembly is constituted by signals each representing a figure of the multiplier and ordered in order of increasing units. 2. Multiplication device according to sub-claim 1, characterized in that said multiplication key assembly comprises X-1 adder circuits comprising each one a signal transfer loop representing digits to be transferred, a first and a second input for them. signals representing the terms to be added and an output for the signals representing their sum; X-1 connected delay devices, the first between one of said inputs of a first of said adder circuits and said output of a second of said adder circuits; the second between one of said inputs of this second adder circuit and said output of a third: of said adder circuits, and so on, the last of these delay devices being arranged in an input channel connected to one of said inputs of the last of said X --1 adder circuits, each of said delay devices being arranged in such a way as to delay the signals which pass through it by a duration equal to the reserved duration, in the series of signals representing the multiplier, at each of the consecutive signals representing a digit, minus the value of the delay experienced by this signal in the adder circuit by which it is supplied, X wicket circuits of which X-1 are each connected in series between said single input of the multiplication assembly intended to receive the signals representing the multiplier and the second of said inputs of said adding circuits, the gui circuit chet remaining being connected in series between this same input of the multiplication assembly and said input channel in which is arranged said "last delay device, dynamicostatic signal converters capable of each converting one of the signals of a slice of X successive signals representing as many digits of the multiplicand, these converters being connected so as to supply key control potentials each to one of said gate circuits, the control potential intended for the first gate circuit being supplied by the dynamicostatic converter capable of converting that of the X signals of said wafer which represents the lowest order number of units, the key command potential intended for the second branch circuit being supplied by the dynamico-static converter capable of converting that of the X signals, of said slice which represents the digit of order of units immediately above, and so on, the control potential intended for: the last branch circuit being supplied by the dynamico-static converter capable of converting that of the X signals of said slice which represents the highest order number of units. 3. Multiplication device according to claim, characterized in that said positive storage device comprises a cathode-ray tube device having several distinct storage lines, one for each of said signal slices representing X digits. . 4. Multiplication device according to claim, characterized in that said positive dis capable of combining said series of signals representing partial products consists of an accumulator device. 5. Multiplication device according to sub-claim 4, characterized in that it comprises means capable of being controlled by an order signal supplied by the machine to be calculated and determining whether each of said partial products will be added to or under. feature of the previous digital content of said accumulator device. 6. Multiplication device according to sub-claim 5, characterized in that said accumulator device comprises a storage device with thodic AC beam tube having several distinct storage lines, each capable of storing a series of signals representing X digits, said accumulator device comprising means capable of being controlled by a signal and capable of selectively exploiting said storage lines in an order determined by this signal. 7. Multiplication device according to claim, characterized in that it comprises means controlled by said control device, under the effect of a command signal supplied. to the latter, and capable of determining the manner in which the multiplication operation will be carried out according to whether at least one of the series of signals respectively representing the multiplicand and the multiplier represents this number in arithmetical form or in algebraic form, in order to obtain a series of signals correctly representing the product of said multiplicand and multiplier. 8. Multiplication device according to sub-claims 2 and 7, characterized in that it comprises a circuit in series with said single input of the multiplication assembly intended to receive the series of signals representing the multiplier and capable of extending this series by repeating the signal representing the highest order of units digit of the multiplier: in each of several times reserved for signals which would each represent an even higher order digit, before this series: signals is applied to said X gate circuits controlled by the signals belonging to said slots and representing digits of the multiplicand. 9. Multiplication device according to sub-claim 8, characterized in that said circuit capable of prolonging the series of signals representing the multiplier is arranged in such a way as to prolong or allow this series to pass without modification. signals, depending on the content of a control signal: derived from an order signal supplied by the calculating machine and indicating whether this series of signals represents the multiplier in arithmetic form or in algebraic form. 10. Multiplication device according to sub-claim 8, characterized in that it comprises conversion means connected in series with said line in which said: last delay device is disposed and capable of converting the series of signals representing the multiplier, when it is applied to this delay device, in a series of signals representing the complement of the multiplier, said means: conversion being capable of being controlled by an electrical signal so as to convert or allow said series of signals to pass without modification, depending on the content of this electrical signal. 11. Multiplication device according to sub-claim 10, characterized in that said conversion means are controlled by a multivibrator assembly with two states of stability capable of being brought beforehand, by an order signal indicating whether in the multiplication to performing the multiple plicand is represented in arithmetical form or in algebraic form, in one or the other of said states of stability according to the. content of this signal-order. 12. Multiplication device according to sub-claims 2 and 5, characterized in that the first of said wicket circuits is connected to said second input of the first adder circuit by means of said accumulator device, the signal output path of this branch circuit being connected directly to an input terminal of said accumulator device, a signal output terminal representing the digits to be transferred that the accumulator device comprises being connected by means of a delay device to said second input of said first adder circuit, and said output of said first adder circuit being connected to a signal input terminal representing. the reported figures also included in the accumulator device.