CA2483593A1 - Multipath logic for error correction in the demodulation of encoded signals in transmission links - Google Patents

Multipath logic for error correction in the demodulation of encoded signals in transmission links Download PDF

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Publication number
CA2483593A1
CA2483593A1 CA 2483593 CA2483593A CA2483593A1 CA 2483593 A1 CA2483593 A1 CA 2483593A1 CA 2483593 CA2483593 CA 2483593 CA 2483593 A CA2483593 A CA 2483593A CA 2483593 A1 CA2483593 A1 CA 2483593A1
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CA
Canada
Prior art keywords
combination
error correction
transmission links
demodulation
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA 2483593
Other languages
French (fr)
Inventor
Yannick K. Lize
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CA 2483593 priority Critical patent/CA2483593A1/en
Priority to PCT/CA2005/001676 priority patent/WO2006053421A1/en
Publication of CA2483593A1 publication Critical patent/CA2483593A1/en
Abandoned legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22Demodulator circuits; Receiver circuits
    • H04L27/233Demodulator circuits; Receiver circuits using non-coherent demodulation
    • H04L27/2331Demodulator circuits; Receiver circuits using non-coherent demodulation wherein the received signal is demodulated using one or more delayed versions of itself

Abstract

The invention provides a novel way of using channel logic gates in encoded transmission links, for example differential phase for telecommunication. The invention includes a plurality of different data path which can be separated by power dividers to perform logical functions on the channels after which they are then individually detected. The logical recombination and logical operations on the received data leads to error correction. The technique is not restricted to optical signals and can be used in other transmission channel like satellite communication, mobile communication as well as computer interconnects.

Description

Description 1. This invention relates to a method of performing error correction in encoded transmission links.
Several methods are commonly used to lower the error rate of a transmission link or increase the bandwidth in the channel while maintaining the error-rate. In an optical fiber channel, new types of optical fibre and amplifiers can increase the transmitted bandwidth over a longer distance but the capital investment required for installation is considerable.
A solution that improves the transmission without incurring a large cost overhead is highly attractive.
A technology commonly used in transmission links is error correction algorithms. For example forward-error-correction (FEC) is an error correction scheme that detects and corrects transmission errors at the receiver end without calling for retransmission. With FEC, bits are added to the message prior to transmission to detect and correct errors at the receiving end. The technology is very low cost and installation cost is insignificant.
The only drawback is that increased bandwidth is necessary for the code bits added which reduces the effective bit-rate of the transmission, and hence lower data capacity.
The Invention is a new method of using channel logic gates in encoded transmission links, for example differential phase for telecommunication along multiple paths which can correct errors without reducing the effective bandwidth of transmission. The installation cost is low and it can significantly lower the bit error rate and the cost per bit. The method has the advantage that it is compatible with existing transmission systems and does not prohibit the use of any other enhancing technology. Error correction schemes like FEC can still be implemented.
When using a flavour of differentially phase-encoded transmission, which at the receiver is usually demodulated in a delay-line interferometer (DLI) with a single bit delay to create an intensity modulated signal. The invention uses a multipath logical demodulation where the signal is split into different paths directed to different DLIs. Each of the DLI has a specific delay so that a given bit in a time slot interferes with a bit in a different time slot; for example it can be with the following bit in the first path, the second following bit in second path, the 4'h bit in the third path, the 8th bit in fourth path, and so on. In this example the DLIs can be viewed as logical XOR gates in which one input is the signal and the other is the signal with a delay. The intensity modulated signal is detected and converted into a logical signal. Then using logic gates, the bit patterns from the different paths are reconverted to the same pattern.
The process relocates the errors in the data pattern and by, for example, comparison of the different paths, error correction can be performed.
In the embodiment shown in figure 1 applied to optical fibre transmission link, the signal is divided in 3 different path which are individually detected by photodetectors.
The following logical operations allow for comparison of the different paths and error-correction.

Claims (8)

  1. Claim 1 A device that allows received serial data to be delayed relative to each transmitted bit with a well defined sequence.
  2. Claim 2 A device composed of logic gates connected together to perform logical operations on data as defined in Claim 1.
  3. Claim 3 The combination defined in claim 2 to perform the logical operations of error correction.
  4. Claim 4 The combination defined in claim 3 using any type of differential phase shift encoded transmission links.
  5. Claim 5 The combination defined in Claim 2 using any type of encoding scheme.
  6. Claim 6 A combination as defined in Claim 5 that is applied to optical communication link.
  7. Claim 7 A combination as defined in Claim 5 that is applied to satellite, radio or mobile communications.
  8. Claim 8 A combination as defined in Claims 6-7 using any type of data transmission format
CA 2483593 2004-11-01 2004-11-01 Multipath logic for error correction in the demodulation of encoded signals in transmission links Abandoned CA2483593A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CA 2483593 CA2483593A1 (en) 2004-11-01 2004-11-01 Multipath logic for error correction in the demodulation of encoded signals in transmission links
PCT/CA2005/001676 WO2006053421A1 (en) 2004-11-01 2005-11-01 Multi-path error-correcting demodulating method and device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA 2483593 CA2483593A1 (en) 2004-11-01 2004-11-01 Multipath logic for error correction in the demodulation of encoded signals in transmission links

Publications (1)

Publication Number Publication Date
CA2483593A1 true CA2483593A1 (en) 2006-05-01

Family

ID=36283086

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2483593 Abandoned CA2483593A1 (en) 2004-11-01 2004-11-01 Multipath logic for error correction in the demodulation of encoded signals in transmission links

Country Status (2)

Country Link
CA (1) CA2483593A1 (en)
WO (1) WO2006053421A1 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3819311B2 (en) * 2002-03-19 2006-09-06 株式会社東芝 Modulation method determination method and modulation method determination device

Also Published As

Publication number Publication date
WO2006053421A1 (en) 2006-05-26

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