CA2430943A1 - Method and device for multiplexing data packets - Google Patents
Method and device for multiplexing data packets Download PDFInfo
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- CA2430943A1 CA2430943A1 CA002430943A CA2430943A CA2430943A1 CA 2430943 A1 CA2430943 A1 CA 2430943A1 CA 002430943 A CA002430943 A CA 002430943A CA 2430943 A CA2430943 A CA 2430943A CA 2430943 A1 CA2430943 A1 CA 2430943A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/24—Time-division multiplex systems in which the allocation is indicated by an address the different channels being transmitted sequentially
- H04J3/247—ATM or packet multiplexing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5672—Multiplexing, e.g. coding, scrambling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
- H04L2012/5681—Buffer or queue management
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
A data packet provided with address information (VPI, VCI) is received at an input connection (5a, 5b, 5c, 5d) of a node (1). The address information is broken down (S1) into an initial section and a subsequent section. The initi al section is used (S2) as an address for addressing a reference table (15), containing entries which define the manner in which the subsequent section i s to be analysed, in order to find routing information for the data packet. Th e entry can be a reference to a connection table, containing the routing information (S4, V), or to a further entry in the reference table (S4, Z).</ SDOAB>
Description
Method and device for multiplexing data packets The present invention relates to a method and a device for multiplexing data packets in a packet data network.
A preferred, but not exclusive use of the method and device lies in the area of ATM
(asynchronous transfer mode) networks. The asynchronous transfer mode (ATM) is used in modern, wide-band telecommunications networks. ATM is based on the transmission of data streams and data packets in cells of constant length. ATM
is connection-oriented, that is to say each transmitted cell can be clearly ascribed to a previously built-up or established connection. This operation uses destination information in the cell header, which is formed from the Virtual Path Identifier (VPI) and the Virtual Channel Identifier (VCI).
The VPI field in the NNI (Network Network Interface) mode comprises 12 bits, in the UNI (User Network Interface) mode 8 bits. The VCI field comprises 16 bits.
Altogether, therefore, it is possible to distinguish up to 22g connections.
The number of possible connections in an ATM multiplexer is considerably less than this theoretical limit, due to the fact that each built-up connection requires an entry in a table containing various parameters, which in the following are briefly described as routing information, for example the values of the VPI or VCI, which must be attached to the data packet when it is forwarded on an output channel, routing information, priorities etc.
The large number of connections which can be distinguished by VPI and VCI and the corresponding variety of their addresses lead to technical problems with the location of the routing information for a data packet. If use of the destination information, with which a data packet is received at a node of the network, was directly wanted for addressing a table of this node containing the routing information, a table would be needed, the size of which would be enough to accommodate the routing information for each possible value of the destination information therein. In order to reduce this storage requirement, a method is known to ascribe to each connection in a multiplexer a so-called internal address, the length of which depends on the maximum expected or feasible number of connections, which can be processed at the same time and to provide a connection table, which includes the routing information for all these connections and the size of which is selected dependent on the number of internal addresses.
Such an address, for example, containing 14 bits can be half as long as the destination information originally transferred with an ATM packet.
In order to find the routing information for a connection, it is necessary to convert the destination information transferred with a data packet, if necessary including the designation of an incoming connection, at which the data packet has been received, into the internal address. In the following, this destination information is described as destination address. Essentially, there are two methods for converting the destination address into the internal address:
First is conversion by means of an associative memory (Content Addressable Memory, CAM). With such a method, the destination address is fed to an associative memory, and as internal address this delivers back the address of which one of its storage locations this destination address is stored. The number of storage locations of such an associative memory does not need to be greater than the maximum number of connections to be processed; possible values of the destination address, for which no connection is established, are not stored in the associative memory.
Associative memories of this kind are, however, costly, and their costs increase disproportionately to their increase in size.
A second cheaper method for converting the address is a table method, in which only one section of the bits of the destination address is analyzed. If, for example, it is known that all virtual paths of a particular ATM network support a maximum of 64 channels, 6 bits are required for their clear identification. This means that 10 bits out of the 16 bits of the VCI field in the destination address can be ignored during conversion to the WO 02/43290 PCT/IBOl/02761 internal address, which reduces the storage requirement of the conversion table by a factor of 2'°. However, it is obvious that such a method results in substantial reduction in the flexibility of the ATM network and that the scaleability is lost in the direction of higher channel numbers.
Although this problem is illustrated here as an example of an ATM network, it always occurs with different types of networks, whenever a node of a data transmission network has to carry out processing steps on received data packets as a function of their destination information and the number of possible values of this destination information is substantially greater than the number of the connections or data flows, which the node can handle simultaneously.
Advantages of the invention A method for multiplexing data packets and a multiplexer are created by the present invention, which can be implemented economically and with low memory complexity and good scalability. A further advantage of the invention is that it permits transparent virtual paths, that is to say optionally the evaluation of a VCI value can be allowed or prevented in the multiplexer.
An additional advantage of the invention lies in the fact that it is able to support in a simple manner non-homogenous connection scenarios. In particular, transparent and non-transparent virtual paths as well as virtual paths with greatly varying numbers of virtual channels can be handled with ease by one multiplexer.
These advantages are achieved according to invention by the fact that routing information for the data packet is determined for a data packet provided with destination information, received at an input terminal of a multiplexer, on the basis of the destination information from a connection table and the data packet is output on the basis of the determined routing information on an output terminal of the multiplexer, whereby the destination information is broken down into an initial section and a subsequent section, and the initial section is used as address for addressing a reference table, that contains the entries defining the manner in which the subsequent section is to be analysed for finding the routing information, and on the basis of the entry addressed in such a way, a choice is made between at least two different methods for analyzing the subsequent section.
A first of these methods can be used if the addressed entry of the reference table contains a connecting pointer to an entry of the connection table. In this case, a destination entry of the connection table found on the basis of this connecting pointer is read and analyzed. The address of the destination entry is preferably calculated here on the basis of the connecting pointer and subsequent section. Thus, for example, the connecting pointer can be a pointer to the start of an area in the connection table, which contains a multiplicity of entries, and the numerical value of the subsequent section in each case can serve as offset for addressing a single one of these entries.
A second method can be used, if the addressed entry of the reference table contains a reference table pointer to a further entry of the reference table. In this case, a further entry of the reference table is read and analyzed at a location found on the basis of the reference table pointer.
In this case, appropriately for fording the location, the subsequent section is also consulted in addition to the reference table pointer. Preferably, this is done by breaking down the subsequent section into a new initial section and a new subsequent section, and by calculating the address of the further entry on the basis of the reference table pointer and the new initial section. The subsequent section can be repeatedly broken ' down into a new initial section and a new subsequent section as often as necessary, until the address of an entry, which contains a connecting pointer, that is to say which points to the connection table, is finally obtained.
In order to be able to break down the subsequent section into a new initial section and a new subsequent section, it is preferable that the addressed entry of the reference table also contains an instruction, which defines what bits of the subsequent section should belong to the new initial section and what bits to the new subsequent section.
In this way, great flexibility is achieved during analysis of the address, which makes the method particularly suitable for application in heterogeneous connection scenarios.
In principle, the bits of incoming destination information or of a subsequent section could be broken down in a completely arbitrary way into an initial section and subsequent section or new initial section and new subsequent section. Thus, it is not impossible that one bit of the incoming destination information or subsequent section is ascribed to the (new) initial section (or subsequent section), while higher and lower value bits are ascribed to the (new) subsequent section (or initial section).
Also, permutations of bits during breakdown into initial sections and subsequent sections are not impossible.
For the sake of simplicity, however, it is preferred that initial section and subsequent section in each case comprise successive bits of the destination information.
If the entire destination information does not have to be analyzed, in order to clearly identify a connection, the initial and subsequent sections are appropriately limited so that they are separated by bits, which are not to be analyzed and not ascribed during breakdown into initial or subsequent sections either to one or the other part.
For increased security, it can be proposed that in the individually addressed entry of the reference table and/or the connection table an instruction is also read, which indicates whether this entry is valid or otherwise, and that the process is aborted if the entry does not prove to be valid. If this happens, the node can deduce from this that it has received incorrect destination information and can request repeated transmission of the data packet concerned.
The destination information of a data packet is updated accordingly before it is re-output by the node on the basis of the routing information found in the connection table.
It is not necessary for all bits of the destination information to be changed, on the contrary the routing information preferably contains information, which defines what bits of the destination information should be changed and what not to be changed.
Further features and advantages of the invention will become evident from the following description of embodiments with reference to the attached figures wherein:
Fig. 1 schematically represents an ATM node with a multiplexer according to the invention;
Fig. 2 shows the structure of the multiplexer according to the invention;
Fig. 3 shows the format of an entry in the reference table of the multiplexer;
Figs. 4 and 5 show examples of the format of an entry in the connection table;
and Fig. 6 shows a flow chart of the method according to the invention.
Description of the preferred embodiments Fig. 1 shows a greatly schematized block diagram of a node 1 of an ATM
network, which contains a multiplexer 2 according to the invention. The node connects a multiplicity of input and output transmission circuits, here four such circuits, which are called 3a, 3b, 3c, 3d or 4a, 4b, 4c, 4d in each case. ATM cells are transmitted via the incoming transmission circuits to the node 1, which in each case contain destination information, on the basis of which the node 1 has to determine the output transmission circuit, on which the cell must be forwarded on. This destination information comprises a Virtual Path Identifier VPI which is 8 or 12 bits long in each case depending on the operating mode (LJNI or NNI) of the ATM network and a Virtual Channel Identifier VCI which is 16 bits long.
The ATM cells arriving via the transmission circuits 3a, 3b, 3c, 3d pass through input connections Sa, Sb, Sc, Sd of the node l, which forward on each received cell to the multiplexer 2, additionally linked with a characteristic port number for the respective input connection Sa, Sb, Sc or Sd. The entire incoming destination information of the cells received by the multiplexes 2 therefore comprises VPI, VCI and port number for each cell.
The object of the multiplexes 2 is to produce destination address information on the basis of this incoming destination information and to re-output this together with the cell on the basis of which the output transmission circuit 4a, 4b, 4c or 4d suitable for forwarding the cell can be selected, and on the basis of which if necessary a node structured accordingly, forming the other terminal of the selected output transmission circuit, can in turn again convert and forward on the address. Each output transmission circuit 4a, 4b, 4c or 4d is ascribed to an output connection 6a, 6b, 6c, 6d, which determines from among the ATM cells output by the multiplexes 2 on the basis of their destination address information those intended for the transmission circuit ascribed in each case and forwards these on to the transmission circuit.
The structure of the multiplexes 2 is shown in detail in Fig. 2. It comprises a control device 11, a combinatorial network 12, two groups of D flipflops 13, 14 and two memory elements 15, 16, of which element 15 is described in the following as reference table and element 16 as connection table. In this case, it is clear that the structure shown here is only given as an example and that there is a large number of other circuit possibilities to implement the multiplexing method performed by the multiplexes 2.
The function of the multiplexes 2 is explained in the following with reference to the flow chart in Fig. 6 and the data formats shown in Figs. 3 to 5.
The method is based on a destination address A of an ATM cell, which is fed to the combinatorial network 12 via an input 17. This destination address A, as indicated above, comprises port number, VPI and VCI of an ATM cell. The length of the port number is generally P bits, unless the number of the inputs of the multiplexes 2 is greater than 2p. In a first step S 1 of the method, this destination address A
is broken down into an initial section AO and a subsequent section A 1 of a definite pre-set length in each case. At the same time, the designations "initial section" and "subsequent section" are only used for the sake of clarity; the initial section does not need to comprise the first and the subsequent section does not need to comprise the following bits of the incoming destination information A, in principle the bits of the initial section and subsequent section can arbitrarily consist of the bits of the incoming destination information.
With the example described here, the P bits of the port number are split off as initial section AO with definite pre-set length; VCI and VPI remain as subsequent section A 1.
The combinatorial network 12 outputs the initial section AO received in such a manner to the D input of the D flipflop 13, into which it is transferred, directed by a control signal of the gate circuit 11 lying on the E input of the D flipflop 13.
Controlled by an external clock Clk, this first initial section is output as address to the connection table 15. By inserting the D flipflop 13 between combinatorial network 12 and connection table 15 it is possible to keep the destination address of the connection table 15 constant over several cycles of the clock Clk so that inexpensive, moderately fast components can be used for the extensive connection table 15.
The format of the entries in the reference table 15 is shown in Fig. 3. Each entry contains a so-called Used bit UB, an individual bit, which indicates whether the entry concerned is valid or otherwise.
This bit UB has a control function; when operating normally and if the destination address is error-free, the Used bit of an addressed entry must indicate its validity.
A substantial element of each entry is the following pointer F-PTR, which represents a pointer to a further table entry. To which of the two tables, reference table 15 or connection table 16, the pointer F-PTR points, is indicated by a pointer type bit PTB.
The length of the following pointer F-PTR is substantially less than that of the incoming destination information, typically it can be approximately half its length, for example 16 bits.
WO 02/43290 PCT/IBOl/02761 The output of the reference table 15 is connected to the control device 11 and the combinatorial network 12, in order to permit the entry to be analyzed.
Therefore the control device 11 in the event that the Used bit UB indicates that the entry is invalid, can deduce from this that when describing the reference table 15 an error must have arisen, and initiate the production of a corresponding error message.
If the pointer type bit indicates that the following pointer F-PTR concerns a pointer to the reference table 15 (step S4), the combinatorial network 12 in steps S5, S6 on the basis of the following pointer F-PTR and subsequent section A 1 of the incoming destination information calculates the address of a further entry of its reference table 15, which is accessed in a following cycle. To determine this address, the elements F-LSB
(Following LSB) and F-S (Following Size) of the entry are consulted in step S5.
These two elements specify the manner in which the subsequent section, which presently comprises the VPI and VCI of the incoming destination information, is broken down into a new initial section AO and a new subsequent section A1. Stated more exactly, the element F-LSB designates the number of that bit in the original subsequent section, which is to become the Least Significant Bit, LSB) of the new initial section AO
', and F-S indicates the length of this initial section in bits. Since the original subsequent section Al comprises 28 bits, in each case a length of 5 bits is sufficient for F-LSB and F-S, so as to be able to specify each of these 28 bits or an arbitrary length for the new initial section of between 1 and 28 bits.
As an example it is assumed that the new initial section AO ' should contain the VPI of the incoming destination information. In this case, F-LSB has the value 16 and the value of F-S can vary, depending on the number of virtual paths the ATM node 1, in which the multiplexer 2 is used, is designed for. If the node 1 is to transmit NNI
cells, F-S
obtains the value 12, when transmitting UNI cells it has the value 8. It should be directly understood however that by choosing other values for F-S analysis of higher value bits of the VPI can be selectively prevented. Operating with a F-LSB
value of more than 16 is also conceivable in order to prevent analysis of least significant bits of the VPI.
Result of the breakdown is a new initial section A1 ' of F-S bit width, which is added in step S6 as offset-value to the following pointer F-PTR determined previously, in order to form an address AO for renewed table access.
The method now returns to step S2, where by means of the address AO formed in this manner the reference table 15 is again accessed, in order to read a further entry there.
If examination of the Used bit UB in step S3 shows that the entry is invalid, an error must have occurred during transmission of the destination information A to the node 1.
This information can be used by the control device 11, in order to request a re-transmission of the cell by the node, which sent this.
In step S4 it is again examined whether the following pointer F-PTR is a pointer to the reference table 15 or to the connection table 16. If it again concerns a pointer to the reference table 15, the steps S5, S6, S2, S3 are repeated. If it concerns a pointer to the connection table 16, the method proceeds to step S7. In this step, subsequent section A1 is added as offset to the following pointer F-PTR, in order to produce an address of an entry in the connection table 16. In step S8, the combinatorial network 12 outputs the address received in such a manner via the D flipflop 14 to the connection table 16, in order to read the entry concerned.
A first example for the format of such an entry is shown in Fig. 4. The entry comprises a Used bit UB, which has the same function as the corresponding bit of an entry of the reference table. A further element NH (new header) 28 bits long contains new values for VPI and VCI, which in the case of non-transparent transmission are added to the ATM
cell as new destination information while they are forwarded via one of the outputs 4a to 4d.
In step S9, it is examined on the basis of this Used bit whether the entry found is valid or otherwise. If not, as in the case of examination in the step S3 re-transmission can be requested. If yes, the entry is analyzed, in order to produce destination address information for the data packet and to output the data packet, provided with this destination address information in step S 10.
Two further elements NH-LSB and NH-MSB (New Header-Least Significant Bit and New Header-Most Significant Bit) are needed as part of the routing information in the connection table 16, even though the multiplexer 2 should also be able to transmit data packets in a transparent manner, that is to say in at least a partially unconcealed manner of transmitting the incoming destination information. These two elements both 5 bits long designate in each case the most significant and the lowest-value bit, which will be affected by a change in address. In the event of non-transparent transmission, these elements each have the value 0 or 27, with the consequence that VPI and VCI of a cell are completely replaced in step S 10. If, for example, NH has the value 16, this means this that in the ATM cell output by node 1 only the VPI field is replaced in step S 10, which - depending on the mode - corresponds to 8 or 12 most significant bits of the destination information, on the other hand the VCI value remains unchanged. If the element NH-MSB has the value 23, then only 8 bits of the VPI can be changed, which corresponds to operation of the ATM network in the UNI mode.
In regard to the format of an entry in the connection table shown in Fig. 5 the two elements NH-LSB, NH-MSB are replaced by a 28 bit long element NHM (New Header Mask). The logic condition 0 or 1 of each element of this element indicates whether the corresponding bit of the destination information should be replaced in step S
10 by the value entered in the element NH, or whether the incoming destination information for this bit should remain unchanged. With this format, even greater flexibility can be achieved with regard to definition of transparent data channels, since arbitrary, even non-contiguous groups of bits of the destination information can be defined as not to be changed.
Further, in regard to the formats in Fig. 4 and 5, identical elements of an entry in the connection table are a UPC bit, which indicates whether a UPC function should be applied to this cell, and a UPC pointer UPC-PTR, which contains a pointer to the UPC
function ascribed to the incoming destination information. As a result, it is possible to keep the number of the independent UPC units (one per connection is required) lower than the total number of the connections processed by the multiplexes.
Further elements which can be present are: a Routing Tag RT, for example 32 bits long for internal routing in the multiplexes, an internal connection number ICN and a element PC, which indicates a priority class for the connection.
When the multiplexes is put to use for the first time, reference table 15 and connection table 16 must be initialized. Since no connections still exist, the Used bits UB of all entries are set to the logic value "false". If a connection is established or switched, an entry is written in the connection table 15 as well as one or several entries in the reference table 16. This will be demonstrated by way of an example. It is assumed that an input interface with the port number 27 uses virtual paths VPO and VPI. VPO
is transparent, virtual channels VC64, VC66 and VC68 are used in the VPI. In order to differentiate between the different connections, it is enough to evaluate the bit 0 of the VPI or bits 1 and 2 of the VCI of destination information.
A first entry necessary for switching the cells of the input interface 27 is registered at the address 27 of the reference table. Its Used Bit UB is given the logic value"true", the following pointer F-PTR is given a value X, and the pointer type bit PTB is given a value, which indicates that the following pointer concerns a pointer to an entry in the reference table. The elements F-LSB and F-S in each case have values 16 or 1, which indicate that in the following iteration stage of the evaluation of the destination information only the 16th bit should be taken into consideration, which permits a distinction to be made between the virtual paths VPO and VPI.
The entry with the address X in the reference table 15 is ascribed to the virtual path VPO. It has a Used bit UB with the logic value "true", a following pointer F-PTR with the value Y and a pointer type bit PTB, which indicates that the following pointer points to the connection table. Since when a reference to the connection table 16 is found, analysis of the incoming destination information is complete, the element F-S
has the value 0 and F-LSB can have any arbitrary value.
The address X+1 of the reference table 15 is ascribed to the virtual path VPI.
It comprises a Used bit UB with the logic value "true", a following pointer F-PTR
with a value Z, a pointer type bit PTB, which indicates that the following pointer F-PTR points to the connection table 16, and the elements U-LSB and F-S with the values 1 or 2, which indicate that in the case of access to the connection table the Oth bit of the VCI is neglected and only bits 1 and 2 are analyzed.
The connection table receives entries at the addresses Y, Z, Z+1 and Z+2. In this case, the address Y receives an entry with the data of the transparent connection VPO, the address Z an entry with the data of the connection VPI, VC64, the address Z+1 data of the connection VPI, VC66 and the address Z+2 data of the connection VPI, VC68.
A
further entry at the address Z+3 is not used and therefore contains a Used bit UB with the logic value "false".
When connections are being established, it may be necessary to re-arrange the storage areas to shift entries of connections and to identify connecting data at storage locations, which are no longer ascribed to a connection, as invalid. In order to shift data blocks in the connection table, the data block is first copied to the new address, then the pointer in the reference table, pointing to this block, is changed and finally the original block is deleted. The same method is used to shift a block within the reference table.
As the above example shows, the number of recursive steps results from the number of blocks of coherent bits in the destination address to be analyzed, and may be different from cell to cell, in particular this number may also be greater than 2.
The multiplexer and its operating method have been described above particularly with reference to an ATM network, however it is obvious that they can be used in a large number of applications, where data are transmitted via nodes, which locally ascribe addresses to identify and transmit a data stream, so that these addresses must be changed when the data are forwarded from one node to the next. Thus, an application of the multiplexer and the method could be considered particularly also for so-called Multiprotocol Label Switching.
A preferred, but not exclusive use of the method and device lies in the area of ATM
(asynchronous transfer mode) networks. The asynchronous transfer mode (ATM) is used in modern, wide-band telecommunications networks. ATM is based on the transmission of data streams and data packets in cells of constant length. ATM
is connection-oriented, that is to say each transmitted cell can be clearly ascribed to a previously built-up or established connection. This operation uses destination information in the cell header, which is formed from the Virtual Path Identifier (VPI) and the Virtual Channel Identifier (VCI).
The VPI field in the NNI (Network Network Interface) mode comprises 12 bits, in the UNI (User Network Interface) mode 8 bits. The VCI field comprises 16 bits.
Altogether, therefore, it is possible to distinguish up to 22g connections.
The number of possible connections in an ATM multiplexer is considerably less than this theoretical limit, due to the fact that each built-up connection requires an entry in a table containing various parameters, which in the following are briefly described as routing information, for example the values of the VPI or VCI, which must be attached to the data packet when it is forwarded on an output channel, routing information, priorities etc.
The large number of connections which can be distinguished by VPI and VCI and the corresponding variety of their addresses lead to technical problems with the location of the routing information for a data packet. If use of the destination information, with which a data packet is received at a node of the network, was directly wanted for addressing a table of this node containing the routing information, a table would be needed, the size of which would be enough to accommodate the routing information for each possible value of the destination information therein. In order to reduce this storage requirement, a method is known to ascribe to each connection in a multiplexer a so-called internal address, the length of which depends on the maximum expected or feasible number of connections, which can be processed at the same time and to provide a connection table, which includes the routing information for all these connections and the size of which is selected dependent on the number of internal addresses.
Such an address, for example, containing 14 bits can be half as long as the destination information originally transferred with an ATM packet.
In order to find the routing information for a connection, it is necessary to convert the destination information transferred with a data packet, if necessary including the designation of an incoming connection, at which the data packet has been received, into the internal address. In the following, this destination information is described as destination address. Essentially, there are two methods for converting the destination address into the internal address:
First is conversion by means of an associative memory (Content Addressable Memory, CAM). With such a method, the destination address is fed to an associative memory, and as internal address this delivers back the address of which one of its storage locations this destination address is stored. The number of storage locations of such an associative memory does not need to be greater than the maximum number of connections to be processed; possible values of the destination address, for which no connection is established, are not stored in the associative memory.
Associative memories of this kind are, however, costly, and their costs increase disproportionately to their increase in size.
A second cheaper method for converting the address is a table method, in which only one section of the bits of the destination address is analyzed. If, for example, it is known that all virtual paths of a particular ATM network support a maximum of 64 channels, 6 bits are required for their clear identification. This means that 10 bits out of the 16 bits of the VCI field in the destination address can be ignored during conversion to the WO 02/43290 PCT/IBOl/02761 internal address, which reduces the storage requirement of the conversion table by a factor of 2'°. However, it is obvious that such a method results in substantial reduction in the flexibility of the ATM network and that the scaleability is lost in the direction of higher channel numbers.
Although this problem is illustrated here as an example of an ATM network, it always occurs with different types of networks, whenever a node of a data transmission network has to carry out processing steps on received data packets as a function of their destination information and the number of possible values of this destination information is substantially greater than the number of the connections or data flows, which the node can handle simultaneously.
Advantages of the invention A method for multiplexing data packets and a multiplexer are created by the present invention, which can be implemented economically and with low memory complexity and good scalability. A further advantage of the invention is that it permits transparent virtual paths, that is to say optionally the evaluation of a VCI value can be allowed or prevented in the multiplexer.
An additional advantage of the invention lies in the fact that it is able to support in a simple manner non-homogenous connection scenarios. In particular, transparent and non-transparent virtual paths as well as virtual paths with greatly varying numbers of virtual channels can be handled with ease by one multiplexer.
These advantages are achieved according to invention by the fact that routing information for the data packet is determined for a data packet provided with destination information, received at an input terminal of a multiplexer, on the basis of the destination information from a connection table and the data packet is output on the basis of the determined routing information on an output terminal of the multiplexer, whereby the destination information is broken down into an initial section and a subsequent section, and the initial section is used as address for addressing a reference table, that contains the entries defining the manner in which the subsequent section is to be analysed for finding the routing information, and on the basis of the entry addressed in such a way, a choice is made between at least two different methods for analyzing the subsequent section.
A first of these methods can be used if the addressed entry of the reference table contains a connecting pointer to an entry of the connection table. In this case, a destination entry of the connection table found on the basis of this connecting pointer is read and analyzed. The address of the destination entry is preferably calculated here on the basis of the connecting pointer and subsequent section. Thus, for example, the connecting pointer can be a pointer to the start of an area in the connection table, which contains a multiplicity of entries, and the numerical value of the subsequent section in each case can serve as offset for addressing a single one of these entries.
A second method can be used, if the addressed entry of the reference table contains a reference table pointer to a further entry of the reference table. In this case, a further entry of the reference table is read and analyzed at a location found on the basis of the reference table pointer.
In this case, appropriately for fording the location, the subsequent section is also consulted in addition to the reference table pointer. Preferably, this is done by breaking down the subsequent section into a new initial section and a new subsequent section, and by calculating the address of the further entry on the basis of the reference table pointer and the new initial section. The subsequent section can be repeatedly broken ' down into a new initial section and a new subsequent section as often as necessary, until the address of an entry, which contains a connecting pointer, that is to say which points to the connection table, is finally obtained.
In order to be able to break down the subsequent section into a new initial section and a new subsequent section, it is preferable that the addressed entry of the reference table also contains an instruction, which defines what bits of the subsequent section should belong to the new initial section and what bits to the new subsequent section.
In this way, great flexibility is achieved during analysis of the address, which makes the method particularly suitable for application in heterogeneous connection scenarios.
In principle, the bits of incoming destination information or of a subsequent section could be broken down in a completely arbitrary way into an initial section and subsequent section or new initial section and new subsequent section. Thus, it is not impossible that one bit of the incoming destination information or subsequent section is ascribed to the (new) initial section (or subsequent section), while higher and lower value bits are ascribed to the (new) subsequent section (or initial section).
Also, permutations of bits during breakdown into initial sections and subsequent sections are not impossible.
For the sake of simplicity, however, it is preferred that initial section and subsequent section in each case comprise successive bits of the destination information.
If the entire destination information does not have to be analyzed, in order to clearly identify a connection, the initial and subsequent sections are appropriately limited so that they are separated by bits, which are not to be analyzed and not ascribed during breakdown into initial or subsequent sections either to one or the other part.
For increased security, it can be proposed that in the individually addressed entry of the reference table and/or the connection table an instruction is also read, which indicates whether this entry is valid or otherwise, and that the process is aborted if the entry does not prove to be valid. If this happens, the node can deduce from this that it has received incorrect destination information and can request repeated transmission of the data packet concerned.
The destination information of a data packet is updated accordingly before it is re-output by the node on the basis of the routing information found in the connection table.
It is not necessary for all bits of the destination information to be changed, on the contrary the routing information preferably contains information, which defines what bits of the destination information should be changed and what not to be changed.
Further features and advantages of the invention will become evident from the following description of embodiments with reference to the attached figures wherein:
Fig. 1 schematically represents an ATM node with a multiplexer according to the invention;
Fig. 2 shows the structure of the multiplexer according to the invention;
Fig. 3 shows the format of an entry in the reference table of the multiplexer;
Figs. 4 and 5 show examples of the format of an entry in the connection table;
and Fig. 6 shows a flow chart of the method according to the invention.
Description of the preferred embodiments Fig. 1 shows a greatly schematized block diagram of a node 1 of an ATM
network, which contains a multiplexer 2 according to the invention. The node connects a multiplicity of input and output transmission circuits, here four such circuits, which are called 3a, 3b, 3c, 3d or 4a, 4b, 4c, 4d in each case. ATM cells are transmitted via the incoming transmission circuits to the node 1, which in each case contain destination information, on the basis of which the node 1 has to determine the output transmission circuit, on which the cell must be forwarded on. This destination information comprises a Virtual Path Identifier VPI which is 8 or 12 bits long in each case depending on the operating mode (LJNI or NNI) of the ATM network and a Virtual Channel Identifier VCI which is 16 bits long.
The ATM cells arriving via the transmission circuits 3a, 3b, 3c, 3d pass through input connections Sa, Sb, Sc, Sd of the node l, which forward on each received cell to the multiplexer 2, additionally linked with a characteristic port number for the respective input connection Sa, Sb, Sc or Sd. The entire incoming destination information of the cells received by the multiplexes 2 therefore comprises VPI, VCI and port number for each cell.
The object of the multiplexes 2 is to produce destination address information on the basis of this incoming destination information and to re-output this together with the cell on the basis of which the output transmission circuit 4a, 4b, 4c or 4d suitable for forwarding the cell can be selected, and on the basis of which if necessary a node structured accordingly, forming the other terminal of the selected output transmission circuit, can in turn again convert and forward on the address. Each output transmission circuit 4a, 4b, 4c or 4d is ascribed to an output connection 6a, 6b, 6c, 6d, which determines from among the ATM cells output by the multiplexes 2 on the basis of their destination address information those intended for the transmission circuit ascribed in each case and forwards these on to the transmission circuit.
The structure of the multiplexes 2 is shown in detail in Fig. 2. It comprises a control device 11, a combinatorial network 12, two groups of D flipflops 13, 14 and two memory elements 15, 16, of which element 15 is described in the following as reference table and element 16 as connection table. In this case, it is clear that the structure shown here is only given as an example and that there is a large number of other circuit possibilities to implement the multiplexing method performed by the multiplexes 2.
The function of the multiplexes 2 is explained in the following with reference to the flow chart in Fig. 6 and the data formats shown in Figs. 3 to 5.
The method is based on a destination address A of an ATM cell, which is fed to the combinatorial network 12 via an input 17. This destination address A, as indicated above, comprises port number, VPI and VCI of an ATM cell. The length of the port number is generally P bits, unless the number of the inputs of the multiplexes 2 is greater than 2p. In a first step S 1 of the method, this destination address A
is broken down into an initial section AO and a subsequent section A 1 of a definite pre-set length in each case. At the same time, the designations "initial section" and "subsequent section" are only used for the sake of clarity; the initial section does not need to comprise the first and the subsequent section does not need to comprise the following bits of the incoming destination information A, in principle the bits of the initial section and subsequent section can arbitrarily consist of the bits of the incoming destination information.
With the example described here, the P bits of the port number are split off as initial section AO with definite pre-set length; VCI and VPI remain as subsequent section A 1.
The combinatorial network 12 outputs the initial section AO received in such a manner to the D input of the D flipflop 13, into which it is transferred, directed by a control signal of the gate circuit 11 lying on the E input of the D flipflop 13.
Controlled by an external clock Clk, this first initial section is output as address to the connection table 15. By inserting the D flipflop 13 between combinatorial network 12 and connection table 15 it is possible to keep the destination address of the connection table 15 constant over several cycles of the clock Clk so that inexpensive, moderately fast components can be used for the extensive connection table 15.
The format of the entries in the reference table 15 is shown in Fig. 3. Each entry contains a so-called Used bit UB, an individual bit, which indicates whether the entry concerned is valid or otherwise.
This bit UB has a control function; when operating normally and if the destination address is error-free, the Used bit of an addressed entry must indicate its validity.
A substantial element of each entry is the following pointer F-PTR, which represents a pointer to a further table entry. To which of the two tables, reference table 15 or connection table 16, the pointer F-PTR points, is indicated by a pointer type bit PTB.
The length of the following pointer F-PTR is substantially less than that of the incoming destination information, typically it can be approximately half its length, for example 16 bits.
WO 02/43290 PCT/IBOl/02761 The output of the reference table 15 is connected to the control device 11 and the combinatorial network 12, in order to permit the entry to be analyzed.
Therefore the control device 11 in the event that the Used bit UB indicates that the entry is invalid, can deduce from this that when describing the reference table 15 an error must have arisen, and initiate the production of a corresponding error message.
If the pointer type bit indicates that the following pointer F-PTR concerns a pointer to the reference table 15 (step S4), the combinatorial network 12 in steps S5, S6 on the basis of the following pointer F-PTR and subsequent section A 1 of the incoming destination information calculates the address of a further entry of its reference table 15, which is accessed in a following cycle. To determine this address, the elements F-LSB
(Following LSB) and F-S (Following Size) of the entry are consulted in step S5.
These two elements specify the manner in which the subsequent section, which presently comprises the VPI and VCI of the incoming destination information, is broken down into a new initial section AO and a new subsequent section A1. Stated more exactly, the element F-LSB designates the number of that bit in the original subsequent section, which is to become the Least Significant Bit, LSB) of the new initial section AO
', and F-S indicates the length of this initial section in bits. Since the original subsequent section Al comprises 28 bits, in each case a length of 5 bits is sufficient for F-LSB and F-S, so as to be able to specify each of these 28 bits or an arbitrary length for the new initial section of between 1 and 28 bits.
As an example it is assumed that the new initial section AO ' should contain the VPI of the incoming destination information. In this case, F-LSB has the value 16 and the value of F-S can vary, depending on the number of virtual paths the ATM node 1, in which the multiplexer 2 is used, is designed for. If the node 1 is to transmit NNI
cells, F-S
obtains the value 12, when transmitting UNI cells it has the value 8. It should be directly understood however that by choosing other values for F-S analysis of higher value bits of the VPI can be selectively prevented. Operating with a F-LSB
value of more than 16 is also conceivable in order to prevent analysis of least significant bits of the VPI.
Result of the breakdown is a new initial section A1 ' of F-S bit width, which is added in step S6 as offset-value to the following pointer F-PTR determined previously, in order to form an address AO for renewed table access.
The method now returns to step S2, where by means of the address AO formed in this manner the reference table 15 is again accessed, in order to read a further entry there.
If examination of the Used bit UB in step S3 shows that the entry is invalid, an error must have occurred during transmission of the destination information A to the node 1.
This information can be used by the control device 11, in order to request a re-transmission of the cell by the node, which sent this.
In step S4 it is again examined whether the following pointer F-PTR is a pointer to the reference table 15 or to the connection table 16. If it again concerns a pointer to the reference table 15, the steps S5, S6, S2, S3 are repeated. If it concerns a pointer to the connection table 16, the method proceeds to step S7. In this step, subsequent section A1 is added as offset to the following pointer F-PTR, in order to produce an address of an entry in the connection table 16. In step S8, the combinatorial network 12 outputs the address received in such a manner via the D flipflop 14 to the connection table 16, in order to read the entry concerned.
A first example for the format of such an entry is shown in Fig. 4. The entry comprises a Used bit UB, which has the same function as the corresponding bit of an entry of the reference table. A further element NH (new header) 28 bits long contains new values for VPI and VCI, which in the case of non-transparent transmission are added to the ATM
cell as new destination information while they are forwarded via one of the outputs 4a to 4d.
In step S9, it is examined on the basis of this Used bit whether the entry found is valid or otherwise. If not, as in the case of examination in the step S3 re-transmission can be requested. If yes, the entry is analyzed, in order to produce destination address information for the data packet and to output the data packet, provided with this destination address information in step S 10.
Two further elements NH-LSB and NH-MSB (New Header-Least Significant Bit and New Header-Most Significant Bit) are needed as part of the routing information in the connection table 16, even though the multiplexer 2 should also be able to transmit data packets in a transparent manner, that is to say in at least a partially unconcealed manner of transmitting the incoming destination information. These two elements both 5 bits long designate in each case the most significant and the lowest-value bit, which will be affected by a change in address. In the event of non-transparent transmission, these elements each have the value 0 or 27, with the consequence that VPI and VCI of a cell are completely replaced in step S 10. If, for example, NH has the value 16, this means this that in the ATM cell output by node 1 only the VPI field is replaced in step S 10, which - depending on the mode - corresponds to 8 or 12 most significant bits of the destination information, on the other hand the VCI value remains unchanged. If the element NH-MSB has the value 23, then only 8 bits of the VPI can be changed, which corresponds to operation of the ATM network in the UNI mode.
In regard to the format of an entry in the connection table shown in Fig. 5 the two elements NH-LSB, NH-MSB are replaced by a 28 bit long element NHM (New Header Mask). The logic condition 0 or 1 of each element of this element indicates whether the corresponding bit of the destination information should be replaced in step S
10 by the value entered in the element NH, or whether the incoming destination information for this bit should remain unchanged. With this format, even greater flexibility can be achieved with regard to definition of transparent data channels, since arbitrary, even non-contiguous groups of bits of the destination information can be defined as not to be changed.
Further, in regard to the formats in Fig. 4 and 5, identical elements of an entry in the connection table are a UPC bit, which indicates whether a UPC function should be applied to this cell, and a UPC pointer UPC-PTR, which contains a pointer to the UPC
function ascribed to the incoming destination information. As a result, it is possible to keep the number of the independent UPC units (one per connection is required) lower than the total number of the connections processed by the multiplexes.
Further elements which can be present are: a Routing Tag RT, for example 32 bits long for internal routing in the multiplexes, an internal connection number ICN and a element PC, which indicates a priority class for the connection.
When the multiplexes is put to use for the first time, reference table 15 and connection table 16 must be initialized. Since no connections still exist, the Used bits UB of all entries are set to the logic value "false". If a connection is established or switched, an entry is written in the connection table 15 as well as one or several entries in the reference table 16. This will be demonstrated by way of an example. It is assumed that an input interface with the port number 27 uses virtual paths VPO and VPI. VPO
is transparent, virtual channels VC64, VC66 and VC68 are used in the VPI. In order to differentiate between the different connections, it is enough to evaluate the bit 0 of the VPI or bits 1 and 2 of the VCI of destination information.
A first entry necessary for switching the cells of the input interface 27 is registered at the address 27 of the reference table. Its Used Bit UB is given the logic value"true", the following pointer F-PTR is given a value X, and the pointer type bit PTB is given a value, which indicates that the following pointer concerns a pointer to an entry in the reference table. The elements F-LSB and F-S in each case have values 16 or 1, which indicate that in the following iteration stage of the evaluation of the destination information only the 16th bit should be taken into consideration, which permits a distinction to be made between the virtual paths VPO and VPI.
The entry with the address X in the reference table 15 is ascribed to the virtual path VPO. It has a Used bit UB with the logic value "true", a following pointer F-PTR with the value Y and a pointer type bit PTB, which indicates that the following pointer points to the connection table. Since when a reference to the connection table 16 is found, analysis of the incoming destination information is complete, the element F-S
has the value 0 and F-LSB can have any arbitrary value.
The address X+1 of the reference table 15 is ascribed to the virtual path VPI.
It comprises a Used bit UB with the logic value "true", a following pointer F-PTR
with a value Z, a pointer type bit PTB, which indicates that the following pointer F-PTR points to the connection table 16, and the elements U-LSB and F-S with the values 1 or 2, which indicate that in the case of access to the connection table the Oth bit of the VCI is neglected and only bits 1 and 2 are analyzed.
The connection table receives entries at the addresses Y, Z, Z+1 and Z+2. In this case, the address Y receives an entry with the data of the transparent connection VPO, the address Z an entry with the data of the connection VPI, VC64, the address Z+1 data of the connection VPI, VC66 and the address Z+2 data of the connection VPI, VC68.
A
further entry at the address Z+3 is not used and therefore contains a Used bit UB with the logic value "false".
When connections are being established, it may be necessary to re-arrange the storage areas to shift entries of connections and to identify connecting data at storage locations, which are no longer ascribed to a connection, as invalid. In order to shift data blocks in the connection table, the data block is first copied to the new address, then the pointer in the reference table, pointing to this block, is changed and finally the original block is deleted. The same method is used to shift a block within the reference table.
As the above example shows, the number of recursive steps results from the number of blocks of coherent bits in the destination address to be analyzed, and may be different from cell to cell, in particular this number may also be greater than 2.
The multiplexer and its operating method have been described above particularly with reference to an ATM network, however it is obvious that they can be used in a large number of applications, where data are transmitted via nodes, which locally ascribe addresses to identify and transmit a data stream, so that these addresses must be changed when the data are forwarded from one node to the next. Thus, an application of the multiplexer and the method could be considered particularly also for so-called Multiprotocol Label Switching.
Claims (30)
1. Method for multiplexing data packets in a node (1) of a transmission network, in which data packets provided with destination information (A; VPI, VCI) are received at an input connection (5a, 5b, 5c, 5d), routing information for a data packet is identified on the basis of the destination information from a connection table (16) and the data packet is output on the basis of the routing information determined at an output terminal (6a, 6b, 6c, 6d), characterized in that the destination information is broken down into an initial section (AO) and a subsequent section (A1), and that the initial section (AO) is used as address for addressing a reference table (15), which contains entries defining the manner in which the subsequent section (A1) is to be analyzed for fording the routing information, and that a selection is made on the basis of the entry addressed in such a manner between at least two different methods for analyzing the subsequent section (A1).
2. Method according to claim 1, characterized in that if the addressed entry of the reference table (15) contains a connecting pointer (F-PTR) to an entry of the connection table (16), a first method is selected in which routing information is read and analyzed in a destination entry of the connection table (16) found on the basis of this connecting pointer (F-PTR).
3. Method according to claim 2, characterized in that the address of the destination entry is calculated on the basis of the connecting pointer (F-PTR) and the subsequent section (A1).
4. Method according to claim 1, 2 or 3, characterized in that if the addressed entry of the reference table (15) contains a reference table pointer (F-PTR) to an entry of the reference table (15), a second method is selected, in which a further entry of the reference table (15) is read and analyzed at a location found on the basis of the reference table pointer (F-PTR).
5. Method according to claim 4, characterized in that the subsequent section (A1) is again broken down into an initial section (A0 ') and a subsequent section (A1 ') and that the address of the further entry is calculated on the basis of the reference table pointer (F-PTR) and the new initial section (A0 ').
6. Method according to claim 5, characterized in that the steps specified in claim 5 are repeated as often as necessary, until the address of an entry, which contains a connecting pointer, is obtained.
7. Method according to claim 5 or 6, characterized in that an instruction (F-LSB, F-S) in the addressed entry of the reference table (15) is also read, which defines what bits of the subsequent section (A1) belong to the new initial section (A0 ' ) and what bits belong to the new subsequent section (A1 ').
8. Method according to any one of the above claims, characterized in that initial section and subsequent section (A0, A1; A0 ', A1 ') in each case comprise a number of successive bits of the destination information (VPI, VCI).
9. Method according to claim 7 or 8, characterized in that initial section (A0, A0 ') and subsequent section (A1, A1') are separated by one or several bits, which remain out of consideration.
10. Method according to any one of the above claims, characterized in that an instruction (UB) in the addressed entry of the reference table (15) and/or the connection table ( 16) is read, which indicates whether the entry is valid or otherwise, and that the method is aborted if the entry does not prove to be valid.
11. Method according to any one of the above claims, characterized in that the destination information of a data packet is updated before it is output on the basis of routing information (NH, NH-LSB, NH-MSB; NH, NHM) found in the connection table ( 16).
12. Method according to claim 11, characterized in that information (NH-LSB, NH-MSB; NHM) in the connection table (16) is read and analyzed, which defines what bits of the destination information are to be changed.
13. Method according to any one of the above claims, characterized in that the data packets are ATM cells.
14. Method according to claim 13, characterized in that the received destination information (A) comprises an instruction concerning the input connection (5a, 5b, 5c, 5d), via which the data packet has been received, a Virtual Path Identifier (VPI) and a Virtual Channel Identifier (VCI).
15. Multiplexer (2) for a node (1) of a transmission network for determining routing information to forward data packets on the basis of destination information (A; VPI, VCI) ascribed to each data packet, with a connection table (16) for storing the routing information, characterized by means (11, 12) for breaking down the destination information into an initial section (A0) and a subsequent section (A1) and a reference table (15), which can be addressed on the basis of the initial section, which contains entries defining the manner, in which the subsequent section (A1) is to be analyzed for fording the routing information.
16. Multiplexer according to claim 15, characterized in that at least one entry of the reference table (15) contains a connecting pointer (F-PTR) to an entry of the connection table (16).
17. Multiplexer according to claim 16, characterized by an address generator (12) for calculating the address of the destination entry in the connection table (16), which contains the routing information, on the basis of the connecting pointer (F-PTR) and the subsequent section (A1).
18. Multiplexer according to any one of claims 15 to 17, characterized in that at least one entry of the reference table (15) contains a reference table pointer (F-PTR) to a further entry of the reference table (15).
19. Multiplexer according to claim 18, characterized by an address generator (12) for calculating the address of the further entry in the reference table (15) on the basis of the reference table pointer (F-PTR) and a new initial section (A0') separated from the subsequent section (A1).
20. Multiplexer according to claim 18 or 19, characterized in that the entry containing at least one of the reference table pointers (F-PTR) also contains an instruction (F-LSB, F-S), which defines what bits of the subsequent section (A1) belong to the new initial section (A0'), to be separated from the subsequent section (A1), and what bits belong to a new subsequent section (A1').
21. Multiplexer according to any one of claims 15 to 20, characterized in that each entry of the reference table (15) has a pointer (F-PTR) and a characteristic bit (PTB), which identifies the pointer (F-PTR) as reference table pointer or as connecting pointer.
22. Multiplexer according to any one of claims 15 to 21, characterized in that the initial section (A0, A0') and subsequent section (A1, A1') in each case comprise a number of successive bits of the destination information (A).
23. Multiplexer according to any one of claims 18 to 22, characterized in that each entry of the reference table (15), which contains a reference table pointer, in each case also contains an instruction concerning the first and the last bit of the new initial section or an instruction concerning the first or the last bit (F-LSB) and concerning the bit number (F-S) of the new initial section.
24. Multiplexer according to any one of claims 15 to 23, characterized in that each entry of the reference table (15) and/or the connection table (16) also contains an instruction (UB) about whether the entry is valid or otherwise.
25. Multiplexes according to any one of claims 15 to 24, characterized in that the routing information, stored in the connection table (16), comprises destination information (NH), to be sent with the data packet.
26. Multiplexes according to claim 25, characterized in that the routing information also contains an instruction (NH-LSB, NH-MSB; NHM) about the bits of the destination information to be changed.
27. Multiplexes according to claim 26, characterized in that the instruction concerning the bits to be changed specifies a first and a last bit to be changed (NH-LSB, NH-MSB) or a first or last bit to be changed and their number.
28. Multiplexes according to claim 26, characterized in that the instruction concerning the bits to be changed comprises a bit mask (NHM) to be linked with the received destination information.
29. Multiplexes according to any one of claims 15 to 28, characterized in that it is an ATM multiplexes.
30. Multiplexes according to claim 29, characterized in that it is designed for processing destination information (A), which comprises an instruction concerning the input connection (5a, 5b, 5c, 5d), via which the data packet has been received, a Virtual Path Identifier (VPI) and a Virtual Channel Identifier (VCI).
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10058457.8 | 2000-11-24 | ||
| DE2000158457 DE10058457A1 (en) | 2000-11-24 | 2000-11-24 | Method and device for multiplexing data packets |
| PCT/IB2001/002761 WO2002043290A2 (en) | 2000-11-24 | 2001-11-23 | Method and device for multiplexing data packets |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2430943A1 true CA2430943A1 (en) | 2002-05-30 |
Family
ID=7664564
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002430943A Abandoned CA2430943A1 (en) | 2000-11-24 | 2001-11-23 | Method and device for multiplexing data packets |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP1340405A2 (en) |
| JP (1) | JP2004515115A (en) |
| AU (1) | AU2002219424A1 (en) |
| CA (1) | CA2430943A1 (en) |
| DE (1) | DE10058457A1 (en) |
| WO (1) | WO2002043290A2 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2507756B2 (en) * | 1987-10-05 | 1996-06-19 | 株式会社日立製作所 | Information processing device |
| SE515275C2 (en) * | 1992-12-14 | 2001-07-09 | Ericsson Telefon Ab L M | packet data network |
| EP0680236A1 (en) * | 1994-04-29 | 1995-11-02 | International Business Machines Corporation | Apparatus for swapping input values into corresponding output values |
| US5956336A (en) * | 1996-09-27 | 1999-09-21 | Motorola, Inc. | Apparatus and method for concurrent search content addressable memory circuit |
| GB2325321B (en) * | 1997-05-12 | 2001-06-06 | Applied Marketing & Technology | Associative memories |
-
2000
- 2000-11-24 DE DE2000158457 patent/DE10058457A1/en not_active Withdrawn
-
2001
- 2001-11-23 WO PCT/IB2001/002761 patent/WO2002043290A2/en not_active Application Discontinuation
- 2001-11-23 CA CA002430943A patent/CA2430943A1/en not_active Abandoned
- 2001-11-23 EP EP01997912A patent/EP1340405A2/en not_active Withdrawn
- 2001-11-23 JP JP2002544894A patent/JP2004515115A/en active Pending
- 2001-11-23 AU AU2002219424A patent/AU2002219424A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| EP1340405A2 (en) | 2003-09-03 |
| DE10058457A1 (en) | 2002-06-13 |
| AU2002219424A1 (en) | 2002-06-03 |
| JP2004515115A (en) | 2004-05-20 |
| WO2002043290A2 (en) | 2002-05-30 |
| WO2002043290A3 (en) | 2002-08-08 |
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