CA2349033A1 - Initial plasma treatment for vertical dry etching of sio2 - Google Patents
Initial plasma treatment for vertical dry etching of sio2 Download PDFInfo
- Publication number
- CA2349033A1 CA2349033A1 CA 2349033 CA2349033A CA2349033A1 CA 2349033 A1 CA2349033 A1 CA 2349033A1 CA 2349033 CA2349033 CA 2349033 CA 2349033 A CA2349033 A CA 2349033A CA 2349033 A1 CA2349033 A1 CA 2349033A1
- Authority
- CA
- Canada
- Prior art keywords
- plasma treatment
- sio2
- dry etching
- plasma
- initial plasma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Abstract
A method of making a semiconductor device is disclosed wherein a plasma treatment is carried out prior to carrying out an etch step.
Description
Initial plasma treatment for vertical dry etching of Si02 Background of the Invention I. Field of the Invention This invention relates to a method of making semiconductor devices, and in particular photonic devices with vertical sidewalls.
2. Description of Related Art The verticality of Si02 sidewalls is critical, particularly for photonic devices. The verticality depends on the sample temperature. It i;> imperative to have a good control of the sample's temperature. However, the sample being etched does not reach a stable-constant temperature before ~ 1 min after starting the plasma (temperature rise induced by ion bombardment); leaving rounded edges (non-verticality near the top of the sidewalk).
Present technology either does nor recognize this problem (and associated advantages) or simply tries to live with it. Present technology is not capable of providing deep, fast and good control of verticality in etching Si02.
Summary of the Invention According to the present invention there is provided a method of making a semiconductor device wherein a plasma treatment is carried out prior to carrying out an etch step.
It has been found surprisingly that by the inventive technique of adding a plasma treatment just before the etch step, a dramatic improvement in the verticality of etched sidewalk can be obtained.
By using an 02 plasma or any inert gas, the sample is. brought to a constant temperature before starting the real plasma etching conditions.
The process parameters (particularly the temperaturEa) should remain constant during etching.
Brief Description of the Drawings The invention will now be described in more detail, by way of example, only with reference to the accompanying drawings, in which:-Figure 1 is an SEM image of a Si02 ridge etched with a non-constant sample temperature, in particular showing a rounded rough edge just below the surface or the hardmask; and Figure 2 is an SEM image of a Si02 ridge etched with the new process at stable sample temperature.
Detailed Description of the Invention 20 During the manufacture of a photonic device vertical Si02 sidewails are formed by etching using a conventional dry plasma etching technique. Just prior to carrying out the dry etch step, a simple and efficient plasma treatment is performed just before the etch step. During subsequent etching the :process parameters, and in particular the temperature, are maintained constant.
By using an OZ plasma or any inert gas plasma, the sample is brought to a constant temperature before starting the plasma etch process.
The following SEM image shown in Figures 1 and 2 illustrate the improvement obtained using the new process: Figure 1 shows a rounded edge induced by a non constant etching temperature, while the Figure 2 shows a sharp edge obtained by using the novel process. It will be seem that the edge is sharp, the straight sidewall starts just below the hardmask.
Present technology either does nor recognize this problem (and associated advantages) or simply tries to live with it. Present technology is not capable of providing deep, fast and good control of verticality in etching Si02.
Summary of the Invention According to the present invention there is provided a method of making a semiconductor device wherein a plasma treatment is carried out prior to carrying out an etch step.
It has been found surprisingly that by the inventive technique of adding a plasma treatment just before the etch step, a dramatic improvement in the verticality of etched sidewalk can be obtained.
By using an 02 plasma or any inert gas, the sample is. brought to a constant temperature before starting the real plasma etching conditions.
The process parameters (particularly the temperaturEa) should remain constant during etching.
Brief Description of the Drawings The invention will now be described in more detail, by way of example, only with reference to the accompanying drawings, in which:-Figure 1 is an SEM image of a Si02 ridge etched with a non-constant sample temperature, in particular showing a rounded rough edge just below the surface or the hardmask; and Figure 2 is an SEM image of a Si02 ridge etched with the new process at stable sample temperature.
Detailed Description of the Invention 20 During the manufacture of a photonic device vertical Si02 sidewails are formed by etching using a conventional dry plasma etching technique. Just prior to carrying out the dry etch step, a simple and efficient plasma treatment is performed just before the etch step. During subsequent etching the :process parameters, and in particular the temperature, are maintained constant.
By using an OZ plasma or any inert gas plasma, the sample is brought to a constant temperature before starting the plasma etch process.
The following SEM image shown in Figures 1 and 2 illustrate the improvement obtained using the new process: Figure 1 shows a rounded edge induced by a non constant etching temperature, while the Figure 2 shows a sharp edge obtained by using the novel process. It will be seem that the edge is sharp, the straight sidewall starts just below the hardmask.
Claims (5)
1. A method of making a semiconductor device wherein a plasma treatment is carried out prior to carrying out an etch step.
2. A method as claimed in claim 1, wherein the plasma treatment is carried out with an oxygen or inert gas plasma.
3. A method as claimed in claim 1, wherein said etch step is carried out to produce vertical sidewalls.
4. A method as claimed in claim 3, wherein said etch step is a dry plasma etch.
5. A method as claimed in claim 1, wherein said semiconductor device is a photonic device.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2349033 CA2349033A1 (en) | 2001-05-28 | 2001-05-28 | Initial plasma treatment for vertical dry etching of sio2 |
| PCT/CA2002/000785 WO2002097866A2 (en) | 2001-05-28 | 2002-05-28 | Method of etching dielectric materials |
| AU2002302264A AU2002302264A1 (en) | 2001-05-28 | 2002-05-28 | Method of etching dielectric materials |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2349033 CA2349033A1 (en) | 2001-05-28 | 2001-05-28 | Initial plasma treatment for vertical dry etching of sio2 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2349033A1 true CA2349033A1 (en) | 2002-11-28 |
Family
ID=4169127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2349033 Abandoned CA2349033A1 (en) | 2001-05-28 | 2001-05-28 | Initial plasma treatment for vertical dry etching of sio2 |
Country Status (3)
| Country | Link |
|---|---|
| AU (1) | AU2002302264A1 (en) |
| CA (1) | CA2349033A1 (en) |
| WO (1) | WO2002097866A2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8679970B2 (en) | 2008-05-21 | 2014-03-25 | International Business Machines Corporation | Structure and process for conductive contact integration |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4445966A (en) * | 1983-06-20 | 1984-05-01 | Honeywell Inc. | Method of plasma etching of films containing chromium |
| US5877032A (en) * | 1995-10-12 | 1999-03-02 | Lucent Technologies Inc. | Process for device fabrication in which the plasma etch is controlled by monitoring optical emission |
| US6140612A (en) * | 1995-06-07 | 2000-10-31 | Lam Research Corporation | Controlling the temperature of a wafer by varying the pressure of gas between the underside of the wafer and the chuck |
| WO1997015073A1 (en) * | 1995-10-17 | 1997-04-24 | Asm Japan K.K. | Semiconductor treatment apparatus |
| JPH11162958A (en) * | 1997-09-16 | 1999-06-18 | Tokyo Electron Ltd | Plasma treating device and plasma treating method |
| DE69723566T2 (en) * | 1997-12-17 | 2004-06-03 | Tokyo Electron Ltd. | Process for treating a semiconductor substrate |
-
2001
- 2001-05-28 CA CA 2349033 patent/CA2349033A1/en not_active Abandoned
-
2002
- 2002-05-28 AU AU2002302264A patent/AU2002302264A1/en not_active Abandoned
- 2002-05-28 WO PCT/CA2002/000785 patent/WO2002097866A2/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8679970B2 (en) | 2008-05-21 | 2014-03-25 | International Business Machines Corporation | Structure and process for conductive contact integration |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2002097866A2 (en) | 2002-12-05 |
| WO2002097866A3 (en) | 2003-07-10 |
| AU2002302264A1 (en) | 2002-12-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Dead |