CA2257659C - Restricted information distribution system apparatus and methods - Google Patents

Restricted information distribution system apparatus and methods Download PDF

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Publication number
CA2257659C
CA2257659C CA 2257659 CA2257659A CA2257659C CA 2257659 C CA2257659 C CA 2257659C CA 2257659 CA2257659 CA 2257659 CA 2257659 A CA2257659 A CA 2257659A CA 2257659 C CA2257659 C CA 2257659C
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cell
pixel
data
video
information
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CA 2257659
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French (fr)
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CA2257659A1 (en
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Joseph S. Nadan
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Market Data Corp
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Market Data Corp
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Abstract

Authorized decoders (60) are provided with enable reception keys (66) so that subsequently transmitted data having an information identification code matching (65) a reception key (66) at a decoder-receiver may be retrieved for subsequent display on the video screen. Tile messaging (72.1) and cellular micrographic transmission techniques are used to reduce the volume of data transmitted to change update data, wherein cells (72.1) of characters are transmitted as one byte of data and cells (72.1) of pixel data are transmitted a plurality of bytes of data. Each decoder-receiver (60) may have a plurality of video screens separately and uniquely identified such that encoded update data and other messages are transmitted for specific video screens. The system includes multiplexing financial market information and television program information signals, and transmitting the multiplexed signals to the decoder-receivers for selectively displaying different combinations of information.

Description

CA 022~76~9 1999-01-12 -W093l23~ PCT/US93/04361 ORRI8-lD

RESTRICTED lN~OK~ATION
DISTRIBUTION SYSTEM APPARATUS AND METHODS

F~eld of the Tnvent~on The subject invention rel_tes to the distribution of information and, more particularly, for distributing this information in a secure _nd restricted manner to a plurality of users.
Back~. ~UIId Of The Invention Applic_nt and other related companies _re in the business of distributing realtime financial market information to various clients who use this inform_tion to c_rry on their business. When a client subscribes for this service, An agreement is entered into in which the client indicates what information is desired And how many video screens will be displaying the information. Based on these parameters, a fee is assessed to the client and the information then is transmitted to the client.
Typically, this financial market information is transmitted to clients as one or more pages or records that may be displayed on a video screen, portions of which, from time to time, are updated to reflect changes in the market information. Various clients subscribe to view different specific y~OU~ of these pages and/or records.
An early method of distributing market information was ~ based upon the transmission of , ~ingle p_ge of real time digital information over A ~ingle telephone line. Page-oriented information (ROW ~, COL ~, C~ CTER STRING) was ~ent from the information vendor's computer over a tel~phone network to a controller, provided by the information vendor, located at the client site. The page-oriented information CA 022~76~9 1999-01-12 W093/23 ~ PCT/US93/04~1 was cubsequently ~o.,~e~Led to video by a video generation unit within the ~o..L.oller. The video ~u-~uL was then conn~cted to a video screen by a single coaxiAl cable.
EAch full page was repeatedly transmitted in video At a field rate for realtime displAy, ~imilar to that of a television transmission. Howeve~, once the video signal was produced, there was nothing, except the personal integrity of the client, to prevent the client from connecting Any number of video screens to A video distribution amplifier connscted to the controller, driving A larger number of video screens above and beyond the number stated in the agreement. This practice dilutes the revenues to which the information vendor would ordinarily be entitled.
This Architecture was costly and unreliable because of the large amount of hardware needed to place financiAl information on a large number of trading desks. For example, if a client~s trading room had thirty traders, each trader needed his own single-user system resulting in thirty keyboards, thirty controllers with thirty internal video generation units, thirty telephone cables, thirty modems, thirty COA~ A l video cables, and thirty video screens to receive and display the required financial information.
This technology also limited the screen presentation format to what was provided by the information vendor. When traders were only interested in one or two fields of information on a screen, they would have to display the entire page of information. If they wanted to look at one or more fields of information on a &econ~ screen at the same time, _n entire additional single-user system would be required. Further, when two traders wanted to look at the same page, they would either have to have two separate single-user systems or the video information would be redistributed to a ~slave~ video screen making it difficult for the information vendor to know how many video screens were connected to a given ~o~ oller and hence how many people were viewing their information. This made billing WOg3/23~8 PCT~US93J~ ~1 difficult ~nd usually created a ~t_eF- of 6urpri~e client-site vi6its that left both information vendor and client t-nh~ppy .
The development of multi-user 6ystems re~l~ce~ the amount S of required hardware and enabled user6 to 6hare resources and view common information. In multi-u6er 6ystems, e~ch trader had one keyboard and 6everal video ~creens. Through the u~e of video ~wi~ching t~chn~ques, thirty trader~ could ~hare perhap6 ten or fifteen col.Lroller6 and contend for their use. Since many trader~ are part of a trading group that uses essentially the same financial market information, --the probability of blocking (not having a co,-LLoller available to fulfill a new page reguest) was 6mall.
Such multi-user 6ystems helped reduce costs by reducing the number of controllers, keyboards, and 6ystem cabling, but did not solv~ either the billing problems or Allow the user to customize screen presentation formats.
~ater, single teleF~onQ line, multi-page distribution systems were developed which reduced the required number of telephone lines. The information syntax for these multi-page sou~er was slightly modified to (PAGE ~, ROW ~, COL #, CHARACTER STRING). User~ of ~uch systems also could create composite pages (fields from different pages displayed simultaneously on one video ~creen) and calculate and insert additional value-added information (e.g., bond yield to maturity). By doing 60, customized ouL~h~ di~play pages could be created ~howing only the information and value-added calculations the user wanted to see.
Users developing value-added applications based upon page oriented data had to ~ssign a symbolic name to an '~ information field located at a specific display location of the input ~ource page. When the information vendor changed ~' the presentation format of the information (i.e., the location of a specific data element), a6 often happens when financial instruments are either added or deleted, the value-added application had to be modified. To overcome CA 022~76~9 1999-01-12 W093/23~ PCT/US93/~361 this difficulty, and to ~upply b~sic information without di~play p~rameters, the information vendor created record-oriented s~u~r~ using the ~ynt~x (SYMRQrTC NAME, CHARACTER
STRING). Examples of ~uch a ~ystem are the Reuters Integrated Data Network and the Telerate TIQ Feed.
Despite the foregoing advance~ in the field of electronic fin~nci~l information di~tribution systems, ~, e..~ 6ystems still allow video ~creens to be added and/or moved freely without either the information vendor~s knowledge or ~onrent. Further, each video screen must be con~ected by its own single-video ~home-run~ cable, i.e., a cable that typically runs for hundreds of feet between the trading floor where the video ~creen is located and the equipment room where either a cGI.Lloller, video switch ou~u~ or a host computer is located.

Summary Of The Invent~on An object o, the present invention is to provide a system capable of ~ecurely providing restricted information.
A further object of the present invention is to provide a system which is capable of uniquely identifying each of the video screens Authorized to display information, to restrict this information to only these individual video screens, to identify which of the information these video screens are to display, and to ~resent only authorized information on each and every video screen; unauthorized video screens would only present unintelligible transmogrified versions of the information.
It al50 i8 a object of the present invention to provide a financial information distribution system that i6 capable of taking inputs simultaneously from both multiple information page andlor record-oriented input ~ources (e.g. video, digital and/or live television) and a multitude of keyboards, to create a multitude of different o~u~
displays for concurrent display on a multitude of video screens all interconnected by a single cable, ~uch that the CA 022~76~9 1999-01-12 W093/23~ -PCT/US93/0436t video s~.ae..~ may contain different combinations of portions of different input 6vU~CeS of information.
It is a further ob~ect of the ~rf~ent invention to provide a financial information distribution system in which each video screen has a unigue display identification code that is used to authorize viewing and/or to permission what input source information each individual video screen will be capable of displaying at any given time.
It is a another object of the present invention to facilitate the ability to provide each user's video ~creen (8) with a customized ouL~L display.
It is yet another object of the ~ ent invention to reduce the cost of transmitting and displaying financial market updates to numerous users.
It i~ further object of the present invention to provide a single host computer device to D~G~L a plurality of users and an even larger plurality of video screens for securely distributing restricted inform~tion to one or more authorized video screens simultaneously. It is another object to allow rapid response to user request~ to view new or additional source of information.
It is Another object to provide for distributing information in a tile format whereby each user can assign a location on that user'~ video screen for display of the tile, and the same display information may be displayed on different locations on different video screens and simult~n~t~sly updated. It is another ob~ect to ~ o~L a larger video screen to provide for displaying tiles from a plurality of information input Sv~LC~_ simultaneously.
Applicant has reco~zed that usu~lly only small portions of the input page or record source information change over a small time, for example, the time oo~.esron~ng to one field time of displayed video. It is, therefore, neco~-ry to transmit only the information which is changing as update data and then to store this update data, along with the CA 022~76~9 1999-01-12 W093/239~8 PCT/US93/~36l ~nchAnged data, in a memory at the video screen for subsequent di~play.
It is, therefore, another object to p~ep~ocess video signals to identify the ch~nged display information to be displayed prior to inputting the video information into a display information distribution system, thereby minimizing the amount of ch~nnel bandwidth nPcesfi~ry to distribute the information.
It is another object of the invention to provide for preprocessing digital and analog video signals for display information including financial market information and - television ~LoyLam information signals. It is another object to provide for preprocessing composite and non composite video signals. It is yet another object to provide a switchable device that can process information in color and monochromatic video signals.
It is another object of the invention to provide a modular residual video converter device that can be constructed as a small printed circuit assembly so that one assembly is used for each source of video signals and several assemblies can be combined onto a single printed circuit board for ease of packaging and e~r~nsion.
It is another object of the present invention to improve the efficiency and messaging capacity of an information distribution system by converting incoming video signals having successive frames of display information to digital video messages identifying the pixel changes from one frame to the next.
Applicant also has recogn;zed that users typically want to view only a portion of a full page or record of source information provided by the vendor and therefore use several video screens displaying different sources of information so that the information they wish to view is concurrently displayed on multiple screens.
With these facts in mind, the above objects are achieved in a system for securely providing restricted information, , . . .. . . . . .. .. .. .

CA 022~76~9 1999-01-12 WOg3~3gS8 PCT/US93/04361 wherein the ~y~tem includes an e~o~er for ~nco~ng update data for updating various tiles (i.e., portion~ of pages or records) of di~play information, and a plurality of ~Pco~ers for ~coA i ng said update data and generating said various ouL~- display~ on video ~creens, characterized in that ~aid enco~r comprises means for generating a first data ~tream, said first data ~tream including respective ~ets of one or more unique display identification codes identifying each video screen and one or more information identification codes for each of ~aid tiles, said sets being indicative of the tiles, i.e., each particular portion of display -information, each video screen of each client or user is authorized to receive; means for generating a seguence of Fecon~ dat~ streams, each of said ~-: Dn~ data ~treams including one of ~aid individual information identification codes, coordinates of an area in a relevant video screen that is to display update data for the portion of display inform~tion, and the respective update data; and ~eans for transmitting said first data ~tream followed by said sequence of recon~ data streams; and in that each of said decoders comprises a video screen; means for identifying the relevant video screen with one of said unique display identification codes; means for recognizing said one unique display identification code and for ~toring the information 2S identification codes in the associated set with said one unique display identification code; means for retrieving said di~play coordinates of the update data corre6pon~ing to each of said stored information identification codes; means for storing said update data at the related coordinates for subsequent display on the video screen; and means for selectively displaying said stored updated display information on the video screens.
In accordance with a preferred embodiment, the ~nco~r (also referred to as a transmitter) i~ a mi~.o~ r-Qr based device that transmits a high bandwidth digital and/or analog signal over a single coaxial cable. The encoAer - CA 022~76~9 1999-01-12 W093/239~ PCT/US93/~361 manages communications between a host computer and the plurality of AecoAers (also referred to as receiver~), caches those particul~r portions of display inform~tion that are being viewed on video screens, and stores symbolic data elements. All data changes and/or specific instructions sent to any one or all of the decoA~rs originates in an application rl~nn~ng on the host computer, and is transmitted via a digit~l-video (DV) bus from the encoA~r to the d~roA~r(s). A delta-modulation type of communication protocol is used to greatly reduce the amount of transmitted information. Unlike a video switch environment, in which almost the same information is transmitted sixty times a r~ - ~nA ~ only display screen changes are signaled.
Display ch~nges are transmitted by tile mes~aging, i.e., tran~mitting the portion of the page or record of financial market information that contains the changed financial market information within a tile of horizontally and vertically ccntiguous cells. Each tile is given an information identification code and has corresponAing data - such that authorized users of the data are enabled with the corresponding information identification code as a symbolic name or reception key for identi'ying the particular tile by its symbolic name or reception key and receiving and retrieving the update data. Further, the tile mAy be given a default size and display loc~tion on a video ~creen, a user-defined size and display location, or both, ~uch that the transmitted data is mapped into any user-defined location as it is stored for display on the video screen.
Some of the transmitted data may not be stored or displayed when the user-defined tile i5 smaller than the transmitted tile.
The cost associated with transmitting the same data for different tiles (pages or records) of information can be greatly reduced in ~ccord~nce with the present invention, by initializing the location of ~n individual data field, through the use of a message identifying (i) the information CA 022~76~9 1999-01-12 -W093~9~8 PCT/US93/04361 _g_ identification code for a particular source page or ~L_v d of display information, (ii) the information identification code for the specific information field tl~ou~l- the use of a 6ymbolic name of a tile contAin~ng the individual data field, and (iii) a location in which the data of the data field are to appear on the particular tile. After this initialization, the information identification code for the symbolic name can be transmitted _long with data, without any display coordinate information, _nd each init~ A l~7ed video screen that displays the data as~ociated with the symbolic name is updated 6imult~neo~1y through the use of :this single data message and previously provided dicplay coordinates.
Each d~coAer receives at least all transmitted messages for its video screens and stores the information to be displayed, i.e., the screen image, in an internal picture store memory. Each AecoAer selects out and ~G~ e~ only those messages on the DV bus that are directed to its video screens or to the AecoAPr. Thus, each decoAer may have more than one video screen and a unique display identification code for each video screen. Each video screen has a unique identification code that ~u~o~Ls permi~sioning of restricted display information to be viewed and is capable of displaying simultaneously either color or monochromatic text and/or pixel based graphics, as well as live TV
pictures. In addition, the decoder can detect and directly pass through unencoAPA video signals to its video ~creens.
Commercially available keyboards and mice may be provided to send information request signals via the AecoAer to a ~ol.L~ol bus connecting the plurality of decoders to the e~co~r or host computer and to define tile size and display locationc. The keyboard optionally may include an internal ~CD display.
A residual video converter (RVC) device allows both view-only and interactive video sources to be utilized on the system. The RVC device accepts one or more video inputs, CA 022~76~9 1999-01-12 W093~2~ PCT/US93/04361 ~On~eL~8 them into a DV bu~ message format conta~n~ng only video ~creen changes suitable for transmission to the ~D~oders over the DV bus, and directly interfaces with the enco~er. Thus, the encoA~r mAy transpArently pass the RVC
ou~L signals at a~.G~iate times.
A television feed converter (TFC) device allows realtime television sources to be utilized on the sy~tem. The TFC
device accepts one or more television inputs, converts them into a format ~uitable for transmission to the ~eco~?r~ over the DV bus, and directly interfaces with the enco~er. The ~nco~er may transparently pass the television ~.G~.am information signals at a~G~iate times.
In addition, financial market information may be brought into the ~ystem via a commercially available Digital Interface Board (DIB) device. On larger systems, the DIB
device also may be configured to manage the cG,IL~ol bus.
The DIB device also allows for authorized individuals to gain remote access to the system, for example, by u6e of passwords. For example, the information vendor may use the interface remotely to ~authorize~ clients to use and/or view predefined subsets of their source information (e.g., to increase the number of authorized video screens). The vendor also is _ble to gather utilization statistics from each client site which i6 useful for marketing and/or billing ~u~Gses. The operator of the system may use the interface remotely to provide routine ~oftware maintenAnce and upgrades, modification of exi~ting composite page definitions, downlo~ng of new composite pages and periodic monitoring of system performance. The client ~ystem administrator may use the remote interface to log onto the system from home or any other remote location.
One advantage of the present invention is that it i8 sufficiently flexible to adapt for use as any of a stand- -alone system in a small sygtem environment having only a digital data feed which the enco~er distributes to a plurality of decoders, an çnhAncçment to an existing system .

CA 022~76~9 1999-01-12 W093~239~ . PCT/US93/~361 having a video 6wi~ohi ng system and user int-rface hardware 6uch that the encoA~r ou~ is connected to a single shared input and pAr-e~ to one or more ~u~u~ 8 on the video switch to the plurality of u6ers, a work station, and a large sy6tem including, for example, separate mach;ne~ for providing value-added calculations.

Descri~tion Of The ~r~win~S
With the above and addition~l object6 and advantages in mind as will hereinafter appear, the invention will be described with reference to the accompanying drawings, in .which:
FIG. l is a block diagram of a sy6tem according to the invention;
FIG. 2 is ~ diagram representing the transmitted fir6t data stream and the sequence of ~econA data stre_ms in a fir6t emhoAi~ent of the invention;
FIG. 3A shows a diagram ~e~.~~nting a characteri6tic fir6t data 6tream, and FIGS. 3B-3F ~how diagrams ~e~ e=enting characteri6tic se~encefi in the second data streams, all in the first embodiment of the invention;
FIG. 4 6hows a v~deo screen having a sample market information page thereon in which a block of data to be updated is shown in cross-hatch;
FIG. 5 shows a block diagram of an encoA~r in the system according to the first embodiment of the invention;
FIG. 6 shows a block diagram of a AecoA~r in the system according to the first embodiment of the invention;
FIG. 7 is a diagram ~ e~ esenting the transmitted video signals in a FeconA embodiment of the invention;
FIGS. 7A-7C illustrate the ~echn~que of transmitting and di~playing a plurality of television ~o~am information signals along with update data;
FIG. 8A shows a diagram ~e~ e~enting the transmitted first data stream, and FIGS. 8B and 8C show diagrams CA 022~76~9 1999-01-12 W093/2~8 PCT/US93/~361 ~e~ ~-enting the ~econ~ transmitted data stream in the CQ~ embodiment of the invention;
FIG. 9 is a block diagram of an encoA~r in the -~con~
embodiment of the invention;
S FIG. 10 is a block diagram of a ~Dco~er in the recon~
embodiment of the invention;
FIG. 11 is a block diagram of a system according to a third embodiment of the ~rent invention;
FIG. llA-llC illustrates the transmission of enable reception messages, enable reception and initialization messAges, initialization messages, and data enable sequences - to produce the displays illustrated in FIGS. 12A ~ 12C
illustrating symbolic signaling;
FIG. llD is a flow chArt for ~LGces~ing messages using symbolic signaling according to one embodiment of the present invention;
FIG. 12 is an illustration of the format for a single page of display information in accordance with the invention;
FIGS. 12A-12C illustrate the dicplays proA~ce~ through the message sequences shown in FIGS. llA-llC, as described above;
FIG. 13 is an illustration of a composite page having a plurality of tiles;
FIG. 13A-13C are illu~trations of tile messaging for updating different user defined tiles having common display information;
FIGS. 14A and 14B are illustrations of composite pages of display information;
FIG. 15 is an illustration of graphic tile messaging with graphic and alphamosaic cells; -FIG. 16 is a block diagram of DV bus signaling for the embodiment of FIG. 11;
FIG. 17 is a diagram of a DV bus message stream over two s~ccescive video signal time periods;

CA 022~76~9 1999-01-12 WOg3/23~ PCT/US93/04361 FIG. 18 i~ a diagram of a guad level (8,9) modulated ~ignal for a DV bus message;
FIG. 19 is a diagram of a heaA~r section of a digital message using the quad level (8,9) modulation;
FIG. 20 i8 a diagram of a double buffered error detection and ~G~.e~Lion interleaving terhn;que;
FIG. 21 is A diagram of a packet messaging sequence including packets of varying length;
FIG. 22 is a diagram illustrating p~cket fields;
FIG. 23 is a diagram illustrating message fields;
FIG. 24A-24G are diagrams of CG~.L~ ol bus messaging -signals;
FIG. 25 is a block schematic diagram of the encoder of FIG. 11;
FIG. 26 is a block diagram of a desk interface unit of an alternate embodiment of the third emhoA;ment of the present invention.
FIG. 27 is a block schemAtic diagram of the decoder of FIG. 11;
FIG. 28 is a block schematic diagram of the video ouLyuL
circuit of FIG. 27;
FIG. 29 is a block diagram of a modular residual video converter device in accordance with a preferred emhoA;ment of the present invention; and FIG. 30 is a block schematic diagram of the video digitizer circuits of FIG. 29.

DescriDtion Of The Preferred ~rh~ment As noted above, the object of the ~.F-ent invention is to distribute information. This information is transmitted over, for example, telephQne lines and converted on the client site into video signals similar to those for , television reception. The information ~h~cribed to takes the form of pages or ~eco~ds of market data, various portions of which are updated from time to time to reflect CA 022~76~9 1999-01-12 WO93~WK8 -PCT/US93/04361 changes in the market, and r~h-equently ~Ie-e~ted on a video screen.
In a fir~t embodiment of the invention, the s~n~l~
le~ enting the market information are being transmitted S asyn~o.. vusly, that is, there are no set characteristic times (e.g., television field or frame rateF) to restrict the transmission. As shown in FTG. 1, one or more portions of source information 10 of market data are e_ch given individual information identification (IID) codes, for example, ~JSN416~ and 'MDC2000~. These portions 10 are then --applied by an encoAPr-transmitter 12 to a digital video transmission line 14. Decoder-receivers 16 are shown cQnnected to the transmission line 14 for receiving and displaying the encoded portions 10. As chown, each AecoAer receiver 16 has _ unique displ~y identification (DID) code, for exAmple, ~PAMU0609~, ~BOBO1205~, ~LRN0122~ and ~TBD12??~.
FIG. 2 shows a diagram representing the digital video siqnals transmitted over the digital video transmission line 14. As shown in FIG. 2, a first line 20 of the transmission includes an encoded signal flag indicating to the ~ecoA~r-receivers 16 that the following information is encoded data.
The exact form of the flag is unimport_nt since the information contained is just one bit. The line or lines 22 contain enable reception messages. The lines 24 following the enable reception message lines 22, contain the various dat_ updates 1, 2 and 3.
Enable reception messages are used to provide information identification (IID) codes or ~e~c~Lion keys (RK) to decoders. The terms ~information identification codes~ and ~ ece~ion keys~ are used interchangeably. ~eco~e~s use reception keys to identify the portions of information that are to be displayed on specifically identified video screens. FIG. 3A shows a representative enable ~ece~ion (ER) message line 22 in detail. An ER synchronizing signal 32 is sent indicating the ensuing transmission of enable CA 022~76~9 1999-01-12 WOg3~23958 PCT/US93/04361 ,e_~Lion messages and on~hlin~ AecoAors to synchronize to the transmission. The ER sync signal 32 i~ followed by di6play identification code (DID) - Le__~Lion key (RX) sets 34, e~ch of which includes at least one of the unique DID
codes and at least one of the IID codes as a reception key (RK) for which the video 6creen identified by the decoder-receiver DID is authorized to displ~y. In the example shown, the sets are the DID/RX pair~ TBD12??/MDC2000, BOBO1205/JSN416 and LRN0122/MDC2000 and indicate that the video screen con~ected to the ~ecoA~r-receiver h~ving the DID code TBD12?? is authorized to display upd te data for the source information cGl,e_l,ol.7ing to RX MDC2000, screen DID BOBO1205, RX JSN416; and gcreen DID LRN0122, RX MDC2000.
It should be noted that in the example, the video Fcreen for the decoder-receiver having DID TBD12?? ig not authorized to display update data for the 60urce information corresponding to RXs JSN416 and MDC2000. The enable Le_e~ion message con~ PC for ~ many lines (each including an ER
synchronizing signal 32) and includes as many sets 34 as are required to associate each of the authorized video 6creens, by their decoA~r-receiver DIDs, with one of the (many) gubscribed-to y~GU~ or portions of source information by their information identification codes/RKc.
The ~LO~e~S for updating each ouL~ display is performed by replacing ~tiles~ in the relevant ~u~ digplay. As shown in FIG. 4, the cross-hatched tile 36 to be updated is located by two row and two column (or two x-y pixel pair) coordinates. FIGS. 3B - 3F show samples of the data enable se~en~es, in which, in FIG. 3B, the sequence for the update of information having the IID code MDC2000 i~ illugtrated.
- In particular, a data synchronizing signal 42 indicates the ensuing transmission of a data enable sequence, and is followed by the IID code 44 for the source of information having IID code MDC2000 and then the coordinates 46 of the tile 36 to be replaced which, in this example, ig 4 rows by 40 columns. The actual data for thig tile 36 ig presented .

CA 022~76~9 1999-01-12 WOg3/~KX PCT/US93/04361 in a series of llnes, ~GLL~POn~ to the number of rows in the tile to be updated, following the data enable sequence line. Note that the corre~pon~Pnce is not one line to one tile row and is expl A ~ ~PA below. Similar examples are shown for the information having IID codes JSN416 and MDC2000 in FIGS. 3C and 3D, in which in the information having IID code JSN416, a tile of 1 row by 11 columns i~ updated, and again in MDC2000, a ~?con~ tile of 6 rows by 40 columns is updated. Alternatively, as shown in FIG. 3E, the update data may AppeAr on the same line as the data enable ~equence. In particular, the sync signal 42' is followed by the IID code 44. However, the coordinates 46' include the pixel start number and the pixel stop number of a eingle row of the update data, along with the line number of the particular line. The update data 48 then follows on the same line. Each tile 36 i~ then com~-~e~ of the update data 48 ApreAring in, for example, a plurality of con~eclltive lines. Further, as ghown in FIG. 3F, the update data may be ~-ented simultaneously on one line for more than one page at a time. In particular, the sync ~ignal 42~ is followed by two IID codes 44~, and then the coordinates 46 of the tile 36 to be replaced, which in this example, is 5 rows by 80 columns, toward the bottom of the portions of information -having IID codes JSN416 and NDC2000. Additionally, all authorized displays connected to the video transmission may be ~imultaneously updated at the same coordinates by using a ~r~ A~ ~e_e~Lion key, e.g., RK e 0.
An encoder for the first embodiment of the invention is shown in FIG. 5. The enco~Pr includes a modem 50 for receiving data from a source of market information. This data may be in the form of entire pages or records of fin~ncial information where portions are updated, or the update data itself along with information for the positioning of the update data on the respective display screen. The ou~uL of modem 50 is connected to an interface 51, which is, in turn, con~Pcted to the input of a CA 022~76~9 1999-01-12 W093t23~ PCT/US93/~361 microcomputer 52. The microcomputer 52 reassigns the data to a~.G~iate locations in new ou~y~L display6 for clients of the information vendor. A keyboard 53 is connected to the microcomputer 52 for ~G..Llolling the microcomputer. A
memory 54 is connected to the microcomputer 52 and ~upplie~
thereto the configuration of the new Gu~U- di6play~, the reception key (RK) codes for each of the new portion~ of di~play information, and the di6play identification (DID) codes of the client'~ video 6creens authorized to receive each of the new portions of information. Based on this information, the microcomputer 52 generates the fir~t data : ctream and the 6equence of second data streams.
The ouL~L of the microcomputer 52 is applied through an interface 55, to a digital video generation unit 56 which reconfigures the ouL~uL of the microcomputer into digital video lines. The digital video generation unit 56 also generates the encoded signal flag and inserts the various synchronizing signals at the beginning of each of the digital video lines. A clock signal generator 57 is con~cted to the digital video generation unit 56 and the microcomputer 52 for applying timing signals thereto at the line frequency. In the event that the update information applied to the modem 50 is in the form of entire pages or records, a memory 58 is co~nocted to the microcomputer 52 into which the pages or leco~ds are entered enabling the microcomputer 52 to compare one page or ~ecO~d with the update of the page or record to extract therefrom only the update data.
FIG. 6 is a block diagram of a ~ecoAor for use with the oncoAor of FIG. 5. The AecoAor includes a receiver 60 for receiving the data transmitted by the digital video generation unit 56. The ouL~uL of the receiver 60 i~
applied to an analog switch 61 for selective application to a video screen in the event that stanA~rd nol- _oded signals are being received. A coded signal detector 62 is coupled to the receiver 60 for receiving the en~oAP~ signal flag and , CA 022~76~9 1999-01-12 WOg3/~K~ ~CT/US93/04361 for switçh~ng the analog switch 61 accordingly. An ER
detection g_te 63 i8 connected to the receiver 60 for receiving the enable reception mess_ge6 contAin~ng the DID/RK code 6et~. Each of the received DID codes is compared with _ unique di6play identification code 6tored in _ ROM 64 by a comparator 65. Upon each match of the DID
code, the individual RK code for the respective portion of information is stored in a memory 66.
The o~y~L of the receiver 60 is further ~-c,l.ected to a ,dat_ detection gate 67 for receiving the data enable -,~eq~Pnce6. The individual RK codes in the received data : enable 6eq~Pnres _re compared in a comparator 68 with the individu_l RK codes ~tored in the memory 66. Upon a match of one of these RK codes, the accompanving display coordinates of the update data are loaded into regi~ters 69.
An analog-to-digit_l converter 70 proceC~es the ayyl G~l iate update data _t the ou~y~ of the receiver 60 _nd applies its ouLyu~ to a write buffer 71, which also receives the ou~u~
of the registers 69. The ouL~L of the write buffer 71 is applied to a picture ~tore memory 72 in which the ~ection therein CG~ L e lon~ing to the location of the update data is updated by using the display coordinates. A synchronizing signal detector 73 is ronnected to the ou~ of the ,receiver 60 for separating the message synchronizing signals. The ouL~uL of the synchronizing signal detector 73 is applied to a timing and ~G~ ol signal generator 74 for generating timing signals for the analog-to-digital converter 70, the data detection gate 67, the ER detection gate 63 and the picture ~tore 72. The ou~ of the picture store 72 is applied to a digital-to-analog c~.. ve~Ler 75 ~Gl--,olled by the timing and cG,-L-ol signal generator 74.
The ou~uL of the digital-to-analog ~G~Ve~ ~er 75 i6 _pplied through a low-pass filter 76 to another input of the _nalog switch 61.
In a ~eron~ embodiment of the invention, the video signal~ representing the market information includes color CA 022~76~9 1999-01-12 WO93/2~K~ PCT/US93/04361 information. In addition, ~ta~ d television ~Gy~am information signal~ are included in the digital video signal6 for selective vie~wing of realtime television ~,roy-ams on the video ~creens. This tran6mis6ion is J 5 nec~6~-rily ~yn~G.. G~s to the cho~en television stAn~d.
When the digital video s;~n~l~ are being transmitted by co~YiAl cable, the usable bandwidth is in ~x~ of 24 MHz.
FIG. 7 show6 a pictorial representation of the transmitted video signal6. The enco~e~ signal flag line 80, the enable ~e~F~ion messages lines 81 and the data enable sequence lines 82 are transmitted during the vertical - bl~nk~ng interval 83 between each field of the video signal.
During the active video portion of the field, in a first h_lf of each scAnning line, the television R, G and B
signAl6 84, each originally having a bandwidth of 4 MHz and each time compressed by _ factor of six to an exrAn~e~
bandwidth of 24 MHz, are sequentially tr_nsmitted. In the ~eCGl~d half of each rcAnning line, the update data for individual pages of the market information are transmitted.
While the television p~G~m inform_tion signAl6 84 are in color, the update information may be monochromatic, color or a mixture of both. In particular, as shown, the first 8 half-lines contain the monochrome update data 85 for the left half _nd right halves, respectively, ~G~ ~e_lo ling to RK code MDC2000. The update date 85 is followed by the update data 86 ~G. ~ ~ ~~~01 ~-1 i ng to RK code JSN416. The update data 86 is presented in color as the three color 6ignals R, G _nd B. The remainder of the right half of the first field is shown as being unused in this example. The left half of the second field contains the G, B and R components of the - television ~Gy.am information signal6 78'. The right half of the F~.conA field contains the monochromatic update data correspon~;ng to RK codes 208, 1234, 5, 19154 and 264.
FIGS. 7A - 7C illustrate the techn1que of tran6mitting and displaying more than one television ~LGy.am information signal at a time along with update data for ouL~L displays CA 022~76~9 1999-01-12 W093/2~K~ PCT/US93/04361 on a plurality of video 6creen~. Specifically, FIG. 7A
illugtratee the transmi6~ion of four fields of digital video ~ign_ls ~o~ rponAing to two televieion video fr mes. A
vertical blAnk;ng interval 83, corr~fiponAing to the vertical S hl Anki ng interval 83 of FIG. 7, i~ shown. Nine different sources of information are Fhown as being transmitted in the fields, namely television ~LGyL~m information ~ignals TV1-TV3 and ~ix tiles numbered TILE 1 to TILF 6 having cGL.~-pon~ing update data to particular portions of fin~ncial market information. The transmi~ion of a field ctru~Lu~ed in this manner is done at the television ~canning : rate, A S mentioned above.
The televi~ion ~LGyl~m information signals TVl-TV3 are shown as being time compressed in a well known manner. The TVl signal~ are shown a8 being tran~mitted during a portion of every horizontal digital video line. Television ~y~m information signals TV2 and TV3 _re ~hown as being transmitted only during certain horizontal digital lines, namely from line W to line X, in the case o$ TV2, and from line Y to line Z, in the case of TV3. The televi~ion program information signals TV1-TV3 are shown ~s pluralities of lines having ~lternAting odd line (TVODD) and even line (TVrn~) fields in ~lcc~cive video fields. The television program information ~ignals _re illustrated in FIG. 7A in the RGB format, i.e., three primary color signsls, but also may be transmitted as one luminAnce and two color difference signals, e.g., Y,U,V. Further, the television ~6yL~m information signals may be digitized and compressed, e.g., using the JPEG or MPEG stAnA~rds or some other te~hni que.
Also, the update data to output display tiles TI~E 1 -TILE 6 are transmitted in various lines _t times when the television ~GyLsm information signals are not being tr~nsmitted.
The update data for an v~ L display tile may appear anywhere in the video screen and may start and stop at any point or in any line of the digital video field, provided CA 022~76~9 1999-01-12 W093~K8 PCT/US93/04361 that the update data doe~ not occur simultaneously with the television ~Gy~m information signals. Thus, update data r may occur during the vertical b1An~in~ interval 83 as shown in the third digital video signal field for update data to TILE 3. Update data al~o may be a lengthy stream of data that f ill6 tho~e portion~ of s~cceF~ive lines that are not filled by television ~LO~ am information signals as illustrated in the fourth digital video signal field with respect to the update to TILE 2 and signals TVl and TV2.
Further, update data may be a relatively short stream of data starting at the beg;nn~ng of a line time, or in the :middle of a line time, see, e.g., updates to TILE 6 and TILE
2 and TILE l in the fourth field.
In addition, there may be no update data for f~n~nc; A
market information as in the first d$gital video signal field cont~in;ng television ~.Gy~am information signals TV1~D~ TV2~D, TV3 ~ , although there will be some digital data (not shown in the first field) that is transmitted, ac described below.
The reculting displayc that are possible with this transmission structure are illustrated in FIGS. 7B and 7C
and 13. FIG. 7B illustrates the display of the television ~Gy~am information signal~ TVl and which, due to the transmission of cuch ~ignals during each digital video scan 2S line, produce full screen televi6ion display~. FIG. 7C, on the other hand, illustrates the display of both TV2 and TV3 signals which, by virtue of their transmission within the stated intervals, are displayed within specific vertical ho~n~Aries within the video screen. Specifically, the TV2 display must be located between horizontal lines W and X in any horizontal location (with the proviso that it not interfere with ou~uL display data) and TV3 must be - displayed between horizontal lines Y and Z, in any horizontal location (with the same proviso). The ou~uL
3S display ~o~L_~G~-ding to one of the source information in tiles TILE l - TILE 6 that the particular video ~creen i~

CA 022~76~9 1999-01-12 W093/~K~ PCT/VS93/04361 en~bled to receive can be displayed above, below or alongside the TV2 and TV3 6ignals (only TILE 1 - TILE 3 are illustrated).
Due to the complex ordering of the update data in the first and recon~ fields, the data enable ~eq~nceC in the lines 82 must n~cee6~rily be more complex than tho~e shown in FIGS. 3B - 3F. In addition, the enable ~e__~Lion messages also must indicate which of the video screens i8 authorized to receive the television ~ Gy r ~m information signals sent with the update data. In particular, a8 ~hown in FIG. 8A, the enable reception messages are similar to those shown in FIG. 3A, with the exception that in addition to the DID/RK code sets, the messages include a set 87 indicating which of the video screens, for example, the screen with DID code 297, i~ authorized to receive which television ~.Gy~am information signals, for example, the television ~.Gy.am information signal having an IID code TV1, which also may be used a8 a ~e_c~ion key (RK) if distribution is to be enabled. FIG. 8B shows ~ sa~ple data enable sequence which includes, in addition to that described with respect to FIGS. 3B - 3F, the coordinates of the update data in the source field. FIG. 8C shows a sample of the data enable sequence for identifying the television y~Gy.am information signals, and includes a data synchronizing signal 88, a television RK code 89 and the ~tarting coordinates 90 of the color signals, red, green and blue, or Y,U,V.
FIG. 9 shows a block diagram of an encoder for the recon~
embodiment. The digital video generation unit 56' has a ~econ~ set of inputs for receiving the th~ee components of the color television ~.Gy.am information signal, Y,CDl,CD2.
In particular, a source of television ~lGy.am information signal is con~ected to a synchronizing signal separation circuit 91 for detecting the vertical and horizontal synchronizing signals in the video signals. The source of the video signals is also connected to a matrix circuit 92 1~ CA 022~76~9 1999-01-12 W093/23~ PCT/US93/04361 for providing the three components. Each of these components i8 subjected to compression in compres6ion circuit 93 and the three components are then applied to the digital video generation unit 56'. The clock and sync signal generator 57~ applies synchronizing signal6 to both the digital video generation unit 56' and the microcomputer 52', and receives the synchronizing signals from the separation circuit 91 for synchronization therewith.
FIG. 10 ~hows a block diagram of a A~oA~r for the ~e~on~
embodiment. CO~G~.~.. LS the same as tho~e in FIG. 6 are designated with the same reference number. The A~coA~r is ~substantially similar as the decoder of the fir~t embodiment with the exception that the decoder i8 now capable of processing color signals and the encoA~A data selectively includes television ~IGyLam information signal6. In particular, a color A~coAer 101 i6 included between the ouL~u~ of the receiver 60 and the input of the analog switch 61.1 - 61.3. The register 69' includes a register element for storing the number of the picture store. The cynchronizing ~ignal detector 73~ GU~ S field ~synchronizing signal~ in addition to line synchronizing signals. The write buffer 71 now acresC~~ three picture ~tores 72.1 - 72.3 correspQnA i ng to the three color components, red, blue and green. The ouL~u-s of these picture stores 72.1 - 72.3 are applied to three digital-to-analog converters 7S.1 - 75.3, and then to three low pass filters 76.1 - 76.3 for application to the other inputs of the three analog switches 61.1 - 61.3.
Referring to FIGS. 11 to 29, a third embodiment of the present invention is shown, which reflects a number of im~ovements to the first and ~ A embodiments described above. One system in accordance with the third embodiment includes an encoA~r 312, a digital-video (DV) bus 314, a plurality of A~coA~rs 316, a plur~lity of video screen~ 317, a control bus 318, a keyboard 319, optionally a mouse 319', and a supply (or source) of display information 310 which CA 022~76~9 1999-01-12 may include realtime television ~Loy.am information signals, and ~nalog and digital video signals le~L ~--nting financi~l market information. The DV bus 314 is preferably a ~h~nnel capable of transmitting digital and video information. This permit~ the use of st~nA~rd cQaxi~l cables or video switches as the DV bus 314.
As illustrated in FIG. 11, each APcoAPr 316 has an associated video screen 317, preferably constructed as an integral unit in a common enclosure. Alternately, as shown in FIG. 26, each APcoAPr 316 mAy be part of a desk interface unit (DIU) 321, which ~u~GLLs a plurality of video screens 317, e.g., four, and a plurality of users and their ~e~pe_Live keyboards 319 and mice 319'. Each user may have one or more video screens 317 arranged in a work space, e.g., on a desk top 320. Each video screen may have a unique DID. Alternately, each user or desk top 320 may have a unique DID such that restricted display information may be displayed on any video screen of the enabled user or desktop.
One aspect of the present invention cc"~e-,-s im~Lovements in the structure of the signals (also referred to as ~DV bus signals~ which are concatenated to form ~DV bus messages~) and their messaging along the DV bus 314 between the encoder 312 and the plurality of decoders 316, and their display on a video screen 317.
FIG. 12 illustrates the image produced on each video screen 317, which is a composite page 200 of financial market information and/or television ~LGyLam information signals, as described below. Each composite page is organized as a plurality of cells 210. Each cell is organized as a plurality of pixels 220. Every cell 210 has an assigned location within composite page 200, by row R and column C, relative to an origin and cannot be arbitrarily -placed. The origin may be selected to be in the upper left corner or elsewhere. Similarly, every pixel 220 has an assigned location within each cell 210, by row r and column CA 022~76~9 1999-01-12 wOg3/23~ PCT/US93/0436l c, rel~tive to a cell origin and cannot be arbitrarily placed. In accordance with the pLE-~-~t invention, and as exp~Ai~-~ below, messAges transmitted _long DV buc 314 are either directly or indirectly addL ~ --6~ to cells.
In a preferred embodiment, e_ch composite p_ge 200 is com~ of 30 rows and 100 columns of uniform and fixed-size rectangul_r cells 210, a~ ~hown in part in FIG. 12.
The coordinates of the cell 210 in the upper left corner of the page 200 are (RO,C0). The cell 210 in the lower right corner of the page 200 is at (R29,C99). Each fixed-~ize cell 210 hac 128 pixel~ 220 organized into 8 column~ by 16 rows. This represents a display screen 317 that is larger than the ~ize of stanA~rd pages or Le_GLds of fi~Anci market information provided by commerciAl information vendorc, and the size video ~creens provided by tho~e vendors with their systems. Such s~A~AArd pages and display ~creens have 18 or 25 row~ by 80 columns or 12 rows by 64 columns. Advantageously, the larger display screen permits the user to create composite pages 200 cont~ini~g more financial market information than previously possible with the prior systems, and further permit~ displaying television ~lGyLam information signal~ and/or value added information without sacrificing the financial market information.
Each pixel 220 within _ cell 210 may have up to 256 different colors, selected from a larger palette of 16,777,216 colors. The number of colors that may be displayed on any given video ~creen 317 A-p-nA~ on the mount of memory of the A-coAer 316 operatively ronnccted to the video screen. For example, if a AecoA~r has been loaded with one byte per pixel of screen ~tore memory, or approximately (800x480 ~ 384,000 pixels) 376 Xbytes of memory, it can display 256 colors per pixel. For another ; example, if a AecoA~r, which has lower cost and functionality, has been loaded with only two bits per pixel of ~creen store memory, or approximately 96 Kbytes of memory, it can only display 4 colors per pixel.

CA 022~76~9 1999-01-12 WOg3t239~8 PCT/US93/~361 R~P~1)C~nt3 the number of colors to be signaled also reAnc~s the length of the messages n~edPA to create or ~paint~ a composite page 200. For ex mple, when four colors ~re being used, only the first two significant bits of a color byte need be transmitted. Even when 256-color APcoA~rs are used, clever ~election of the color definitions can reduce the amount of messages nece~-ry to transmit information con~erning a small tile on the page. For ex mple, a first tile may have colors 0, 1, 2, and 3 while a rs~-on~ tile may :-have colors 16, 17, 18, and 19. Changing the colors in the -e-onA tile only reguires the transmission of two bits of information per pixel.
In this third embodiment also, DV bus messages are transmitted as tiles. As already noted, a tile is a rectangular region that will appear on the video screen 317 and is illustrated here by the bold black rectangle 250 on the right side of composite page 200 in FIG. 12. It may contain any number of horizontally and vertically contiguous cells 210. Preferably, each tile is defined by the location of its first cell, i.e., the coordinates (row R and column C), in its upper left corner and either its size (i.e., number of rows and columns of cells in the tile) or the coordinates of the cell in its lower right corner.
This third embodiment of the invention preferably employs 2S two concepts of tile messaging to reduce further the amount of overall data that i8 required to be transmitted. The fir~t concert is called cell wrapping. This provides for renAing one large single continuous message to a tile for one cell 210 after another (either horizontally or vertically aligned) within a tile having determined boundaries CO that the first cell to cross the tile ~o~l~AAry in the direction of continuity automatically ~wraps back~
within the tile to the beginn1ng of the next row or column so that each cell is successively filled. The tile hol~nA~ries are preferably i.,~GL~G~ted into the tile dicplay boundary coordinates provided to the decoder for the update CA 022~76~9 l999-0l-l2 W093/~958 PCT/US93/~ ~1 data. ThiP avoids having to monitor when the next cell 210 will be outside of a ho~nA~ry of the tile and P-en~ either a new message or next row or next column indic_tor. The decision to u~e horizontally aligned mes~ageC or vertically aligned messages m_y be ba~ed on the aspect ratio of the tile ho~ln~Ary so a~ to minimize the number of wrapping event~ and maximize painting ~peed. When combined with run length ~ncoAing of mesFage~, de~cribed below, cell wrapping greatly im~.vves messaging efficiency.
The r.:Dn~ concept i~ the use of implied motion where portions of finAn~ market information contain regions --that must be moved, either vertically (~crolled) or horizontally (pAnne~). For example, cG..~el.~ional financial instrument tickers are u~ually panned horizontally across a video ~creen, while news headlines are 60metimes ~crolled vertically. Thi~ movement can be accompl 1 ~h~ by either retransmitting all of the required information such that the relative location of each column (pan~ng) or row (scrolling) i8 ad~usted for each incremental move, or in accordance with a preferred embodiment, by transmitting only the new information and ~implying~ the desired motion by the prior definition of a pAn~i~g or 6crolling tile type.
Implied motion within a tile greatly improves the messaging efficiency.
Referring to FIGS. 12, and 13, the video screen 317 may be referred to as the underlying tile 350. One top of the underlying tile 350, one or more of the following types of tiles, referred to as tile 250 with a letter suffix, can be di~played as illustrated in FIG. 13.
A graphic tile 250-G may be defined to display -- information on a pixel by pixel basi~. It is used to display graphs, charts, Fca~ne~ image~, e.g., ~till pi~ules~ value-added presentations of historical data, and ~imilar non-~lphAnumeric character di~play information.
An alphamosaic tile 250-A is a tile entirely defined by an extended set of ASCII characters or the equivalent (i.e., CA 022~76~9 1999-01-12 WO93~K~ PCT/US93/04361 alp~an~meric characters). It is u~ed to display normal Alph-n--meric character text plus _ny predefined extenAPA
ASCII character~. Each pixel tlr~ y may have up to 256 color6. In FIG. 13, the alphamosaic tile 250-A is illustrated as displaying information conc~rning U.S.
Government securities th_t are periodically updated.
Alrh~n~meric tiles 250-A are static unleFs they are further defined for relative movement.
A p~nn~ng tile 250-P i8 an alphamosaic tile that is ~G,--~olled to create horizontal motion, left or right. In FIG. 13, pAnn;ng tile 250-P i8 illustrated as the (NYSE) - Ticker which is being p~nne~ right to left. The character ~tring update ~NYSE~ has been received at the entry (partial ~S~ char_cter) and is being automatically p~nn~~ (partial ~E~ character) under the ~Gl~L~ ol of decoder 316 using implied movement. The pAnn1ng effect may be a cell by a cell advance or a pixel by pixel advance, the latter providing a smoother image trAneition and presentation of partial characters.
A scrolling tile 250-S is an alphamosaic tile that is controlled to create vertical motion, up or down. In FIG.
13, the scrolling tile 250-S is illustrated as the ~Financial News~ and is being ~crolled upwardly. The entire lower row of characters has been received at the entry and is being automatically scrolled (partial top and bottom rows) under the ~G~-L,ol of ~e~o~Pr 316 using implied motion.
The scrolling may be a cell by cell advance or pixel by pixel advance, the latter providing a smoother image transition and presentation of partial character~.
A video tile 250-V is used to display a realtime television ~, Gy~ _m information signal. Each pixel within the video tile may take on any color ~ o~ed by the relative television transmission st~n~rd and the picture store memory size of the given decoder 316. In an emho~;ment wherein the deco~Pr 316 includes a picture etore memory, different TV signals may be selected for di~play CA 022~76~9 1999-01-12 W093~23~ PCT/US93/04361 within a video tile 250-V so long as they are being transmitted within the ~ame vertical format. If, htwever, a picture frame memory is used, which can ~tore an entire frame of television ~Gy-om information ~ignals, then the video tile 250-V need not be limited to the same vertical format and may be located anywhere on underlying tile 350.
The ~ize and display location of each tile 250 on underlying tile 350 i~ preferably initially estab~
u~ing a tile default ~ize and position. Each tile 250 may be locally resized and repositioned by each user. Thu~, for example, by using a mouse 319 or keyboard 319', each user : may redefine any tile 250 by (1) overlaying any one tile over any other tile and overwriting the display information of the other tile(s), (2) changing the fo,ey.o~.d/backy~Gund attributes among the displayed tiles, (3) moving a tile to any new di~play location on the video ~creen (except for real time television video tiles 2S0-V, which may only be moved horizontally in the absence of a picture frame memory), and (4) changing its size either to display more or less display information or to display the ~ame information in larger or smaller size.
In accordance with the third embodiment of the present invention, tile messaging embodies the following five principles:
1. Each tile 250 is uniquely named, i.e., it has a unique IID code that is used as a Le~e~Lion key, and is assigned system default di~play location and size, typically as an offset referenced to the origin cell (e.g., (RO,C0)) on the underlying tile 350 or to the origin cell of a tile 250 within the underlying tile 350. Thus, a tile 250 may be - nested within other tiles 250 on an underlying tile 350, such that relative offset of each tile in the chain to its antec~nt associated tile is ~eD~E--Led and maintained by the decoder.
2. Tiles 250 may be locally resized and repositioned from their ~ystem default conditions locations by individual CA 022~76~9 1999-01-12 W093~W~8 PCT/US93/04361 u~ers and may be given an offset refe~enced to an origin cell on the underlying tile, or to an origin cell of any other tile. The remapping of the tile default location and ~ize to the user-defined tile location and size o~ in each user's ~coAPr. DV bus messages to update the user-defined tile are transmitted with the default display coordinates (unless the symbolic siqnAling te~hni~ue described below is used) and the default tile message is mApped onto the user-defined tile within the picture store memory of the decoder. If a~u~Liate, the user'~
-definition of the tile will provide displAy coordinates for selecting a~u~iate cells selected by the user ~nd disregarding other cells in the DV bus message of the default tile, so that only the display information in the user defined tile is stored and displayed. Thus, the user's redefinition of the tile has no effect on the DV bus messages and only the user selected information is displayed and updated.
3. It is often more efficient to retransmit the whole tile using cell wrapping rather than transmitting just the updates. This is because computational efficiency is obtaine~ by filling in time lengths of DV bus signals with useful data rather than blanks. This is not usually true -for retransmitting the whole page of financial market information.
4. Related page or record updates often occur in bursts and are usually received from the information vendor one row of financial market information immediately after the other.
It i~ far more efficient to ~tore all of these received multiple contiguous-column row updates to a tile within a portion of finAnci~l market information for a very small time (perhaps 1/20th of a second) before transmitting them as a single group within a single tile on the DV Bus 314 to all of the dPco~Prs 316. This technique avoids retransmitting the same tile each time one row of the tile is updated, and retransmitting each update data, but not the .

CA 022~76~9 1999-01-12 W093/23~ PCT/US93/~361 complete tile, with the a~o~iate hsa~r and offset display coordinates, e.g., starting and en~ing row and column to display the update in the relevant display location of the video screen. Similarly, with reference to J 5 FIGS. 13A-13C where two user6 have defined tiles that include some common portions of the same page or record of f~n~nc~Al market information, e.g., tile SA and tile SB, the update data for the underlying page or record of financial market information may be transmitted in one of three formats. The first format is to create two separate tiles SA and SB and transmit update data for those tiles a~
necPeeAry with a duplication of messages. The r?con~ and more uceful tec~ni~ue is to decompose the overlapping tiles SA and SB into three tiles SAl which is unique to user A, SB1 which is unique to user B, and SAB which is common to users A and B. Then updates for the three tiles are _eparately provided as a~lG~iate. A third teçhnique is to create a ~supertile~ S which includes all of the financial market information. In this latter embodiment, user A i6 enabled to receive Du~e~ile S with display coordinate information for retrieving only those portions of information selected by user A, and user B is similarly enabled to receive supertile S with display coordinate information for retrieving only those portions selected by user B. Thus, the update message is only sent once, yielding im~oved DV bus messaging efficiency.
5. Both contiguous-column row messaging and contiguous-row column messaging should be Dù~GL~ed within tile messaging for efficient updating of tiles.
The application of tile messaging greatly reduces the ~ amount of message traffic on the DV bus 314. One example is explained with reference to FIGS. 14A and 14B, which respectively illustrate composite page 200a having tiles Tl, T2, T3 and T~ and composite page 200b having tiles Tl, T5, T3 and T~', such that tiles T~ and T~' are different user-CA 022~76~9 1999-01-12 W093~958 PCT/US93/04361 defined tiles based on the same original portion of financial market information T~*.
First, it i~ noted that in prior art ~ystems, all vendors of video f~nAnc~Al market information typically use contiguous-column row oriented messaging; all ~creen changes are signaled by multiple individual messages, each mes~age roncerning only contiguously located columns in one row of the page or ~e_G~d. A stAn~Ard page from one commercial vendor may be tho~ght of as one large 6tatic alphamosaic -tile 250-A that is 80 columns wide and 18 rows high. When the page i8 transmitted to the client site for the first time in Le~G..se to a page reguest by a user, it may be sent using eighteen messages, one for each displ_y row. Each message will include a header identifying the page or record number of the source f~nAnciAl market information, the row number, and the starting column number of the following message, and up to 80 columns of character data. Each message CO~e~G~dS to a 6ingle row and is about 100 characters (one byte per character) in length. Thu~, for an 18 row display, the total page reguires 1800 characters to be transmitted over the telephone line. At 180 characters per ~eCQn~, it takes about ten r~oon~s to ~paint~ the screen for the first time.
: When an information change o~ , the information vendor updates the page by ~6n~g only the new information. When one character changes, for example, a single message i~ sent having ~G-.~ol information (in brackets) and the new data as follows:
[{PAGE NO}{ROW}{STARTING CQTTn~}] DATA
t{P16251}{R0}{C13}31.
Thus, most update messages only Le~r- -çnt one or two new data characters to be di~played on the video ~creen to be di~played on the video screen accompanied by about ten information ~G-,L,ol ~characters~ for placing the data characters in the proper display locations. Further, when one fundamental data element changes it often causes a CA 022~76~9 1999-01-12 W093~3958 PCT/VS93/04361 flurry of very 8mall individu_l me~s_ges to upd_te other rows or column~.
With the foregoing in mind, _nd referring to FIGS. 14A
and 14B, if the original portion T,* i~ defined _6 _n alph mosaic tile 250-A, then, without tile mes~aging and according to the prior art, receiving _ new hP~ ne would require transmitting a total of nineteen mes~_ge (_bout 1900 ch_r_cters); seven mes6ages to compo~ite page 2OOA- and twelve messages to composite page 200b. Seven of the messages tr_nsmitted to composite p~ge 200B would be identical to those transmitted to composite 200a e~e~L that - the row display location would be different to reflect the f_ct that the heA~l;n~ information is displ_yed higher on composite page 200b th_n on composite page 200a.
~uever, with tile mess_ging, receiving a new headline would require tr_nsmitting a total of one messAge (under one thous_nd ch_racter~). Both composite pages 200a _nd 200b would receive the s me tile mesF~~e~ e.g., T~', _nd u~e cell wr_pping _nd the user-defined tile loc_tion offsets and displ_y coordin_tes to displ_y ~G~eL1Y the information on the respective composite pages 200a and 200b.
If the original portion T~* w_s defined as a scrolling ~lph_mosaic tile 250-S, then using tile mess_ging would h_ve resulted in both composite p_ges 200a _nd 200b being properly ~ed~wn by only one DV bus mess_ge of less th_n one hu..dLed ch_racter~. This ~e~L ~ ~ent8 a nineteen times reduction in DV bus message traffic for this simple ca6e.
The im~ovement i~ even more ~Lo..ou..ced when more tiles _nd composite pages _re involved.
The third embodiment of the invention preferably employs tile messaging of upd_te d_ta using _ ~ymbolic gignAlin~
terh~ique, which will now be described with refe~e..ce to - FIGS. llA, llB, llC, llD, 12A, 12B, and 12C. FIG. llA
illustrates a transmi6sion terhn~que similar to that Ai~c~-cced above with reference to FIGS. 3A - 3E. However, for the ~L~-e6 of clarity, no synchronization signals are CA 022~76~9 1999-01-12 WO93/~K~ PCT/US93/04361 shown, and only a single row _nd single column transmiscion are shown. The tile row and column starting and ~nA; ng loc~tions will be transmitted in the manner described el~e~}.ere.
S FIGS. llA-llC and 12A-12C illustr_teg message types for alternative techniques of customizing and displaying composite page_ 200 of display information And updating the di~play information for part~c~la~ user~. With specific reference to a FIG. llA, one technique uses an enable ~eccpLion message 100 and data enable se~enc~C 102, 103 snd 104 at time tl and data enable se~l~nc~s 112, 113 and 114 at : time t2. The enable ~ecc~Lion message 100 is shown aS being comprised of display identification (DID) code 120 -reception key (RK) code 106 pairs, in this case, three code pairs DIDl/RKl, DID2/RK2 and DID3/RX3. The .e_epLion key 106 is used to authorize the ~coA~r to retrieve update data for a portion of financial m_rket information having an IID
code that is the same as the ,ece~Lion key. Thus, a ~eco~er video ~creen 317 having the DID 120 of IDl is authorized to receive information for reception key 106a RKl, the decoder video screen 317b with DID 120b of ID2 ic authorized to display financial market information for ~e_epLion key 106b of RK2, and so on. It should be understood that, although the RK's 106 and DID's 120 are illustrated as Alphanumeric characters RKn and IDn (n being an integer) in pr_ctice it is preferred that they be multibit, e.g., 21 or 24 bit~, code words that e.,~ L the actual ~ource of financial market information. This is so that an unauthorized user cannot identify and retrieve a certain financial market information by tapping into the DV bus.
Following the enable reception message 100, at time t three separate data enable sequences 102-104 are illustrated, each of which is comprised of a reception key 106, row and column display location information 108, followed by data 110. Although the data 110 ic shown as directly following the reception key 106 and row and column CA 022~76~9 1999-01-12 W093/23~ PCT/US93/~361 information 108, it can be transmitted on a ~eparate line, immediately following the data enabling seguence.
For the purpo6es of thi6 example, the information displayed on the leD~ective portions of f~nAnc~ ~ 1 m~rket information having IID code6 RKl-RK3 can be different, but each contains at leAst one common information field of data 110, which is represented by ~DATAl~ relating to a 30-year U.S. Trea~ury bond. By transmitting the information field data 110 with the foregoing data enable se~nc~6 102, 103 and 104 for the three ,ecc~Lion keys 106, namely RKs 106a-106b of RRl-RX3, the three different video screen6 317a, - 317b and 317c, having correspon~ing DIDs 120a-120c of DID1-DID3, can display the same information field 110 in different location6 as illustrated by boxes llla, lllb and lllc in FIGS. 12A-12C le~ectively, using display coordinates 108a-108c.
For example, the data enable sequence 102 places the data 110 in the upper left hand corner represented by display coordinates 108a (ROWl,COLl) of video screen 317a (box llla) having the DID 120a of DIDl, which was enabled with reception key 106a of RKl. In a similar mAnner, 6eguence 103 places the information field 110 near the center of video screen 317b (box lllb) having the DID 120b DID2, represented by the display coordinates 108b (ROW10,COL40), which was enabled with ~Lcep~ion key 120b of RK2. Sequence 104 places the information field data 110 toward the lower right hand corner of video ~creen 317c (box lllc) having the DID 120c of DID3, repre6ented by the display coordinates 108c (ROW3,COL3) which was enabled with the reception key 106c of RX3.
Thus, the information field data 110 is transmitted by three ~eparate tile message6 102, 103 and 104 at a time t~
- such that each tile has a different offset relative to the upper left corner of the underlying ti~e 350. In order to customize the information displayed on various displays, separate tiles must be transmitted to each video display .. ..

CA 022~76~9 1999-01-12 W093~U~8 PCT/VS93/04361 317. When it is ne~ ry to update the finAn~iAl market information for information field data 110 during time interval t2, again three tile~, e.g., illustrated a~ dat_ en_ble 6e~n~efi 112-114, must be tran~mitted, each having the ap~G~-iate ~e~e~Lion key 106, row and column 108, and the new f~nAnci~l m_rket inform_tion for information field data 110, e.g., DATA2, as ~hown in ~IG. llA.
The application of symbolic 6iq~Al1n~ is ba~ed on the reAl~7Ation that the trader6 of financial instruments prefer to ~elect the fi~nci~l market information they use to formulate their trades, and th_t ~ome of that financial - market information will be the ~ame as that used by other tr~der~, and some information will be different. It also is based on the realization that the traders do not nece~c~rily want to view all of the inform_tion provided by a commercial information vendor and prefer to customize their video ~creens to ~atisfy their desires.
Accordingly, the customization of the information displayed on multiple APcoA~r video ~creens is greatly facilitated, and at the ~ame time, the overhead required to update information commonly used is greatly reduced, _ccording to the present invention, in the following manners. Referring to FIG. llB, one aspect of the present '~'invention provides for using enable reception and ~"'initialization messages 116-118 and data enable ~equences 128 at time tl and 134 at time t2. Each enable reception and init;Aliz~tion message 116-118 ~e~e~-ively includes a DID code 120 for a video screen, an IID code which, in this instance, i~ uged as A FeCQnA~ry .e~ep~ion key (SRK) 122, in thi~ case ~LONGBOND~, and display coordinate information 108, e.g., row R and column C. The display coordinate information 108 row R and column C will place the data 110 asgociated with the secondary ~e_e~ion key 122 in the designated display location only for the video ~creen identified in the DID/SRK ~et. The term ~FecQn~ry e_e~ion key~ is a reception key th_t i~ associated with , .
.

~ CA 022~76~9 1999-01-12 WOg3~ PCT/US93/04361 another ~e_e~ion key 6uch that a A0roA~r mu~t be enabled with the other firQt or primary &__~ ion key before it can be enAhl~A by a r~c~nAary .e_e~ion key. The other ~ L oc~Lion key also may be a eqconAAry reception key S a~sociated with yet another first or primary reception key as explained below.
Thus, each enable reception and initiAl;7ation message both enables a video screen to receive _nd display certain data and init~ al ~ 7es the relative di~play location of th~t data on that video screen, even though no data has been sent. Import~ntly, this permit~ each user to 6elect the display location on the user's video ~creen to display the dat_ ~Gl~e~,o~.l;ng to the ~e~QnA~ry ~ece~Lion key SRK
;nAepenA~ntly of the other users so that only the particular Fe~onA~ry le~e~Lion key and the cG~.eD~o.,iing data need be sent to effect the co~e~-t display. Again, the use of LONGBOND a~ an IID code and an SRK is for illustrative ~L~-~eF and in practice an encrypted multibit bit code word would be used as the SRK.
Thus, using enable reception and init;al;zation messages 116-118, video screen 317a having the DID 120a of DID1 i5 enabled in this example, e.g., at the beg;n~;nq of the day, with SRK 122 LONGBOND and will display the subsequently transmitted data 110 information ~tarting at display 2S coordinates 108a (ROWl,COLl). Similarly, video screen 317b having the DID 120b of DID2 is enabled with the SRK 122 LONGBOND and to receive and di~play the data 110 information at its selected display coordinates 108b (ROW10,COL10).
Video screen 317c having the DID 120c of DID3 will likewise place the data 110 information at its selected display coordinates 108c (ROW20,COL60). Then, at time t, a single tile data message 128 is transmitted compri~ing the SRK 122 ONGRO~n and the financial market information data 110, shown as DATA1. Upon receiving the tile data message 128, 3S decoder video screen 317a will reCo~n~ze the SRR 122 LONGBOND as matrhing its previously enabled SRK 122 and CA 022~76~9 1999-01-12 W093~ ~ PCT/US93/~ ~1 place the data ~10 DATA1 in the designated location according to the previously initialized di~play coordinates 108a, i.e., the upper left hand corner (ROWl,COL1) box llla as shown in FIG. 12A; video screen 317b will likewise display the data 110 DATAl of message 128 in its center (ROW10,CO~40) box lllb, and video screen 317c will similarly display the data 110 DATA1 of message 128 in its lower right hand corner (ROW20,COL60) box lllc. When it is n~ce~-~ry to update the financial market information at time t2, a single tile data message 134, is transmitted, comprising the SRK
122 LONGBOND and the data 110 DATA2 to update the video :screen. This data 110 is then displayed in the ~Lo~e-location of each video screen 317, in the same manner, to update the display.
lS Referring now to FIG. llC, Another aspect of the invention conrerns using three types of messages to display and update information, enable reception messages 100, initialization messages 136, 137 and 13~, and data enable seguences 128 and 134. The enable reception messages 100 are used in the same manner and for the same ~u~ as described above in connection with FIG. llA. Then, once a decoder is enabled with a reception key 106, the enabled decoder is initialized with a secondary reception key SRK
122 for that enabled reception key 106, and di~play coordinates 108 for displaying the subseguently transmitted data 110 in the selected display location 111 on a video screen 317. Thus, each initialization message 136, 137 and 138 includes a first IID code co~e~o~ n~ to a previously received reception key 106, a second IID code which is used as a secondary ~ece~Lion key (SRK) 122 (in thi~ case LONGBOND), and display coordinate information 108, e.g., row and column or offset fin~nc;~l market information, which may be unigue for each video ~creen 317. Then, at times t1 and t2, the data messages 128 and 132 described above in ronnection with FIG. llB are transmitted, having the SRK
codes 122 LONGBOND, which will be received by the enabled CA 022~76~9 1999-01-12 W093/239~ PCT/US93/0436t ~nd init~ zed ~co~-rs, and the data 110 for display at the indicated display locations llla, lllb and lllc on the respective video s~le~ 317a, 317b ~nd 317c.
The initi~li7ing messages 136, 137 and 138 are not ~n~hl~ng ~ece~ion messages 100. Thus, if the ~eCoA~r iB
not first enabled with the reception key 106 by an enable e-~e~Lion message 100, it will not retrieve the stAsn~ry ece~ion key 122 by an initialization message and will not retrieve the data 110 from a dAta enable seguence of the type 128 and 134 data message.
A compari~on of the information that must be transmitted using the scheme of FIG. llA, at time tz~ with that of FIGS.
llB or llC at time tz readily demonstrates the reduction in message transmi~sion overhead produced using either symbolic 6ignaling scheme in accordance with this form of the present invention. Al~o, the tech~;~ues illustrated in FIGS. llB
and llC ~nhAnc~ the flexibility for producing user-customized displays in accordance with particular client requests while reducing the volume of data enAble se~nces to display ~nd update financial market information.
In this regard, the user who is enabled with a ~e_e~ion key may select locally a new location for a tile of financial market information selected from the enabled finAnC;Al market information. To do so, the user would ~elect the tile using the keyboard 319 or a mouse 319', and define an offset of the ~elected information by moving the tile to its new display location on the video ~creen, relative to either the origin of the underlying source portion of the financial market information or to the origin of the default tile location. This new tile po~ition -. information is communicated over cGl.~.ol bu~ 318 to host CPU
425 (see FIG. 11) which may generate a new initialization message with the SRK for the tile (i.e., an information identification code) and new display coordinates.
Thereafter, any update data for that tile will be mapped from the position of the update data relative to the default CA 022~76~9 1999-01-12 W093~ PCT/US93/04361 origin onto the user-defined tile and di~played (to the extent the update data C~1D in the u~er-defined tile).
The u~er may relocate the tile to a different position on the display screen. This change also will be either followed by an initi~lizAtion message so that any update data falling within the first defined tile is mapped into the new display loc~tion, which remains the same with respect to the dicplay location relative to the original page or is remembered ~o that any update data falling within the firgt defined tile is mapped into the new dicplay location by the APcoA~r, e.g., by ad~usting the display : coordinAtes as the update data are stored.
The use of ~econA~ry ~ecc~ion keys provides a convenient t~c~nique to minimize message overload. Moving a tile lS defined by an enabled rsconAAry ~e_c~ion key and initial (or default) display coordinates, has the effect of changing the display coordinates ~o that the data co. L e~lJOl"i i ng to the ~econA~ry e~e~ion key will be mapped into the tile in its new location. Thus, the user may easily customize the provided data for commonly used data by using stcon~ry reception keys and initiAlizing the display coordinated for the financial market information.
Referring now to FIG. llD, an embodiment of a decoA~r 316 --employing symbolic signaling operates in the following ~manner. The following definitions are used. DID is a unique AeCoAer identification code; DIDR is a DID code in a message received by a given A~coAer; DIDo is the unique DID
code stored in a given A~CoAe~; RK is a reception key; RKR
is the f irst reception key in a message received by a A~coA~r; RX~ ic a ~e_e~-ion key in a message received by a A~co~er that was not previously stored in the ~coA~r; RKo is a reception key that was previously stored in the AecoAPr; R~ is a start row number; Ct is a start column number; and D is a string of data to be displayed.

. . , _ ~

W093/23~ PCT/US93/04361 There are at least seven types of message6, wherein the brackets contain the identified field~ of the mes6age as follows:
~nable Rece~Lion Messaaes DID, RK~
[DID, RKN, Rt, Ct]
Tnitialization Messages tRKo~ Rt, Ct]
tRKo~ RK"]
tRKo~ RK~, Rt, Ct]
Data Fnable Se~uence tRKo~ D]
tRKo~ Rt, Ct, D]
The enable ~ece~Lion mes~age that as60ciates a DID and an RK~ provides the A~coAPr having a DIDo matching the DIDR code in the messAge with a new reception key RX~, which i8 stored and thus becomes an RKo as to subseguent messages. The APcoAPr may 6tore one or more RKos At any given time.
The enable reception message that associates a DID, an RK~
and an Rt and Ct provides the APcoAer having a DIDo matrhin~
the DIDR in the message with a new reception key RK~ and display coordinate information (Rt, Ct) for that RK~. The display coordinates are relative to the video screen origin (on the underlying tile). The AProAPr can 6tore many different RKos and their ~GlLe~,o~ ng di6play coordinates intenA~A for display on any particular video screen. Each enable ~eca~Lion message will be ignored by any AecoA~r not having a DIDo matching the DIDR in the received message.
The initiAl~zation message that associates an RKo and display coordinate information R~ and Ct will provide the new display coordinate information for the already stored reception key RKo for each AecoAer that was previously ; enabled with that ~ec~Lion key RX~. The display coordinate information defines the off6et of RRo relative to the video screen origin (on the underlying tile).

CA 022~76~9 1999-01-12 WOg3/2~8 PCT/US93/04361 The init~A11~Ation mes6age that A~oc-~Ates _n RX~ _nd _n RX~ will enable e_ch A~coA~r that was previou~ly enabled with RXo with an additional new ~e_e~Lion keY RX~ in the received message for the same portion of displ_y S information.
The initialization mess~ge th~t associates an RX~, RK~ and R# and C~ enables each AecoA~r previously enabled with reception key RK~ with an additional new le~e~Lion key RK~
and display coordinate information (R#, C#). The display coordinate information defines an offset for the reception key RK~ relative to the video screen origin (on the underlying tile).
Each initialization message will be ignored by a AecoA~r ~ that was not previously enabled with the reception key (RK~) that matches the reception key RK~ in the received message.
The data enable sequence that associates an RK~ and data D
is provided to each A~coAPr and the data is retrieved by each AecoA~r that was previously enabled with the identified RKo and i8 ignored by the other AecoA~rs. If no display coordinate information R~, C~ has been stored in the decoder for the identified la~ayLion key RX~ in the received message, then the decoder will store and display the data D
without an offset rel~tive to the stored origin of the tile corresponAing to RK~; when there i~ associated display coordinate information stored it will be used.
The data enable sequence that associates an RXo, data D to be updated and display coordinate information R#, C# is provided to each AecoA~r and is retrieved by each A~coA~r that was previously enabled with the identified RX~ and i8 iyl-G~ed by the other decoAPrs. The data D is stored and di~played using the provided displAy offset information (R#, C#). Thus, the data is displayed at a location offset by R#
and C# relative to either the video screen origin (if no previous RKo offset was stored in the d~coAer) or the data is displayed offset by R# and C~ relative to the previously stored offset of RK~.

CA 022~76~9 1999-01-12 W093/2~ PCT/US93/~361 Referring still to FIG. llD, a flow chart for symbolic si~n~l~ng, from the perspective of me~sage~ received at the PCOA~r, will now be ~C~ A. The y~o~~Rsing routine i6 entered at node 1200, and it p~-e8 to step 1202, which tests for a received message. When no message is received, the APco~Pr Oystem leLu~o to node 1200 and waits for a message. When a message is received, the routine yLbf~e~3s to ~tep 1204 where the message iB evaluated first to determine if the firOt ,L__yLion key RKR in the mes6age is a received code DIDk that matches the unigue DIDo (typically a code stored in a ROM device in the AecoAPr). Upon a match -the sy6tem moves to step 1206 where the r~~onA received ~e~eyLion key RKR in that message is considered a new reception key RK~ and is stored in the AecoA~r. That RX~
thus becomes a stored ~e~eyLion key RKo as to any subseguently received message.
Following storage of a ~e~eyLion key at step 1206, the routine advances to step 1208, which determines whether the mess~ge contains row R~ and column C~ information associated with the received and just stored reception key. If offset information is present, the associated display coordinate information R#, C~ is ~tored in step 1210, and defines the offset for that received and stored ~ece~Lion key RK~ The offset is defined relative to the origin of the underlying tile. Following storage of the information, the system ~eLuuns to node 1200 for the next message. If there is n display coordinate information in the message, then the 6ystem returns to node 1200 for the next mes6age.
If at step 1204 it is determined that the first reception key RR~ in the message does not match the DIDo code, then the routine moves to step 1212 and the message is evaluated to determine whether the first received ~e eyLion key RR~
; matches a previously stored reception key RKo for the A~coAe~. If it does not, then the routine ~eLul,.s to node 1200 and waits for the next message. If it does, then the routine proceeds to step 1214 where the message is evaluated CA 022~76~9 1999-01-12 W093~2~ PCT/US93/04361 to determine if it also contains a new ~çcon~ reception key RX~.
If a new ~ecey~ion key RX~ is y~e~nt, then the routine procee~ to step 1216 And the new ~çcon~ Le_eyLion key RK~
is stored, and thus becomes a stored reception key RR~ as to any subsequently received message. After storage of _ new ~e_c~Lion key, the routine next ~Lo~Pe~l~ to step 1218 where the message is ev_lu_ted to determine if it contains display coordinate information R~, C~.
- If new display coordin_te information R~, C# is ~-ent at step 1218, the offset location information for RK~ i8 :stored at step 1220. If the message does not contain a new ~ecc~ion key RX~ as determined at ~tep 1214, then the routine pA~r?s to step 1226 where the mess_ge is ev_luated to determine if new display coordinate information R#, C~ is present. If it iB~ it is stored at ~tep 1228 to define the offset for the data associated with the reception key RK~.
If the message does not contain displAy coordinate information, or after any such information is stored, the routine pA~?r to step 1222 where the message iB evaluated to determine if any data iB present. If no data D iB
present, then the routine ~eL~ns to node 1200 and waits for another message. If data D is present, then it is stored and displayed using the display coordinate information most recently associated with the ~tored ~e_c~ion key RX~
matc~ing the received reception key RK~ in the message at step 1212. Thereafter, the routine .eL~L..8 to node 1200 and waits for the next me~ e.
It iB noted that the symbolic signaling routine may be combined with the nonsymbolic sign~ling tec~niques described above. It al~o is noted that other enabling, init~Ali7ation and data messages and complementary messages for disabling ~e_eyLion and/or removing ~LceyLion keys and display coordinate information can be created, sent, and processed in a similar manner.

CA 022~76~9 1999-01-12 WOg3r23s58 PCT/US93/04361 According to the ~.~qnt invention, the ~n~oAPr store~ a composite page 200 as a number of tile definitions ~nd mes6Ages. Thi~ allows the ~y~tem to ~tore, tran~mit, ~nd/or display informAtion in an efficient manner using _ terhnique ; 5 referred to as cellular mi~oyL~phics. Cellular micrGy.aphics is described with reference to FIG. 15, Tables I and II, and an illustrative cellular mi~lGy.aphic~
transmission algorithm, using two (one fo.ey-G~.d/one hAckJ~o~.d) color~ per pixel wherein: all cells 210 in an alphamos_ic tile 250-A are tran~mitted _s exte~P~ ASCII
charActer~, i.e., e_ch character is represented by one byte :of data and there is one character per cell 210; cells of a graphic tile 250-G _re transmitted as one or more bits per pixel and, hence, multiple bytes of data per cell 210;
graphic tiles 250-G mAy contain both gr_phic cells (multiple bytes of data per cell) and alph_mosaic cells (a single byte of data per cell); and, for the sake of processing efficiency, e_ch tile 250 (exce~L video tiles 250-V) may run-length encode the signals (either horizontally or vertically) prior to tr_nsmission.
FIG. 15 shows a graphic tile 251-G th_t has ten cell rows _nd ten cell columns _nd is described in Table I, where b=blank character per cell, a~one ASCII character per cell, _nd p=pixel defined cell.
TARTF I
Cell Row Contents Notat~on R0 10 blank ch_racters lOb R1 10 ASCII characters lOa R2 10 blank char_cters lOb -. R3 5 blank ch_racters, 3 pixel defined 5b,3p,2b cells, 2 blank ch_racter~
R4 3 blank character~, 3 pixel defined 3b,3p,4b cells, 4 blAnk characters . . .

- CA 022~76~9 1999-01-12 .
WOg3~K8 PCT/US93/04~1 R5 2 blank characters, 2 pixel defined 2b,2p,6b cellc, 6 blank characters R6 2 blank characters, 1 pixel defined 2b,1p,7b cell, 7 blank characters R7 1 blank character, 2 pixel defined lb,20,7b cells, 7 blank characters R8 10 blank characters lOb R9 10 blank characters lOb Because the cellular mi~lGy,aphic alqorithm preferably uses run length ~ncoAing and cell wrapping within the tile 251-G, the tile 251-G can be completely defined by the messages described in Table II. The calculations in Table II assume that ~ingle-bit-per-pixel signaling is being used and that each pixel-defined cell 210 is individually specified by 16 bytes of data (sixteen rows of eight columns of single bit values).

TABLE II
Message number Representina T-~nath r in bYtesl 1 llb 1 ~1]
2 8a 9 ~1 + 8]
3 16b 1 tl]
4 3p 49 ~1 + 3(16)]
5b 1 [1]
6 3p 49 ~1 + 3(16)~
7 6b 1 ~1]
8 2p 33 ~1 + 2(16)]
9 8b 1 ~1]
lp 17 ~1 + 1(16)]
11 8b 1 tli CA 022~76~9 1999-01-12 W093~23~ PCT/US93/~361 12 2p 33 11 + 2(16)]
13 27b 2 tl + 1]
TOTALS: 100 cells 198 bytes Thus, by using the cellular mi~.G~raphics technique of the present invention, the amount of required transmitted data to displAy the tile 251-G is rPAl~r~A by a factor of a~Loximately eight from 1,600 bytes to 198 bytes. The 1,600 bytes is based on 16 bytes per cell and 100 cells.
The 198 bytes represent 13 co..Llol bytes, 8 ASCII
character~, 11 pixel cells (16 bytes each), and 1 blank, or:
13 + 8 + 11(16) + 1 ~ 198 Still greAter efficiencies may be accomplished by using run length encoAi~ within pixel defined cells.
Referring to FIGS. 11, 16, and 25-27, a DV bus signal structure and signaling method, between the ~ncoAer 312 and a plurality of A~coAPrs 316 and/or desk interface units 321, in accordance with a preferred embodiment of the invention, is shown. The PnroAer 312 includes a receiver 510 for receiving input messages from A host central processing unit (CPU) 425 and a residual video converter (RVC) 400. These messages are then applied to ~n error detection and ..e_~ion (EDAC) circuit 520, which adds parity and interleaving to protect against both single and burst errors. The o~ L of the D AC circuit 520 is pAs~e~ to modulation circuit 530, which functions to increa~e the data throuyl.~uL rate and facilitate cubsequent signal ~Lo~e~sing and clock recovery in each APcoAPr. References to a APcoAer should be understood to include desk interface units 321 where the context permits.
Modulation circuit 530 ~G~I~e~ ~s the binary digital data into a guad level (8,9) modulated signal, as described below. The ouL~L of the modulation circuit 530 is passed to the multiplexor (MnX) circuit 540 which switches between, on the one hand, the digital data from CPU 425 and video CA 022~76~9 1999-01-12 WOg3/2~ PCT/US93/04361 dat_ from RVC 400 and on the other h_nd time-compressed television ~LGy.~m information sign_ls which are received from television feed ~ elLer (TFC) 450. MnX circuit 540 drives the ~uLy~L of ~ncoAPr 312 onto DV bus 314.
E_ch A~coA~r 316 (only one is Ai-cl~c-6~ for the sake of convenience) includes an analog front-end signal proce~~or (AFESP) circuit 610, which receives the DV bus ~ignals, recovers a clock signal from the modul_ted ~ignal and e8t~Abl 1 ~h~C detection thresholds for ~GcEssing the guad level DV bus signals. The Gu-~u- of AFESP circuit 610 i8 -p~sre~ to demultiplexor (DEMUX) circuit 620, which - demultiplexes the television ~o~am information signals and the digital-video cignals, 6uch that each may be further proceF--~ and provided to video ~creen 317. DEMUX circuit 620 passes the digital-video signals to demodulator circuit 630 which converts the guad level (8,9) modulated 6ignals into binary sign_ls.
The ouLpuL of demodulator circuit 630 is pas-~~ to error detection and correction (EDAC) circuitry 640, which uses and then removes the p_rity bits to ouL~u~ digital signals that correspond to the ~ignAls input to ~ncoAer EDAC circuit 520 a8 a best estimate of the intended messAge. The message is then transmitted to circuit 650, which chec~ the synt_x of the message _nd stores the displ_y information in the designated address locations of ~ picture 6tore memory.
The television ~Loy~am information signals separated from the DV bus message by DENUX circuit 620 are separately sr~~ to circuit 670 which ~6-.ve~ Ls the compres~ed television ~lGy~m information signal into displayable television image signals, and then provides those image ~ignals to switch 680. Switch 680 selects between passing the television image signals and the digitAl display inform_tion to video screen 317.
As illustr_ted in FIG. 17, signals trAnsmitted on DV bus 314 are transmitted in packets t. If no television ~Gy~am information sign_ls are to be transmitted on the system, the _.

- CA 022~76~9 1999-01-12 W093/239~ PCT/US93/~361 packet t may have a time length that is variable, according to the amount of data in each mes~age. If television ~oy~m information signals are to be transmitted, then the packet t has a fixed and uniform time length ~Le~rQnAing to time length of the television etAnA~rd video ~can line.
Thus, for NTSC television, the packet t time block is about 63.s mi~ nAc.
Each packet t includes a digital display information packet d including a h~ r portion H, a data portion D and a parity portion P. The he~Aer H contains information that allows each A~oAer 316 to identify the beginn~ng of a packet t, and to detect digital signal transitions to compensate for the transmission loss characteristics of the communication chi~nnel. The parity bits P are collectively illustrated as following the data D in FIG. 17, but in practice may be interspersed among the data D according to conventional parity and interleaving error detection and correction coAing ~echniques.
The digital packets d carry all the display information except television ~LG~Lam information ~ignals. One or more digital packets d constitute a DV bus ~message~ used by each AecoAPr 316 to modify the displayed screen image.
Each packet t also may include a television (signal) packet v, including one or more realtime television p~Gy~am signals illustrated as ~TV~. Signals for different television images are given different letters, such that TVA, TVB, and TVC represent three different television display images. The subscript numbers l, 2, and 3, represent consecutive lines of a given television image field, such that ~ignal TVAl is followed by TVA2 in a following video packet v, thereby to provide the first and ~?conA lines of the odd line (or even line) field of -~ television image TVA. As noted above in ronn~ction with FIG. 7A, the fields alternate odd and even video scan lines on the video screen, and two fields form a frame of video, e.g., about one-sixtieth of a seconA per field and one .. . . . ..

CA 022~76~9 1999-01-12 W093~23 ~ PCT/US93/~361 thirtieth of a r-: ~nA per frame. The televi6ion ~Gy~am information signal~ TV are preferably time-compressed and may be either an analog ~ignal, for example, using multiplexed analog component (MAC) enco~ing~ or a digital signal, for example, using digital compression methodology (e.g., JPEG, MPEG). In an embodiment where digital television ~Gylam information cignals are used, the video packet v may be omitted so that all the digital data is transmitted in the portion data D of a digital packet d, and 0 ~ G~ as a tile of pixel based digital di~play information.
- The digital packet d of each packet t may vary from one time length tn to the next t~l, AepPn~ing on the amount of data D and television video information TV that i~ to be transmitted in each packet t. To reduce the amount of memory required in each Aeco~Pr 316 that is equipped to receive a reAltime television ~,o~.am information signal, it is useful to ~ignal an amount of information e-ess~ry to generate about one TV scan line within the time period t of one TV line. With reference to FIG. 17, this means that the ~ecQn~ TVB line TVB2 must occur no later thAn 63.5 mi~o~~conAC after the first TVB line TVB~. This does not however, require that the co~ec~tive TVB line signals be uniformly or periodically spaced.
Typically, DV bus messages are not sent to a decoA~r 316 faster than the decoder 316 can buffer and act upon them.
Because the DV bus 314 is a simplex transmission ch~nnel, the e~coA~r 312 must keep track of the messages being sent to each AecoA~r 316 and the time required to execute each message. Subsequent messages are queued until all of the decoA~rs 316 that have to receive and act upon a given message are able to do so.
Referr~ng to FIGS. 16 and 18-19, modulation circuit 530 and demodulation circuit 630 are complementary for the selected modulation protocol. There are four considerations for selecting a signal modulation method: (1) clock CA 022~76~9 1999-01-12 W093/239~8 PCT/US93/~36 ~e_ove~, (2) ~t_rt of message identification, (3) information tr_nsmi~sion rate, and (4) bit error rate. All ~C0~8 316 must ~ac~eL a digit_l clock from the received DV bus ~ign_l. Therefore, the tran~mitted DV bus signAl must have an adequate number of digit_l transitions for this ~_-e~ regardless of data D content. Further, the decoder 316 must be Able to determine the ctart of the message in a reliable manner.
In the present invention, a qu_d level digital signal, tr_nsmitting two bits of information every signAl~ng interval SI is used as a reAronAhle engineering trade-off :between data thro~3~ L and bit error rate. Since each signaling interval SI carries exactly two bits of information, it is also referred to as a ~dibit~ interval.
An (8,9) interval modulation method is implemented to transfer one word tl6 bits) of demodulated data D to the decoder EDAC 640 At a time. The structure of this modulation method is illustrated in FIG. 18, wherein SI is the si~Aling interval and MI is the modulation interval.
The rule for determining the si~nAl ing~ level of the modulation interval MI is to maximize the transition occurring at the leA~i~g edge of the modulation interval MI.
That is, if the signal level in the signaling interval SI
just before the modulation interval MI is level 2 or 3, then the modulation interval MI signal is set to level 0. If the signal level in the signaling interval SI just before the modulation interval MI is level 0 or 1, then the modulation interval MI signal is set to level 3.
Referring to FIG. 19, the heA~r field H i~ 50 signaling intervals SI long and includes six subfields. These subfields provide information to each decoder for the decoder to recover the clock signal and compensate for the transmission characteristics of the DV bus 314 and any intercQrnections.
Subfield one h_s a length of 9 signaling interval~ and contains eight dibits of the maximum value signal. This is .

.' CA 022~76~9 1999-01-12 . ~
WOg3/239~8 PCT/US93/04361 followed by ~ubfield two, which ~180 is 9 si~na~
interval~ long and which contains eight dibit~ of the minimum value signal. These two ~ubfields intentionally violate the modulation rule and ~et the maximum and minimum input signal range to allow the ~PcoAPr 316 to detect the ctart of a packet d and fine-tune its decision thresholds to compen~ate for attenuated received-~ignal level~, and may be used to ~ignal the possibility of the beg~ nn~ ng of a hPA~Pr field H. However, the start of a data decision will only be -made after all six ~ubfields are properly received.
- Subfields three, four, and five each have a length of 8 ~ignaling intervals and may be used to fine-tune decision thresholds to discriminate between signals at levelg 1 And 2, Tl2, levels 2 and 3, T23, and levels 0 and 1, Tol, le~e_Lively. This is analogous to double-ended clamping of a binary digital signal.
Subfield 8iX has a length of 8 signaling intervals SI and is used as a delay and clock run-in prior to the ~tart of data field D. It is al80 used to ~pecify the interleaving depth for Error Detection and C~L.e_Lion (EDAC) as expl A ine~
next.
Referring to FIGS. 16 and 19, the ~ncoA~r EDAC circuit 520 adds parity bits to the message. This permits the d~coA~r 316 to detect and co~,e_t the errors that occur during signal transmission. Parity both increases the reliability of the messaging, as evidenced by a decreased bit error rate, at the DYpen-- of decreasing the message data throu~ uL.
Development efforts indicated that an error detection (e.g., che~k~um) and replication cG~.e_Lion method would likely be ~nA~e~uate. It was dis~vYe~ad that system performance was im~loved by using a ~ingle error ~G~Le_ting and double error detecting code (e.g., Hamming) within a single level interleaving framework. While non-interleaved burst error correcting codes exist (e.g., Reed-Solomon), their implementation was believed to be more difficult in an CA 022~76~9 1999-01-12 W093/~ PCT/US93/~ ~1 ASIC environment in which the pre~ent invention i~
preferably implemented.
Referring to FIG. 20, digital data D to be transmitted i8 written bit by bit horizontally into a double buffer. When the first row of data is filled, data is written into the next row and the parity bits P ~G~e_lol,~ing to the data D
in the first row are calculated according to the EDAC
methodology rule 6elected. This ~ce~-8 con~n-~e~ until the entire buffer is filled. The buffer is then locked to prevent further input, and transmitted to the modulator circuit 530 bit by bit vertically. The buffer may be reused :after its entire contents have been transmitted; double buffering sustains continuous message ouL~uL from the ~ncoA~r 312.
Each buffer row includes both data D and parity P, and represent~ one codeword. Assuming that a single error ~G~.e~ing double error detecting code h~s been used, without interleaving the following errors illustrated in FIG. 20 have the results indicated in Table III:

TAR~ ~ TII
Error Codeword errors Action A,J,K,L Single in data field Correctable B Single in pArity field Correct~ble C,Z Double in data field Detectable, not correctable E,F Double Detectable, not correctable G,H,I Triple Not detectable, may not give error -- The nature of the digital video bus 314 is that errors occur in bursts. Apart from randomly G~ ing single bit errors, the probability of a ~econ~ error immediately following the first error is relatively high. For example, .. .. ...

CA 022~76~9 l999-0l-l2 W093~ PCT/US93/~361 if the probability of a first error is 10-9, the probability of the next bit being in error is not 10-9 but might be o.s, and the probability of the following bit being in error might be 0.8. Therefore, a single-correcting methodology is ineffective in this type of transmis~ion chAnnel.
Interle~ving, i.e., buffering the data to be mes~aged horizontally and transmitting it vertically, causes burst errors to be spre~d among ~everal codewords. In this regard, a burst error J,K, and L of length three in the channel is mapped into three cingle codeword e~LG-C and this is correctable by the chosen error detection and correction , scheme.
By choosing a large interleaving depth of n codewords, e.g., 32 codewords, it is possible to protect against lS relatively long burst ellGLs with a relatively simple single error correcting code. For example, when using _n interleaving depth n of 32, _ burst error of up to 32 bits is fully correctable, all errors of length 33 to 64 are detectable, ~nd all those with greater length could possibly result in errors. The oc~ ence of single bit errors plus burst errors will degrade the performance of the system in a manner determined by their location.
The maximum possible interleaving depth ~p~n~c on both the maximum buffer size ~nd the number of TY signals to be transmitted. This is because each time-compressed TV signal must o~u~y a time slot G~uLLing once a line time, i.e., in s1~ccescive packets t. Therefore, the maximum length of digital packet d is determined by both the television ~LGy~am information signal compression factor and the number of TV signals being transmitted simultaneously. Preferably, the interleaving depth n should be maximized within the time constraints imposed by the number of TV signals being transmitted. Thus, with reference to FIG. 7A, the possible interleaving depth n between lines U and W and between lines X and Y are the same, and is greater than the interleaving depth m between lines W and X and between lines Z and V.

CA 022~76~9 1999-01-12 This i~ hecA~re the latter two series of DV bus signals algo include TV line~ for television ~Gy,am information signal~
TV2 and TV3. Accordingly, the interleaving depth n will change with the amount of television ~Loy~am information ~ignalg being transmitted.
Referring to FIGS. 21-23, a plurality of digital video bus mes~ages are now described. The messageg are ~iGl-LLolled in two layer~, a transport layer, for detecting and receiving data ~;ent to a gpecific ~PcoAPr 316, and a message layer, for executing application firmware or software.
~L G~e_Sing iS done by _ cugtom Packet Reception Application-Specific Integrated Circuit (ASIC) including a mi~.o~.o~,ecsQr located in the receiver module 610 of the ~pecific ~eco~3~r 316. The ASIC module 610 may have any structural implementation 60 long as it performs the signal .ocer-sing functions described and illustrated.
Configuration of an ASIC i8 within the ability of a person of ordinary gkill in the art.
Regarding the transport layer, referring to FIG. 21, the transmission of variable length packets d are concatenated to form complete messages in the presence of time multiplexed television ~oy.am information gignals (e.g., TVA and TVB), are ghown. The message format is summarized in Table IV below:
TABLE TV

Mess~qe fM) Packet (t) Interleavinq Depth . 4 D2 -. 35 2 D2 CA 022~76~9 1999-01-12 W093~9~8 -PCT/US93/04361 3 1 Dl The interleaving depth i~ defined in terms of the total time of television y~GyLam information signal~ yL -~nt in the video packet v of a packet t. For example, the fourth packet t in me~sage 1, designated Ml-P4 in FIG. 21, has an interleaving depth of D2 COL 1 e~1~O. ~-1; ng to the time used by the two TV signals.
Referring to FIG. 22, the location of the digital packet d fields are illustrated. Field 0 contains a message h~A~r. Field 1 contains the end of message (EOM) flag which indicates thAt the current packet d is the last one in the current mescage when the EOM flag is set. This enables the hardware to process the ~e_eyLion keys contAin~ in fields 2 and 3 of the packet d, to determine whether further processing of this packet d is reguired.
Fields 2 and 3 contain the ~e_cyLion key which is formed by the address type and address. More specifically, Field 2 contains the ~address type~ which is used to specify the me~ning and use of the contents in the address (Field 3).
In a preferred embodiment, the address type field contains two bits. A value of 00 indicates that the following address field contains a unique display identification code for a given a ~ecoAer video ccreen, i.e., a DIDo. If the address field value is 01, then the address field contains a new to be stored information identification code for a tile 250, i.e., an R~. If the address field is 10, then the address field contains a previously stored information identification code for a tile 250, i.e., an RKo~ If the address field value is 11, then the address field contains a packet sequence number (PSN), having a value of from 1 to 31, and the decoder 316 checks for sequential numbering of CA 022~76~9 1999-01-12 W093~23~8 PCT/US93/04~1 packets d within the m~r-gc. An out-of-sequence number causes the entire message to be re~ected.
Field 3 is the 'address field' and may have up to 21 bit6. Accordingly, there may be up to 22l e 2,097,152 different unigue identification codes for each address type, i.e., video screens and pages, ~ecv~ds, portions and tiles of display information.
Field 4 has sixteen bits and provides the 'message length' which is only transmitted in the first packet d of a mes6age. It indicates the total length of the message in bytes.
Field 5 contains the data D used to form the display information message. It has a variable bit length.
Regarding the message layer of the DV bus 314, there are two clA~F~~ of messages that can be accommodated, supervi60ry messages and image data messages. Supervisory messages direct one or more A~coA~rs to perform control and/or hookkeeping actions, such as enabling a le_e~ion key or defining a tile. Image data messages refresh or update the contents of a displayed tile. Such messages always cause the decoA~r video screen 317 to update even if the display information is ~n~h~nged.
All received packets d are concatenated into messages at the decoder 316. The location of the received message fields is illustrated in FIG. 23. Field 0 is the reception key (RK) and contains 3 bytes. Bit 0 i6 set to 0, bits 1 &
2 contain address type and bits 3-23 contain the address (cf. FIG. 22). Field 1 contains the ~mes6age length~; it uses two bytes to specify the length of the message in bytes.
Field 2 is the ~message seguence number~ and is a one byte field. It contains a message seguence number for messages to the reception key RK specified in Field 0. The AecsA~r 316-verifies that the difference between the current and last received message ~equence number is always one modulo 256 to ensure that all messages to the current .. . . _ _ CA 022~76~9 1999-01-12 W093~23 ~ PCT/US93/04361 reception key RK are received in order. When an out of ~equence number i6 detected, an error reguest is transmitted by the ~coADr 316 over the ~G-,L,ol bus 318 (See FIG. 11) indicating the last ~6~ ~ e_ ~ly received me~sage.
Field 3 is the ~Command~ field, and has one byte which indicates the operation to be performed on the contents of the data in following Field 4, the variable length part of the message. A Command mAy be self acting, i.e., the data field contents immediately following is null. The byte -length of the data in Field 4 is limited by the time length t of eAch message and the video signal6 v in each message.
- In a preferred embodiment, the message Command field 3 has the following commands and data Field 4 has the following associated data: A messAge Command byte 0 initializes AecoAD~ hardware And cle~rs the video screen.
There is no associated data. A message Command byte 1 sets the parameters to configure the video ~creen hardware and software. Associated data bytes 0-7 contain the ON and OFF
period for four blink counters, and data bytes 8-11 contain the motion period for four motion counters. A message Command byte 2 operates to clear the video screen, making all pixels the background color. There is no associated data. A message Command byte 3 operates enable reception.
It instructs the uniguely identified decoAer 316 to enable ,ece~Lion for the specified reception key, and associates this reception key with the reguest string for the specific tile 250 ~ent by the dPcoA~r 316 to the host CPU 425 via the cG.I~ol bus 318. For this message Command, the associated data is, for bytes 0-2, the tile ~e_ep~ion key, and for bytes 3-23, the tile reguest string. A message Command byte 4 sets the tile definition. It defines the tile 250 whose number is specified in the address Field 3. The first associated data byte specifies the default color index for the portion of display information. The recQnA data byte specifies the default display attribute. The third data byte represents the number of 6ymbolic tile def initions (the CA 022~76~9 1999-01-12 WOg3/23 ~ PCT/US93/04361 number of 11 byte packet~ following). Each of the~e definitions contains a 16 bit symbol number (tile IID or RK), the two corner display coordinates (upper left and lower right; a rectangular tile holln~ry i~ acsumed), the default ~ymbolic tile attributes and the value of the motion counter if the tile is a p~nning or scrolling tile. The associated data bytes are:

byte 0 default color index byte 1 default di~play attribute byte 2-3 default upper left row and column number byte 4-5 default lower right row and column number byte 6 tile motion attribute byte 7 current motion index byte 8 default character table byte 9 number of text messages composing the tile byte lo current message sequence number(s) for tile messages 1 to n A message Command byte 5 sets the color table. It contAins a number (specified in data byte 0) of definitions for the color table. Each definition contains four bytes.
The first data byte is an index (0-255) into a color table.
The three other data bytes represent backyLGul-d color, foley.G~r.d color and line color respectively. Each of these three data bytes is enco~P~ internally as IIRRGGBB: two bits to define the overall INTENSITY (I), two bits to define the RED (R) intensity, two bits for the GREEN (G) and two bits for the BLUE (B). The associated data bytes are:

byte 0 number of color definitions byte 1 new color index byte 2-4 background, fo-e~our,d, line colors byte 5-8 next color definition (same as bytes 1-4) byte 9-12 next color definition (same as bytes 1-4) A message Command byte 6 operates to send new text to the video screen. The characters contA~n~ in the data section are put on the screen in contiguous columns or row~, CA 022~76~9 1999-01-12 W093~958 PCT/US93/04361 depen~ng on the axis of ron~.c~tivenesC~ using cell wrapping. The a~roc1~ted data bytec are:

byte 0 message id (Tile-relative) S byte 1 message sequence number byte 2 relative row number byte 3 relative column number byte 4 number of data bytes following byte 5...... data in TEXT format A message Command byte 7 provides for downloa~;ng p~Gy.omming code into the ~ecoAer 316 application ~lGy~am memory. The associated data bytes are:
byte 0 ~ Gy~ am revision code byte 1-4 section address byte 5 lAst section flag byte 6...... ~Gy.am code A mes~Age Command byte 8 clears a tile. It causes all pixels in the tile to be set to the default backy-G~.d color. There is no associated data. A message Command byte 9 i8 a ~Genlock~, which is functionAlly eguivalent to a vertical sync pulse in a video signal. There is no associated data. A message Command byte 10 is to define a character set. It downloads a pixel map for a character set for converting a one character byte to a multibyte pixel ~e~e~entation. The associated data bytes are:

byte 0 Character table ID
byte 1 Starting character code byte 2 Number of codes defined byte 3...... Bit map definitions (16 bytes each) When a tile 250 is defined in the encoder 312, a static array of messages is allocated to, and associated with, that tile 250. All mes~ages in the Pnco~Pr 312 are kept in a queue and are sent out, in their entirety, in a message ~ CA 022~76~9 1999-01-12 W093/2t~ PCT/US93/04~1 cycle whose period varies according to system Fch~A~lling constraints.
The system i6 preferably tuned to optimize me~age ~ch~ ;ng for its particular mix of static ~lph~mosaic tiles 250-A, graphic tiles 350-G, motion tiles 350-P, 350-S, RVC tiles 350-V, TFC ~tiles~ 350-V, and the number of AecoAers and video 8~e~D- One ~uitable mescage prioritizing ~-hPA~le i6 the following order: individual ~co~r directed messages, rohPAt~led messages (tile motion cGl.L~ol), tile update data messages, APcoA~r re-requested tile update messages, alphamosaic refresh messages, administrative messages, and graphics refresh messages.
The message layer protocol ~ o-Ls three kinds of attributes for cells 210: motion, cell and color. The motion attribute i8 an eight bit word that is encoAPA MOV, Cl, C0, V, NU, NU, NU, NU, where MOV, Cl, C0, V are movement, movement col.~.ol byte 1, movement cG,-~.ol byte O, video and NU stands for ~n~r~ bits. The cell attribute is an eight bit word and it combines both software and hardware attributes. The byte is encoAP~ REV, ULIN, NU, NU BRl, BR0 BE1, BE0 where BRl, BR0, BEl, BE0 are blink rate 1, blink rate 0, blink effect 1, blink effect 0, REV stands for reverse video and ULIN stands for underline. These last two attributes are implemented in software and therefore need not reside in the character cell. The color attribute is an index into the color table.
The message layer protocol uses a byte oriented TEXT
format to specify co-.L-ol, alphanumeric text, and graphics.
The lowest nine bytes are ~OI.~ ol bytes and have the following special me~n~ngS: Byte 0 specifies that the next byte will contain a repetition factor for run length encoA~ng to specify how many times the cell definition th~t follows should be repeated along the axis of consecutiveness. Byte 1 specifies that the next 2 bytes will contain the rel~tive row and column number applicable to the following text. Byte 2 specifies that the next 16 CA 022~76~9 1999-01-12 WO93~2~K~ PCT/VS93/~ ~1 bytee define a graphic cell to be put in ~ e~L location.
Byte 3 specifies that the next byte is to become the e~CI~
cell attribute, me~n~ng that it will apply to every ~h~eguent cell defined in the message. Byte 4 specifies that the next byte contains the size of the cell specifications to come. The sizeQ allowed are 0 for normal size, 1 for double eize, 2 for triple size and 3 for guadruple eize. Byte 5 specifies that the next byte is to become the current color index, meAning that it will apply ~to every ~h-~~uent cell defined in the message. It is not used for graphic cells. Byte 6 specifies that the following cell specifications ehould be put in consecutive locations horizontally. In other words, to define the address of the next cell, the e~el~ column number should be incremented.
Byte 7 epecifies that the following cell specifications should be put in con~ tive locations vertically. In other words, to define the address of the next cell, the current row number should be incremented. Byte 8 specifies that the ~le~ cell location is not to be modified, e.g., if the cell contains a character that is defined on another line.
For example, if the line 1 contains triple size characters, it also will use line 2 and 3 to display 6uch characters.
Therefore, all character~ on line 2 and 3 will be ~phantom characters.~ Byte 9 specifies that the next byte identifies the character table from which the following characters will be drawn. The new character set remains in effect until another change character set command, or the end of message.
Bytes OAH-OFH are not used and bytes 20H-FFH are normal cell representations. Printable ASCII character codes are preferably used wherever possible.
The following illustrates how the overall messaging efficiency and ~ystem thro~J~p ~, in accordance with this third emho~iment of the invention, may be calculated.
Consider a system in which signal bandwidth is 22.5 MHz, the packet time length t (including the header H) is 63.5 ~s, the error detection and correction code is a 24/30 CA 022~76~9 1999-01-12 W093/23 ~ PCT/US93/04361 H~mming code, interleaving efficiency is 100%, modulation is quad level (8,9), and packet efficiency is 100%.
The si~nAlin~ interval SI may be determined from the system bandwidth as follows:
! S a) the signal edge rise time (tr) 6ho~ be less than or equal to one-third of the signaling interval SI, and b) the bandwidth of the signal (fb) is related to the signal edge rise time by:
(fb) (tr) ~ 0.35 Hence, the minimum signal interval corresponAing to a 22.5 MHz bandwidth is:
~ SId" ~ 3(tr) ~ l-OS/(fb) e 1-05t22-5 MHz ~ 46.6 ns.
The signaling interval is therefore cho~en to be:
SI e 50 ns.
lS Regarding information throughrl~t, ~ince quad level modulation is chosen, two bits are transported in every ~i~nAling interval. The capacity of the ch~n~l is therefore:
~hAnn~~ ~ 2/SI = 2/SO ns ~ 40.0 Mbits/sec ~ 5.0 Mbytes/sec.
This capacity is not actually att~in_~ because first, every packet starts with a SO SI header, every ninth SI
after the header contains no information ((8,9) modulation is used to aid clock recovery), and the EDAC circuits appends six parity bits to every twenty four data bits (a (24,30) Hamming code is used).
~~co.l, each packet maximally lasts 63.5 ~s. Thus, there can be _ maximum of (63,500ns/SOns) ~ 1,270 SI per packet.
The 50 SI h~A~r therefore reduceg the capacity by a factor of (1270 - SO)/ 1,270 - 96.1%. The modulation efficiency i8 (8/9) - 88.8% and the EDAC efficiency is (24/30)~ 80%.
Therefore, the overall efficiency of the DV bus signaling i~
approximately ~ 0.961 x 0.888 x 0.800 ~ 68.27%. This results in an effective DV bus capacity of:
0.6827 x 40 - 27.3 Mbits/sec ~ 3.4 MBytes/sec.

.

CA 022~76~9 1999-01-12 W093~ 8 PCT/US93/0436t In practice the DV bus 314 should be tr~ Ling information at a rate of about 20 Mbits/~ec or more, which is more than ~ -Y t20x) times that of conventional Ethernet sy6tems. It should be noted that Ethernet has a 10 Mbits/~ec r~pac~ty of which perhaps only 1 Mbits/6ec i6 realized after protocol and/or error ~ e_ging.
Referring now to FIGS. 11 and 26, ~G..L,ol bu6 318 ~GI.~016 bi-directional communication between a APcoA~r 316 (or a desk interface unit 321) and the 6y6tem. Host CPU 425 may i6sue messages targeted to a 6pecific decoder or to all decoders, or may request information from a gpecific : decoder. A AecoAPr will 6end a message to the host CPU 425 when requested by the host CPU 425.
Typical uses of the ~G-.L~ol bus 318 from the host CPU 425 to ~0coAer6 316 are to poll a AecoA~r 316 for a message, ingtall a new decoder 316 on the sygtem, update an LED
digplay of a keyboard 319 at a AecoA~r 316 and maintAin the con~lol bus protocol. Typical uses of the ~G..L.ol bus 318 from the decoder 316 to host CPU 425 are to transmit keyboard and/or mouse data (i.e., user requests for display information, or to define or move tiles), ~e~ol~ decoA~r malfunctions, and request 6ystem resoulce~, e.g., DV bus 314 message retransmiggion due to a detected error in message gequenceg .
The structure of ~G.. L.ol bus 318 ig modeled after conventional industry-stand-rd ghared bus models. A
preferred protocol ig one similar to an HDLC llnh~l~nc~A
configuration in normal response mode. A preferred cG..L.ol bug 318 i6 a sy6tem-wide multi-drop RS-422 or 485 network, where the host CPU 425 serves as the primary station and up to 63 decoderg 316 are ~onn~cted as ~conA~ry stations to each RS-422 or 485 strand. Bi-directional communication between each decoA~r 316 and the host CPU 425 i6 ~G--L~olled by a preselected polling scheme emitted by the host CPU 425.
At installation, the host CPU 425 assigns a unique control bus address to each decoA~r. This address consists CA 022~76~9 1999-01-12 W093/23~8 PCT/US93/04~1 of a strand ID, which identifies the RS-422 or 485 line to which the APcoAPr is connected, and a 5-bit polling ID. The polling scheme allows the host CPU 425 to poll each AecoAPr using a single byte, thus making the most frequently used signal the shortest length.
In addition, the host CPU 425 sends commands to a specific A~oAPr 316 using its unique 21-bit A~coAer ID.
Unless there are any errors detected, every APcoAPr 316 along a strand is polled before any APcoA~r is polled a second time. This polling seguence represents a polling cycle. The suitable nominal polling frequency of .2 ~econA, that is, an outstanding message at a decoder will wait not longer than .2 s~cQ~A before it is solicited by the host CPU
425. The baud rate (nominally 9600 baud) i6 configurable, ~epenAing on the number of ~ecoAers in the system. Thi~
means that smaller systems may be able to realize a savings by using fewer communications cG,.LLollers. It also meAns that ~ystems are easily upgradeable, since the system's ~61~ ol bus capacity can be increased by A~Aing communications controllers. Where desk interface units are used, CPU 425 assigns a polling ID for each video screen 317 and polling and command messages are sent for each video screen 317 on the system, rather than to each decoAer 316.
Messages between the host CPU 425 and each A~coAPr 316 are in the form of a transaction. All transactions are initiated by the host CPU 425 and take place between the host CPU 425 and a single AecoAer. Referring to FIGS. 24A
and 24E, the host CPU 425 begins ~ts signal by renAing a probe message (if it has no command for the decoA~r 316) or a command message (if it has a command outs~ nq for the decoAPr) to a specific AecoAPr. Alternately, the host CPU
425 may send a ~Broadcast~ message to all ~ecoAers on that CGnLl ol bue strand 318. Broadcast messages serve a number of ~u.,~-e- (e.g., transmission failure, system-wide keyboard messages, changing communication parameters, etc.).

CA 022~76~9 1999-01-12 ;
WOg3~ ~ PCT/US93/04361 Both comm_nd ~nd Bro~Aca~t messages consist of a uPAA~r~ a seguence element (Seg), and one or more reguests tR-Frame).
Referring to FIG. 24B, each ~ProAPr .~A~G,.-lA to A host CPU 425 signal with either a solicitation message or, if no solicitation is re_dy, an idle message. Idle messages consist of a Seq element only (message bit ~ O).
Solicitation messAges consist of a Seg element (message bit - 1), a poll element, and one or more reguest frames. A
reguest frame (R-Fr_me) contains one or more reguests from lo either the host CPU 425 or the ~ProAPr 316. No more than 64 reguests can be sent in one R-Frame. FIG. 24C shows the structure of an R-Frame and FIG. 24D shows the ~tructure of a single reguest.
Of the three message cl ~F~-~ generated by the host CPU
425, two (Probe and Command) constitute ~ignals. The deroAer must respond within a configurable response interval (nominally set at 5 ch_racter times), otherwise the host CPU
425 regards this as a failed transaction. If the number of failed transactions pAA~ss a configurable Aisco.l.o~L
threshold (nominally set at 5), the host CPU 425 logically Ai rCo~nects the AecoAPr from the network and displays a suitable message to the system adminictrator.
The ignaled decoAPr rc~u-lds to each host CPU signal with a solicitation or idle message. The value of the AK
bit in the Seq element (see FIG. 24G and the A;~c~C~ion below) reflects the ~ece~Lion status of the signal. If the ~ignal was a Probe or a ~uccessfully received Command, the AK bit is 1. If the signal was a Command, and the R-Frame was not received s~cressfully, the AK bit is 0.
The de~oA~r regards the transaction as sl~crPficful if the next message sent by the host is a signal to another ~ProAPr. Otherwise, a negative acknowledgement is assumed.
If the next host message is another ~ignal to this Aero~Pr, it retransmits the solicitation. On an error, the host CPU
425 will re-signal a A~coAPr up to a configurable number of times (nominally 5), ind then send a broadcast message.

WOg3/23 ~ PCT/US93/04361 This inA~cates a communication failure without providing A
~cD~r -~ v~GLLunity. The hoct CPU 425 then cont1n~s its polling 6equence.
As 6hown in FIG. 24E, bit 7 of the poll message i~ always set. Since a poll message can originate from either the host CPU 425 or the APcoAPr 316, bit 6 is used to indicate the source of the poll (0 ~ Host, 1 - APcoAPr). The remaining 8iX bits are the polling ID of the APcoA~r (1 to 63).
Referring to FIG. 24F, Command and 8roAAca~t messAges alway~ originate in the host CPU 425. The 6tructure of byte 0 of these two messAges is identical; however, whereas the command message is ~ent to A 6pecific decoAPr, wherein bytes 1, 2, and 3 of the comm_nd element contains the polling ID
of the dPCoAPr~ the broaAc~st mess_ge i~ 6ent out to all AecoAPr6 on the entire 6trand, wherein bytes 1, 2, and 3 of the broadca6t message have a polling ID - 0.
In addition to mecsage-by-message acknowledgements, each command and 601icitation message i~ assigned a 6equence number (6ee FIG. 24G). The sequence numbers are ron~ec~ltive, modulo 4. These are ~e~G~ ~ed by each station in the NR and NS bit fields of the Seq element. Commands are numbered in the NS field by the host CPU 425 and the NR
field by the APCoApr 316; 601icitations are numbered in the NR field by the host CPU 425 and in the NS field by the A~coAPr 316. In each ca6e, the ~equence number fields contain the next e~e_~ed 6equence number. In other words, the NS field of the ~ e..~ message contains the 6equence number of the next message the sPnAing station ex~e_Ls to send. The host CPU 425 m~intains a unique NR/NS pair for each decoA~Pr. In ~ro~Aca~t messages, only the NS field is meaningful.
Thi6 feature provides an additional means of error correction and detection, since a f~ilure to match one station's NS with the other' 8 NR is interpreted as a request to ~ nA messages with prior sequence numbers. This means CA 022~i76~i9 1999-01-12 WO g3~23g58 PCr/USg3/04361 that each station keeps a gueue of the last 4 me~r~3-~
transmitted. In the event of a sequence number mismatch, ~ll Regs (up to 64) from all outstAnA~ ng ou~ho~nA messages may be concatenated into a new message with the lowest outst~nAing seguence number.
Referring now to FIGS. 11, 16, and 25, a preferred embodiment of an encoA~r 312 of FIG. 11 is shown. ~ncoA~r 312 is ~u..O~.~cted to interface with host CPU 425, and to accept signals from digital s~u~es, analog ~ou~eO~ digital ~video coulce~, analog video 80U~eo~ and realtime television -image signals, in addition to the host CPU 425. Preferably, : the encoder 312 receives video signals from one or more residual video converters 400 and television y~Gy.am information signals from one or more television feed converters 450.
~n~oA~r 312 is preferably configured a~ a single printed circuit board assembly that can be installed in a backplane of the host CPU 425, and may be ~ u~Led by one of ISA, EISA, and VME bus protocols, or an equivalent protocol.
The en~o~r 312 originates messaging over the simplex DV
bus 314 to the plurality of individual AecoA~r~ 316, and also provides duplex communication over the cG.IL.ol bus 318.
It includes an encoA~r CPU 505, which i~ preferably a high ~performance 32 bit central p~G~e~sing unit with direct memory address (DMA) and other integrated functions (e.g., counter-timer). A suitable CPU 505 is model 68332 available from Motorola. It is responsible for ~G..~olling all of the encoA~r functions, including collection of incoming data, message manipulation, determination of transmission priority, and dissemination of outgoing data.
The CPU 505 has an associated ROM memory 506, which contains a small amount of pLGy.am ROM code, e.g., the basic boot code and rudimentary ~Gy.~m functions to allow the encoA~r 312 to perform self-test and communicate with the host CPU 425. The bulk of the e~coA~r executable code iF
preferably stored in a RAM 507, and may be downloaded via CA 022~76~9 1999-01-12 W093/~ PCT/US93/04~1 the host interface 427, thereby providing m~ximum flexibility for reconfiguring the functionality of Pnco~er 312. Alternately of course, the Gxe_~able code could be contA;ne~ in the ROM 506.
Data received via the host interface 427 or the serial interface 508 are transferred by DMA into the ~,GyLam and Data RAM 507 along data bus 504. The encoAPr CPU 505 can then access these messages and perform any n~ce---ry mAnipulation or re ~
The Dual-Ported RAM 512 stores current mess_ges queued by the system, for transmission on DV bus 314. When a new message h~s been prepared by the P~coAPr CPU 505, it is then trAnsferred via DMA bus 504 from the ~lGy~am and Dat_ RAM
507 into the Du_l-Ported RAM 512. These transfers occur during the header period of the signals on the DV bus 314, and are initiated by a high-level interrupt provided by a timing generator 513. The Nessage Formatter and Seguence circuit 514 arc~e-~s new messages loaded into the Dual-Ported RAM 512, and formats the message a8 ~i~c~ for transmission over the DV bus 314.
The host interface and FIFO 427 allows bi-directional communication between the host CPU 425 and the encoA~r 312.
Host messages that are to be transmitted by the encoA~r 312 on DV bus 314 are p~e~ from the host CPU 425 to the encoA~r 312 via the interface 427. Because these messages are only composed of changes to displayed 6creens, i.e., update data, the average bandwidth requirement~ are much lower than for 'realtime' video switched systems.
Messages from the host CPU 425 are loaded into an input FIFO memory device in interface 427 for retrieval by the encoder CPU 505. Configuration information is also pACse~
from the host CPU 425 to the encoder 312. The encoAPr CPU
- 505 will periodically DMA transfer the incoming messages from the FIFO memory in interface 427 to its local ~LGy~am and Data RAM 507 over bus 504.

CA 022~76~9 1999-01-12 W093~ ~ PCT/US93/04361 The host interface 427 can also be used for limited information flow in the other direction. Re_~& ~e~C and command ac~n~wledgements from the encoAor 312 are communicated to the host 425 via interface 427. In addition, data received over the ~G,-L~ol bus 318, e.g., data generated by the user's keyboard 319 or mouse 319', are transferred to the host CPU 425 through this same interface 427 via cG~.L,ol bus mi~.G~ol-L~oller 550. Alternately, the ~G,.L~ol bus 318 may be arc~nre~ by ho~t CPU 425 directly through host I/F and FIF0 device 426 as illustrated in FIG.
25.
The RVC interface 509a consists of a mono-directional data port 509 and ~ bi-directional co..~.ol port 509b that communicate between external RVC modulec 400 and a bus mi~ G~G,.~loller 509c. RVC modules 400 send messages to the encoder 312 that identify pixel change data on video display adapters to which they are conn~cted as described below.
The encoA~r data bus 504 could possibly be busy when multiple RVC modules 400 attempt to send messages asynchronously to the encoA~r 312. Arbitration and flow .-L~ol is, therefore, required. Further, bus and priority arbitration by the interface circuit 509a is preferably provided by RVC bus controller and FIFO 509c in a conventional manner. Typical techniques include: interrupt requests generated by RVC modules 400 and subsequent polling -of data by the encoder CPU 505; ~token passing~ between con~Pcted RVC modules 400 to enable sequential access to the interface bus 504; and time domain multiplexing (TDM) of the interface bus 504 to allow periodic access by each RVC
module 400.
Messages delivered by the RVC modules 400 are identical in structure to those created by the ~n~o~r CPU 505 and are DMA'ed directly into the Dual-Ported RAM 512. Therefore, messages delivered by the RVC modules 400 present no processing overhead to the encoA~r CPU 505. However, the encoder 312 may apply cellular mi~,Gy,aphic te~hniques CA 022~76~9 1999-01-12 !
W093~3~ PCT/US93/04361 (optionally with run length encoA~n~) to further reduce me~sage volume on the DV bus 314.
The serial interface 508 allow~ easy communication and downloaA~ng of executable code, even when the host Interface 427 is not operational. Typically, this port will not be used during normal operation of the sy~tem.
The DV bus signaling protocol described above incGL~oL~tes robust EDAC circuity 520 ~h~n~A by interle~ving of data. The li~el;hooA of erroneous data being dieplayed on a monitor is, therefore, extremely low.
The signal to noise performance should have a bit error rate - better than lO10 in a 38 dB signal to noise ratio, interleaving for burst error protection greater than 16 bits and decompressed TV signal to noise ratio better than 40 dB.
Nevertheless, a further added level of protection is provided by replication roAing~ i.e., retransmi~sion of previously transmitted data, termed ~refresh;ng.~ In other words, undetected cG,Lu~Led data is displayed for only a brief period of time, since the ~ame information will be periodically retransmitted (refreshed) and ~G~le~ed a short time later, e.g., 0.5 ~econA~. Thu6, the probability of erroneous data being displayed for a significant period of time is further reduced by the number of refreshes, until the message is eventually displaced from the Dual-Ported RAM
512 by more recent data. Thus, the Dual-Ported RAN serves as a cache for each portion of display information that is transmitted to a video screen on the system.
Yet another level of protection i~ i..LL~d~ced with respect to enco~;ng and refrec~ng. In this regard, an ESF
time-out period is used (see FIG. 2) such that an enable -. signal flag and enable ~e~e~Lion messages must be retransmitted before the time-out period expires or else the - previously enabled decoder will become intentionally disabled. Further, retransmission of enable reception messages permits periodically changing the information identification codes for each portion of restricted display CA 022~76~9 1999-01-12 WO93~nK~ -PCT/US93/04361 information. ThiQ will minimize the l1~el~hooA that an unauthorized A~coA~r will be able to retrieve and display restricted display information, and because ~ll display information data will be retransmitted, removes the likelihood of ~G.~ ed data being di6played for any significant period of time.
The PncoA~r 312 is designed to use as much of the DV bus 314 bandwidth as possible. Priority i8 given to transmission of new data to keep latency time low. Once this requirement has been fulfilled, the remaining DV bus bandwidth i6 used for refreFhing .ecel.Lly transmitted data.
In one embodiment, the DV bus 314 may include up to 2000 feet of type RG-8U coAY~Al c~ble, and may have attached to it up to 128 AecoA~rs 316 with a 3 dB bandwidth on the order of from 100 Hz to 25 MHz.
The Message Formatter and Seq~encer 514 performs a hardware function ~eD~o~s~ ble for retrieving prepared messages (in proper priority) from the Dual-Ported RAM 512 and generating the ~YGpe~ hP~Aer and message for transmission on DV bus 314. The preferred DV bus definition requires that one packet i8 transmitted every 63.5 ~8 cG.~eD~o..ling to a television video scan line for a VGA
format; for other television formats, other packet time lengths could be used. Long mes6ages are thus broken into ~several ro~ec~tive digital packets d. The Message Formatter and Se~ncer 514 performs division of long messages into multiple digital packets d with ron~?~tive packet sequence numbers.
The Dual-Ported RAM 512 is preferably implemented as a circular message store buffer, with new messages loaded by the CPU 505 overwriting the oldest messages left in the RAM
512. Every movement of the starting data pointer by the CPU
505 causes the Message Formatter and Se~nc~r 514 to begin E?n~ng the new messages before resuming the transmission of refresh messages.

CA 022~76~9 1999-01-12 WOg3~23~ PCT/US93/~ ~1 The interleave ~oA~ 522 burst error protects the outgoing packet data stream. In summary, the outgoing packet data D and parity P are stored in the interleaving RAM buffer 524 in ~raster 6can~ format. The interleave PncoAPr 522 then reads the data D and parity P with the axes rever6ed. Consequently, each decoder 316 is able to detect and ~GL ~ C~ L most errors caused by burst noise. As noted, the degree of interleaving in each packet is APpenAPnt upon the number of television ~Gy.am information signals TV
being multiplexed onto the DV bus 314. The interleave level in each packet d is co..L.olled by the encoAPr CPU 505 and is : communicated to the decoders 316 via the aforementioned message field.
The timing generator 513 generates the various DV bus depenAPnt timing signals used by the PncoA~r 312. An interrupt to the encoder CPU 505 is timed to allow new messages to be loaded into the Dual-Ported RAM 512 during the period when the Message Formatter and Se~Pncer 514 is not accessing the RAM 512. Horizontal and vertical sync ~ignals are provided at ou~uL 515 of timing generator 513 for dissemination to an optional Television Feed Converter (TFC) 450. Multiplexor ~G~ ol signals are also generated at ou~uL 516 for use by an ouL~L multiplexor device 540 to inject the converted TV signals at the a~.G~,iate time in a video packet v during each TV scan line time length t.
Regarding TFC 450, a number of live TV ~ignals may be time compressed and transmitted over the DV bus 314 for display by remotely located AecoAPrs 316. These stAnAArd NTSC video signals will be time-compressed (e.g., by a Multiplexed Analog Component (MAC) ter~n~ue), ~nd then ~. injected onto the DV Bus 314 in a Time Domain Multiplexed (TDM) fashion. Further, the same televi~ion y-G~.am information signal can be provided with different line numbers ~o that one video screen can display the signal at full ~ize and another can di~play it at a different ~ize, e.g., 1/4 size.

CA 022~76~9 1999-01-12 Thus, TFC ~n~oA~r interface 451 accept6 the MAC analog signal~ from several different TFC~ 450. When other television ~LGy,~m information signal compression formats are u~ed, interface 451 is a~.G~,iately modified. In addition, interface 451 provides horizontAl and vertical sync signal6 to the TFCs 450 to ~genlock~ these signals to the master time clock in encoA~r 312. Configuration and ~ L~ol messAges Are also rA~~e~ ~et~Len the host computer 425 and the TFC 450 via a conventional low bandwidth ~erial communications link (not shown).
Digital signals generated by the Me~Age Formatter and Sequence 514 are modulated in the ~dibit~ format, i.e., with four discrete analog levels representing two binary bits of information per ~i~nAl~n~ interval. Signal~ supplied by the TFC Interface 451 are typically high frequency MAC analog ~ignal~. These two ~ignal types are time multiplexed together by multiplexor 540 to form a hybrid signal for transmission over the DV bus 314.
The multiplexor 540 performs this selection ~,G~es8 in ,~ o.. se to ~Gl-L.ol ~ignals provided by timing generator 513. The exact number of TY ~ignal~, and their location within the DV bus packet, are determined by configuration information pA~e~ from the host computer 425.
The DV bus driver 516 interfaces the analog ouL~uL signal from the multiplexor 540 onto the 75 ohm DY bus coAYi~
cable 314 in a conventional manner.
The control bus mi~Lo~o..L~oller 550 poll~ the cG,.L,ol bus interface 552 collects the data from remotely located AecoAe~s 316 and pA~Fes the data to host computer 425. On large systems, this functionality may be performed on a separate Digital Interface Board (see DIB 426 FIG. 11.) The conL,ol bus interface 552 connects the enco~r 312 to a multi-point twisted pair control bus 318. Drivers are used to send and receive differential signals on this cG.-~ol bus 318.

CA 022~76~9 1999-01-12 W093/23 ~ PCT/US93/W36l In one version of the third embodiment of the ~ ent invention, the encoAPr 312 was de6igned u~ing Application--~pec~ f iC Integrated Circuit6 (ASICs). Three Field ~-Gy.~mmable Gate Array (FPGA) ASICs were defined using commercially ~vailable device~. Increases in FPGA densities will allow partitioning the design into fewer FPGA6. The functions of the three FPGAs are distributed ~s follows.

a~I~ FUNCTIONS
1. Host Interface Host Interface & FIFO 427 (except the FIFO itself) (ISA bus) 2. Video Dual-Ported RAM 512 3. Message Message Formatter & Sequencer 514 Timing Generator 513 Interleave ~ncoAPr 522 Referring now to FIG. 29, a modular residual video converter (RVC) 400 in accordance with a preferred embodiment of the present invention i~ ~hown. In thi~
embodiment, RVC 400 includes a video front end and sync separator circuit 710, three video digitizer circuits 720, a video data switch 730, a 6ystem image RAM bank 740, a last fr_me RAM bank 750, _ pixel comparator 760, and a pixel change circuit 770 for identifying which cells 210 of a composite page 200 of display information have changed pixel information and the pixel change information.
Preferably, each RVC 400 operates under the cG.. ~ol of a mi~LG~ocesFor (CPU) 780. CPU 780 has associated memory RAM
781 and memory ROM 782 and a direct memory address capability, and a DMA control and data bus 785. CPU 780 _lso has an Pnco~r interface 783, for interfacing with an enco~Pr data bus interface 509a and ~GIlL.ol bus interface 509b (FIG. 25) and a host CPU interface 784, for interfacing with a host CPU 425.
The RVC 400 may be configured to accept one of three different types of input video signal6, namely monochrome, CA 022~76~9 1999-01-12 WOg3~K8 PCT/US93/04361 EGA/CGA, or VGA. For monochrome video signals, three BNC
connector~ 711 ~re provided to accept video feeds from three inAepenADnt monochrome video signal feeds. For EGA/CGA
video ~ign~ls, one type DB-9 ~Q,,,~C .-or 712 i8 provided to accept one EGA or one CGA input video ~ignal feed. For VGA
video ~1qnAl~, one type DB-15 co~n~ctor 713 is provided to accept a single VGA input video ~ignal feed, ~uch that the ~ignal may be anAlog or digital RGB ~ignals. The~e co~n~ctor~ and their pin rQ~nections, are conventional and known in the art. Preferably, RVC 400 includes a jumper or ~witch selection (not shown) to select which connçGtor ouL~, col~e~o,-ding to the type of video ~ignal feed, will be input to the RVC 400. Thi~ may be in~o~o~ated into front end circuit 710 or into a cable converter having a stA~AArd connector on one end.
Referring to FIG. 29, the front end circuit 710 includes circuits to separate the horizontal and vertical sync signals from the input video signals. In the case of non composite video inputs, the a~, G~ iate video connector pins must be selected for provision of these same signAl~. When RVC 400 is to be used to digitize A three color signAl, e.g., CGA, EGA, or VGA, the sync signals respectively fed to the three video digitizers 720 are synchronous. Further, front end circuit 710 may include an analog color matrixing circuit to ~GIlVe~ L color R,G,B signals into Y,U,V signals for more efficient digital encoAing of the signals. When the RVC 400 is used to digitize three monochrome video signAls, all three sets of sync signals may be asynchronous.
Alternately, each RVC could be configured with one type of co~nector~ e.g., cG~ or 711, 712 or 713, in a dedicated manner for processing only the coL~e~l,o~ ng type of video signal. This configuration would simplify the manufacture of moA~lAr circuits, 80 that different RVC 400~s would be used for processing the different format video signals. Thus, the user of the RVC 400 may ~elect the appropriately configured module and insert it into the CA 022~76~9 1999-01-12 WO 93/23958 PCI~/VS93/04361 printed circuit board for CG~VL~ ~ing the received video signal.
Referring to FIGS. 29 and 30, the three video digitizer circuits 720 have the ~ame construction and operate in the 6ame manner, and therefore only one such circuit i~
described. E_ch video digitizer circuit 720 receives from front end circuit 710 one video signal video input feed at input 721, a vertical sync ~ignal VSYNC for th_t video signal at input 721v, and a horizontal sync 6ignal RSYNC for that video ~ignal at input 721h. The vertical sync signals are r~ directly through circuit 720 to ouL~L 722v.
: A double-throw switch 723 is provided to configure circuit 720 to ~GCC_S digital video sign~ls and analog video signals. Switch 723 may be manually configured or, more preferably, configured by RVC CPU 780 by a~,op.iate commands over the control and data bus 783. Switch 723 is illustrated in FIG. 30 in the po~ition for accepting and digitizing analog video signals. In this configuration, the signal VIDEO at input 721 is pA~ to a flash analog to digital converter (flash ADC) 724 and a digital threshold comparator 725.
Flash ADC 724 accepts differential analog video signals, for minimization of common-mode ground noise, where it is loc~lly converted to a single ended signal. The flash ADC
724 is preferably capable of operating at the 32 MHz VGA
video rate, and its Gu~L may be asynchronous, and not ~er~n~Pnt on any timing clock. Thus, flash ADC 724 converts the 6ampled analog signal VIDEO into, e.g., an eight bit digitized ouL~u~.
In the preferred embodiment, the digital threshold - comparator 725 performs a combinatorial logic function that maps the m-bit ou~u- value of flash ADC 724 into an n-bit pixel value, e.g., a two bit value. This renders the analog signal VIDEO compatible with conventional video signals that are digitally transmitted. Digit~l threshold comparator 725 uses three ~LGyLammable binary thresholds that define four ~- CA 022~76~9 1999-01-12 WOg3/2~ PCT/US93/04361 video 6$gnal amplitude region~. The binary tl~hold value6 are ~Gy.ammed by CPU 780 at input 725. Thus, the two bit digital rignal assigns the analog input ~ignal amplitude to four level~. More particularly, the 8-bit digital value is mapped into a quad level (8,9) modulated signal which has two bits of data per ~ignal ing interval.
Thir is usu_lly adequate when y~Gcessing monochrome ~ignals. ucw-~e~ when p.e_~~ring color 6ignalc, this results in four possible values for each of the R,G,B, (or Y,U,V) signals. Hence, only ~ixty-four different colors may be represented by the RVC 400. Further, assigning two bits :to each of the R,G,B (or Y,U,V) ~ignals does not nec~ssArily ~e~ snt the best use of digital bandwidth.
In an alternate embodiment more than two bits could be u6ed. For exAmple, R'3, Gc3, and B~2 bits (and 6imil_rly YC3,U=3, and V=2 bits) may be used when a~LGp~iate for the video signals being ~,o.~-e~. Also, when other transmission system formats are used, flash ADC 724 digital threshold comparator 725 r-hould be ad~usted to provide and an ayy~oyLiate m-bit digital conversion rate and the desired mapping of the m-bit digital value of the sampled analog video data to an n-bit pixel d~t_ sign_l compatible with the system.
When the video signals VIDEO at input 721 are digital, - typically a two bit signal, switch 723 is placed in the digital position (not shown), the video signals VIDEO are simply rAsre~ through for further y~o~essing. Thus, in the present embodiment, the two bit digital pixel data representing the input video signal6 VIDEO are available at node 726. The ouLyuL of circuit 720 provides the pixel data at ouL~uL 726 to video data switch 730, along with the vertical sync r~lre- VSYNC at ouLyuL 722v, the horizontal sync p~ HSYNC _t ouLyuL 722h, and the phase locked horizontal sync p~ e~ PHASE LOCKED at ouLyuL 722pl.
It has been realized that simply sampling the video signal6 at the pixel frequency is not likely to be : CA 022~76~9 1999-01-12 W093r23958 PCT/VS93/~ ~1 ~ufficient to digitize the incoming video data at the proper sampling rate and pha~e. Sampling the analog video 6ignals at a freguency different from the pixel rate of the video signal would result in aliasing the frame of pixel data and its 6ync pul6e resulting from the difference between the two frequencie~.
Sampling near the middle of each pixel minimizes any threshold ambiguity. However, simply matching the campling frequency and the pixel rate frequency does not guarantee this will occur. Con~quently, in accordance with the current invention, e~ch video digitizer circuit 720 al~o contains two phase locked loop (PPL) circuits to meet the two criteri~ of freguency matçhing and mid-point sampling (collectively referred to as ~pixel phase lock~).
The video ~ignal at input 721 can be arbitrary.
Therefore, it is impossible to determine the pixel clock frequency from the video data alone. However, the nominal horizontal ccan rate and exact number of pixels n per horizont~l line are known from configuration information supplied to RVC CPU 780. As noted, each display has a defined number of cells per row and a defined number of pixels per line in a cell and the video scan line used to display a line of pixels acro~s the video screen is known, e.g., 63.5 ~s. This information may be used to generate a divisor value for a ~divide by n~ counter 727, which value n is provided by CPU 780 at input 728. The ~divide by n~
counter 728 is thus loaded with a ~GYL mmed divi~or n ~uch that n i~ equal to the number of pixels per horizontal video scan line of the video screen 317 (total pixels, not just visible pixels). The ouL~ from counter 727 may be a pulse, since only the rising edge of the signal is used for phase lock ~ es.
The le~ng edge of the horizont~l sync pulse HSYNC input at 721h is passed through an adjustable delay circuit 728, and then i5 passed to one input of a first phase comparator 731. The other input to phase comparator 731 is the ou~

CA 022~76~9 1999-01-12 WOg3/23 ~ PCT/US93/04361 of divide by n counter 727. Phase comparator 731 proA~es an error ~ignal that ,e~L~-ent6 the phase difference between the delayed pulse HSYNC and the ~uLyuL of counter 727. This error cignal is then used to adjust the frequency of a voltage c6l,L,olled oscillator (VC0) 732 so that ~ampling freguency matching phase lock i~ maintAine~. The error signal is amplified a~G~iately ~uch that VC0 732 ouL~uL
freguency is driven in the direction to minimize the ~ampling frequency phase error.
This phase comparator 731 i8 preferably a 6tate-machine ~variety, ~ince only the rising edges of the incoming ignals -are used for phase comparison. The phase comparator 731 also may incorporate ~ample-and-hold circuitry to minimize VC0 732 ouLyuL frequency ripple, while maint~inin~ an acceptably fast loop response. The Motorola MC145159 Frequency Synthesizer IC in~oL~G~ates a s~mple-and-hold phase detector plus ~G~Lammable counters, and may be used to implement much of the PLL circuitry of video digitizer 720.
The GuL~L of the VC0 732 may not n~c~fisA~ily be a precise 50/S0 duty factor. Therefore, the oscillator is designed to run at twice the pixel frequency, and its o~L~uL
is fed into a ~divide by 2~ flip-flop 733. The ouL~uL from flip-flop 733 is a uniform square wave that is the sample clock rate at ouLyuL 729 and, as noted, is input to divide by n counter 727.
The phase ~G~.L~ol circuitry described above thus assures that the pixel sample clock at ouL~uL 729, which is generated by the RVC 400, matches the incoming video pixel data frequency at ouL~uL 726.
A recon~ pha~e comparator 734 is used to compare the pixel phase with the ~ample clock at ouLyuL 729. Thus, one input is the digital pixel data at node 726, and the other input is the sampling rate ouL~uL from divider 733. The GuLyuL from the pixel phase comparator 734 is used to cG..L~ol delay circuit 728, which is preferably line~rly CA 022~76~9 1999-01-12 W093l23958 PCT/US93/~ ~1 adjustable. The delay may be implemented as a simple variable RC circuit, ~ince only ~1/2 pixel delay must be proA~c~A. When the delay is ad~u6ted by the pixel pha6e comparator 734, the pha6e reference for the pixel frequency i6 changed. Thi6, in turn, proA~ceF a comparable 6hift in the pha6e of the pixel sample clock at vu~L 729.
Preferably, phase comparator 734 also is a state-machine variety to compare only rising edges of the input signals.
However, 6pecial consideration must be made in pha~e comparator 734 to a~G~.L for the arbitrary nature of the incoming video signal data. In this regard, phase : comparator 734 muct in~G~o~ate a sample-and-hold type circuit, because phase error information may be proA~reA by only a dozen or 80 pixels (one character), while the ouL~uL
6ignal mu6t be held stable for an entire video frame. The rerpo~-? of the ph~se cor.L~ol loop must take into acco~-~
the fact that phase error 6ampling may occur only once per video frame (e.g., every 16.7 ms).
Referring to FIG. 29, the vu~ s from the three video digitizer circuits 720 co~nect to a 2-bit video data switch 730. Switch 730 is preferably operated in rotary fashion, ~o that each video input (illustrated as number~ 1, 2, and 3) i6 connected in turn for one video frame of pixel data.
As a result, each video signal input i6 sampled for changes once every three frame6, for a signal transmission latency of about 50 ms. In the case of asynchronous monorhrome inputs, the average latency may be slightly longer, and is A~p~nA~nt upon the frame phase relationships between the non gen-locked video signals.
~he high sampling rate of each video signal input assures that minor screen changes (e.g., blinking characters) are rapidly detected and broadcast quickly ~no-lgh to maintain the desired visual effect on the video screens 317 of the decoAPrs 316.

CA 022~76~9 1999-01-12 WO93~KK8 PCT/US93104361 Switch 730 al80 m_y be ~G"~.olled by CPU 780 to ~onnr~
selectively to one p_rticular video input more or less frequently than the other inputs.
The ou~u~ of ~witch 730 is a stream of pixel data ~GLleDl,~".ling to one current frame of display information.
This pixel d_ta i~ pASf-~ to a ~sy~tem image~ RAM bank 740, ~ ~last frame~ RAM bank 750, and a pixel comparator 760.
The pixel comparator 760 has as input~ the gtream of pixel d_tA from the ou~u~ of video data switch 730 corresponAing to the one ~lLe~l~ frame of display information for a given video ~ignal, the pixel data co~esl,o,~ing to the last frame of displ_y information for the given video signal, which was previously stored in l_st fr_me RAM b_nk 750, _nd the pixel data correspo~ g to the frame of display information that is currently di6played for the given video signal, which was previously stored in ~ystem image RAM bank 740. The pixel comparator 760 uges these three inputs to test for changes in ~cceseive frames.
The system im_ge RAM bAnk 740 is a memory device (or ~n area of memory in a large memory device) containing a cache of pixel data correspon~ng to the images displayed on a ~ystem video screen 317 for each particulAr portion of display information that ie transmitted by the three video !signals inputs. The cached pixel data match the ~net pixel change data~ previously transmitted to the ~ncoA~r 312, i.e., the pixel data for displ_ying the ouL~u~ display information correspQnAi ng to the video signAls VIDEO and _ny subsequent messages providing upd_te data (pixel change data) for updating the o~ - display based on differences between s~cceefiive fr_mes of the 60urce VIDE0. The net pixel change data also is stored in _ picture memory of each remotely located deco~r 316 and is used to generate the ou~ images displayed on _ video screen 317. As expl A i ne~
in more detail below, the pixel data contA~ne~ in RAM 740 for any given frame is only updated when update data messages are broadcast, e.g., to or by an encoder 312, CA 022~76~9 1999-01-12 W093/239~ PCT/US93/~361 thereby to update the pixel data displ_y information held in the ~eD~ ive memories of the remotely located ~ec~A~rs 316 and system image bank 740.
The last frame RAM Bank 750 is a memory device (or an area of memory in a large memory device) contA~ning pixel data for the last frame of display information for each input video signal. The corresponAin~ pixel data for each ~laet~ frame of display information in RAM 750 is completely updated with the ~ lC~ pixel data for that frame (from video data switch 730) as the ~ e.... L~ frame pixel data is compared with the ~o~.espon~i~g prior l_st frame and the - sy~tem image frame.
The sy~tem image and last frame RAM bank~ 740 and 750 are orgAnized with byte-wide (8-bit) data paths. Thi~ allows the data to be read and written with a 120 ns cycle time at the VGA data rate. Buffering and wider memory orgAnization may be used, if n~ce~F-ry, to further increase cycle time.
Once the video data cwitch 730 has celected a new video cignal input chAnnel, the last frame RAM Bank 750 i6 operated in a ~Read-Modify-Write~ mode. This allows the contents of the RAM 750 to be read into pixel comparator 760, while new data from the ou~ of video ~witch 730 is written into RAM 750 later in the same cycle.
The pixel comparator 730 ~ocesFe~ the three input frames of pixel data to determine if a valid pixel change has G~ Led. If the ~..e..t frame pixel data (2-bit value) matches the last frame pixel data, and the~e data are different than the corre~epon~1n~ pixel data retrieved from the Qystem image RAM bank 740, then a change over two successive frames has been detected and it is considered that a valid pixel change has been detected. If, instead, the current pixel data does not m_tch the la~t frame data, then it is considered that either the last frame or the c~..e..~ frame contained an error (noise) or it does not correspond to a valid change. In other word~, the system waits for correspon~ing pixels in two successive frames to CA 022~76~9 1999-01-12 W093/~ PCT/US93/~ ~1 be different than the ~ e~ponA~ng pixel in the ~ystem image frame before A~cl~ring that a valid pixel change has . u.~ - ~1 .
Even ~ho--gh the RAMs 740 and 750 may be delivering byte-S wide data, each set of ~ e~l,o"l~ng 2-bit pixels is preferably compared ~nA~penAently. The two bits represent four possible different intenuity levels. The ~L~u~ from the pixel comparator 760 is a two bit value ~e~ enting the absolute value of the pixel intensity change. The ouL~uL i8 0 ~AC~e~ to pixel data change circuit 770 for ~.ocer~sing and identifying pixel change data that is to be provided to an encoAer 312.
The foregoing comparison algorithm is highly immune to noiQe, since only ~table (but changed) pixel data is flagged as changed. If greater noise immunity i~ desired, additional ~next to last~ frame RAM device~ could be used and the algorithm modified to wait for more than two con~ec~tive frames to have the ~ame changed pixel data different from the system image.
Referring to FIG. 29, pixel data change circuit 770, in the preferred embodiment of the ~ ent invention includes a cell change RAM device 771, a change threshold comparator 772, a CO~LLO1 logic device 773, a cell address change fir~t-in-first-out (FIF0) device 774, and a binary adder 775.
The cell change RAM ?71 i~ a small RAM memory bank (or an area of memory in a large memory device) partitioned into cells 776 ~uch that each cell 776 ~G~ e~G~.d~ to one cell 210 of a video screen image of display information and each cell 210 (FIG. 12) can display a display character, e.g., an Alph~ntlmeriC or ascii character. Each cell 776 contains an 8-bit binary value representing the ~um of the absolute value of the intensity level change of the pixel~ in the cell. This sum is referred to as a ~weighted sum~ because it reflect~ the magnitude of the intensity level difference of the pixels, and not just the number of pixelr~ that have CA 022~76~9 1999-01-12 W093/23958 PCT/US93/~361 changed. In other words, a larger intensity change i8 more ~ignificant than a ~maller intensity change and the magnitude of the change is weighted accordingly.
In the present invention, there are Pno~yh cells 776 in cell change RAM 771 to compare each cell 210 of a video frame of di6play information tran~mitted by the input video ~ignals, and thus RAM 771 need only be 1/16th the size of either system image or last frame RAM bank 740 and 750.
Preferably, RAMs 740, 750 and 771 are discrete memory devices with DMA access so to minimize the time required to read and write data.
: The cell change RAM 771 is operated in Read-Modify-Write mode. The contents of one cell 776 are read and numerically added, at binary adder 775, to the pixel change value that is supplied by the pixel comparator 760 for the ~G~e l,ol.l;ng cell 210 of display information. The weighted sum is then rewritten into the sAme cell 776 in the same cycle. Thus, each cell 776 acts as a cumulative counter that is incremented by the pixel change value from 20 - comparator 760 corresponAing to the absolute value of the intensity change. The dat~ in a given cell 776 of cell ch~nge RAM 720 is reset to zero when the RVC CPU 780 or the en~oA~r 312 broadcasts the pixel change data CG esponA i ng to the given cell 776 to the encoAPr 312 or decoAer 316 respectively.
In a preferred embodiment, the corresponAing cells 210 of the ~.e"L video frame, last video frame and pixel map for a complete page 200 of display information are compared, one cell at a time, and the corresponAing cells 776 are updated with pixel change values. At the end of each complete frame . 200, each cell 776 for that frame 200 contains a binary value that represents the weighted 6um of the absolute values of the number of pixel data changes in the corresponAing cell 210, since the cell 210 was last updated and the cell 776 count was last reset. Each cell 776 thus .

CA 022~76~9 1999-01-12 W093/2~8 -PCT/US93/04361 holds the weighted sum of 128 pixel change v_lues, since each cell 210 contains 128 pixels.
~or example, referring to FIG. 29, no pixel changes have been detected for the cell~ labeled 776a and 776b. How~veL, 7 weighted pixel counts have been detected for the cell labeled 776c in row 1 column 3. The cell labeled 776d in row 2 column 2 holds the value FF, indicating that at least 255 weighted pixel changes have been detected. Since each cell 776 only holds an 8-bit value, the binary adder 776 mu~t ~clamp~ the total at FF, and not allow the weighted count data to rollover. Note, the maximum possible weighted sum for a cell having 128 pixels and four intensity levels (two bits per pixel) is 512.
The change threshold comparator 772 i~ a binary comparator whose threshold is p~Gy~ammed by the CPU 780.
Whenever a cell change value, i.e., the weighted sum ou~u~
from adder 776, re~rhPs that preset count threghold, the ~onL.ol logic device 773 is actuated to load the address of the cell 210 correspon~ing to cell 776 into the cell change address FIFO device 774. The comparator 772 is enabled only during the compari60n of the last pixel 220 of each cell 210 (i.e., the lower right-hand pixel) to minimize multiple detection of cells 210 with ~ubstantial changes.
During periods of minimal change activity, the CPU 780 -may program the count threshold as low a 1, thereby enabling it to detect single-level single-pixel changes in a given cell 210. However, during periods of high system activity, or during rapidly changing video frames, the count threshold may be selectively ~oy~ammed at a level high enough to reduce message traffic to an accept_ble level and still detect significant changes in the video information that will provide an accurate display to the user.
The cell address data that is contained in cell change address FIFO 774 is later used by the converter CPU 780 to identify those cells 210 with cumulative weighted pixel changes at or above the predetermined count threshold. In CA 022~76~9 1999-01-12 W093~239~8 PCT/US93/04361 this regard, the CPU 780 may simply accer- the FIFO 774 to determine the cell 210 addresse~ correrrQnAing to cell~ 776 with above threshold changes, rather than sequentially re~Aing every cell 776 in the cell change RAM 771.
Further, by lo~Ai~g the cell change values into the FI~0 774 along with the cell 210 addresses, the converter CPU 780 can make further priority decisions regarding the order in which cell 210 pixel change data is broaAc~t.
The co..L,ol logic device 773 i~ ~e~ol.sible for coordinating and ~ynchronizing the actions of the RAM banks 740 and 750, pixel comparator 760, threshold comparator 772, and cell ch~nge address FIFO 774. It also inte~ Ls the CPU 780 at the a~G~iate time to initiate retrieval and manipulation of pixel data.
RYC CPU 780 i5 responsible for configuring all the various ~G~ ol register~ within the RVC 400 and for retrieving and manipulating the pixel data in the indicated or identified cells 210 with changes. After a complete video frame has been digitized and compared, the CPU 780 i~
interrupted by the control logic 773. The CPU 780 then performs the following functions: (1) Addresses of cells 210 with corresponAi~g cells 776 having counts at or above the predetermined count threshold are read from the FIFO
774; (2) Pixel data for changed cell~ 210 corresponAing to cells 726 in RAM 775 are transferred to the CPU RAM 781 from the system image and last frame RAM banks 740 and 750 (this dual transfer G~ D because the ~current~ frame pixel dat~
has by this time already been written into the last frame data via DMA bus 785); (3) new pixel change data are written from the last frame RAM bank 750 into the system image RAM
-~ bank 740 (via DMA bus 785); (4) Updated cells 776 in the cell change RAM 771 are zeroed for detection of new change data and non updated cells 776 are left as incremented, if at all, ~uch that pixel changes in subsequent frames may cause such cells to exceed the established count threshold;
and (5) Message(s) containing update data, i.e., the pixel CA 022~76~9 1999-01-12 W093/23 ~ -PCT/US93/04361 change data from the changed cells, are prepared for broAAca~t to the 6y~tem encoAPr 312, for di~tribution to remotely con~Pcted AecoA~rs 316 during s~mpling of the next frame of digplay information.
The CPU 780 should be fast ~no~gh to handle modegt amountg of video ch~nges during the vertical blanking interval (1.4 ms). ~ho~ the CPU 780 beco~e overloaded with ~.~o~ cr~ changes, the CG~ ol logic 773 may be configured to insert blank video frames ~et -~e-. actual frame comparisons, thereby allowing the CPU 780 to access the RAMs 740, 750 and 771 for extenAP~ periods of time. The only side-effect of inserting blank frames is a temporary increa~ed latency for broaAç~ct of pixel change information.
The CPU 780 software ~hol~lA be c~pable of detecting certain special case video changes. For example, a screen going completely blank should be detected and encoAeA
without reguiring direct messaging of each pixel.
The CPU RAM 781 preferably contains exe~Lable code, p~oy ~m data, and pixel data. Pixel data are temporarily moved from the 6ygtem image and lagt frame RAM bankg 740 and 750 via bus 775 to the CPU RAM 781 for generation of pixel change data messages as explained below.
In a preferred embodiment, RVC 400 is configured with an interface 783 that cQ~nsctg to an encoder 312 via two buses:
2S a mono-directional data bus 783d and a bi-directional co-,L~ol bus 783c. Thi6 allows the RVC 400 to format complete messages, and transmit each message to the PncoAPr 312 when instructed to do so by the PncoAPr 312 or host CPU
425. By completely formatting the messages, and notifying the encoA~r 312, the ~oce~sing burden on the ~oAPr CPU
(not shown in FIG. 30) is substantially reduced. This results in increasing the message handling capacity and throughput of the encoA~r 312 and its ability to digtribute more digplay information and update data more quickly to the plur~lity of decoA~rs 316.

CA 022~76~9 1999-01-12 W093/23~ PCT/US93/~ ~1 The ~ncoA~r interface 783 typically receives polling signal6 from an Qn~o~Pr 312 to determine whether an RVC 400 has any penA~g me~ages. At the poll, the RVC 400 empties it~ ou~uL message gueue into an input me~r-~e gueue for the ~ncoA~r 312. The polling is preferably performed at a configurable rate (nominally .25 ~ec).
~urther, the RVC 400 is preferably ~..L~olled by host CPU
425 and includes a hogt computer interface 484. The host CPU 425 provides the RVC 400 with ~G,.L ol information, over a bus 784b. From the pe.~e_Live of the encoA~r 312, me~sAges originating from RVC 400 appear to be updates to a pixel-ba~ed video or graphic tile rather than A character~
cell-based alphamos~ic tile.
The host CPU 425 can, for example, tell the RVC 400 to:
(1) generate a test image, (2) enable/disable s mpling of a 6pecific video signal input, (3) set the input sampling interval (nominally .25 seconds), (4) assign a tile identification code to messages derived from a ~pecified portion of a video image, (5) assemble a ~l.e--L complete image derived from a video input (rather than ~ust the changes), and (6) empty it~ ouL~uL gueue.
There are two types of user reguests for an ouL~u~
display to which the RVC 400 is adapted to le_~G--d, a new page delivered by the information vendor, and an old page reguested by a new viewer.
For a new page, RVC 400 cre~tes and sends a blank screen message and thus resets the 'System Image~ and ~Last Frame~
RAM banks 740 and 750 for that video sign~l to all blanks.
As the new portion of display information is received from the information vendor, it may be 6ent to the enco~Pr 312 for transmission to the ~eco~r 316 and video screen 317.
There is a 3-frame latency delay that is insignificant when - compared to the time required for transmitting the new di6play information from the information vendor site over a telephone line to the client (i.e., subscriber) site.

CA 022~76~9 1999-01-12 W093~39~8 -PCT/US93/04361 --9 o--When a new viewer request~ a portion of di~play information that i~ ~uL~en~ly 6tored in the 6y~tem image RAM
bank 740, the RVC 400 immediately transm$ts the entire portion ~e an update me6sage to the encoAer 312 for transmission to the user requesting the display. This latency is less than one frame time. Thereafter, the new user will receive only updAte data messages for that page in the ~ame manner as the exi~ting user~.
It ~hould be understood that more or le~s than three 10 - video digitizer circuit6 720, with a~G~.iate changes in the corresponAing switch 730 and data processing circuits, could be used in other embodiments for ~Lo~essing more or less than three discrete video signals and composite, non composite or both composite and non composite video signals using the s me residual video converter unit 400.
Advantageously, the ~erent invention provides for a reAl~ceA time to respond to a user'~ request to view a page or record of display information that is already being viewed by another user by caching the ou~u~ di~play at the client's ~ite, and providing the complete ou~u~ di~play as change information to the new user and cont; ntl i ng to provide only relative changes in each of the plurality of cached portions to other existing user~ of that display - information. Further, the invention ~O~C~0~ video information in a manner that is essentially transparent to the user and does not add significantly to the time required to display ~ new page of information and reA~cee the burden on an encoA~r type device at the ~ubscriber~ ~ite. Further, because each converter can be made as a module, ~u~o.~ing additional video signal 8uU~'e_ can easily be obt~;ne~ by ~AAing more modules, without significantly bur~ening the encoA~r device.
Referring to FIGS. 11, 16 and 26 to 28, a decoA~r 316 in accordance with a preferred embodiment of the present invention is shown.

CA 022~76~9 1999-01-12 W093/23958 ~CT/US93/04361 In the ~ ent invention, and with reference to FIG. 26, the AeroAer 316 of the ~.er?nt invention may be resident in~ide a desk interface unit (DIU) 321, which i6 adapted to handle ~eroAPr functionality, including mouse 319' handling, keyboard 319 and mes6age retransmi6sion/flow redirection, and to drive several video screens 317, and which may be posit;on~ for the use of one or more than one user on one or more trading disks 320. Preferably, a single DIU 321 is designed to ~ GlL up to four individual users and thus includes conn~rtors for four keybo~rds 319, four mice 319~, and four color video screens 317. Alternately, the four color monitor ports may be configured to drive a total of twelve monochrome video screens 317.
As Ai ~CllCEe~ above in connection with FIG. 11, the ~ProAPr 316 mAy be installed as a separate printed circuit board assembly inside an enclosure also housing the video screen 317. This provides for a moA~lAr-6y6tem whereby each video screen has a unigue display identification code stored in memory of the ~roAer 316, and thereby enhanr~6 restriction of secure display information to authorized and permitted video screens.
Regardless of its location, each ~eco~r 316 (or DIU 321, and herein collectively referred to as ~AeroAer 316~) is provided to connect each user's input devices 319, 319' and video screens 317 to both the DV bus 314 and the con-~ol bus 318.
Referring to FIGS. 16 and 27, a preferred embodiment of a decoder 316 is shown. The Analog Front-End circuit 610 connects to the DV bus 314 and (1) receives the DV bus signals and maintains proper impe~Anre matching; (2) post--. equalizes the DV bus analog signal; (3) double-end clamps the signal for threshold setting; and (4) converts the guad-- level signal into a 2-bit binary signal.
The Analog Front-End circuit 610 provides a high impe~nr~ input to maintain proper tran6mis6ion line imp~nAnc~ matc~ing; Overvoltage protection ~lso is provided CA 022~76~9 1999-01-12 WOg3/2~ PCT/US93tO4361 to make ~coA~r 316 tolerant of electrical disturh~nc~fi.
The DV bus roAYiAl cable 314 will eYh~hit freguency ~epen~nt loss and group delay (disper~ion) characteristics.
The magnitude of the~e effects ~epenA~ upon the length and type of cable selected. For example, RG-59U will exhibit much higher loss per unit length at high freguencies than will RG-8U foam core cable. The Analog Front-End circuit 610 is thus preferably designed to accept widely varying signal levels and high frequency rolloff, ~pen~g upon its location along the DV bus 314.
Some form of additional adaptive equalization may be used : to ~G~e_~ for loss and dispersion effects. This signal eq~ i2Ation improves the error performance and noise toler~nce of the system.
To CO~V~L ~ the quad-level analog ~ignal received from the DV bus 314 into a 2-bit binary signal, detection thresholds are established by the analog circuitry. By double-end clamping the DV bus packet d heA~r H signal, the Analog Front-End circuit 610 can determine the upper and lower signal levels and the three signal thresholds as described.
The Front-End circuitry 610 then cGI.veLLs the quad-level signal into 2-bit binary input signal for processing by the Packet Reception ASIC 622.
-- The Analog Front-End circuit 610 al60 may be adapted to -receive, recon~tion, and repeat the DV bus messaging data if the received signal level falls below a predetermined threshold. This repeater function could be bypassed by a mech~nical relay ~ho~ signal level~ be adequate, or if the d~co~r 316 i8 inoper_tive. The ~eco~r 316 also may recon~ition and repeat the television ~Gy.am information signals on the DV bus 316 by using information contAineA
within the message heA~r H.
The Packet Reception ASIC 622 receives signals from the Analog Front-End circuit 610, and (1) ~co~ t~he heA~er H
to identify the beginning of each packet d, ~GYLamS the dibit threshold levelc, and determines the interle_ving W093/23~ PCT/US93/~ ~1 depth; (2) creates horizontal and vertical ~ync r~lr~s for use by the Video OuL~u- Circuits 660 and TV D-~cAPr 670; (3) perform~ error detection and co~e_~ion (EDAC) on each data packet d received; (4) compare~ each data packet against the stored ~reception key~ information (a display identification code or an information identification code) to determine if the data reguires further y~ rring by the ~ecoAer cpu 690;
(5) inte.~u~s the ~ecoA~r CPU 690 at the beginni~g of vertical blAn~ing 60 that updates may be made to the Video RAM 662 and Attribute RAM 664 of the Video O~L~uL Circuit 660 (see FIG. 28); and (6) loads accepted data packets d - into the Mess-ge 8uffer 625, and int-~,u~-s the ~eco~Pr CPU
690 for further processing.
The incoming data is first stored in the Interleave RAM
642. The Packet Reception ASIC 622 then reads the data with the axes reversed, and performs the EDAC function. The Packet Re-~c~ion ASIC 622 decodes the he~r bits to determine the interleave factor to reconfigure the interleave structure on a packet-by-packet basis. As with the e~co~r circuit, the ~co~r ASIC may be implemented by any number of circuits and structures, so long as the described functions are performed, which i6 within the abilities of a person of ordinary skill in the art.
The Mecr-ge Buffer 625 is a dual-ported 6tatic RAM device that can be a__Qrse1 by both the Packet Reception ASIC 622 and the ~co~er CPU 690.- Arbitration is provided by the conventional RAM cG-.~rol circuitry within the Message Buffer 625 to prevent simult~neo~6 acce6s. Messages that have been ~ro~P~ and error co~ected are compared against hardwired or previously enabled ~e_e~Lion keys, which also are stored -- in the RAM of Me~6Age Buffer 625. Those messages that match reception keys are then loaded into the RAM of Message - Buffer 625 from the Packet Reception ASIC 622. Once a complete message (that matches a reception key) has been loaded into the Message Buffer 625, the CPU 690 is notified via an interrupt from ASIC 622 over bus 623. The CPU 690 CA 022~76~9 1999-01-12 W093/2~* PCT/US93/~361 may then intc~yL its normal ~G~L~m operation and retrieve the complete message from the Message Buffer 625.
In the preferred embodiment, APcoAPr CPU 690 i8 a 32-Bit PeA~c~A Instruction Set Computer (RISC) CPU having a suitable ~lG~.am for ~GnLLolling AecoAPr 316 operations.
One such device is the LSI Logic Model No. ~R33000 CPU, which i8 capable of exe~Ling an average of 61ightly less than one in~truction per clock cycle, providing an execution ~peed of approximately 20 million instructions per ~Pron~
~ (MIPS). The CPU 690 is preferably capable of both high -- speed ~G~.am exe~u-ion, and high speed data transfers via its two ~ G~ mable direct memory access chAnn~l~ DMA~ and DMAl. It is responsible for (1) collection and processing mess_ges that match .e~c~Lion key ; (2) ~eDl~o~ ng to ~6~sre~ messages by specific actions and modification of di~played information; (3) DMA transfer of video and attribute information to/from the various video display memories; (4) delivery and collection of data to/from the C~ ol Bus Interface 626; and (5) collection of input information from keyboards 319 and mice 319'.
In an alternate embodiment, the functionality previously described may be accompli~hpA by a lower performance 16-bit CISC CPU such that a ~ingle decoA~r 317 may contain a CPU
- 690 which is a type 80188 CPU, thereby reducing the cost of the d~coAPr 317.
The CPU 690 has an associated ROM device 692 and an associated ~ Gy~ ~m and Data RAM device 694. RON 692 preferably contains a ~mall amount of ~lGyLam ROM including, for example, the basic boot code, and rudimentary ~Gy.am functions to allow the dPcoAer to perform self-test and communicate with the host computer 425 via the DV and ol buses 314 and 318. Only basic operating functions are executed from ROM 692, thereby allowing sy6tem flexibility with executable code downloaded via the DV bus 314. Thus, upon power up, the CPU 690 will begin execution of the ~ Gy~am stored in ROM 692 first performing self-test CA 022~76S9 1999-01-12 W093/23~8 PCT/US93/~361 of all circuitry, then acknowledging the status to the host 425 via the cG..LLol bus 318.
RAM 694 contains both executable code (instructions) and ~Gy~m data. In this ~mhodiment, the bulk of the execut_ble code for A COAPr 316 is stored in the RAM 694, thereby providing maximum flexibility for reconfiguring the A?ooAPr oper_tion. Alternately, of course, the entire ~Gy.am code could be contA~n~A in ROM 692. Upon interrupt by the Packet Reception ASIC 622, the CPU 690 operates to DMA tran6fer the incoming message from the Mess-ge Buffer 62s to the ~Gyram _nd Data RAM. The CPU 690 may then resume normal ~roy.~m execution, and perform interpretation of the newly received message at A later time.
In one embodiment, a A~coAer 316 using a 20 MIPS
proc~ssQr 690 can ~e1LaW Zl complete bit-mapped graphics image (2 bits/pixel) in approximately 165 ms. The DV bus 314 can deliver a full screen graphics image in approximately 32 ms. Because the ~nco~r 312 will not repeat a DV bus message until its refresh period (nominally 200 ms) has elapsed, no decoder 316 will lose a message due to overflow even under worst-case conditions.
Referring to FIGS. 27 and 28, the deco~er 316 preferably contains a number of identical video ou~u~ circuits 660.
~our are illustrated in FIG. 28. All video fiignals are preferably delivered to a single 60-pin co~n~ctor 668 and conventional output cables may be attached to connector 668 to drive four or twelve video screens.
Each video ou~u~ circuit 660 (only one is described) accepts bit-mapped pixel data from the CPU 690 and displays the pixels on associated video screens 317 (not shown in ~- FIGS. 27 and 28). Functions such as p3r.ning, scrolling, blink~ng and insertion of live TV are ~ 1 performed by the -- video ou~ circuit 660. A single vic -:. ou~L circuit 660 can provide signals to one VGA color video screens, or to three VGA scan rate monochrome video screens. When configured for three monochrome video ~creens, all three CA 022~76~9 1999-01-12 WOg3~3g~8 PCT/US93/04361 video 6~e~_ may contain different information, with separate tile~ and Cync signals. ~we~, limitations within the illustrated archite~u~e of video o~ circuit 660 ~evell~ use of the pAnn~ng and ~crolling fe,tures when configured for non genlocked mG.,G~ome video ~creen~.
Referring to FIG. 28, the video RAM 662 i~ preferably configured as 512R words of 32 bits each. During the active video time (non-blAnk~g), the video ou~uL circuit 660 reads pixel data from the video RAM 662 on a realtime basis.
-At VGA ~can rates, the video RAM 662 must supply a 32-bit ~word to the video data register 663 every 120ns.
The address bus 661 driving the video RAM 662 is multiplexed between the video ASIC 665 and the CPU 690.
~ During active display time, the video ASIC 665 CG~L~ ols the address bus 661. During vertical blAnking the CPU 690 has ~o.,L.ol over the address bus 661. The Packet Reception ASIC
622 provides an interrupt to the CPU 690 to notify it that vertical blAnk~ing has begun, and commence any required data transfers by the CPU 690.
The CPU 690 utilizes the time during vertical bl~nki ng to load new pixel data into the video RAM 662 via DMA transfer.
When the video output circuit 660 is configured to drive a ~ingle color video screen, all the video data ~O~e_~G~dS to the same video ~creen, and the CPU 690 may ~imply overwrite ~old pixel data with new data. ~cwev.~, when configured to drive three monochrome video s~eer,~, the pixel data contained in a single 32-bit word may relate to three in~Ppen~pnt Ccreens. Therefore, the CPU 690 must first read the pixel data from the video RAM 662, modify the bits relating to the updated tile, and rewrite the pixel data into the video RAM 662.
Assuming a 120ns cycle time on both the video RAM 662 and r-o~am and Data RAM 694, the CPU 690 can transfer approximately 6000 words during a single vertical retrace period (assuming negligible interrupt latency and DMA ~etup time). This is sufficient data to update approximately 188 CA 022~76~9 1999-01-12 W093/23958 PCT/US93/~361 cells on a single color video ~creen. Read and write transfers may be pipelined, ~o that the read and write data may not relate to the same cells on the screen. This r~Al~res the number of cells that can be updated on a single monochrome screen during the retrace period to ay~.oximately 94. Even so, the data transfer bandwidth between the CPU's P.GyL~m and Data RAM 694 and the video RAM 662 far ~xree~C
the ability of CPU 690 to ~eco~P messages and format pixel data.
The video data register 663 receives a 32-bit word from the video RAM 662 approximately every 120ns during active video time. The ou~u~s from regi~ter 663 directly drive the pixel multiplexor 666. Alternatively, multiplexor 666 mAy be an integral part of register 663 with ~election performed by tri-state cG~ ol.
pA~n1ng and scrolling of display information is ~o..~.olled by the video ASIC 665, and may be implemented by a combination of video RAM 662 address manipulation and multiplexor 666. Implied movement may be performed by reading the stored data and rewriting it in the memory in the new addresses (one pixel at a time) or by adjusting the address when reading ~tored data for dicplay.
The video palette DAC 667 i8 st~n~Ardly available and provides RGB ~uL~u~ signals based on a ~G~lammable color lookup table. It contains a 256 element lookup table, where each entry contains an 8-bit value for each of the three color ouL~uL signals. The table is ~.Gy-ammed directly by the CPU 690 using data bus 661 and address bus 661A.
The video palette DAC 667 is capable of Gu~uL~ing the three analog video signals (RGB) at VGA pixel rates (approximately 32 MHz). The values for each ouL~ are determined by indexing the internal RAM array of pallet DDC
667, based upon the address supplied by the video data multiplexor 666. The three ou~u~ can represent RGB
signals for a single VGA color video screen, or can be used independently for three monochrome video screens. The video CA 022~76~9 1999-01-12 WO93~K8 PCT/US93/04361 palette DAC 667 also can also be u~ed to combine sync signals with the video ~ Ls, thereby providing composite video, if desired.
The video switching circuit 680 allows the A~coAPr 316 to feed alternative video input 6ignals through to the video ouL~uLs from the AecoAPr 316. This ~witchin~ i~ under re_ltime ~G~lam ~ol,L,ol. In addition, the Video Switchin~
680 provides a high speed video switch to select either the palette DAC 667 ouLyu~s or oUL~uL8 from an optional TV
~AecoAer 670. Signals provided by the video ASIC 665 cG-,L~ol ~the actu~tion of these video switches, based upon the TV
cignals selected, and the beam position on the video screen 317.
TnAepenAent attributes may be assigned for each cell on the video screen(s). Therefore an Attribute RAM 664 is included for storage of these attribute values. Typic_l attributes include blink, highlight, cursor, ranning, scrolling, etc. As with the video RAM 662, the CPU 690 may update the Attribute RAM 664 during the vertical bl A~i ng interval by enabling its Address A and data D drivers.
The video ASIC 665 reads the Attribute RAM 664 during active video time once for every horizontal cell location (approximately every 240ns). The video ASIC 665 also ~ coordinates the display of video information from the video ~ RAM 662 and Attribute RAM 664. Once the CPU 690 has loaded the neces~-ry data into RAMs 662 and 664, the video ASIC 665 will continllollsly display the stored information without the intervention of the CPU 690.
The video ASIC 665 cG~ ols (1) r~AAing data from the video RAM 662, and clo~king it into the video data register 663; (2) reAAin~ data from the Attribute RAM 664, and clorking it into its internal regi~ters; (3) ~G---,olling the video multiplexor 666 selection of data input to the video DAC 667 (neceCcAry for rAnning); (4) generating ~G~e~
horizontal 6ync, vertical ~ync, and bl An~ ng signals for use by the video palette DAC 667 and video ~witc~ing circuits CA 022~76~9 1999-01-12 _99_ 680; and (5) generating c~..L.ol 6ignal~ for ~ctuation of the video switch~ng circuit 680 to display realtime television .~m information si~nA~ and stored f1nan~;Al market information. Video ASIC 665 ~lso may be implemented by any number of circuits and structure so long as the described functions are performed, which is within the abilities of a per~on of ordinary skill in the art.
Referring to FIG. 27, the cG..L-ol bus interface 626 connects A~coA~ 316 to a multi-point twisted-pair cG.,L~ol bus 318. RS-422 or 485 Arivers (or similar interface devices) are used to ~end and receive differential signals : on cGnLlol bus 318. The col.L~ol bus interface 626 is interrupt-driven using industry-stAnAArd teçhniques.
The keyboard interface 682 provides a 6erial interface to a number of, for example, four, QWERTY type keyboards 319.
Keyboard data is retrieved from the keyboard interface 682 via the data bus 661D once an interrupt has been received.
Keyboard 319 is preferably operated in a block transfer, multid~G~e~, polled mode. Keystrokes are not made 20 - available to the system until a block terminator is entered.
At least two types of keyboards may be used: One with an internal LCD display and one without. The LCD display preferably ~u~po~Ls two lines of data with forty characters each. The keyboard may be similar to a s~A~AAFd IBM
keyboard with twelve function keys across the top.
Keyboards 319 are connected to the host CPU 425 through the control bus 318. The cG--L~ol bus 318 allows a maximum of 63 desk interface unit 321 per cable, or a theoretical maximum of 252 keyboards (assuming 4 keyboards are attached to each DIU 21). System response time is a function of the information content, the number of DIUs 321 per cable, and the transmission rate. A polling period of approximately .2 ~econds can be achieved with 63 DIUs 321 at a 38.4 Kbaud rate. This means that an outst~nA;~g request on ~GI~L~ ol bus 318 will be presented to the system in at most .2 seconds, CA 022~76~9 1999-01-12 W093~9~8 PCT/US93/04361 even if all DIUs 321 on the ~ame cable have outst~nA~ng reguests.
Typed charactere are displayed on a video screen without any ~L~e~Lible delay. The polling cycle of .2 ~econA~ is ~nA~equate for thi~ ~uL~ . Therefore, the APcoAer 316 c~rç~ the key~L~oke~, buffers them and al60 immediately creates a di~play ouL~uL in the 6elected location on the - eelected video screen 317. When the next poll G~ , the A~coA~r 316 will not respond with the buffered character~
~unless a block terminator has been entered prior to the ~poll.
: If there is an individual AecoAer 316 for each digplay monitor 317 rather than a DIU 321, keyboard and mouse commands are Ctill communicated to all APcoAPrs by interconn~ ting them. This configuration i~ functionally identical to a DIU configuration, exce~L that the ability to gen-lock must be externally messaged.
The mouse interface 684 provides a serial interface to, for example, four mice 319'. Mouse d~ta is retrieved from the mouse interface 684 via the data bus 661D, once an interrupt has been received. Simply providing mouse 319' functionality to A trading desk can significantly raise the cost of a trading room. Without the ~~ent invention, the workstation must either be located at the trading desk or ~eYrenfiive cabling and ~ignal amplifiers must be used to transport the mouse signal between the eguipment room ~nd the trading desk. Advantageously, according to the present invention, the encoA~r and ~PcoAPr information distribution system performs most mouse signal ~Loca_sing locally at the desk and when appropriate communicates the result to the eguipment room via the multidL6~ed c6--L~ol bus 318. This design also reA~ces the ~6~e~sing load on the host CPU 425.
Mouse 319' functions are broadly classifiable as (1) cursor motion and/or field h~ghl1~hting, (2) clicking, and (3) dragging. All mouse 319' actions ex~e~L clicking are handled locally at the trader's desk. Mouse clicks are CA 022~76~9 1999-01-12 W093J23~ PCT/VS93/~361 transmitted t~hyl- the polled keyboard 319 to the host CPU
425, which then acts upon them.
Referring to FIG. 12, each video ~creen 317 has page-~pe~A~t default ~ettings for cur60r style and/or field highlighting for each tile 250. The mouse position on the ~creen is communicated instantly through the keyboard 319 to the A~COA~ 316 which then temporarily overwrites the selected cells in the required manner. The cur~or (not shown) is smoothly moved on a pixel-by-pixel b~
Overwritten cells 210 are buffered within the A~coADr 316 and are replaced when the cursor position is moved away.
: When required by the application generating the displayed page, the cursor may be replaced by automatic field highlighting without any required click input.
Clicking, the ~G~ess of pressing and releasing a mouse button, or double clicking, the process of clicking a mouse button twice in rapid s"cce5~ ion, indicates that the application generating the ou~L display must take ~ome computational action in response to a u~er request. Mouse clicks (and/or double clicks) are transmitted through the polled keyboard 319 to the host CPU 425. The host CPU 425 then executes the indicated act~on and the results (e.g., new tiles 250) are then transmitted through the encoA~r 312 to the appropriate video screen 317. The polling rate is sufficiently high that no perceptible delay is generated by this signaling methodology.
Dragging is the ~ OC~BS of holding down a mouse button while moving the mouse. Most mouse applications do not drag the ~contents~ of the window. That is, the window and its contents remains stationary while a new temporary ~ubstitute marquee border is drawn and moved across the video ~creen.
When the button is released the temporary substitute marguee border is removed and the contents of the window are redrawn at the new location on the screen. The contents of the window are not contin~lly redrawn as it is dragged across the page to reduce the amount of CPU processing that would CA 022~76~9 1999-01-12 WOg3/2~8 PCT/US93/04361 be reguired to const_ntly rewrite the video memory.
ApplicAtions that redraw the content~ while being dr_gged significantly loAd the CPU aB ev; A~nc - ~ by the inability of all but the faste~t mach;ne~ to keep up with rapid dragging.
It i~ not practical to have a single ho~t CPU machine ~lG~e~S multiple composite pages of windcw d~agging ~imultAn~ cly unle~s this border substitution methodology is employed.
The ~mallest part of the composite page 200 that may be - drAgged is A tile 250. The tile substitute marquee border may be moved to any location on the display screen; the tile - 250 will be ~n~rpeA~ to the nearest cell 210 boundary when e~ ~wn.
When a mouse button i~ pressed, the ~button down~ command is sent to the host CPU 425; when it is released, the ~button up~ location of the mou6e and celected tile 250 identifier are transmitted through the polled keyboard 319 to the host CPU 425 which _cts upon them by (1) transmitting a Define Tile Location command byte to the ap~ G~ iate A~coAP~ redefining the new location for only that video screen, and (2) refrech;ng the entire tile 250 to all A~coA~rs 316 presently displaying the tile 250. Symbolic ~ignAl;ng i~ preferably employed so that all cubsequent ~ updates to that composite page 200 will be transmitted only once, regardless of how many APcoA~rs 316 have had their -- tile locations moved.
Mouse ~,G-E,ring is effectively decom~z-e~ into two parts (1) local processing of all high bandwidth video redrawing operations _nd (2) remote application ~oca~sing followed by _ one-time redrawing of the video 6creen. Local (i.e., distributed) h~nAling of high bandwidth page drawing associated with mouse motion reAl~ceC the CPU load on the remote application generating the ou~ di~play. This can be significant when the remote _pplication is gener_ting many interactive mouse tile changes.

_ CA 022~76~9 1999-01-12 W093/23 ~ PCT/US93/04361 Provi~ion is also made for the host CPU 425 to .e_~vr,d to e~ and other requests. Each mesuage that goes out to a AecoAer 316 is ~equentially numbered. When a given A~co~Pr 316 Fer~?~; an out-of-seguence message number, it re-requests the missing mes~ages by ren~n~ the number of the last message received to the host CPU 425 via the ~o..L~ol bus 318. To save ~oc.e~sing time, all keyboard 319 requests are concatenated and action i~ only taken after all keyboards 319 on the control bus have been polled at least once. In effect, this means that the host computer 425 will make one polling loop around all decoders 316 on the cGI.L~ol bus before respon~ng to an error request. If the Bit Error Rate is 10-9 at a throughput of 25 Mbit/sec, then on average there will be 0.025 error requests per second or 1 error retransmi~sion request every 40 seconds.
In a preferred embodiment, the encoder 312 is capable of caching at least 500 composite pages 200 (100 x 30 characters per page) including cell attributes, and gtoring at least 4,000 tile names and have a memory base address set to any one of four locations using a Berg clip. The Host CPU 425 input/ou~u~ should include a base address set to any one of four locations using a Berg clip and an interrupt (if required) may be set to any one of four locations using a Berg clip. The data throughput is at about 2.5 MB/sec (20 Mbit/sec) after protocol processing in the Ah-ence of any co-transmitted TV signals, and each co-transmitted full screen TV signal may not degrade the data throughput by more than 0.5 MB/sec (4 Mbits/sec). Codeword lengths for the video screen display ID code may be 21 bits (2,097,152 possibilities) and the tile information ID code may be 24 bits (16,777,216 possibilities). A preferred display screen 317 includes screen attributes of 100 horizontal cells and 30 vertical cells, each cell having 8 horizontal pixels and 16 vertical pixels, with each cell bl~n~i~g at 4 rates of on/off; scrolling for 2 separate alphamosaic tiles of any size, up or down, with soft or hard scrolling, with 4 soft CA 022~76~9 1999-01-12 W093/239~8 PCT/US93/04~1 rates; ran~ng for 4 separate alphamosaic tiles of any ~ize, left or right, with 4 soft p~nnjng rates. Al~o, the character ~ize may be single, double, triple, or guadruple height and width. Up to 8 different simult~nq~ realtime TV sign~ls, having a total dieplay area of not more than four video screens, each displayable at full, 1/4 or 1/8 screen size may be ~y~G~ ~ed. Each TV 6ignal may be shifted horizontally to within 1 cell, but may not be vertically shifted (unless a frame store RAM is used in place of a picture store RAM 662 in the decoADrs).
Numerous alterations of the ~tructure herein disclosed - will suggest themselves to those skilled in the art.
However it i5 to be understood that the embodiments herein disclosed are for purposes of illustr~tion only and not to ~5 be construed as a limitation of the invention.

Claims (24)

CLAIMS:
1. Apparatus for identifying changes in successive frames of video signals for updating an image display of the video signals comprising:
means for separating the video signals into successive frames of display information, each frame having a vertical sync pulse and a plurality of horizontal sync pulses;
means for providing each frame of display information as a plurality of pixels organized in a plurality of cells, each cell having a plurality of pixels;
a first memory containing a first pixel map corresponding to the pixels of the image display; and a comparator for comparing the pixels of one frame of display information to the corresponding pixels of the preceding frame of display information and the first pixel map, one cell at a time, the output of the comparator indicating when the corresponding pixels of the one frame are the same as the pixels in the preceding frame and different from the pixels in the first pixel map; and means for determining whether a cell contains pixel change data based on the indicated changed pixels of the cell.
2. The apparatus of claim 1 further comprising:
a circuit for providing the pixel data for the cells of the one frame determined to have pixel change data for updating the corresponding pixels of the image display; and means for updating the first pixel map with the pixels data so that the first pixel map corresponds to the updated image display.
3. The apparatus of claim 1 further comprising a second memory for storing the pixels of the one frame of display information for use as the pixels of the preceding frame for comparison with the next frame of display information.
4. The apparatus of claim 1 in which the providing means is characterized by a converter for converting analog video signals to digital video signals characterized by a first converter for converting the analog signals to m-bit digital values at a first sampling rate; and a second comparator for comparing the m-bit digital values to a plurality of mapping thresholds and converting the digital values to n-bit pixels, where m is not equal to n.
5. The apparatus of claim 4 wherein the converter further comprises a phase lock circuit for providing a clock signal phase locked to the pixel frequency and for sampling at the midpoint of each pixel, thereby to minimize aliasing of a frame of display information.
6. The apparatus of claim 1 wherein the video signal further comprises a plurality of discrete video signals and the providing means further comprises means for providing each discrete video signal as a plurality of pixels having corresponding horizontal and vertical sync pulse; further comprising:
a switch for selecting one of said plurality of discrete video signals for processing one frame of display information at a time; and a second memory for storing the plurality of pixels of the preceding selected frame of display information for each of the discrete video signals, wherein said first memory further comprises one pixel map for each frame of display information for each discrete video signal that is displayed.
7. The apparatus of claim 2 wherein the determining means determines whether a cell contains pixel change data based on the cumulative weighted sum of the absolute value of the indicated changes of intensity of each pixel in the cell since the corresponding pixels of the image display were last updated, further comprising means for indicating that the cell contains pixel change data when the cumulative weighted sum of each cell exceeds a predetermined count threshold.
8. The apparatus of claim 7 wherein the determining means further comprises:
a first adder for summing the weighted count of the intensity change for each pixel in a given cell of the first frame that is the same as the corresponding pixel in the second frame and different from the corresponding pixel in the first pixel map;
a cell change RAM for maintaining a cumulative count of the weighted count of the changed pixels for each cell of a frame of display information;
a second adder for summing the count of the first adder and the cumulative count of the cell change RAM for the given cell and storing the sum as the cumulative count;
and a second comparator for comparing the second adder sum to a predetermined count threshold and indicating that the given cell contains pixel change data when the second adder sum is above the predetermined count threshold.
9. The apparatus of claim 8 further comprising:
means for transmitting the pixel change data of the given one cell to update the corresponding cell of the image display in response to the second adder sum being above the predetermined count threshold;
means for updating the first pixel map with the pixel change data of the first frame in response to transmitting the pixel change data of the given one cell to update the image display; and means for resetting to zero the cumulative count of the cell change RAM corresponding to the given one cell in response to transmitting the pixel change data of the given one cell to update the image display.
10. The apparatus of claim 9 further comprising means for adjusting the predetermined count threshold in response to the number of transmitted cells of pixel data to update the display so that the threshold is higher during more frequent transmissions and lower during less frequent transmissions.
11. The apparatus of claims 1-10 wherein the pixels in each cell are compared one pixel at a time.
12. A method for identifying changes in successive frames of video signals for updating an image display of the video signals comprising:
(a) separating the video signals into successive frames of display information, each frame having a vertical sync pulse and a plurality of horizontal sync pulses;
(b) providing each frame of display information as a plurality of cells, each cell having a plurality of pixels;
(c) creating and maintaining a first pixel map corresponding to the pixels of the image display;
(d) comparing the pixels of one frame of display information to the corresponding pixels of the preceding frame of display information and the first pixel map one cell at a time;
(e) indicating changes in the display information when the corresponding pixels of the one frame and the preceding frame are the same and are different from the corresponding pixels in the first pixel map; and (f) determining whether a cell contains pixel change data based on the indicated changed pixels of the cell.
13. The method of claim 12 further comprising:
(g) providing an output video signal containing the indicated different pixels of each cell having pixel change data for updating the corresponding pixels of the image display; and (h) updating the first pixel map with the indicated different pixels of each cell having pixel change data so that the first pixel map corresponds to the updated image display.
14. The method of claim 12 further comprising storing the pixels corresponding to the one frame of display information as the preceding frame for use as the preceding frame for comparing the next frame of display information in step (d).
15. The method of claim 12 wherein step (b) further comprises determining when the video signals are analog signals, converting the analog signals to an m-bit digital values at a first sampling rate, and mapping the m-bit digital values to n-bit pixels, where m is different than n.
16. The method of claim 12 wherein the video signals further comprise a plurality of discrete video signals and further comprising separately processing each video signal by steps (a) and (b), selecting one frame of pixel data for one said discrete video signal and applying steps (c), (d), (e) and (f) to the one selected frame, and thereafter selecting another frame of pixel data from among the discrete video signals, one frame of pixel data at a time, and applying steps (c), (d), (e) and (f) to each selected said other frame.
17. The method of claim 16 wherein step (b) further comprises, for each discrete video signal:
determining when the video signals are analog video signals;
converting the analog video signals into digital video signals at a first sampling rate; and phase locking the sampling frequency of the pixel data and phase sampling at the midpoint of pixel, thereby to minimize aliasing of the frame of display information.
18. The method of claims 12-17 wherein step (f) further comprises:
(g) maintaining a cell change counter for each cell of a frame of display information, and, for each cell, (i) comparing the pixels of one cell of one frame of display information to the corresponding pixels in the preceding frame and the first pixel map;
(ii) identifying the weighted number of changed pixels in said one cell;
(iii) summing the weighted number of changed pixels in said one cell with the contents of the cell change counter corresponding to said one cell and storing the weighted sum in said cell change counter;
(iv) comparing the weighted sum to a predetermined count threshold; and (v) determining that the one cell contains pixel change data corresponding to update information in response to the weighted sum exceeding the predetermined count threshold.
19. The method of claim 18 wherein step (g) further comprises:
updating the first pixel map with each cell of the one frame determined to contain pixel change data; and transmitting the pixel data for each cell determined to contain pixel change data of the one frame to update the image display.
20. The method of claim 19 wherein step (g) further comprises adjusting the predetermined count threshold in response to the number of transmitted cells of pixel data so that the count threshold is higher during more frequent transmissions and lower during less frequent transmissions.
21. The method of claim 18 further comprising:
creating a record identifying each cell indicated to contain pixel change data, and, following processing of the cells of a frame;
transmitting the pixels for each cell of the one frame identified in the created record to update the display image;
storing the pixels of each identified cell of the one frame in each corresponding pixel locations in the first pixel map;
storing the pixels corresponding to the one frame of display information as the pixels for the preceding frame of display information; and clearing the contents of the cell change counter for each identified cell.
22. The method of claims 12-17 wherein steps (e) and (f) further comprise:
determining the weighted number of pixels of each cell that have changed relative to the corresponding pixels of the first pixel map;
determining that a cell has pixel change data when the determined number of changed pixels exceeds a predetermined count threshold; and updating the first pixel map for each cell having pixel change data and transmitting the pixels of each cell having pixel change data to update the image display.
23. The method of claims 12-17 wherein step (f) further comprises determining whether a cell contains pixel change data based on the sum of the magnitude of the intensity change of each pixel in the cell.
24. The method of claims 12-23 wherein the pixels in each cell are compared one pixel at a time.
CA 2257659 1992-05-08 1993-05-07 Restricted information distribution system apparatus and methods Expired - Fee Related CA2257659C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US07/880,582 US5321750A (en) 1989-02-07 1992-05-08 Restricted information distribution system apparatus and methods
US880,582 1992-05-08
CA002113078A CA2113078C (en) 1992-05-08 1993-05-07 Restricted information distribution system apparatus and methods

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Cited By (9)

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Publication number Priority date Publication date Assignee Title
US7716349B1 (en) 1992-12-09 2010-05-11 Discovery Communications, Inc. Electronic book library/bookstore system
US7835989B1 (en) 1992-12-09 2010-11-16 Discovery Communications, Inc. Electronic book alternative delivery systems
US7849393B1 (en) 1992-12-09 2010-12-07 Discovery Communications, Inc. Electronic book connection to world watch live
US7861166B1 (en) 1993-12-02 2010-12-28 Discovery Patent Holding, Llc Resizing document pages to fit available hardware screens
US7865405B2 (en) 1992-12-09 2011-01-04 Discovery Patent Holdings, Llc Electronic book having electronic commerce features
US7865567B1 (en) 1993-12-02 2011-01-04 Discovery Patent Holdings, Llc Virtual on-demand electronic book
US8073695B1 (en) 1992-12-09 2011-12-06 Adrea, LLC Electronic book with voice emulation features
US8095949B1 (en) 1993-12-02 2012-01-10 Adrea, LLC Electronic book with restricted access features
US9053640B1 (en) 1993-12-02 2015-06-09 Adrea, LLC Interactive electronic book

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109171701B (en) * 2018-07-05 2023-02-03 北京谷山丰生物医学技术有限公司 Method and device for improving frequency response of electrocardio acquisition system

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7716349B1 (en) 1992-12-09 2010-05-11 Discovery Communications, Inc. Electronic book library/bookstore system
US7835989B1 (en) 1992-12-09 2010-11-16 Discovery Communications, Inc. Electronic book alternative delivery systems
US7849393B1 (en) 1992-12-09 2010-12-07 Discovery Communications, Inc. Electronic book connection to world watch live
US7865405B2 (en) 1992-12-09 2011-01-04 Discovery Patent Holdings, Llc Electronic book having electronic commerce features
US8073695B1 (en) 1992-12-09 2011-12-06 Adrea, LLC Electronic book with voice emulation features
US7861166B1 (en) 1993-12-02 2010-12-28 Discovery Patent Holding, Llc Resizing document pages to fit available hardware screens
US7865567B1 (en) 1993-12-02 2011-01-04 Discovery Patent Holdings, Llc Virtual on-demand electronic book
US8095949B1 (en) 1993-12-02 2012-01-10 Adrea, LLC Electronic book with restricted access features
US9053640B1 (en) 1993-12-02 2015-06-09 Adrea, LLC Interactive electronic book
US8548813B2 (en) 1999-06-25 2013-10-01 Adrea, LLC Electronic book with voice emulation features
US9099097B2 (en) 1999-06-25 2015-08-04 Adrea, LLC Electronic book with voice emulation features

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CA2257658A1 (en) 1993-11-25
CA2257658C (en) 2000-09-12
CA2257657A1 (en) 1993-11-25
CA2257659A1 (en) 1993-11-25

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