CA2161921C - State machine architecture for concurrent processing of multiplexed data streams - Google Patents
State machine architecture for concurrent processing of multiplexed data streamsInfo
- Publication number
- CA2161921C CA2161921C CA002161921A CA2161921A CA2161921C CA 2161921 C CA2161921 C CA 2161921C CA 002161921 A CA002161921 A CA 002161921A CA 2161921 A CA2161921 A CA 2161921A CA 2161921 C CA2161921 C CA 2161921C
- Authority
- CA
- Canada
- Prior art keywords
- state vector
- data word
- output
- clock cycle
- during
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000013598 vector Substances 0.000 claims abstract 27
- 238000000034 method Methods 0.000 claims abstract 9
- 230000003111 delayed effect Effects 0.000 claims 4
- 230000000977 initiatory effect Effects 0.000 claims 2
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Complex Calculations (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
A plurality of data streams time-division multi-plexed into a single stream are concurrently processed.
State vectors characteristic of each data stream are stored in unique read-write memory locations having known ad-dresses. During an initial clock cycle the next sequential data word is received from the single data stream and an input state vector characteristic of the data stream in which the received data originated is retrieved from the memory. The data word and the input state vector are passed to state machine logic which, during one or more intermediate clock cycles, processes the data word and the input state vector to produce an output data word and an output state vector. During a final clock cycle the output data word is transferred to an outgoing data stream and the output state vector is stored in the memory location from which the input state vector was retrieved. The process repeats sequentially, with the next group of three clock cycles commencing immediately after the initial clock cycle of the immediately preceding group of three clock cycles.
State vectors characteristic of each data stream are stored in unique read-write memory locations having known ad-dresses. During an initial clock cycle the next sequential data word is received from the single data stream and an input state vector characteristic of the data stream in which the received data originated is retrieved from the memory. The data word and the input state vector are passed to state machine logic which, during one or more intermediate clock cycles, processes the data word and the input state vector to produce an output data word and an output state vector. During a final clock cycle the output data word is transferred to an outgoing data stream and the output state vector is stored in the memory location from which the input state vector was retrieved. The process repeats sequentially, with the next group of three clock cycles commencing immediately after the initial clock cycle of the immediately preceding group of three clock cycles.
Claims (10)
1. Apparatus for concurrently processing a plurality of time-division multiplexed data streams, each of said data streams containing a plurality of data words and having a characteristic state vector, said apparatus comprising:
a. read-write memory means having a plurality of addressable memory locations for storing said state vectors;
b. a pipeline for:
i. during an initial clock cycle:
(1) receiving an input data word from one of said data streams;
(2) receiving, from a predefined memory location address in said memory means, an input state vector characterizing said one data stream;
(3) receiving said predefined memory location address of said input state vector;
ii. during one or more intermediate clock cycles, processing said input data word and said input state vector to yield an output data word and an output state vector;
iii. during a final clock cycle:
(1) transferring said output data word to an outgoing data stream;
(2) transferring said output state vector to said predefined memory location address in said memory means; and, c. control means coupled to said memory means and to said pipeline for synchronizing operation there-of.
a. read-write memory means having a plurality of addressable memory locations for storing said state vectors;
b. a pipeline for:
i. during an initial clock cycle:
(1) receiving an input data word from one of said data streams;
(2) receiving, from a predefined memory location address in said memory means, an input state vector characterizing said one data stream;
(3) receiving said predefined memory location address of said input state vector;
ii. during one or more intermediate clock cycles, processing said input data word and said input state vector to yield an output data word and an output state vector;
iii. during a final clock cycle:
(1) transferring said output data word to an outgoing data stream;
(2) transferring said output state vector to said predefined memory location address in said memory means; and, c. control means coupled to said memory means and to said pipeline for synchronizing operation there-of.
2. Apparatus as defined in Claim 1, wherein said pipeline further comprises first delay means, second delay means and state machine logic means, wherein:
a. said first delay means is for:
i. delayed storage and output to said state machine logic means of said input data word and said input state vector;
ii. delayed storage and output to said second delay means of said predefined memory location address;
b. said state machine logic means performs said processing during said one or more intermediate clock cycles;
c. said second delay means is for:
i. delayed storage and output to said memory means of said output state vector and said predefined memory location address; and, ii. delayed storage and output of said output data word.
a. said first delay means is for:
i. delayed storage and output to said state machine logic means of said input data word and said input state vector;
ii. delayed storage and output to said second delay means of said predefined memory location address;
b. said state machine logic means performs said processing during said one or more intermediate clock cycles;
c. said second delay means is for:
i. delayed storage and output to said memory means of said output state vector and said predefined memory location address; and, ii. delayed storage and output of said output data word.
3. Apparatus as defined in Claim 1, wherein:
a. said control means further comprises a clock having a selected clock cycle; and, b. said pipeline has a delay characteristic equal to one of said clock cycles.
a. said control means further comprises a clock having a selected clock cycle; and, b. said pipeline has a delay characteristic equal to one of said clock cycles.
4. Apparatus as defined in Claim 1, wherein:
a. said control means further comprises a clock having a selected clock cycle; and, b. said pipeline has a delay characteristic equal to a selected multiple of said clock cycles.
a. said control means further comprises a clock having a selected clock cycle; and, b. said pipeline has a delay characteristic equal to a selected multiple of said clock cycles.
5. Apparatus as defined in Claim 1, wherein said memory means is a random access memory.
6. A method of concurrently processing a plurality of data streams time-division multiplexed into a single stream, said method comprising the steps of:
a. for each one of said data streams, storing a state vector characteristic of said one stream in a read-write memory location having a prede-fined address;
b. during an initial clock cycle:
i. receiving a next sequential data word from said single stream, said data word originat-ing in one of said plurality of data streams;
ii. retrieving from one of said memory loca-tions an input state vector characteristic of said originating one of said plurality of data streams;
c. after said initial clock cycle, delivering said data word and said input state vector to a state machine logic means and then, during one or more intermediate clock cycles following said initial clock cycle, processing said data word and said input state vector in said state machine logic means to produce an output data word and an output state vector;
d. during a final clock cycle following said one or more intermediate clock cycles:
i. transferring said output data word to an outgoing data stream;
ii. storing said output state vector in said memory location from which said input state vector was retrieved; and, e. sequentially repeating said steps b, c and d.
a. for each one of said data streams, storing a state vector characteristic of said one stream in a read-write memory location having a prede-fined address;
b. during an initial clock cycle:
i. receiving a next sequential data word from said single stream, said data word originat-ing in one of said plurality of data streams;
ii. retrieving from one of said memory loca-tions an input state vector characteristic of said originating one of said plurality of data streams;
c. after said initial clock cycle, delivering said data word and said input state vector to a state machine logic means and then, during one or more intermediate clock cycles following said initial clock cycle, processing said data word and said input state vector in said state machine logic means to produce an output data word and an output state vector;
d. during a final clock cycle following said one or more intermediate clock cycles:
i. transferring said output data word to an outgoing data stream;
ii. storing said output state vector in said memory location from which said input state vector was retrieved; and, e. sequentially repeating said steps b, c and d.
7. A method as defined in Claim 6, further comprising performing said processing of said data word and said input state vector during one and only one of said intermediate clock cycles.
8. A method as defined in Claim 6, further comprising performing said processing of said data word and said input state vector during a selected plurality of said intermediate clock cycles.
9. A method as defined in Claim 6, further comprising, during said processing of said data word and said input state vector, preserving said address of said memory location from which said input state vector was retrieved.
10. A method as defined in Claim 6, wherein said initial, intermediate and final clock cycles are repeated in endless, grouped succession such that a final clock cycle in a first such group occurs simultaneously with an intermediate clock cycle in a second such group immediately following said first group and simulta-neously with an initial clock cycle in a third such group immediately following said second group, said method further comprising:
a. immediately after said initial clock cycle of said first group, initiating repetition of said steps 6(b) through 6(e) with respect to said second group; and, b. immediately after said initial clock cycle of said second group, initiating repetition of said steps 6(b) through 6(e) with respect to said third group.
a. immediately after said initial clock cycle of said first group, initiating repetition of said steps 6(b) through 6(e) with respect to said second group; and, b. immediately after said initial clock cycle of said second group, initiating repetition of said steps 6(b) through 6(e) with respect to said third group.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002161921A CA2161921C (en) | 1995-11-01 | 1995-11-01 | State machine architecture for concurrent processing of multiplexed data streams |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002161921A CA2161921C (en) | 1995-11-01 | 1995-11-01 | State machine architecture for concurrent processing of multiplexed data streams |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2161921A1 CA2161921A1 (en) | 1997-05-02 |
| CA2161921C true CA2161921C (en) | 1999-12-28 |
Family
ID=4156894
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002161921A Expired - Fee Related CA2161921C (en) | 1995-11-01 | 1995-11-01 | State machine architecture for concurrent processing of multiplexed data streams |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2161921C (en) |
-
1995
- 1995-11-01 CA CA002161921A patent/CA2161921C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CA2161921A1 (en) | 1997-05-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |
Effective date: 20131101 |