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Surface mount solder assembly of leadless integrated circuit packages to substrates

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Publication number
CA2127948C
CA2127948C CA 2127948 CA2127948A CA2127948C CA 2127948 C CA2127948 C CA 2127948C CA 2127948 CA2127948 CA 2127948 CA 2127948 A CA2127948 A CA 2127948A CA 2127948 C CA2127948 C CA 2127948C
Authority
CA
Grant status
Grant
Patent type
Prior art keywords
solder
paste
bumps
stencil
process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CA 2127948
Other languages
French (fr)
Other versions
CA2127948A1 (en )
Inventor
Yinon Degani
Thomas Dixon Dudderar
William Lonzo Woods, Jr.
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1216Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by screen printing or stencil printing
    • H05K3/1225Screens or stencils ; Holders therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions ; Methods of application thereof
    • H05K3/3478Applying solder paste, particles or preforms; Transferring prefabricated solder patterns
    • H05K3/3484Paste or slurry or powder
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
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    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01013Aluminum [Al]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0103Zinc [Zn]
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    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01051Antimony [Sb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01052Tellurium [Te]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01076Osmium [Os]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
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    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0364Conductor shape
    • H05K2201/0379Stacked conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954Other details of electrical connections
    • H05K2201/10992Using different connection materials, e.g. different solders, for the same connection
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/043Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0502Patterning and lithography
    • H05K2203/0545Pattern for applying drops or paste; Applying a pattern made of drops or paste
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product
    • Y02P70/60Greenhouse gas [GHG] capture, heat recovery or other energy efficient measures relating to production or assembly of electric or electronic components or products, e.g. motor control
    • Y02P70/613Greenhouse gas [GHG] capture, heat recovery or other energy efficient measures relating to production or assembly of electric or electronic components or products, e.g. motor control involving the assembly of several electronic elements

Abstract

Described are a process for soldering at least one component having solder bumps to a substrate and a process for forming solder bumps on metal pads of an element, such as an IC package or substrate or both. The bumps are formed by stencil printing solder paste deposits on the metal pads, heating the solder paste deposits to reflow temperature of the solder in the solder paste deposits, and allowing the molten solder in each deposit to coalesce and during subsequent cooling solidify forming the bumps on the metal pads. The bumps are formed by conducting the stencil printing through apertures in an ultra-thick stencil, the apertures having trapezoidal crossection in the plane normal to the broad surfaces of the stencil with the top opening being smaller than the bottom opening and with the walls of the aperture sloping at an angle within a range of from 1 to 45 degrees from the vertical, the solder paste having a low tackiness and high metal loading, and the solder paste deposits covering an area which is equal to or exceeds an area of the metal pad in any ratio between 1.5:1 and 5:1. Bumps formed in this manner lead to the formation of reliable solder joints.

Description

CA 02127948 1998-0~-27 U.S. Patent 4,878,611 issued on Nov. 7, 1989 to Francis LoVasco et al., describes a process for controlling solder joint geometry when surface mounting leadless IC packages on a substrate. The solder joint assembly technique is used to 5 apply controlled volumes of solder to pads of both the package and the substrate.
The solder volume deposits may assume various forms including truncated spherical bumps, solder preforms and solder paste deposits. The two units are positioned adjacent each other with the bumps and solder preforms or paste deposits mechanically maintained in registration with each other. The assembly is reflowed 10 and the final separation between package and substrate at which the resultant solder joint solidifies is mechanically controlled in order to control the geometry of the resultant solidified joint.
However, mechanically controlled separation is not always practical or advantageous. Therefore, one of the problems arising in the solder assembly of the 15 IC packages on the board, namely, the provision of a sufficient amount of solder needed to establish a reliable solder joint while at the same time avoiding shorts between adjacent solder joints, still remains.
Summary of the Invention This invention embodies a process for soldering at least one component 20 having solder bumps to a substrate and a process for forming solder bumps on metal pads of an element, such as an IC package or substrate or both. The bumps are formed by stencil printing solder paste deposits on the metal pads, heating the solder paste deposits to reflow temperature of the solder in the solder paste deposits, and allowing the molten solder in each deposit to consolidate into a single mass and25 during subsequent cooling solidify forming the bumps on the metal pads. The bumps are formed by conducting the stencil printing through apertures in an ultra-thick stencil, the apertures having trapezoidal cross section in the plane normal to the broad surfaces of the stencil with the top opening being smaller than thebottom opening and with the walls of the apertures sloping at an angle within a 30 range of from 1 to 45 degrees from the vertical, the solder paste having a low tackiness and high metal loading, and the solder paste deposits covering an areawhich is equal to or exceeds an area of the metal pad in a ratio ranging from 1.5:1 to 5:1. Bumps formed in this manner lead to the formation of reliable solder joints.

' .._ - 2a--In accordance with one aspect of the present invention there is provided a process of soldering at least one component to a substrate, said process comprising forming a plurality of solder bumps on pads of said at least one component, placing S the component with solder bumps adjacent pads on the substrate, heating the bumps to a temperature sufficient to reflow said bumps, and allowing the bumps to resolidify joining the component to the substrate, said bumps are formed by stencil printing solder paste deposits on said pads of the component, heating the solder paste deposits to the reflow temperature of the solder in the solder paste, and allowing the 10 solder to solidify forming the bumps on the pads of the component, wherein said stencil printing is conducted through apertures in an ultra-thick stencil, the apertures have trapezoidal cross section in the plane normal to the broad surfaces of the stencil, with the top opening of the aperture being smaller than the bottom opening and with the walls of the aperture sloping at an angle within a range of from 1 to 45 15 degrees from the vertical, said solder paste has a low tackiness and high metal loading characteristics, and said solder paste deposit covers an area which is equal to or exceeds an area of the metal pad in a ratio of from 1.5:1 to 5:1.
In accordance with another aspect of the present invention there is provided a process of forming solder bumps on metal pads of an element, which comprises 20 stencil printing solder paste deposits on the pads of the element, applying heat to melt the solder, and allowing the molten solder to solidify forming truncated spherical solder bumps of said pads, wherein said stencil printing is conducted through apertures in an ultra thick stencil, said apertures have trapezoidal cross section in the plane normal to the broad surfaces of the stencil, with the top opening 25 of the aperture being smaller than the bottom opening and with the walls of the aperture sloping at an angle within a range of from 1 to 45 degrees from the vertical, said solder paste has a low tackiness and high metal loading characteristics, and said solder paste deposit covers an area which is equal to or exceeds an area of the metal padinaratiooffrom 1.5:1 toS:I.
30 Brief Desel ;I,tion of the Dl ~. in~
FIG. I is an exploded view of a solder bumped IC package positioned over terminal pads on a substrate prior to the solder assembly operation;

A

~ CA 02127948 1998-0~-27 -FIG. 2 is a crossectional view of a solder bumped IC package positioned on a substrate, shown prior to reflow soldering;
FM. 3 is a crossectional view of the package and substrate joined together by reflow solder joints;
S FM. 4 is a crossectional view of a solder bumped IC package positioned on a solder bumped substrate, shown prior to reflow soldering;
FM. 5 is a crossectional view of a solder bumped IC package positioned on a substrate with solder paste deposits, shown prior to reflow soldering;
FM. 6 is crossectional view of an IC package or a substrate with a 10 stencil plate and solder paste deposits positioned over pads on the IC package or a substrate; and FIG. 7 is a view of a flipside of an IC package with a 10 x 10 grid array of contact pads.
Detailed Description FM. 1 is a view of an IC package, 10, shown spaced above a substrate, such as a printed board, 11, upon which the IC package is to be mounted. The bottom or flipside of the IC package includes a plurality of solder bumps, 12, positioned on contact pads, 13 (FIG. 2). Solder bumps 12 and contact pads 13 aredisposed in positions directly opposite terminal pads, 14, provided on board 11. In 20 this illustration, the contact pads, and thus the bumps, are arranged on the periphery of the IC package. However, the contact pads may also be arranged in the form of a grid array of contacts on the package and on the board as suggested in phantom lines in FIG. 1. Also, in practice some of the contact pads may not be provided with solder bumps, thus avoiding an electrically conductive connection between such 25 contact pads and corresponding terminal pads on the board.
FM. 2 is a crossection view of an IC package 10 positioned atop board 11 so that solder bumps 12 on the IC package engage abuttingly corresponding terrninal pads 14 on the board. A typical solder bump 12 has a shape resembling a trllncated sphere. The bumps are formed by depositing a controlled volume of solder 30 paste onto contact pads 13, heating to melt the solder material in the paste deposit, and permitting the solder to solidify during subsequent cooling. In the process, the solder assumes the shape of the truncated sphere. Prior to placing IC package 10 atop board 11, the board or at least terminal pads 14, are provided with a thin layer of flux. Preferably, this flux has a tacky or sticky characteristic which is useful in 35 retaining alignment between the package and the board. In the process of assembling, the IC package and the board are aligned each with another. Lateral ' CA 02127948 1998-0~-27 alignment of bumps 13 and of the terminal pads 14 is accomplished during the preassembly of the IC package and the board. Upon being heated sufficiently to melt the solder, the package floats upon the molten solder which, when subsequently permitted to solidify, forms a solid joint, 16, shown in FIG. 3.
In FIG. 4 is shown an assembly with solder bumps 12 and 17 formed on both the IC package and on the board, respectively. In FIG. 5 is shown an assembly with solder bumps formed on the IC package and solder paste deposits, 18, formedover terminal pads on the board. Upon heating, the bumps on the package and on the board or the bumps on the package and solder paste deposits on the board, 10 respectively, are caused to melt and resolidify forming solder joints similar to joints 16 shown in FIG. 3. Of course, these joints will be higher than joints 16.
The process of forming the solder bumps involves stencil-printing solder paste deposits on pads of the IC package or the board or both, and reflowing to form the solder bumps. The paste includes a solder alloy powder and a flux 15 vehicle mixed together, a process based on standard surface mount technology (SMT). A conventional view of such a printed paste based process would be that it could not provide the solder bump volumes required to assure the interconnectionjoint heights needed to minimi7P the effects of thçrm~lly driven fatigue in the assembled package in subsequent use.
In general, all solder pastes are combinations of a flux and a solder alloy powder. The combination of the flux and solder powder controls the printing, slump, t~r1~iness and activity of the solder paste as described in Solder Paste Technology by C. C. Johnson and J. Kevra TAB Books Inc. 1989 pp. 41-43. A flux suitable for a solder paste applications must be a vehicle that can both hold a large volume of the 25 solder alloy powder (normal metal loadings are on the order of 50% to 60% powder, by volume, the rest being flux) and provide for stencil printability. It must also remove metal oxides from both the powder and the wettable metal surfaces of the pads to be soldered during the reflow process so as to assure solder wetting andminimi7e the formation of stray, detached balls of solder during the reflow process 30 (so-called reflow solder balls).
Conventional SMT solder pastes provide high stickyness in order to hold components to the circuit board throughout the SMT assembly process and until reflow is completed. Unfortunately, this adhesive property limits the use of very thick stencils because it promotes an uncontrollable retention of the paste in the 35 necessarily deeper stencil apertures intended to provide a greater volume of solder paste needed to establish reliable solder joints. Consequently, the volume of CA 02127948 1998-0~-27 conventional SMT paste that can be deposited through a stencil aperture of any given area is severely restricted, and cannot be easily increased by simply using a thicker stencil.
The present process, however, achieves exceptional joint volumes and reliable interconnection heights by means of a unique combination of a speciallyoptimized solder paste, ultra-thick stencils having apertures with trapezoidal cross section configuration (see FIG. 6), and by grossly ov~l~r;nlillg the pad areas. This process can readily be carried out on conventional SMT equipment.
The specially optimized solder paste is required to provide reproducible printing through very thick stencils, slump very little when heated to reflow, and assure that each solder paste deposit consolidates into a single solder ball upon reflow leaving no more than one percent by volume of solder balls behind. Also the residue that is left after reflow should preferably have high surface insulation15 resistance and allow probe testing so that the process can be completed and the solder bumped package can be tested without cleaning. The solder paste, specially optimized for use with extra-thick stencils and hereinafter referred to as a YD solder paste, includes a YD flux and a solder alloy powder or powders, whose composition and processing are described herein below. The YD flux (and, consequently, the YD
20 paste) is formulated to have a low stickiness so as to be readily printable through the very thick stencils needed to deposit large paste volumes. The YD flux is a low-residue formulation which is qualified for use without the need for subsequent cleaning, if reflowed in an inert atmosphere. This avoids the need for a post-bumping cleaning of the IC package which must experience refluxing anyway 25 when it is eventually soldered to the board.
As described in U.S. Patent No. 5,211,764 issued on May 18, 1993 to Yinon Degani, a flux vehicle for solder paste includes the following basic constituents: a solvent, an oxide removing component and a rheological additive to improve printability. A flux vehicle suitable for the stencil printing according to the 30 invention comprises 1 to 10 weight percent (wt. %) of an organic acid, 1 to 5 wt. %
of a rheological additive comprising a polymer having a molecular weight greaterthan 50,000, 60 to 98 wt. % of solvent system, and 0 to 25 wt. % of a further additives whose residue m~int~in~ high surface insulation. To provide for the low tackiness that helps with the printing through a thick stencil, the prior flux described 35 in U.S. Patent No. 5,211,764 is used with concentration of the rheological additive toward the lower end of the range, e.g., by using from 1 to 3 weight percent of the rheological additive instead of 4 to 5 weight ' CA 02127948 1998-0~-27 ~_ - 6 -percent. This generates a low stickyness paste and allows high metal loading which results in low slump.
An example of YD flux composition is as follows:

Ch.omic~l Weight% Range Weight% Preferred 5 Sebacic acid 1-3 2.5 propyl 4-hydroxybenzoate 20-30 25 ethyl cellulose 1-3 1.5 dimerized rosin 1-5 3 pentaerythritol tetrabenzoate 1-5 3 10 castor oil 1-5 3 tripropyiene glycol remainder remainder Another example of a YD flux composition is as follows:

Chemical Weight% Range Weight% Preferred 4-hydroxybenzoic acid 1-8 6.0 propyl 4-hydroxybenzoate 20-30 25.0 ethyl cellulose 1-3 1.5 hydrogenized rosin gum 0-25 14.0 ropylene glycol remainder remainder A stencil, 19, (FIG. 6) for use in the inventive bumping process is a few 20 times as thick as conventional SMT stencils. While conventional stencils may run from 3 to 10 mils in thickness, the stencils for this process may run up to 30 mils in thickness For the specific embodiment, described in Example 3 below, the stencil is 21 mils thick. This is roughly three times the thickness of a conventional SMT
stencil. Furthermore, the stencil has apertures, 20, trapezoidal in crossection in a 25 plane normal to broad surfaces of the stencil wherein the top or paste entry opening is somewhat smaller than the bottom opening. The walls of the apertures are in the form of a truncated cone, a truncated pyramid or some other configuration with walls sloping within a range of from 1 to 45, preferably 5-10 degrees from the vertical.
This aperture configuration, in combination with the low stickiness of the YD solder 30 flux in the paste, greatly facilitates release of the special paste from the stencil after printing.

CA 02127948 1998-0~-27 f, f~
'_ The stencil is designed with apertures in which a ratio of a diameter, "D"
(or one side of a square) at the bottom of the aperture to the height "h" (or the thickness of the stencil) is >1.5:1, preferably 22.5:1. Also the ratio of the diameter D
to the distance "p" between the centers of two adjoining pads being approximately 5 D:p = 2:3, with a limit of D:p <3:4. The stencil with paste deposits, 21, within a~ es 20 of the stencil is shown in FIG. 6 of the drawings.
In order to achieve large solder bump volumes, the process requires overprinting the pads with solder paste in a ratio of 1.5-5, preferably 3-4. This means that the cross sectional areas of the base openings in the stencil are made so 10 large that each solder paste deposit covers from 1.5 to 5 times the area of contact pad 13 (or terminal pad 14) over which they are printed. During reflow with such extreme overprinting, many conventional SMT solder pastes would generally leave significant residues of unconsolid~te-l solder in the form of numerous unwanted,isolated balls which would have to be removed lest they become a reliability 15 problem by causing electrical shorts, etc, should they eventually come loose on their own and start to move about. This would necessitate a cleaning step prior to assembly. More of a problem, however, would be the variability of consolidation during solder reflow which can result in shorts and uncontrolled deviations in the volumes, and hence the heights, of the solder bumps themselves. For example, when 20 two solder paste deposits cluster together and during reflow form a single large deposit bridging two pads or when a portion of one deposit joins partially an adjacent deposit resulting after reflow in two bumps of a differing si~ or even when one pad is without solder and a second pad with a double volume of solder on it.However, such variability does not occur with the specially optimized YD solder 25 paste. All but an insignificant trace of each overprinted solder paste deposit is consolidated into a single, large volume bump wholly affixed to the contact pad.This assures consistent bump to bump uniformity and reliable performance without cle~ning.
Finally, one should consider the choice of an appropriate solder alloy.
30 The composition of the solder alloy is, in general, not critical to the bumping process and includes, for example common solder alloys such as Sn/Pb (63/37, 60t40 and 5/95 wt.%), Sn/Ag (96.5/3.5 wt.%), Sn/Sb (95/5 wt.%), Sn/Zn (94/6 wt.%), Sn/Bi (42/48 wt.%) and Sn/Pb/Bi (43/43/14 wt.%). Often, the placement and wave solder assembly of other components to the board is accomplished prior to affixing the 35 bumped IC packages; therefore it may be necessary to carry out the process ofattaching the bumped IC packages to the board with the board being upside down CA 02127948 1998-0~-27 "_ Consequently, use of a solder alloy that reflows at a temperature at or above the melting point of a solder alloy conventionally used to wave solder the through-hole components in place might cause such components to come loose and fall from the board. An example of such a conventional alloy is a Sn/Pb eutectic or near eutectic 5 alloy with a melting point at or above 183 degrees. Consequently, a solder alloy with a lower melting point must be used in the bumping paste. A Sn/Pb/Bi (43/43/14) powder, known to be unaffected by small variations in Pb content, andwith a melting point below 183 degrees C would be most suitable for the YD solder paste. This alloy, commercially available in powder form, has respectable fatigue 10 characteristics, especially when compared to the Sn/Bi alloy (although it cannot match those of most commonly used Sn/Pb alloys).
The following examples are illustrative of the inventive flux and solder paste composition and the inventive process.

Exarnple 1 To prepare 1.5 kg of the YD flux approximately 90gram (g) 4-hydroxybenzoic acid, 210g hydrogenated rosins, 22.5g ethyl cellulose, and 375g propyl 4-hydroxybenzoate are mixed with 802g tripropylene glycol in a 2 liter glass beaker on a hot plate equipped with a magnetic stirrer. The temperature of the n~ ure is allowed to rise to 120-130 degrees C and remain at that temperature for 25 minutes with continuous stirring. The flux is then cooled to room temperature.

Example 2 To prepare 5.0 kg of paste with flux of Example 1 and with Sn/Pb/Bi 43/43/14 solder, combine 375g of the flux with 4625g Sn/Pb/Bi 43/43/14 solder powder, -325+500 mesh, by placing the flux in a stainless steel mixing bowl of a KitchenAid mixer, and then, while mixing at about 40 RPM, slowly adding the solder powder. The flux and the powder are mixed for about 1 minute to obtain an homogeneous paste. After scraping any leftover of flux or powder into the bulk of the paste, the paste is mixed again for additional 30 seconds. The resulting paste is divided into convenient small quantities, e.g., 125 ml, and stored in plastic jars.

. CA 02127948 1998-0~-27 '_ _ 9 _ Example 3 The YD solder paste of Example 2 is then used to fabricate solder bumps on a 10 unit array of IC circuits on a wafer. A flipside of one such unit is shown in FIG. 7, disclosing a 10 x 10 grid array of contact pads 13 and an associated conductor scheme. Contact pads are exposed while conductors are-insulated so that no electrical contact is formed by solder contacting the conductors.
The pads in the array are 32-35 mils in diameter and are arranged on a 100 mil pitch, which means that the center of any pad is at a distance of 100 mils from the center of any other adjacent pad. The paste of Example 2 was printed through a stencil 21 mils thick and having apertures with 60 mil diameter top opening and 64 mil diameter bottom opening, the latter being adjacent to the contact pad on the device. Upon reflow, the solder paste deposits provided bump height nearly as great as the contact pad diameters.
The above-described stencil printed solder paste bumping technology 15 was developed as a SMT compatible batch process for the high throughput, relatively large volume application. As designed, it consistently provides bump heights nearly as great as the pad diametérs, a performance that here-to-for always necessitated the use of preforms and the associated problems of placement, fluxing, stabilization, etc. The inventive bumping technology can also be applied to fine20 pitch designs for use on products where multilayer mother boards relax the routing demands. In such designs, an example of which would be a 60 mil pitch with 30 mil diameter pads, the opportunity to overprint is rather restricted, especially when compared to the 100 mil pitch and 35 mil pad configuration described above.
However, experiments on such fine pitch arrays using equivalently proportioned 25 stencils with smaller openings and the same flux system have also demonstrated 30 mil bump heights. This was accomplished, despite the necessarily smaller overpinting, by increasing the effective "metal loading" (or proportion of the solder powder) in the paste. However, if this were done by simply adding more powder tothe existing paste/flux combination, the resulting loss of printability would render 30 the effort hopeless before any significant improvement in bump volume could be achieved. In order to avoid this problem, the metal loading was increased through the use of solder alloy powders of signific~ntly different si~ (or mesh) such that one powder effectively fits into the interstices of the other, thereby directly increasing the metal content of the YD solder paste and assuring more solder alloy in a given 35 volume of deposited paste without significantly compromising printability. Of ' CA 02127948 1998-OS-27 ~",,,~,~,, course, this "multi-powder" approach requires the proper pairing of powder sizes (or "cuts") but it is very effective for improving printed solder bump volumes. Such a "multi-powder" YD paste could as readily be prepared for the bumping the 100 milpitch grid arrays if even greater bump volumes were desired. Another approach for 5 providing sufficient bump volume without excessive overprinting in the fine pitch designs, includes a "double-printing" of the solder paste. This involves a first bump formation with only moderate overprinting, e.g., 1.5-3 times the pad area, reflow formation of the bumps and printing the solder paste over the bumps followed by another reflow of the solder in the bumps and in the solder paste deposits on the 10 bumps. In this manner a solder joint may be produced which has a height in excess of that obtainable with the single printing, and without danger of shorts between the fine-pitched pads.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the 15 specific details, representative devices, and illustrated examples shown and described. Accordingly, various modifications may be made without departing fromthe spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

Claims (20)

1. A process of soldering at least one component to a substrate, said process comprising forming a plurality of solder bumps on pads of said at least one component, placing the component with solder bumps adjacent pads on the substrate, heating the bumps to a temperature sufficient to reflow said bumps, and allowing the bumps to resolidify joining the component to the substrate, said bumps are formed by stencil printing solder paste deposits on said pads of the component, heating the solder paste deposits to the reflow temperature of the solder in the solder paste, and allowing the solder to solidify forming the bumps on the pads of the component, wherein said stencil printing is conducted through apertures in an ultra-thick stencil, the apertures have trapezoidal cross section in the plane normal to the broad surfaces of the stencil, with the top opening of the aperture being smaller than the bottom opening and with the walls of the aperture sloping at an angle within a range of from 1 to 45 degrees from the vertical, said solder paste has a low tackiness and high metal loading characteristics, and said solder paste deposit covers an area which is equal to or exceeds an area of the metal pad in a ratio of from 1.5:1 to 5:1.
2. The process of claim 1, in which the stencil is 12-30 mils thick.
3. The process of claim 1, in which the area covered by the solder paste deposit is at least 3.5 times as large as the area of the pad.
4. The process of claim 1, in which the walls of the apertures slope 5-10 degrees from the broad surface of the stencil.
5. The process of claim 1, in which an effective diameter of the base of the trapezoid is greater than the height of the trapezoid in a ratio greater than 1.5.
6. The process of claim 1, in which the solder paste is selected from the group consisting of Sn/Pb, Sn/Ag, Sn/Sb, Sn/Zn, Sn/Bi and Sn/Pb/Bi solder alloys and their combinations.
7. The process of claim 1, in which said solder powder is a Sn/Pb/Bi (43/43/14) solder powder.
8. The process of claim 1, in which said solder paste comprises solder particles and a flux vehicle, said flux vehicle comprises 1 to 10 wt. % of an organic acid, 1 to 5 wt. % of rheological additive comprising a polymer having molecularweight greater than 50,000, 60 to 98 wt. % of solvent system, and 0 to 25 wt. % of further additives whose residue maintains high surface insulation.
9. The process of claim 8, in which said flux vehicle comprises 1-8 weight percent 4-hydroxybenzoic acid, 1-3 wt. % ethyl cellulose, 20-30 wt. %
propyl-4-hydroxybenzoate, 0-25 wt. % of hydrogenized rosin gum, and the remainder being tripropylene glycol.
10. The process of claim 9, in which said flux vehicle comprises 6.0 wt.
% 4-hydroxybenzoic acid, 1.5 wt. % ethyl cellulose, 25 wt. %
propyl-4-hydroxybenzoate, 14 wt. % of hydrogenized rosin gum, and 53.5 tripropylene glycol.
11. A process of forming solder bumps on metal pads of an element, which comprises stencil printing solder paste deposits on the pads of the element, applying heat to melt the solder, and allowing the molten solder to solidify forming truncated spherical solder bumps of said pads, wherein said stencil printing is conducted through apertures in an ultra thick stencil, said apertures have trapezoidal cross section in the plane normal to the broad surfaces of the stencil, with the top opening of the aperture being smaller than the bottom opening and with the walls of the aperture sloping at an angle within a range of from 1 to 45 degrees from the vertical, said solder paste has a low tackiness and high metal loading characteristics, and said solder paste deposit covers an area which is equal to or exceeds an area of the metal pad in a ratio of from 1.5:1 to 5:1.
12. The process of claim 11, in which the stencil is 12-30 mils thick.
13. The process of claim 11, in which the area covered by the solder paste deposit is at least 3.5 times as large as the area of the pad.
14. The process of claim 11, in which the walls of the apertures slope 5 to 10 degrees from the broad surface of the stencil.
15. The process of claim 11, in which an effective diameter of the base of the trapezoid is greater than the height of the trapezoid in a ratio greater than 1.5.
16. The process of claim 11, in which the solder paste is selected from the group consisting of Sn/Pb, Sn/Ag, Sn/Sb, Sn/Zn, Sn/Bi and Sn/Pb/Bi solder alloys and their combinations.
17. The process of claim 11, in which said solder powder is a Sn/Pb/Bi (43/43/14) solder powder.
18. The process of claim 11, in which said solder paste comprises solder particles and a flux vehicle, said flux vehicle comprises l to 10 wt. % of an organic acid, 1 to 5 wt. % of rheological additive comprising a polymer having molecularweight greater than 50,000, 60 to 98 wt. % of solvent system, and 0 to 25 wt. % of further additives whose residue maintains high surface insulation.
19. The process of claim 18, in which said vehicle comprises 1-8 wt. %
4-hydroxybenzoic acid, 1-3 wt. % ethyl cellulose, 20-30 wt. %
propyl-4-hydroxybenzoate, 0-25 wt. % of hydrogenized rosin gum, and the remainder being tripropylene glycol.
20. The process of claim 19, in which said vehicle comprises 6 weight percent 4-hydroxybenzoic acid, 1.5 wt. % ethyl cellulose, 25 wt. %
propyl-4-hydroxybenzoate, 14 wt. % of hydrogenized rosin gum, and 53.5 wt. %
tripropylene glycol.
CA 2127948 1993-09-28 1994-07-12 Surface mount solder assembly of leadless integrated circuit packages to substrates Expired - Lifetime CA2127948C (en)

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CA2127948A1 (en) 1995-03-29 application
JPH07154061A (en) 1995-06-16 application
DE69401108T2 (en) 1997-04-03 grant
US5346118A (en) 1994-09-13 grant
DE69401108D1 (en) 1997-01-23 grant
KR950009989A (en) 1995-04-26 application
EP0645948A1 (en) 1995-03-29 application
EP0645948B1 (en) 1996-12-11 grant
JP2682807B2 (en) 1997-11-26 grant

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