WO 91/~2395 2~ PCT~US90/04~96 , CURRENT ADAPTTVE: FAUI.T INDICATOR
This application is a continuation-in-part application of Serial No. 390,541, filed ~ugus~ 7, 1989, ~y Thomas Yeh, ~or Current Adaptive Fault Indicator.
BACKGROIJND OF ~HE INVENTIoN
This invention relates to ~aulted current indicators, and particularly to fault indicators which can accommodate themselves to wide variations of load conditions in a distribution networX.
A conventional fault indicator indicates the passage of power cable current -above a predetermined magnitude, i.e. trip current. ~he fault indicator's trip current is selected to be greater than the expected current at the installation site. Proper selection of the trip current magnitude is very important for the proper application o fault indicators. Typically, the trip current is selected about two to three times ~o the maximum load current and less than one half the available fault currentO This method of application provides a good trade off between maximum sensitivity while minimizing the un-wanted trips by periodic overloads.
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Applying conventional fault indicators in a large distribution network often requires many fault indicators with different trip currents ~o coordinate with loading variations within the network. In addition to the cost o~ stocking many di~ferent fault indicators, the chance o~ miss-application also increases.
OBJECTS AND SIJM~Y OF THE INVENTION
An object of the invention is to overcome these difficulties.
Another object of the invention is to furnish reliable fault indicators capable of adapting the trip to the load current of a power line to accommodate the wide variations in load condition of a distribution networX.
According to a feature of the invention, such objects are achieved with fault indicating method and means by tripping the fault indicator in response to increases in currents in the cable over time. An example of such an increase is 50 amperes within 3 line cycles of a 60 Hz current, or 50 milliseconds.
According to another feature of the invention, the trip signal is held and the trip operation is disabled long enough for a fuse or .
WO 91/0239~ PClr/USg~ll/04396 circuit breaker to open in response to a fault, and then the trip operation enabled only if the curren~
then falls to zero.
These and other features o~ the invention are pointed out in the claims. Other objects and advantages o~ the invention will become evident ~rom the following detailed description of preferred embodiments of the inventio~ when read in light of the following drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram illustrating an em~odiment of the invention.
Fig. 2 is a detailed showing o~ a portion of the circuit in Fig. 1.
Fig. 3 is a circuit diagram illustrating details of part of the circuitry in Yig. 1.
Fig. 4 are graphs showing the operation of t~e circuit in Fig. 1.
Fig. 5 is a block diagram of another embodiment of the invention.
Fig. 6 is a diagram illustrating details of part of the circuitry in Fig. 4.
- . ~ -- , - - . ~ -- ' :' ' ' ': ,, WO 91/0~395 P~T/US90/0~13g6 Figs. 7 and 8 are time current diagrams illustrating conditions for tripping the fault indicator.
Fig. 9 is a block diagram illustrating another embodiment of the invention.
Fig. 10 is a schematic diagram illustrating yet another embodiment of the invention.
DETAILED DESCRIPTION OF PREFER~ED EMBODIMENTS
Fig. 1 illustrates an embodiment of the invention. In Fig. 1 a power source PS energizes a load LO through a circuit breaker CB and a power cable PC. Fault indicators FIl, FI2, FI3, and FI4 inductively coupled to the cable PC by inductive sensors IS1, IS2, IS3, and I54 at spaced locations along the cable PC, sense whether a fault exists at positions between any fault indicators. The sensors IS1 to IS5 may ~e regarded as part of the fault indioators FI1 to FI5. A ~ault between fault indicator FI4 and fault indicator FI5 trips fault indicators FI1 to F~4 while leaving fault indicator FI5 reset. This identifies the location of the fault as being between fauIt indicator FI4 and fault indicator FI5. The langth of the cable PC appe~rs 2~ shortened for the purposes of illustration.
WO91/02395 2 ~ ~ L~ ~ PCT/US90/04396 Although only fault indicator FI3 is shown in de~ail, the other fault indicators are substantially identical thereto.
The inductive sensors ISl to IS5 produce respective alternating voltages corresponding in amplitude to the amplitude o~ the alternating currents they sense in the cable PC. In the ~ault indicator FI3, a capacitor C1 tunes the inductive sensor IS3 to the ~re~uency in the cable PC. A
bridge circuit BR recti~ies the alternating current in the sensor IS3 to form an output voltage whose peak is proportional to the current ~lowing in the power cable 16. Three isolating diodes Dl, D2, and D3 furnish the bridge BR output voltage to a reset circuit RC, a trip circuit ~C, and a power circuit PO that furnishes a voltage Vcc to the elements of the fault indicator. The diodes D1, D2, and D3 isolate the various circuits ~rom each other.
In the power circuit PO a capacitor C2 captures the peak of the rectified output of th~
bridge BR and s~oothes ripple. A 12 volt zener diode Zl regulates the voltage across the capacitor C2 so the latter carries a 12 volt potential that serves as the voltage source Vcc for elements of the circuit in the ~ault indicator FI3.
In the fault indicator FI3, the reset circuit ~C responds to a minimum voltage Vmin at the bridge BR to produce a reset signal. The minimum voltage Vmin corresponds to a minimum current Imin -- . ' ', ' . ~ ' ,, ' :
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in the cable Pc. The reset signal energizes a resetwinding WR in a fault display actuator DA which then drives a target (or display) TA to a visibly distinguishable reset position.
The trip circuit TC operates in response to the voltage at the bridge BR appeari~g at the diode D2 and representing the operating current in the cable PC. The trip circuit TC produces a trip signal when the rate o~ change o~ current in the cable PC causes the rate of change of the voltage at the bridge BR to exceed a predetermined va}ue, and the cable current thereafter drops to 0 within a pred~termined time in response to the current opening the circuit breaker cs. The trip signal energizes a winding W2 in the display actuator DA.
. The ~atter turns the target to a trip position.
An inrush restraint circuit I~ between the reset circuit RC and the winding Wl, and between the trip circuit TC and the wind ing W2 pr~vents the display actuator DA from either resetting or tripping for a preset time a~ter. the onset of the minimum voltage Vmin at the reset circuit RC. A
sample preset time is 1/4 to 1/2 cycles. However for particular purposes other delays are useful.
According to one embodiment o~ the invention the preset time is 60 seconds.
Reset circuits such as circuit RC are well Xnown in the art. They include a threshold circuit to establish the reset signal or signals when the W~t/~23g5 PCT/U~90/04396 r `` 2~ ? ~
''l'~ '.`. ' ~oltage at the bridge BR exceeds the minimum value vmin.
In the inrush reskraint circuit IR a start up delay circui~ DE responds to the snset o~ the s voltage Vcc and a re~et signal and produces an inhibiting low at one input o~ AND gates ADl and AD~
for the preset time such as one-quarter or one half cycles or perhaps 60 seconds. Therea~ter~ the start up delay circuit DE enables the gates ADl and AD2 until thrae events occur; khe current in cable PC
drops to 0 to expunge Vcc, the current resumes to re-prod~ce Vcc, and a reset signal appears at the start up delay circuit DE. The start up delay cirouit D~ is in the form ~f a timer responsive to a reset signal followed by a latch that resets in the absence of Vcc and is enabled by the presence of Vcc .
The other input of the gate AD2 is connected to the output of the reset circuit RC, and the o~her input of the AND gate AD2 is connected to the trip circuit TC. The AND gate ADl serves to energiz~ the reset winding Wl when the input signal at both inputs are high. The AND gate A~2 serves to energize the trip winding when both inputs are high.
The start up delay circuit DE causes the inhibit signal at the inputs of AND gates ADl and ~D2 to last for a given time, such as one-quarter or one-half cycle,~and then enables the AND gates AD1 and AD2 so they can pass reset or trip signals. In this way the inrush restraint circuit prevents resets or ~., WO~1/02395 PCr/US90/04396 .. ~
trips in response to inrush currents.
In Fig. 1, the trip circuit produces a trip signal in response to the rate of change of current. In the trip circuit TC an integrator INl integrates the rectified voltage at the bridge ~R at a ~irst rate and an integrator IN2 i~tegrates the voltage at a second rate much slower than the firs~
rate. A voltage divider composed o~ resistors R1 and R2 takes a slightly lower proportion o~ the output o~ integrator INl than does a voltage divider composed of resistor R3 and R4 take o* the integrator IN2. Thus the effective output of the integrator IN2 measured at the voltage divider R3,R4 produces a slightly higher absolute voltage than the ef~ective voltage of integrator INl measured at ~oltage divider Rl,R2.
A comparator U1 compares the voltages at divider Rl,R2 with the voltages at divider R3~R4O
When the voltage at capacitor C2 is changing only slowly, the output o~ the c~mparator Ul is low because the both integrators' effective outputs respond similarly to their inputs and the effective output of integrator IN1 is lower than that of integrator IN2. When the voltage at the bridge BR
ri~es rapidly, the lower ef~ective output of ~aster integrator IN1 climbs above the effective output of integrator IN2. The comparator U1 then produces a high. A latch LAl such as a flip-flop latches the high and applies the high to an input of an AND gate AD3. A timer TIl responds to the high and resets '' "' ,` , ~'~
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the latch after a predetermined time such as one minute. The timer TI thus allows the comparator U1 to arm the AND gate AD3 and hence the trip winding WT ~or only the predetermined time, e.g. one minute.
S An inverter IVl produces an inhibit signal at the other input o~ the AND gate AD3 as long as there exists a voltage at the bridge BR. As soon as the voltage at the bridge BR goes to 0 in response to the circuit bre~ker CB opening the cable PC the inverter applies a high to the AND gate AD3. If this occurs within the predetermined time, e.g. one minute that the timer TIl allows the latch LA1 to apply a high to the ~ND gate AD3 the latter goes high. If this high occurs after the inrush restraint period of the start up delay circuit DE, i.e. after the start up delay circuit places highs on ~ND gates AD1 and AD2, the high at AND gate ~D3 caUces energization of winding W2.
Fig. 2 illustrates details of the integrators INl and IN2 and their environments.
Here, a capacitor C2 forms the integrator INl. The time constant of the integrator INl is determined mainly by the capacitor C2 and the effective impedance of the resonant circuit composed of the inductive sensor IS3 and the capacitor Cl which tunes the sensor IS3 to the.frequency of the currPnt in the cable PC.
Ths values are chosen so that the voltage vtrip across the capacitor C2 reaches 95% of the , . ~ - . ... , ~ . : -:. . . .
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voltage of the bridge BR in about 3 line cycles.
According to one embodiment of the invention the capacitor C2. has a value of 4.7 microfarads and the effective impedance a value 3 Kohm although these values are only examples.
A capacitor C3 and a resistor R6 form the second integrator IN2. According to one embodiment of the invention the capacitor C3 has a values such as 1.0 microfarad while the resistor R6 has a value of 15 Kohms. Because the resistor R6 and the capacitor C3 are both connected to the capacitor C2 and the impedance of the tuned circuit Cl,IS3, the time constant o~ the sPcond integrator IN2 includes the effects of the tuned circuit impedance and the capacitor C2. Hence, the time constant of the integrator IN2 is inherently greater than the time constant of integrator INl. The values of the integrator IN2 are chosen to allow the ~oltage across capacitor C3 to reach 95~ of the voltage at the bridge BR 3 cycles later than the time the voltage across capacitor C2 reaches 95% of the voltage across bridge BR.
The very high values of resistors Rl to R4 affect the time constants of the integrators IN1 and IN~ only slightly. However their voltage dividing ratios are such as to apply a smaller proportion of the signal at the output of integrator INl than that of integrator IN2. This assures that the faster input from integrator INl to the non-inverting terminal of the comparator U1 is less than .. . ..
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WO91/0239S PC~/US90/D4396 I I
the slower input from the integrator IN2 to the inverting terminal as long as the currents sensed - are varying slowly enough for both integrators INl and IN2 to follow.
The capaoitor C2 serves two other functions. It serves to reduce the ripple at ~he bridge BR and to store a voltage Vtrip for energizing the trip windin~ WT. Fig. 3 illustrates the manner in which the trip signal energizes the trip winding WT. Here, a ~ield e~ect transistor Ql has a gate which receives the trip signal from the AND gate AD2. A high trip signal causes current flow from alon~ a path from the voltage Vtrip at the capacitor C2 throuyh the trip winding WT, the drain lS and source of field e~fect transistor Q, and groundO
A similar arrangement enerqizes the reset winding at the output of AND gate AD1.
The integrators INl and IN2 and the comparator Ul may be considered as functioning as a di~ferentiator for that responds only to positive di/dt or dv/dt. They may also be regarded as a differentiator followed by a diode that permits only positive *low.
In operation, the inductively coupled sensor IS3 senses the current in the power cable PC
on a continuous basis. The bridge BR rectifies the output of the current sensor IS3 to obtain unidirectional sine pulses with peak values proportional to the current magnitude in the power - . . ........... ~ . . - :
WO91/02395 PCT/~90/04396 l2 Z~
cable PC. The integrator IN2 with its capacitor C3and longer time constant than the integrator IN1 generates the reference for the comparator circult Ul. Tha time constant of the integrating circuit IN2 is such that ~he reference of the comparator represents some time average current o~ the power cable, ~or example, three line cycle~, or 50 ~illiseconds.
The time constant o~ the integrating circuit INl is less than that of IN2. The ef~ective output of the integrator INl is slightly lower than the integrator IN2 as long as the rate of change in the sensed current is slower than the differences between the charging rates of the capacitors in the integrators INl and IN2. This is so because then both integrating circuits IN1, and IN2 Xeep up with the rate of change at the output of the bridge circuit BR. When the current in the power cable PC
exhibits a rate of change that is faster than that of the integrator IN2, the integrator INl reacts faster than the integrator IN2 and a voltage differential occurs at the inputs of the comparator When the current increase in the power cable PC is sufficient to raise the output of integrator INl fast enough to overcome the threshold established by the effective output of the integrator IN2, the result triggers the output of comparator U1. The comparator Ul then sets the latch L~l and initiates the timer circuit TIl and - . . . '-: . :-., ' : - :. . .
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W091~02~9s PCT~US90/0~396 , ~, provides a high at the input of the AND gate ND3.
An inverter IV1 disables the AND circuit AD3 as long as the bridge circuit BR indicates that current continue~ to flow in the cable PC. The timer maintains the high at the output o~ the la~ch L~l for a predetermined period. If the current in the line PC drops to zero during that period, the inverter IV enables the AND gate AD3 to pass a trlp signal to the winding ~2. -Figs. 4, 5, and 6 demonstrate conditions that will not cause a trip operation. Figs. 7 and 8 show conditions for tripping the ~ault indicator.
In Fig. 4, the initial "nominal~ curren~ Il is the relative reference for the fault dete~mination. ~he current increase from Il to I2 is over a relatively long enough period of time (dt) so that its rate of change is insufficient to cause a trip operation.
At the end of the time ~dt), the fault indicator is referenced to I2 for the fault operation.
In Fig. 5, the increase in the magnitude of the current over time is su~ficient to trip the fault indicator. However, in Fig. 5, the current - remains at I2 after the increa~e, thereby indicating that the circuit breaker C8 did not interrupt the current in the power cable PC and thP entire trip condi~ion was not satisfied. Fig. 7 shows the current dropping to zero after reaching I2, thereby indicating the loss of current in the power cable PC, thereby tripping the fault indicator.
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Fig. 6, shows a condition where the fault indicator adapts to the variations in the load current. ~nitially, the power cable PC carries current of the level Il. Similar to Fig. 4, the current is increasiny in response to an increase in load. During the time when the current is changing from Il to T3 over the period dtl, the reference against which the fault is judged is also changing.
The fault indicator is "adapting" to the changing load current. At the end of the time dtl the fault indicator is referenced to I3. The subsequent current increase of I3 to I2 over the time period dt2 is not suf~iciently high relative to I3 to arm the trip circuit.
~ig. 8 shows the condition where an increase is sufficiently fast relative to I3 to arm the trip circuit. The trip operation occurs when the breaker CB interrupts the line current after the arming condition. The loss of current represents this in Fig. 8.
The adaptive fault indicator operates to trip when the increase of current in the power cable PC, as referenced to the steady state "nominal" load current is sufficiently high and is over a short -25 enough period of time to generate the necessary di/dt value to arm the trip circuit. If the line voltage or current signal is not available, the arming of the trip circuit will cause the target TA
to operate to trip. If line current is aYailable, - . . ~ ~ ,. - , . ~ . : :
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then the line current must also be interrupted within a period of time such as one minute to enable the trip circllit to operate to trip. I ~ the l ine current is still present after a given time such as one minute, the latch LAl produces a low and then disables the AND gate AD3 so that the trip circuit is disarmed and ready ~or the next trip condition.
The adaptive fault indicator adapts to the nominal loading current o~ the power line to accommodate the wide variations of load conditions in a distribution network. The ~ault indicator according to the inven~ion does not reac~ to absolute magnitude of current but instead responds to increase in current over period of time (di/dt)o The adaptive fault indicator uses the nominal load currant as a reference to which a relative increase of current such as 50 amperes within a certain amount of timP such as three cycles or 50 milliseconds will cause the indicator to trip.
Fault indicators according to the invention thus significantly reduce stocking of fault indicators having different trip setting and thus reduce the chances for misapplication.
According to an asp~ct of the invention, two events must occur in sequence to cause the indicator to trip, for example a relative increase in current such as 50 amperes within thrçe cycles "arms" the trip circuit. The second event, namel~
the loss of current within a predetermined time, such as one minute. This will trip the indicatorO
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WO91/02395 PCT/~90/04396 ` ~t?~ 16 If after one minute the current in the line still persists, the trip circuit will be "disarmed". The timing is chosen to be longer than the opening time of the circuit breaker CB in the power line PC. If 5 the circuit breaker includes a recloser switch, then the time of timer TIl should be chosen to be longer than the final lockout time. The purpose of the timer TIl is to prevent the fault indicator ~rom responding to current before the line protection device has a chance to operate. This is especially true for a recloser breaker where the line voltage disappears and appears upon open and r~close of the breaker. The timer Tl will then hold the trip circuit until the breaker has a chance to lock-ou~
be~ore deciding to trip. Upon starting of current, or any resumption of current, the reset circuit RC
responds to a current Imin and initiates the start up delay circuit DE in the inrush restraint IR. The time of the delay is preferably short, for example one quarter to one half cycle. However, delay times of 60 seconds are sometimes used for special purposes. The start up delay circuit DE inhibits - the AND gates ADl and AD2 at the initiation or resumption o~ current and prevents the display actuator DA from changing the reset or trip condition of the target TA for the delay time.
Thereafter, the start up delay circuit DE enables the AND gate ADl and ~D2 and allows them to pass highs to the windings ~ and WT.
The capacitor C2 serves three purposes.
First, it converts the full wave sine pulses into - - . : - . :-: .
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W O 91/02395 PC~r/US90/04396 ;., ~, low ripple DC voltage. It also stores the necessary energy to activate the trip winding WT in the display actuator DA. Its third function is to serve as an integrating member in the integrator IN1.
The invention may also be embodied as shown in Fig. 9. Here, a dlfferentiator DI
substitutes ~or the integrator IN1. The different.iator produces signals proportional to the rate of change of the output of the bridge circuit BR. A large rate of change at the output of the bridge circuit BR produces a large output at the differentiator DI. A smaller rate of change produces a comparatively smaller output. A
comparator U1 compares the ~ifferentiating circuit DI output to the nominal current based reference in integrator IN2. The integrator IN2 here has a time constant that depends mainly on the members within it. The threshold of the comparator is such that rate of change in current, say an increase of 50 amperes over three cycles, triggers the comparator output. This output arms ~he trip circuit and initiates the timer circuit TIl.
The circuits IN1 and IN2 may be regarded as energy storage devices with different storage rates.
In that sense the circuit IN2 has the faster storage rate. The integrator circuits IN1 and IN2 may also - be considered delay circuits having information storage functions with different write delay times.
In that sense the circuit IN2 has the longer delay time. As such the information storage aspects of - :- - - . .
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circuits INl may be replaced for example with semiconductor memories.
Another embodiment o~ the invention appears in Fig. 10. Here, the sensor SI3 output, a~ter full wave recti~cation, is peak detected by capacitor C2. ThP DC voltage across capacitor C2 is proportional to the cUrrent magnitude being sensed by the sensor SI3. The charging time constant o~
capacitor C2, composed o~ the equivalent impedance "looking back" into the terminals of the sensor 5I3 coil and the capacitance of capacitor C2, a~lows the DC voltage across capacitor C2 to capture the peak amplitude of the 60 Hz current. The discharge time constant of capacitor C2~ determined by resistance of resistor R6 and capacitance of capacitor C2, is much longer than 60 cycles period to hold the information between 60 Hz period.
The rate-of-increase of the DC voltage across capacitor c2 is derived by the differentiator circuit composed of capacitor capacitor C3 and resistor R7. For this case capacitor C3 is 1 microfarad and resistor R7 is approximately 50K
ohms. The "differentiator" formed by capacitor C3 and resistor R7 has a time constant of approximately three cycles of the 60 Hz signal or 50 milliseconds.
When the sensed ~0 Hz current exhibits an increase that occurs within three 50 Hz cycles, the ~oltage across capacitor C2 also exhibits a corresponding increase. The output of the differentiator, at the cathode of zener diode D14, is proportional to the - .. :-. - - . : ~' - . . . ~ .
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rate-of-increase of the voltage across capacitor C20 When the rate-of-increase is sufficient in rate and magnitude, the output of the differe~tiator will overco~e the zener diode voltage Dl4 and turn ON transistor Ql. The collector of transistor Ql will go l~w and turn on transistor Q2. The collector of transistor Q2 is tied to the SET input o~ the SET/RESET Flip Flop a~d initiates the counter IC U3. The counter IC U3 then counts ~or a predetermined time period. During this period the trip circuit is enabled at pin l of gate U2. If during this time the line current drops to zero as detected by resistor R21, resistor R22, and capacitor C12, pin 3 of gat~ U2 will go high and turn on the trip driver transistor Q6 to turn the display actuator into FAULT registration. ~iodes Dll, Dl2, and Dl3 will discharge all of the internal energy storage capacitor to prevent the circuit from reset and re-initiate the circuit into a predic~able state. If the sensed current did not decay to zero before the counter IC U3 times out, the SET/RESET
Flip Flop is reset and the trip circuit returns to nominal state.
The voltage supply for the trip circuit includes diode D5, resistor ~4, capacitor C4, and diode D7.
In the reset circuit, the reset time delay provided by U4 also serves as the inrush restraint timer. At start up, the sensor-output charges the WO91/02395 PCT/U590/04396 ~' Z~
reset energy storage capacitor capacitor C5. When the magnitude of the sensed current produce sufficient voltage across capacitor C5, transistor Q4 is turned ON by resistor R24 and capacitor C~ and enables the reset timer IC U4. Another SET/RESET
Flip FLop is SET by detecting the presence of line current and disables the adaptive trip circult by turning transistor Q3 on and clamp the SET terminal o~ the trip Flip Flop low. When the reset/inrush restraint time elapses, the timer IC U4 produces a high at pin 5 o~ U4 which cause the RESET Flip Flop to release transistor Q3 and enables the adaptlve trip circuit.
While embodiments of the invention have been described in detail, it will be evident to those skilled in the art that the invention may be embodied otherwise.
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