CA1312920C - Fast settling tone/data processing circuit - Google Patents

Abstract

FAST SETTLING TONE/DATA PROCESSING CIRCUIT
ABSTRACT
In a radio employing continuous tone or digital coded squelch system, fast settling tone processing circuitry is disclosed for a tone processing path which includes an FM detector, low pass filters and a tone limiter. In an exemplary embodiment, a capacitor at the output of the FM detector in the tone/data processing path is charged as rapidly as possible to a new DC level, for example, by an off frequency transmitter. A pulse is generated by, for example, the transceiver microprocessor which initiates the rapid charging of the capacitor as soon as it is detected that data needs to be read from the tone/digital data processing circuitry for decoding.
Such a pulse is generated by the microprocessor whenever channel frequencies are changed and/or the carrier activity sensor becomes active.

Description

FAST SgTTLING TQN~fDAT~ PROGE5SING CI~S~IT

FIELD OF ~ IN~ENTION

This invention generally rela~es ~o a diyitally controlled radio communica~ions device. More par~icularly, the in~ention relates to a method and apparatu~ which allows rapid scanning of multiple channel frequencies in ~earch o~ a pred~termined tone or data pattern by reducing the settling time of the radio receiver'~ ~one/data proce~ing circuitry.

BACgGROUN~ AND SUMNA~Y OF T9E INVENTION

Mobile and/or portable radio transceiving device~ ~ave h~reto~ore incorporated a "channel guard" coding option which permits an operator to selectively call desired parties by transmitting a low frequency tone or digital data patt~rn. Such a .
~channel guard" coding option is al o referred to a~
a continuous tone coded squelch ~y tem (CTCSS) or a continuous digital coded squelch sy3tem (CDCSS).
~hannel guard provides a mea~s of restricting calls to specific radios. Only the desired partie~' r~ceivers are programmed to decode the transmitted tono or d~gital data pattern.
By using the channel guard op~ion, many u~ers can ~hare a repeater ~ygtem, with only the r~ceivers programmed to receive thQ particular transmitted channel guard coded ~one ~ein~ enabled to receive a tran~mitt~d me~age. The tran~mitted tones in a tone channel guard system may, for example, range ~

`
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r-from 67 Hz tQ 210.7 Hz in .1 Hz steps. In a digital channel guard system, there may be over 80 standard digital codes. The requency of transmitted digital channel guard signals is typically significantly lower than in tone channel guard systems.
The tones or digital codes frequency modulate the transmit~ed RF carrier at typically +0.75 kHz deviation. The specification tolerance is 0.5 to 1.0 kH~ deviation. Voice si~nals frequency modulate the carrier at +3.~5 kHz deviation. Therefore, the total channel deviation is 3.75 plu5 0.75 or 4. 5 kH2 deviation which is within the FCC's 5 kHz maximum limit.
Systems incorporating such tone or data cha~nel quard features include tone or data processing circuitry for proces~ing and decodin~ the received tones or digital data to detect the proper tone or data sequence. To process such low frequency tones or digital data to correctly detect predetermined tone or data patterns, it is necessary for the RC
time constant in the tone processing circuitry to be long enough to preserve ~he tone or data signal pattern for reliable decoding of noisy signals. In a digital channel guard system, a digital pattern may consist of a len~thy string of logic "l's" or "O' s" .
In conventional radios incorporating such a ch~nnal guard feature, when a receiver detects a carrier in the channel guard mode, it attempts to decode a channel guard tone pattern. In such prior art radios, if the proper channel guard is not detected, the receiver audio is simply muted.
The time required to decode a channel guard ..
.
' 45-MR-o0567 -~, 3 ~ 3 1 2920 tone pattern was not heretofore considered an important limitation in previous designs o tone/data processing circuits. In this regard, a hundred millisecond or more se~tling delay was not viewed as presenting any significant operating problems.
The present invention, by reducing this settling delay to a minimum, permits scanning multiple channel frequencies to search for the correct channel guard tones or data. In the channel guard operating mode, when a RF carrier is detected, the tone or data processinq circuitry of the present invention, rapidly begins to produce tones and digital data which may be reliably decoded by the transceiver microprocessor. If an "incorrect"
channel guard pattern is detected, the channel scanning process continues immediately. The present invention allows low frequency data to be sensed as fast as possible while scanning different channel frequencies.
In simultaneously implementing both channel scannins and chamlel guard features, the present invention recognizes that a problem inhibiting fast scanning of multiple channel fre~lencies results from the failure of a transmitter to be precisely on frequency with the receiver. In this re~ard, it is noted that the output of a FM detector with no RF
carrier present, consists of noise at an averaqe DC
level. Xf the transmitter is on frequency with the receiver, when an on fre~lency carrier i~ detected, the DC level at the output of the FM datector will not shift. Thus, the DC level at the output of the EM detector remains relatively consta~t when an on ., ~' ~, , _ 4 1312~20 frequency carrier appears.
However, if the receiver and transmitter differ by, for example, .5 kilo~ertz in frequency, the DC
level at the output of the FM detector will shift.
This shift in DC level creates a pulse which is detected by the tGne or data processing circuitry which will be misinterpreted as valid data by the processing circuitry until the RC networks therein charge to the new DC level. Since under such circumstances it may ~ake the RC networks in the tone processing circuitry approximately 100 milliseconds to charge to the new DC level, data detected during this `'settling" time period may be erroneously interpreted as a part of a tone or data channel guard pattern.
If a receiver and transmitter differ by, for example, 2 kilohertz or more, even longer settling times are required before khe tone or data processing circuitry will, in fact, produce valid, reliable channel guard data. Since tone signals or digital data typically frequency modulate an RE
carrier at a minimum of plus or minus .5 kHz deviation, such a deviation creates a significant impediment to implementing the rapid scannin~ of multiple channel frequencies while employing the channel guard feature described above.
In an exemplary embodiment of the pre~ent invention, a capacitor at the output of the FM
detector in the tone/data processing path is charged as rapidly as possible to a new DC level cau~ed, for example, by an off frequency transmitter. In the present invention, a pulse is generated by, for example, the transceiver microprocessor which initiate~ the rapid charging of the capacitor as 800n as it is detected that data need~ to be read from ~h~ tone/d~gital data proce~sing circuitry for decoding. Such a pulse may be initiated by the microprocessor whenever channel frequencies are changed and/or the carrier ac~ivity sensor becomes active.

BRIEF D~CRIPTION OF T~E DR~WINGS
These a~ well as other objects and advantages o thi~ invention will be better appreciated by reading the following detailed description of the presently preferred ~xemplary embodiments taken in conjunction with the accompanying drawings o~ which:

FIGURE 1 is a schematic diagram which shows the tone/data proce~ing circuitry in accordance wlth an exemplary embodiment of the present invention;

FIGURES 2a - 2c respectively show ~he F~
detQctor output with no RF signal, the FM detector output with an on-frequency RF carrier, and the FM
detector output with the RF carri~r 1 kHz off-frequency;

FIGURE 3a shows a simplified version of the proce~ng path including a simplified tone limiter circuit;

EIGURES 3b -3g show the detector and tone limiter output for exemplary on-requency and off-frequency RE carriers;

- ' ' ' ~ .

45~ 00567 6 1 31 2q20 EI~URE 4 i~ an exemplary waveform generated in the circuit of FIGURE 1 af~er capacitor Cl when an off-frequency RF carrier is applied without turning on Ql; and FIGURE 5 i8 an al~ernatiYe embodiment of tone data/proce3~ing circuitry in accordance with the present invention.

DETAILED DESCRIPTION OF TEE DRA~INGS

Figure 1 ~hows a channel guard tone or data procQRsing path in accordance with an axemplary embodiment of the present i~ention fed by the output of a conven~ional FM r~ceiver detector ~. It i~ emphasized ~hat the ~pecific component value~ and bia~ potentials shown in Figure 1 are exemplary only and should not be con~trued as limiting ~he ~cope of the present invention.

The purpo~e o~ the FM detector 2 i8 to recover the freguency modulated audio or da~a information on a RE carrier. The detector 2 converts the freguency variation~ of tha RF carrier to amplitude variation~. The output of a FM detector with no carrier present consi~ts of noise at an average dc le~cl. Assume ~hi8 level is 5.O Vdc a~ shown in Fiqure ~a.

~ ormally, this dc level remain~ relatively constant when an on-frequency carrier appea~. If we a~-~ume that the F~ detector 2 ou~put~ 8wi~g8 0.1 volts per 1.O kHz frequency change, then a~ shown in , -Figure 21a, a RF carrier frequency modulated wil:h a tone at +1.0 kEIz ~leviation produce~ a 0.2 volt peak-to-peak output signal. ~owever, if the received carriar i~3 1 kEIz off frequency, the ave!rage dc level will ~hift 0.1 Vdc. ~s shown in Figure 2c, the dc level is shifted low.

Th~ output of the FM detector 2 is coupled to conventional DC coupled filters and amplifier3 4 via a DC blocking capacitor Cl . It iY noted ~hat the channel guard tone signaling de~cribed above, i8 accomplished with sig~als of a frequency no higher than approximately 210 Hz. The DC coupled filters in block 4 are low pa85 filters, which pa-~s frequen~ie~ below, for example, 220 Hz, but which significantly a~tenuate voice and noi~e signal~
above 220 ~z to in~ure that such signals do not affect the tone limiter operation.

DC coupled filters and amplifiers 4 are in turn coupled to tone limi~er 5 which serve~ to convert, for example, sine wave tone signals into a square wav~ pulse train. The generated squar~ wave pul~e train i9 decoded by the transceiver microprocessor ~0 which recognizes a predetermined tone pattern (or pattern of digital data) and thereafter closes the audio signal path~ in the tran~ceiv~r (not ~hown) to unmute the audio to allow the audio si~nal to be received ~n a predetermined channel.

The DC co~pled filters in block 4 al~o Berve to couple a ~C bias potential via re~i~tor 18 to ~he tone limiter 5. For example, the DC coupled filter~

45~ 00567 -1312q20 and amplifier~ 4, and the tone limiter 5 are provided with a DC bias vol~age from a 5 volt ~ource via re~i~tor 18 which may be a ~0 K resistor.

As will be explained further belsw, the manner in which the bias voltage is applied is cha~ged when field effect transi3tor (~T) Ql is turned on.
However, before de~cribing the operation of FET Q1 and its associated circuitry, the operation o Figure 1 with Ql off and not conducting will fir~t be described.

As noted above, when proces~ing tone ~ignals in tone channel guard applications, the 'one limiter 5 receive~ sine wave signals and generates square wav~
~ignals (which are thereafter processed by the transceiver microproce~sor 20 which decodes the channel guard tones). Before describing the tone limiter 5 shown in Figure 1, the operation of a simplified tone limiter will be fir~ de~cribed in Figure 3a.

The tone limiter in Figure 3a is a high gain comparator 22. Here the comparator's reference voltage is 5 Vdc at the non-inverting (+) input.
The EM detector 2 feeds the inverting (-) input.
~Any variance rom the normal 5 Vdc on the detec~or's output will be amplified greatly. If the detector output ~win~s a few millivolts less than S volt~, the tone limiter output will saturate to a positive voltage.

When an on-frequency carrier i8 fre~uency modulated by a tone at 0.5 kHz deviation as repraRented in Figure 3b, ~he limiter will produce a symmetrical square wave as in Figure 3c. Thi~
square wave signal of the ~one or data is sent to microprocessor 20 where i~ will be reliably decoded.

I~ ~he RE carrier frequency is, for example, 400 Kæ low as in Figure 3d, an unsymmetrical square wave, as shown in Figure 3e, will be produced which cannot be decoded r~liably under noisey conditions.
If the carrier requency error is greater than the O.5 kHz deviation, a~ shown in Figure 3f, no useul output will be produced from the limiter as shown in Eigure 3g.

Turning back to Figure 1, the off-frequency carrier problem descri~ed above i~ obviated by blockin~ the FM detector's dc component with capacitor Cl. The comparator's inverting input will always be at S volts with only the amplitude variations from the detector 2 passing to the limiter.

As noted above, active low pass filters 4 provide a 220 Hz cutoff to remove voice and noise ~ignals beore the limiter 5. Capacitor Cl serve3 to pravant the op amp~ in the active filters 4 rom possible satu~ation wi~h off-frequency ~ignals. The ilter~ 4 always receive a con-~tant 5 volt dc bia3.

When the active filter~ 4 are introduced into the tone processing path, the dc o~fset~ in the op 45~ 00567 _~
13129~0 1~

amps in 4 are amplified causing a slight error in the 5 volt dc bias on the filter'~ output (typically les~ than 100 mV). This offset will cau~e a similar symmetry problem a~ in Fi~ure 3d.

To ~olve thi3 problem, ~he limiter's reference i~ derived from the do voltage on the output of filter~ 4 as ~hown in Figure 1. Resi~tor 8 and capacitor 10 filter all signal information to provide a smooth dc reference to the comparator.
Resister 6 minimize~ the dc offset of the comparator 12. Therefore, the invarting input of comparator 12 receives ~he tone si~nals from the filters 4 and the non-inverting input xeceives a dc reference egual to the inverting input.

Turning to ~he detailed operation of the tone limiter S with tran~istor Ql off, th~ 5 volt bias potential is applied via re~istor 18 to set the DC
level for the tone limiter 5 and to provide the re~uired bia~ voltage for the filters in block 4.

As noted above, with Ql off when no carrier is present, the output of t~e FM d~tector 2 con3ists of noi~e at an average DC level. When the FM detector detect~ a ~ignal from a transmitter which i3 on fr~quency with the receiver~ the average DC level output by the FM detector does not change a~ ~hown in Flgure 2b. The appropriate DC bias voltage i~
then fed to tone limiter 5 which operate~ to generate valid data.

Tone limiter 5, as noted above, receive~ the , ~ .

_ .

11 1 3 1 ~920 output of the DC coupled filters and amplifier~ 4 and lncludes a re~istor 6 which may, for ex~mple, be a 22K resistor and which is co~pled to ~he invexting input of tone limiter comparator 12. Also receiving the output of the ~C coupled ~ilters and amplifier~
4 i~ a re~i~tor 8 (which may, for example, al80 be a 22 K resi3tor) and which is csupled to ~he non-inverting input of the tone limiter comparator 12. Also couple~ to ~he non-i~verting input of comparator 12 is capacitor lO which i~ also connected to ground and which operate~ as described a~ove to provide a mooth DC reference to the comparator 12.

When an on-frequency carrier i~ de~ected by the FM detector 2, the DC level remain3 con~tant. Wlth no shift in thi 8 DC level, the voltage at the inverting and non-inverting input~ of ~one limiter comparator 12, likewi~e remain~ at a predetermined de~ired voltage e.g., 5 volt~.

If, for example, ~he DC level at the output of FM detector lO rises to a predetermined voltage level, then the inverting input of tone limiter comparator 12 will correspondingly rise initially in voltage level to, for example, 6 volt~ before capacitor Cl char~es through resistor 18. The non-inverting input, however, will for a predatermined period of time remain at five volt3 due to the RC time constant of the 22 K re~istor 8 and the capacitance of capacitor lO (which may, for example, be 10 ~). With the inverting input at 6 voltQ and the non-inverting input a~ S volt~, the 12 l 31 2920 output of comparator 12 will go to a negative or low level.

I~, alternatively, the output of the FM
detector 2 falls from ~he above-mentioned average DC
level to a lowex DC level ~due to a shift in carrier frequency), the inver~ing input of compaxator 12 correspondingly drop~ initially to, for example, 4 volts. The positive input remains at 5 volts due to the aforementioned RC time constant. Thus, the output of tone limiter 5 will go initially to a positive voltage indicative of a logic l level.

As noted above, upon raceipt of a predetermined sequence of logic 1's or 0's, ~he microproce~sor 20 detect~ the preRence of a predetermined tone pattern (if tone channel guard is being utilized) or a predetermined string of logic l's or 0'~ (if digital channel guard is being utilized). Upon decQding such a pattern, microprocessor 20 close~ a predetermined audio signal path in the transceiver to unmute the audio to thereby allow the transmitted audio to be heard in the receiver.

If the radio transceiver is being controlled by the microprocessor 20 to operate in a scanning mode, up~n datection of such a correct tone pattern or data stream the scanning operation stop~ and the audio input is received. If the received tone pattern or data pattern doe~ not reflect ~he predetermined sequence of 1's and O's, ~hen the scanning process continues.

.

-13 l 3 1 2~20 If the transmitter is operating off frequency by, for axample, 1 kHz the ~C level output from the FM detector may shift from the desired dc level of 5 volts to, for example, 6 volts. A3 noted above, typical manufacturer specifications permit tone signals or digital data to freguency modulate an RF
carrier at a minimum of plus or minus 0.5 kHz deviation.

Al~hough, as described above, Cl allows the limiter 5 to provide useful data when the RF carrier is o~f-frequency, Cl must charge initially when the carrier appears. During this charging period, the tone limiter 5 is providing either no data or unsymmetrical data. Figure 4 shows the waveform presented to the limiter after capacitor Cl when an off-frequency RF carrier is applied. The RC time constant must be long enough to preserve the data waveforms. Thus, during the time that it take~ to charge capacitor Cl through resistor 18, the to~e limiter 5 will generate invalid data.

In accordance with the present invention, a pulse .is introduced into the receiver tone or data processing path which triggers a ~uicker settling time for the tone limiter 5 so that valid data will be produced as quickly as possible. In this regard, the pulse introduced into the path serves to turn on transistor Ql which results in capacitor Cl being charged to a new DC leveL to reflect the s~ift in A the DC level at the output of FM detector ~.

If the output of FM detector 2 i~ shited to, , 14 1 3 1 2q20 for example, 6 volts due to the txansmitter being off frequency by 1 kHz and the tone limiter S
requires a 5 volt bias voltage, then capacitor Cl needs to be charged as rapidly as pos~ibla in order to control tone limiter 5 to generate valid data as rapidly as pos~ible.

The pulse which triggers the initiation of a quicXer tone limiter "settling" time is shown in Figure 1 as being a 10 millisecond pulse which is input to the gate of FET Ql. The 10 millisecond pulse in the pr~sently preferred embodiment is generated by the transceiver microprocessor 20 upon the detection of 1) a change in the receiver'.~
channel frequency and 2~ the activation of the carrier activity sensor ~i.e., the noise squelch).
The carrier activity sensor circuit becomes activ2 when it detects a drop in the high frequenGy noise output from the FM detector 2 to indicate that a RF
signal is quieting the receiver. Thu~, in one exemplary embodiment, in order to generate the 10 millisecond pulse, the transceiver microprocessor 20 is programmed to implement a logic -AND" function to gen~rate th~ 10 millisecond pulse upon detecting that the receiver's channel freguency is changed while the carrier activity sensor is active.

It i~ empha ized, however, that the 10 milli~econd pulse may be generated in accordance .
with the present invention, whenever the carrior activity sensor becomes active. In this regard, even when the receiver is not operating in a channel scanning mode, but rather i3 attempting to detect a i -- .

1 3 1 2q20 correct channel guard ~equenc~, generation of the 10 milli~econd pulse will aid the rec~iver in detecting the channel ~uard Yequance more rapidly. In thi~
fashion, it may be po~ ible to avoid delay~ in unmuting ~he audio which might cau~e the loss of a portion of a conversion, e.g., a ~yllable of a word.

The 10 milli~econd pulse width generated by microproce~sor 20 i5 0~ sufficient pulse width to insure that, even if the transmitter is as much a3 5 kHz off frequency, there is sufficient time to charge capacitor Cl up ~o the large dc level shift due to the tran~mitter being off frequency. It is noted that the width of the pulse may be set to le~
than 10 milliseconds if the resistor 16 is reduced in value.

I the outpu~ of FM de~ector 2 i~ at 5 ~olts with no carrier pre~ent, th~n capacitor Cl has substantially 0 volts across it, pre~ming that the voltage on the opposite plate of capacitor Cl (which i~ to be coupled to the tone limiter 5~ i~ likewise at S volt~. If the output of FM detector 2 shifts to 6 volt~ due to an off frequency transmitter, then without transistor Ql conducting, Cl must charge up to 1 volt ~hrough re3i~tor 18. The time required or capacitor Cl to charge up to 1 volt i~ a unction of the RC time constant of resistor 18 and capacitor Cl. Until capacitor Cl charge~ up to the 1 volt level, the tone limiter 5 is unable to provide valid data.

.. ..

' ': ' ~'''''' ": . , :: :
.
~ : .

Upon the generation of ~he 10 millisecond pul~e ~t the gate of transistor Ql, transistox Ql is turned on and begins to conduct. When tran~istor Ql becomes conductive, 5 volts is then supplied via resistor 16. As a result, Cl charges through ~he e~sentially parallel combination of resistors 16 and 18. Thus, with resistor 18 having the value of 40 K
and resistor 16 having the value of 1 K, capacitor Cl is able to charge up essentially 40 times faster than it could charge through resistor 18 alone.

As noted a~ove, during the time period that it takes capacitor Cl to reflect the new DC level, any data output from tone limiter 5 is not valid data.
Accordingly, by controlling capacitor Cl to charge to the required DC value 40 times faster, the operation of the tone data processing circuitry is signiicantly improved.

In the embodiment of Figure 1, as noted above, the specific component values shown are not critical to the presant invention. Resistor 16 should, however, have a much lower resistance than resistor 18. Additionally, resistor 6 should have a resistance equal to resistor 8 and the time constant o~ resistor 18 and C1 should be less than the time con~tant of re~istor 8 and capacitor 10.

Since the 10 millisecond pulse is suficient to rapidly ch~rge capacitor Cl through the parallel combination of resistors 16 and 18 to the FM
detector's new DC level, no significank timing degradation of tone or data decoding occur~. Tone ~ , ~

::
.:

17 1312~20 limiter 5 produceY valid digi~al data immediately after the lO millisecond pulse. In thi~ regard, capacitor Cl, resistor 16 and FET Ql have a low frequency cut-off of 60 Hz, and the tone limiter rapidly produces valid tone data ~above 60 Hz) i.e., once capacitor Cl is charged during the pulse.

An alternative embodiment of a fast settling tone processing circuit of the present invention is shown in Figure 5. This circuit (which does no~ use a capacitor Cl, such as shown in Figure l) is similar to the circuit o Figure l and will only be brie1y described below. Similarly labelled components operate identically in Figures l and 5.
In Figure 5, resistor 6 has a resistance equal to resistor 8 and resistor Rl has a re istance much less than resistor 8.

In Figure S, the FM detector level mu~t be low enough so the filters ~ and limiter 12 can still function properly without saturating when the RF
carrier is off frequency. The filter output must have a low impedance to source the charging current of C2 through Ql during the lO millisecond pulse applied to Ql. Therefore, when an off-frequency carrier appears, C2 is charged quickly so the dc re~erenc~ to the comparator will equal the dc level on the inverting signal input. This circuit will operate well if the filters 4 and limiter 12 can operate over a wide dc bias range determined by the FM detector output.

The present invention may be advantageou~ly ~.
1 31 2~20 lB

utilized in radio~ which allow searching of priority channels while li~ting to an active channel. In this regard, it is noted that chec~ing a priority channel ~or carrier activi~y and correct tone3 or data may place a gap in the active channel' 3 audio.
Thu~, a slow scanning rate can cause long holes to actually d~lete words in the conversation. In this regard, wh~n the receiver changes its channel frequency to check the priority channel freguency for carrier activity, the audio of the active channel is muted while ~he carrier activity on a priority channel is being sensed. If nothing i3 detected or if a detected channel guard is not valid, the conversation on the active chann~l is returned to. However, prior to the present invention 2 ~ignificant time period was i~volved in staying at ~he priority channel long enough to insure that the tone processing circuit had enough time to decode valid data. By virtue of the generation of the 10 millisecond pulse in the manner de~cribed above, no significant timing degradation o tone or data decoding occurs.

While the invention has been described in connection with what is presently con~idered to be the mo~t pr~ctical and preferred embodiment~, it i~
to b~ understood that the invention is not to be limited to the disclosed embodiments, but on the contrary, i~ intended to cover various modification and equivalent arrangements included within the ~pirit and scope of the appended claims.

Claims (47)

1. In a radio having an FM detector for receiving predetermined audio signals and a predetermined pattern of tones or digital data, a fast settling tone, data processing circuit comprising:
processing means for receiving a pattern of tones or digital data from said FM detector and for generating radio enabling data; and bias voltage control means coupled to the output of said FM detector and to said processing means for providing a bias voltage to said processing means and including means responsive to the detection of an RF
carrier for initiating a high speed generation of the bias voltage required for the processing means to enable the processing means to rapidly generate valid radio enabling data, whereby a predetermined pattern of valid enabling data may be detected to enable the predetermined audio signals to be heard.

2. A circuit according to claim 1, wherein said bias voltage control means includes means for permitting valid data to be generated by said processing means even when the FM detector detects an off-frequency carrier.

3. A circuit according to claim 2, wherein said means for permitting valid data to be generated includes a direct current: (dc) blocking capacitor coupled to receive the output of said FM detector.

4. A circuit according to claim 1 wherein said bias voltage control means includes a capacitor coupled to receive the output from said FM detector and wherein said means for initiating high speed generation of the bias voltage includes means for rapidly charging said capacitor in response to the detection of an RF carrier.

5. A circuit according to claim 1, wherein said means for initiating the high speed generation of the bias voltage includes means for generating a predetermined plus whenever an RF carrier is detected;
and switching means responsive to said predetermined plus whenever an RF carrier is detected; and switching means responsive to said predetermined plus to initiate said high speed generation of the bias voltage.

6. A circuit according to claim 5, wherein said means for generating said predetermined pulse includes a microprocessor.

7. A circuit according to claim 6, wherein said microprocessor includes means for decoding the radio enabling data generated by said processing means.

8. A circuit according to claim 1, wherein said bias voltage control means includes a capacitor coupled to a supply voltage via a first resistor; and wherein said means for initiating a high speed generation of the bias voltage includes a second resistor, and switching means responsive to the detection of an RF carrier for coupling the first resistor and second resistor so as to rapidly charge said capacitor.

9. A circuit according to claim 8, further including means responsive to a drop in the high frequency noise output from the FM detector to generate a predetermined pulse; and wherein said switching means is responsive to said predetermined pulse.

10. A circuit according to claim 5, wherein said predetermined pulses has a pulse width on the order of 10 milliseconds.

11. A circuit according to claim 1, wherein said processing means includes:
filter means coupled to said FM detector for passing low frequency signals and for significantly attenuating high frequency signals; and tone limiter means for receiving tone or digital data signals from said filter means and for generating digital signals indicative thereof.

12. A circuit according to claim 11 wherein said tone limiter includes a voltage comparator having an inverting input and a non-inverting input;
a first resistor coupled to the output of said filter means and the inverting input of said voltage comparator;
a second resistor being to the output of said filter means and the non-inverting input of said voltage comparator.

13. A circuit according to claim 12 wherein a capacitor is also coupled to the non-inverting input of the voltage comparator.

14. In a radio receiver having an FM detector for receiving predetermined audio signals and a predetermined pattern of tones or digital data and means for decoding said predetermined pattern to enable said predetermined audio signals to be heard, a fast settling tone/data processing circuit comprising:
means for processing a pattern of tones or digital data to generate data for enabling the predetermined audio signals to be heard in the receiver and for coupling said data to said means for decoding;
means coupled to said FM detector and to said means for processing for preventing a received off-frequency carrier from causing said means for processing to generate unreliable data; and means, coupled to said means for preventing and responsive to an indication that a pattern of tones or digital data must be decoded, for initiating a high speed operation of said means for preventing.

15. A circuit according to claim 14, wherein said means for preventing comprises a capacitor coupled to receive the output from said FM detector.

16. A circuit according to claim 15 further including first means for charging said capacitor.

17. A circuit according to claim 16, wherein said first means for charging includes a voltage source and first resistor.

18. A circuit according to claim 17, wherein said means for initiating high speed operation of said means for preventing includes means for rapidly charging said capacitor in response to the detection of an RF
carrier or the changing of the receiver's channel frequency.

19. A circuit according to claim 18, wherein said means for rapidly charging includes means for generating a predetermined pulse; and switching means responsive to said predetermined pulse to initiate said rapid charging of said capacitor.

20. A circuit according to claim 19, wherein said means for rapidly charging includes a second resistor, and wherein said switching means upon receiving said predetermined pulse being operable to couple said first and second resistor to rapidly charge said capacitor.

21. A circuit according to claim 14, wherein said means for processing includes:
filter means coupled to said FM director for passing low frequency signals and for significantly attenuating high frequency signals, and tone limiter means for receiving tone or digital data signals from said filter means and for generating digital signals indicative thereof.

22. A circuit according to claim 21, wherein said tone limiter includes a voltage comparator having an

23 45-MR-00567 inventing input and a non-inverting input;
a first resistor coupled to the output of said filter means and the inverting input of said voltage comparator;
a second resistor being to the output of said filter means and the non-inverting input of said voltage comparator.
23. A circuit according to claim 22, wherein a capacitor is also coupled to the non-inverting input of the voltage comparator.

24. In a radio having an FM detector for receiving predetermined audio signals and a pattern of tones or digital data and tone processing means for processing said pattern and for generating data indicative thereof for enabling the predetermined audio signals to be heard, a method for rapidly settling the tone processing means comprising the steps of:
preventing an off-frequency carrier from causing invalid data to be generated by said tone processing means by disposing a dc blocking capacitor between the FM
detector and said tone processing means; and rapidly charging said dc blocking capacitor in response to at least one of the sensing of a RF carrier or the changing of the receiver channel frequency to rapidly settle the tone processing means.

25. A method according to claim 24, wherein said rapidly charging step includes the steps of generating a pulse whenever an RF carrier is detected, and applying said pulse to a switching means coupled to said dc blocking capacitor.

26. A method according to claim 25, further including the step of coupling a pair of resistors in parallel in response to the application of the pulse to the switching means to thereby rapidly charge said capacitor.

27. A method according to claim 25, wherein said radio includes a transceiver microprocessor which decodes the data generated by said tone processing means, said method further including the step of generating said pulse with said transceiver microprocessor.

28. In a radio having an FM detector for receiving a predetermined pattern of tones or digital data, a fast settling tone, data processing circuit comprising:
processing means for receiving and processing a predetermined pattern of tones or digital data from said FM detector; and bias voltage control means coupled to the output of said FM detector and to said processing means for providing a bias voltage to said processing means, said control means including means responsive to the detection of an RF carrier for initiating a high speed generation of the bias voltage required for the processing means to generate valid data, whereby a predetermined pattern of valid data may be detected.

29. A circuit according to claim 28, wherein said bias voltage control means includes means for permitting valid data to be generated by said processing means even when the FM detector detects an off-frequency carrier.

30. A circuit according to claim 29, wherein said means for permitting valid data to be generated includes a direct current (dc) blocking capacitor coupled to receive the output of said FM detector.

31. A circuit according to claim 28, wherein said bias voltage control means includes a capacitor coupled to receive the output from said FM detector and wherein said means for initiating high speed generation of the bias voltage includes means for rapidly charging said capacitor in response to the detection of an RF

carrier.

32. A circuit according to claim 28, wherein said means for initiating the high speed generation of the bias voltage includes means for generating a predetermined pulse whenever an RF carrier is detected;
and switching means responsive to said predetermined pulse to initiate said high speed generation of the bias voltage.

33. A circuit according to claim 32, wherein said means for generating said predetermined pulse includes a microprocessor.

34. A circuit according to claim 33, wherein said microprocessor includes means for decoding the processed data generated by said processing means.

35. A circuit according to claim 28, wherein said bias voltage control means includes a capacitor coupled to a supply voltage via a first resistor; and wherein said means for initiating high speed generation of the bias voltage includes a second resistor, and switching means responsive to the detection of an RF carrier for coupling the first resistor and second resistor so as to rapidly charge said capacitor.

36. A circuit according to claim 35, further including means responsive to a drop in the high frequency noise output from the FM detector to generate a predetermined pulse; and wherein said switching means is responsive to said predetermined pulse.

37. In a radio receiver having an FM detector for receiving a predetermined pattern of tones or digital data and means for decoding said predetermined pattern, a fast settling tone/data processing circuit comprising:
means for processing a predetermined pattern of tones or digital data to generate data and for coupling said data to said means for decoding;
means coupled to said FM detector and to said means for processing for preventing a received off-frequency carrier from causing said means for processing to generate unreliable data; and means, coupled to said means for preventing and responsive to an indication that a predetermined pattern of tones or digital data must be decoded, for initiating a high speed operation of said means for preventing.

38. A circuit according to claim 37, wherein said means for preventing comprises a capacitor coupled to receive the output from said FM detector.

39. A circuit according to claim 38 further including first means for charging said capacitor.

40. A circuit according to claim 39, wherein said first means for charging includes a voltage source and first resistor.

41. A circuit according to claim 40, wherein said means for initiating high speed operation of said means for preventing includes means for rapidly charging said capacitor in response to the detection of an RF
carrier or the changing of the receiver's channel frequency.

42. A circuit according to claim 41, wherein said means for rapidly charging includes means for generating a predetermined pulse; and switching means responsive to said predetermined pulse to initiate said rapid charging of said capacitor.

43. A circuit according to claim 41, wherein said means for rapidly charging includes a second resistor, and wherein said switching means upon receiving said predetermined pulse being operable to couple said first and second resistor to rapidly charge said capacitor.

44. In a radio receiver having an FM detector for receiving a predetermined pattern of tones or digital data and tone processing means for processing said pattern and for generating data indicative thereof, a method for rapidly settling the tone processing means comprising the steps of:
preventing an off-frequency carrier from causing invalid data to be generated by said tone processing means by disposing a dc blocking capacitor between the FM
detector and said tone processing means; and rapidly charging said dc blocking capacitor in response to at least one of the sensing of a RF carrier or the changing of the receiver channel frequency to rapidly settle the tone processing means.

45. A method according to claim 44, wherein said rapidly charging step includes the steps of generating a pulse whenever an RF carrier is detected, and applying said pulse to a switching means coupled to said dc blocking capacitor.

46. A method according to claim 45 further including the step of coupling a pair of resistors in parallel in response to said application of the pulse to the switching means to rapidly charge said capacitor.

47. A method according to claim 45, further including the steps of decoding the data generated by said tone processing means using a transceiver microprocessor, and generating said pulse with said transceiver microprocessor.