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CA1253572A - Device for demodulating a spread spectrum signal - Google Patents

Device for demodulating a spread spectrum signal

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Publication number
CA1253572A
CA1253572A CA 531531 CA531531A CA1253572A CA 1253572 A CA1253572 A CA 1253572A CA 531531 CA531531 CA 531531 CA 531531 A CA531531 A CA 531531A CA 1253572 A CA1253572 A CA 1253572A
Authority
CA
Grant status
Grant
Patent type
Prior art keywords
signal
signals
decoding
data
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA 531531
Other languages
French (fr)
Inventor
Steven Messenger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aironet Canada Ltd
Original Assignee
Telesystems SLW Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69Spread spectrum techniques
    • H04B1/707Spread spectrum techniques using direct sequence modulation
    • H04B1/7073Synchronisation aspects
    • H04B1/7075Synchronisation aspects with code phase acquisition
    • H04B1/7077Multi-step acquisition, e.g. multi-dwell, coarse-fine or validation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69Spread spectrum techniques
    • H04B1/707Spread spectrum techniques using direct sequence modulation
    • H04B1/709Correlator structure

Abstract

INVENTION: DEVICE FOR DEMODULATING
A SPREAD SPECTRUM SIGNAL
INVENTOR: STEVEN MESSENGER

ABSTRACT OF THE DISCLOSURE
Circuitry for receiving and demodulating a spread spectrum signal integrates signal acquisition and tracking functions and also accommodates signal drift.
Two data decoding signals are generated which correspond to the pseudo noise code used to modulate the received signal and which are phase-shifted by a half-chip interval. Two correlators use the decoding signals to demodulate the received signal, both during acquisition and tracking, producing two data signals. A summer combines the two data signals to produce a signal whose strength is less dependent on the degree of synchronization of each data decoding signal with the received signal.
Tracking error circuitry periodically compares the two demodulated data signals and incrementally phase shifts the two data decoding signals, the magnitude of the increment being one-quarter chip and the polarity being selected to strengthen the weaker of the two data signals. This causes the circuitry to track the received signal despite gradual signal drift. A bank of correlators also demodulate the received signal using test decoding signals having different phase angles. The phase angles of the test decoding signals are periodically adjusted to locate stronger signals. Control circuitry constantly compares the strength of the demodulated test signals and of the two data signals and adjusts the phase of the two data decoding signals to correspond to that phase producing the strongest demodulated signal.

Description

~L~2S3~;72 FELD OF TEIE INVENTIQN
The invention relates to deviees and methods for deeoding spread speetrum signals, and more particularly, to matters of synehronizing deeoding signals generated by a reeeiver with a reeeived spread speehum signaL
5 DESCRIPTIO~ OF THE PRIQR AR~
Teehniques for direct sequence, spread spectrum modulating and demodulating data signals are well known. Modulation involves generating a periodic, eomparatively high-frequency, repetitive pseudo noise eode (PN code) and effeetively mixing the data signal with the PN code as with an exelusive OR gate or a balanced 10 mixer. The resulting signal is charaeterized by very wide bandwidth and very low spectral energy density. To deeode or demodulate a reeeived spread speetrum signal, it is neeessary to generate a deeoding signal eorresponding to the partieuklr PN code previously used for encoding purposes and to apply both the reeeived signal and the PN eode to a balaneed mixer or other mean eomlllonly referred to as a "eorrelator"
Spread speetrum modulation and demodulation might be partieularly useful for ~ansmission of data signals such as analog voice signals or digitized data in building interio~s over radio firequency earriers. The low spec~al density charaeteristie of sueh signal reduees the tendeney for interferenee with other radio sensitive equipment. Also, spread spectrum techniques are known intrinsically to reduee 20 interferenee between multiply reflectecl versions of a transmitted signal, as minimal phase differences between the local PN decoding signal and reflected signals results in low signal eorrelation and eonsequently minimal democlulation of such multiple signals.
The advantages assoeiated with spread spectrum techniques also 25 create problems regarding acquisition and ~acking of a desired signal. Basically, it ;s dif~leult to synehronize a loeally generated PN decoding signal with a received signal as no significant indieation of the degree of non-synchronization between such signals ~g ~L25357;;2 is available until ~e phase difference between the signals is min;mal. The ability to reject multiple reflections of a signal consequently ~reates dif~lculties in synchronizlng to a desired signal. These features of spread spectrum techniques also create problems regarding continued tracking of a received signal. In particular, mismatch between the 5 oscillators or clock signal generators required to produce PN code signals Ln the transmitting and receiving units tends to cause an apparent drift of the received signal relative to the receivers PN decoding signals. To ensure proper decoding, there is preferrably no more than a one-half chip phase difference between the received signal and the local PN decoding signal. ~ven a gradual drifting of the received signal can 10 cause a total loss of synchronization.
In the prior art, both digital and analog techniques have been developed to synchronize a local PN decoding signal to a transmi~ted spread spectrum signal. These techniques have effectively involved two distinct processes: initial acquisition of the transmitted signal, that is, a process of adjusting the phase angle of a 15 local PN decoding signal to match that of the received signal; and traclcing, that is, - demodulating the received si~nal using the phase angle selected during the acquisition process.
During acquisition, the phase angle of the PN decoding signal might be shifted in one-half chip intervals through the full range of possible phase angles to 20 obtain the phase angle which produces the strongest demodulated signal. This approach has serious shortcomings. In particular, tracking and decoding of a received signal is delayed until the assessment of all useful phase angles is complete. In the context of transmissions in the inter~or of an office buildmg, changes in or obstruction of transrnission paths owing to movement of persons or equipment may frequently 25 necessitate r~initiation of the acquisition process. Lack of an ability to quickly respond to such transmission p~th problems may be particularly critical if the tranxmissions occur in bursts as, for example, in the transmission of data packets containing digitized ~Zs3~

data. In such a context, the resulting transmission errors and reduction of transmission rates may be unacceptable.
BRIEF SUMMARY OF THE INVEN7 IC~
In one aspect, the invention provides a d~vice for demodulating a 5 received signal which has been direct sequence encoded with a predetermined pseudo noise code. The device includes means for generating a data decoding signal corresponding to the predete~nined pseudo noise code, and means for spread spectrum demodulating the received signal using the data decoding signal. Means are also provided for generating a test decoding signal which also corresponds to the 10 predetermined noise code, and means for spread spectrum demodulating the received signal using the test decoding signal to produce a test signal. Comparator meanscontinually compare the strength of the test signal and the data signal, and phase adjustment means adjust the phase of the decoding signal to correspond to the phase of the test signal when it is determined that the strength of the test signal exceeds that of 15 the data signal. Means are provided for continually changing the phase of the test decoding signal, effectively to search for alternative phase angles which are perhaps more appropr~ate for demodulation of the received signal.
For purposes of the invention, the data decoding signal may comprise a plurality of signals which result in a plurality of demodulated data signals. Similarly 20 the test decoding signal may comprise a phlrality of signals which result in a plurality of demodulated test signals. Such an arrangement is incorporated into the preferred embodiment described herein.
Such a device integrates the acquisition and tracking functions necessary to demodulate a spreacl spectrum signal. Faster acquisition times can be 25 achieved as demodulation of a received signal can be commenced as soon as anycorrelation occurs between a received signal and a locally generated data decoding signal. The device then hunts continually ~or alternative phase angles which produces ~2535i7~

stronger demodulated signal without disrupting the tracking and demodulation of ~e received signal. Such a devi&e can better accommodate the types of transmission path obstructions and changes which are apt to occur when data is transmitted over radio frequency carriers in the interior of an of fice building than prior devices. Basically, if a principal signal begins to fade, the device can potential1y ]locate a signal received along an alternative transmission path and switch the demodulation process to decode that alternative signal without disrupting associated data processing. This ensures more efficient and reliable data transmission.
Other inventive features will be described below in connection with a preferred embodiment and will be more specifically identified in the appended claims.
D~S~RTPl ION Q~ THE~ DRAWINC3S
The invention will be better understood with reference to drawings illustrating preferred embodiments in which:
fig. l diagrammatically illustrates a receiver adapted for direct sequence spread spectrum demodulation of received signals;
fig. 2 diagraïnmatically illustrates a typical correlator associated with the receiver;
fig. 3 diagrammatically illustrates an alternative colrelator which may be incorporatcd into the receiver;
fig. 4 diagrammatically illustrates comparator circuitry used by the receiver to compare demodulated signal strengths;
figs. Sa-5c diagrammatically indicate how drifting of a received signal is accormnodated by the receiver; and, ~IgS. 6a-6c diagrammatically indicate how the phase of a plurality of test decoding can be va~ied ~o search for decoding signal phase angles more conducive to proper decoding of a received signal.
DE~ÇRIPIIQ~I OF PI~EFERRED EMB~DIMENT

~.~25i35~

Reference is made to fig. 1 which illustrates the overall configuration of a receiver 10 embodying the principles of the invention. A wideband signal spread spectrum encoded according to a predetermined PN code is received by the receiver 10 ~or demodulation. The received signal might comprise, for example, digitized data 5 packets appropriately modulated according to a differential phase shift keying process (DPSK) and encoded onto an RF carrier in addition to being spread spectruun modulated. The present invention is concerned only with the manner in which such a wideband signal is to be spread spectrum demodulated to produce a narrow-band signal, the further decoding or processing required to convert such a signal into a 10 digital data signal ultimately use~ul to digital data processing equipment being a matter which will be apparent to those skilled in the art.
The receiver 10 has a demodulation section 12 comprising two correlators DCOR1, DCOR2 and the received signal is applied to each of these correlators. In this embodiment of the invention, two PN data decoding signals 15 DDSl, DDS2 are applied to the two correlators DCORl, DCOR2 to spread spectrumdemodulate the received signal thereby producing two data signals DS i, DS2. Both PN data decoding signals DDSl, DDS2 correspond to the predetermined PN code used initially to spread spectrum modulate the received signal prior to its transmission;
that is, each consists essentially of the same pseudo random chip sequence 20 characterising the predetermined PN code. The two PN data decoding signals DDS1, DDS2 are, however, phase-shifted relative to one another by the duration of one-half chip. What should be noted in that regard is that the phase difference b~tween the two PN data decoding signals DDS1, DDS2 is sufficiently small that both PN decoding signals can be simultaneously synchronized to the received signal to an appreciable 25 degree. I~is relationship between the two data decoding signals DDSl, I)DS2 has considerable bear~ng on the manner in which the receiver 10 is adapted to track a drifting signal, a matter which will be discussed more fully below. The two data ~2535;7~

signals DSl, DS2 are combined by a summer 14 to produce a DPSK narrow band signal corresponding t~ the sum of the two data signals, which can ihen receive whatever further processing may be required.
The receiver 10 also includes a bank 16 of correlators which are used 5 essentially to test for alternative synchronization phase angles for the two Pl~ data decoding signals DDSl, DDS2. In the correlator bank 16, there may be an arbitrary number of correlator which number is designated herein by ~he integer value 'IN".
Fig. 4 has accordingly been fragmented to indicate N correlators designated TCORl-TCC3RN. These correlators demodulate the received signal using N different10 PN test decoding signals designated TDSl-TDSN. Each of the test decoding signals TDSl-TDSN corresponds to the predetermined PN originally used to encode the received signal, but each has a different phase angle. Accordingly, these rnay be expected to produce demodulated "test" signals TSl-TSN of different st~ength.
A typical correlator 18 which may be used in the demodulation section 12 and the correlator bank 16 is illustrated in fig. 2. The correlator 18 includes a low pass filter 20 which removes unnecessary high frequency components of a locally-generated PN decoding signal (assumed of course to correspond to the encoding PN signal used to spread spectrum modulate the received signal). A
balanced rnixer 22 combines the wideband received signal with the filtered PN
20 decoding signal thereby spread spectrum demodulating the received signal. If the received signal and the PN decoding signal are substantially synchronized, having a phase difference of less than 1 chip duration, the received signal is effectively collapsed into a narrowband signal of higher spectral energy densi~. Such a collapsed signal can then passed by a bandpass filter 24 tuned to the expected frequency range of 25 the collapsed signal, eli~unating wideband noise and any multiply reflected signals of different phase. The f~ltered signal is received by a limiting amplifier 26 to increase the strength of the demodulated signal ~or subsequent processing ~such as RF

~53572 demodulation and DPSK decoding).
Fig. 3 illustrates an alternative embodiment of a correlator 28 which may be used in the demodulation section 12 and the correLItor bank 16, a heterodyne correlator. In this correlator, a PN decodmg signal is first rnodulated to radio5 frequencies by a balanced mixer 30 which use for such purposes an oscillatory RF
signal (generated by a conventional source which has not been illustrated). The resulting RF signa~ is then bandpass filtered by a filter 32 to remove extraneous spectral content and applied to a balanced m~xer 34 for combining with the wide band signal. The resulting spread spectrum demodulated signal is then applied to a 10 bandpass filter 36 having a pass band appropriate for the expected demodulated signal and for filtering of wideband noise. The filtered signal is then processed by a limiting amplifier 38 to produce a DPSK narrow band signal.
Certain components of the receiver 10 serve to generate local decoding signals intended both for phase angle testing and for general d~ta decoding.
15 To that end, a local osclllator 40 generates a clock signal norninally of the same frequency as one associated with the transrnitting Imit (not illustrated) and used to generate the received signal. The frequency o~ the local oscillator 40 ultimately determines the frequency at which the chips of the basic decoding signals are generated. This clock signal is received by a synchronization processor 42 (a digital 20 state machine) which regulates the generation of the PN decoding signals. Thesynchronization processor 42 controls a first PN code generator 44 to produce a first basic PN decoding signal for use in connection with the correlators DCORl~ DCOR2of ~e demodulation section 12. It also controls a second PN code generator 46 which produces a second basic PN decoding signal for use in connection witlh the correlators 25 TCORl-TCORN of the co~elator bank 16.
The synchronization processor 42 is also adapted to control the general nature of the basic PN decoding signals and to control their phase. In ~L2S35~

rPsponse to sign~ls received from appropriate external control circuitry along control intel~ce lines 48, 50, the synchronization processor 42 applies signals along lines 52J
54 to the two PN code generators to cause them to generate a particular P~ code.Such an arrangement is not essential to the inYention, but permits added flexibility, S allowing an operator at ~e external controls to select a basic PN decoding signal corresponding to one of a range of encoding signals used in such transm~tters (not illustrated) as may be intended to convey data to the receiver lQ The synchronization processor 42 also controls the first and second PN code generators by transmitting signals along lines 56, 58 to adjust the phase angle of the two basic signals relative to 10 the received signal.
The basic data decoding signal generated by the first PN code generator 44 is applied directly to the correlator DCORl of the demodulation section 12 and is in fact the data decoding signal previously designated DI~Sl. The basic decoding signal DDSl is also phase-shifted by a one-half chip delay 60 to produce the 15 second PN data decoding signal DDS2 that is applied to the other correlator DCOR2 of the demodulation section 12.
The basic test decoding signal designated TDSl produced by the second generator 46 is applied to a shift register 62 (fragmented) comprising a total of N- 1 flip-flops designated FFl to FFN- 1. Each fli~flop is adapted to produce a 20 one-chip delay and together they in effect produces the test decoding signalsTDS2-TDSN by successively phase-shifting the basic test decoding signal TDSl by one-chip amounts. Each test decoding signal is then applied to a different one of the correlators TCORl-TCORN in the correlator bank 16 for purposes of demodulating the received signal and producing the test signals TS l-TSN corresponding to different 25 phase angle which might be considered for use in the demodulation section 12.An amplitude comparator 64 serves to deterrnine which of the test signals TSl-TSN and data signals DSl, DS2 resulting -from demodulation of the 7~2 received signal is strongest. The amplitude comparator 64 is illustrated in greater detail in the view of fig. 4 where it may be seen to comprise a multiplicity of transistors.
Two of these transistors QDi, QD2 serve to charge capacitors CDl, CD2 in response to the data signals DSl, DS2. Resistors RDl, RD2 in par,allel with the capacitors S CDl, CD2 cause controlled discharge of the capacitors CDl, CD2 thereby pennit the voltages developed in the capacitors to follow general decreases in the voltage levels of the data signals DSl, DS2. Basically, each set consisting of a transistor, capacitor and resistor functions as a level detector, specifically a conventional peak detector, generating in response to the data signals DSl and DS2 corresponding level signals 10 LSDl and LSD2. Transistors TTl-l~, capacitors CTl-CTN and resistors RTl-RTN are similarly configured and serve as level detectors converting the test signals TSl-TSN into corresponding level signals LSTl-LSTN.
The amplitude comparator 64 includes a plurality of differential amplifiers which receive the various level signals. Two of these amplifiers have been 15 designated ADl and AD2 and receive at their non-inverting terminals the level signals LSDl and LSD2 associated with two data signals DSl, DS2 generated by the demodulation section 12. Another N differential amplifiers have been designated ATl-ATN and receive at their non-inverting terminals the level signals LSTl-LSTNassociated with test signals TSl-TSN generated by the correlator bank 16. The ~0 inverting terminals of the differential amplifiers ADl-AD2 and ATl-ATN are connected together and ~eedback between the output terminals of these amplifiers and the connected inverting terminals is provided in part by N+2 diodes Dl to DN+2, each ` diode connect~ng a different amplifier output terminal to feedback resistors RFl and RF2. ~is arrangemen¢ places the inverting terminals of the amplifiers ADl-AD2 and 25 ATl-ATN at a voltage corresponding to the level signal of greatest magnitude.Accordingly, all output terminals will tend to be at the negative supply voltage except for the one output terminal corresponding to the level signal of greatest strength.

~53S72 The output terminals of the various ampl;fiers ADl, AD2 and ATl-ATN are connected to a digital encoder 66 which can conveniently generate from the polari~y of t~e output signals an address signal uniquely identifying the strongest signal. The address signal is received by the synchronization processor 42 whichS responds by adjusting the phase of the basic data decoding signal DDSl generated by the firs~ PN code generator 44 to correspond to the phase of the one of the testdecoding signals TDSl-TDSN corresponding to the strongest of the demodulated test signals TSl-TSN, if the strongest of test signals TSl-TSN is in fact stronger than either of the two data signals DSl, DS2 produced by the correlators DCO~l, DCOR2of the demodulation section 12.
Means are also provided for correcting tracking errors arising, for example, from a mismatch in the clock frequency used to encode the received signal and the clock frequency of the local oscillator 40. To that end, the arnplitude comparator 64 illustrated in fig. 4 includes a low gain differential amplifier 68 which receives at its inverting and non-inverting terminals the level signals LSDl and LSD2 corresponding to the two demodulated data signals DSl, DS2. The resulting amplified difference signal is processed by a low pass filter 70 to remove high frequency components which might affect comparison of the difference signal to a DC reference value. The filtered signal is then received by a comparator 72 which responds to the polari~ of the difference signal, producing a tracking error signal indicating which of the data signals DSl, DS2 has the greatest strength. The comparator 72 may simply take the form of an operational amplifier operated with little or no feedback, whose non-inverting teln~inal receives the difference signal and whose inver~ng terminal is coupled to a ground reference.
The synchronization processor 42 receives the ~acking error signal and adjusts the phase of the basic data decoding signal DDSl generated by the ~lrst signal generator M, but only incrementally. Essentially, the phase of the basic data ~S3~'72 decoding signal DDSl is adjusted by an amount co~respo~ding to the duration of aone-quarter chip, the polarity of the increment being selected so that the weaker of the two data signals DSl, DS2 is strengthened, basically synchronizing the decoding operation of the correlator associated with the weaker of the two data signals DSl, 5 DS2 more closely with the received signal.
The manner in which the tracking error correction means accommodate apparent drifting of the received signal is symbolically illustratecl in a very simplified fashion in figs. Sa-5c. In ~lgS. 5a-Sc the phase angles of the first and second data decoding signals DDSl, DDS2 applied to the demodulation section 12 10 have been indicated respectively as vertical lines PAl and PA2. The phase angle of the received signal haq been indicated by a T-shape }abelled P~RS. These are indicators of relative phase only.
Reviewing figs. 5a-5c in succession it will be apparent that the received signal is subject to drift, its relative phase angle PARS changing continually.
lS In fig. Sa it has been arbitrarily assumed that the first data decoding signal DDSl is more closely synchroni~ed with the received signal (having a smaller phase difference relative to the received signal) and accordingly the corresponding data signal DS l generated by demodulation is stronger. The tracking error signal would in such circumstances indicate that the second data signal DS2 corresponding to phase angle 20 PA2 is weaker, and the synchronization processor 42 would then shift the phase angles PAl and PA2 by one-quarter chip to tend to reduce the phase difference between the second data decoding signal DDS2 and the received signal thereby tending to increase the strength of the second data signal DS2. However, as shown in fig. Sb, the received signal has drifted further, this drifting tending once again to increase the 25 phase separation between the second data decoding signal DDS2 and the received signal. The synchronization ~rocessor 42 once again responds by effectively incrementing the phase angles PAl and PA2 by a quarter-chip to attempt to better ~2~;35~2 synchronize the second data decoding signal DDS2 with the received signal. This an~angement effectively causes ~e data decoding ~ignals DDSl, DDS2 to track the received signal.
The principles of operation inherent in the tracking error means can accommodate any conditions producing a gradual drift of the received signal. Thesummer 14 is important in such an arrangement, as it cannot be guaranteed at anygiven time which of the decoding signals DDSl, DDS2 will be more closely synchronized with the received signal and which of the demodulated data signals DSl, DS2 would have a signal strength more appropriate for further processing. Summing the two data signals DSI, DS2 ensures that a signal of reasonable strength is always provided. The summing of the two signals DSl, DS2 has another significant aspect:
if either of the two demodulated data signals DSl, DS2 were relied upon exclusively for subsequent data retrieval, its amplitude would appear significantly modulated by the incremental phase shifting implemented by the tracking error means, successively increasing and decreasing. The combined data signal produced by the summer 14 tends to display a more constant amplitude.
The frequency at which the synchronization processor 42 incrementally adjusts phase angles of the two data decodmg signals DDSl, DDS2 isselected according to the manufacturer's specified tolerances in the frequency of operation of the local oscillator 40 and the corresponding oscillator (not illustrated) in the transmitting unit (not illus~rated) which transrn~ts the received signal. It will be readily apparent to those skilled in the art how such information can be used tocalculate the maximum expected rate of drift of ~e received signal. The synchronization process m~ght typically be timed to perform its incremental adjustment of phase angles once in ~very 1000 cycles of the local oscillator 40, a triggering signal for such adjustment being generated and timed by dividing the local oscillator's signal in a conventional manner. Although the phase angles might be adjusted more ~ii35~72 frequently, it is desirable even with use of the summer 14 to avoid ulmecessa~y amplitude modulation of the combination of the two data data signals DSl, DS2.
Figs. 6a-6c indicate in a symbolic manner how the receiver 10 continually hunts for decoding signal phase angles which can produce stronger 5 demodulated data signals and continually adjusts the phase angles of the data decoding signals DS I and DS2, the latter phase again once again being designated PAl andPA2. Ihe phase angles associated wlth the test decoding signals Tl )S l-TDSN having been illustrated as a set vertical of lines collectively labelled with the word "TEST', there being N such lines in total, but the draw~ng being fragmented in the regard and 10 showing only s~x. Two relative phase angles of two received signal have been indicated by T-shapes and labelled PARSl and PARS2, these representing, for exarnple, the received signal transmitted along different transmission paths due to multiple reflections and resulting phase differences. The relative horizontal spacing of the vertical lines and the T-shapes is intended to indicate relative phase differences.
For the initial phase settings of the test decoding signals in fig. 6a, one of the test decoding signals arbitrarily assumed to be TDS3 may be seen to be more closely synchronized wi~ the received signal having phase angle PARSl and would consequently produce a comparatively strong demodulated test signal. If the receiver 10 were just initiating decoding of the received signal, the phase of the data 20 decoding signals DDSl, DDS2 might be set to correspond the phase of thè t~st decoding signal TDS3 as indicated in fig. 6b.
The synchronization processor 42 then shifts the phases of each test decoding signals by an increment corresponding to N+l chip durations as in fig. 6b.
The test decoding signal TDS2 might then be substantially synchronized with the 25 received signal having the phase angle PARS2. If the associated demodulated test signal is ~e strongest of the other test signals TSl-TSN and also the two demodulated data signals DSl, OS2, the synchronization processor 42 would adjust the phase of 35~2 the two data decoding signals DDS 1, DDS2 used by the demodulation section 12 tocorrespond to the phase angle of the test signal TS2, as illustrated in f~lg. 6c.
Otherwise their phase angles would remain unchanged.
In fig. 6c, the synchronization processor 42 has once again shiited 5 the phase angle of each of the test decoding signals TDSl-TDSN by N+l chip durations. With the new phase angle settings, no version of the received signal is detected, and accordingly the phase angles of the two data decoding signals DDSl, DDS2 are not adjusted by the synchronization processor 42. Assuming that all possible phase angles (at one chip intervals) have been exhausted, the synchronization 10 processor 42 rnight once again restore the phase angles of the test decoding signals to correspond to those illustrated in fig. 6a. This process would be repeated periodically to continuously scan for stronger versions of the received signal. The manner inwhich the receiver 10 scans for better phase reladonships with the received signal is not a cAtical aspect of the invention: alternative phase angles may be checked in any 15 manner which canvasses a wide range of possible angles.
The integrated acquisition and tracking system of the receiver l0 can significantly reduce acquisition time, as useful data decoding begins as soon as a useful received signal is detected. Also, use of a parallel arrangement of correlators to locate alternative phase relationships further reduces signal acquisition time. This is 20 critical in the context of spread spectrum data packet transmission where a very finite amount of data is transm~tted and quick synchronization to a given data packet is re~ired if high data transfer rates are to be achieved. Also, since the receiver 10 continually scans for stronger signals to decode, it can accommodate the fading of a signal transmitted along a par~icular signal path, causing the demodu}ation section 12 25 to lock onto a stronger signal transmitted along a different signal path without disrupting the decoding process and subsequent data processing. In the context of data transmission in packet form in ~e interior of an offilce building, where multiple ~2535~7 transmission paths may be expected and where signal obstructions and changes in transmission paths can be eYpected to occur quite ~equently9 the receiver 10 can in many instances lock onto a different signal for data decoding before a given signal is entirely lost, ~ereby reducing data transmission errors and increasing data throughput.
It will be appreciated that a particular embodiment of the invention has been described, and that modifications may be made therein without depa~ting from ~e spirit of the inventiGn or the scope of the appended claims. In particular, although the advantages of the spread spectrum demodulation techniques taught herein have been described largely in connection with spread spectrum modulation of digitized data packets, the techniques also have application to transmission of analog signals.

Claims (14)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A device for demodulating a spread spectrum signal which has been direct sequence encoded with a predetermined pseudo noise code, comprising:
means for generating a data decoding signal corresponding to the predetermined pseudo noise code;
means for spread spectrum demodulating the spread spectrum signal with the data decoding signal to produce a data signal;
means for generating a test decoding signal corresponding to the predetermined pseudo noise code;
means for spread spectrum demodulating the spread spectrum signal using the test decoding signal to produce a test signal;
comparator means for comparing the strength of the test signal with the strength of the data signal;
means responsive to the comparator means for adjusting the phase of the decoding signal relative to the spread spectrum signal to correspond to the phase of the the test signal when the strength of the test signal exceeds the strength of the data signal; and, means for continually adjusting the phase of the test decoding signal in a predetermined manner such that alternative phase relationships resulting in a synchronization between the test decoding signal and the spread spectrum signal can be produced.
2. A device for demodulating a spread spectrum signal which has been direct sequence encoded with a predetermined pseudo noise code, comprising:
decoding signal generating means for generating a first data decoding signal corresponding to the predetermined pseudo noise code;
data demodulation means for demodulating the spread spectrum signal with the first data decoding signal to produce a first data signal;

test signal generating means for generating a plurality of test decoding signals corresponding to the predetermined pseudo noise code, each of the test decoding signals being phase-shifted relative to any other of the test decoding signals by a predetermined amount;
test demodulation means for spread spectrum demodulating the spread spectrum signal using the test decoding signals to produce a plurality of test signal, each test signal corresponding to the demodulation of the spread spectrum signal with a different one of the test signals;
comparator means for comparing the strength of the test signals and the first data signal;
decoding signal phase adjusting means responsive to the comparator means for adjusting the phase of the first data decoding signal relative to the spread spectrum signal to correspond to the phase of the test decoding signal corresponding to the strongest of the test signals when the strength of the strongest of the test signals exceeds the strength of the first data signal; and, test decoding signal phase adjusting means for continually adjusting the phase of the test decoding signals relative to the spread spectrum signal in a predetermined manner such that alternative phase relationships resulting in a synchronization between the test decoding signals and the spread spectrum signal can be produced.
3. A device as claimed in claim 2 in which:
the decoding signal generating means comprise means for generating a second data decoding signal corresponding to the predetermined pseudo noise code, the second data decoding signal being phase-shifted relative to the first data decoding signal by an amount so selected that the second data decoding signal tends to besynchronized relative to the spread spectrum whenever the first data decoding signal is synchronized with the spread spectrum signal;

the data demodulation means comprise means for demodulating the spread spectrum signal with the second data decoding signal to produce a second data signal; and, the comparator means are adapted to compare the strength of the second data signal with the strength of the first data signal and the test signals; and, the decoding signal phase adjusting means are adapted to adjust the phase of the first and second data decoding signals relative to the spread spectrum signal to correspond to the phase of the test decoding signal corresponding to the strongest of the test signals when the strength of the strongest of the test signals exceeds the strength of the first and second data signals.
4. A device as claimed in claim 3 comprising summing means for producing a signal corresponding to the sum of the first and second data signals.
5. A device as claimed in claim 4 in which the comparator means comprise:
data signal comparison means for comparing the strength of the first and second data signals;
incremental phase adjustment means for adjusting the phase angles of the first and second data decoding signals by an incremental amount, the polarity of the incremental amount being selected such that the weaker of the first and second data signals tends to increase in strength.
6. A device as claimed in claim 1 in which the comparator means comprise:
a plurality of signal level detectors, each signal level detector receiving a different one of the test signals and the first data signal and producing a level signal corresponding to the magnitude of the received one of the test signals and the first data signal;
a plurality of amplifiers, each amplifier having an inverting terminal, a non-inverting terminal and an output terminals the inverting terminals being connected together and each non-inverting terminals being coupled to a different one of the peak detectors to receive a different one of the level signals; and, feedback means for coupling the output terminals of the amplifiers to the connected inverting terminals such that a signal corresponding to the one of the level signals having the largest magnitude is generated at each of the invertingterminals;
whereby, the output terminals of each of the amplifiers has voltage with a particular polarity except the output terminal of the amplifier receiving the one of the level signals having the largest magnitude.
7. A device for demodulating a spread spectrum signal which has been direct sequence encoded with a predetermined pseudo noise code, comprising:
decoding signal generating means for a plurality of data decoding signals, each data decoding signal corresponding to the predetermined pseudo noise code, each of the data decoding signals being phase-shifted relative to any other of the data decoding signals by a predetermined amount;
data demodulation means for demodulating the spread spectrum signal with the plurality of data decoding signals to produce a plurality of data signals, each data signal corresponding to the demodulation of the spread spectrum signal with a different one of the plurality of data decoding signals;
test signal generating means for generating a plurality of test decoding signals corresponding to the predetermined pseudo noise code, each of the test decoding signals being phase-shifted relative to any other of the test decoding signals by a predetermined amount, test demodulation means for spread spectrum demodulating the spread spectrum signal using the test decoding signals to produce a plurality of test signal, each test signal corresponding to the demodulation of the spread spectrum signal with a different one of the test signals;
comparator means for comparing the strength of the test signals and the data signals;
decoding signal phase adjusting means responsive to the comparator means for adjusting the phase of the decoding signals relative to the spread spectrum signal to correspond to the phase of the test decoding signal corresponding to the strongest of the test signals whenever the strength of the test signals exceeds the strength of the data signal; and, test decoding signal phase adjusting means for continually adjusting the phase of each test decoding signal relative to the spread spectrum signal in a predetermined manner such that alternative phase relationships resulting in a synchronization between the test decoding signals and the spread spectrum signal can be produced.
8. A device as claimed in claim 7 comprising summing means for producing a signal corresponding to the sum of the data signals.
9. A device as claimed in claim 8 in which the comparator means comprise:
data signal comparison means for comparing the strength of the data signals;
incremental phase adjustment means for adjusting the phase angles of the decoding signals by an incremental amount, the polarity of the incremental amount being selected such that the weakest of the plurality of data signals tends to increase in strength.
10. A device as claimed in claim 7 in which the comparator means comprise:
a plurality of level detectors, each level detector receiving a different one of the test signals and the data signals and producing a level signal corresponding to the magnitude of the received one of the test signals and the data signals;
a plurality of amplifiers, each amplifier having an inverting terminal, a non-inverting terminal and an output terminal, the inverting terminals being connected together and each non-inverting terminals being coupled to a different one of the level detectors to receive a different one of the level signals; and, feedback means for coupling the output terminals of the amplifiers to the connected inverting terminals such that a signal corresponding to the one of the level signals having the largest magnitude is generated at each of the invertingterminals;
whereby, the output terminals of each of the amplifiers has voltage with a particular polarity except the output terminal of the amplifier receiving the one of the level signals having the largest magnitude.
11. A device as claimed in claim 7 in which the test signal generating means comprise:
means for generating a base signal corresponding to the predetermined pseudo noise code; and, delay means for producing the test signals by successively delaying the base signal relative to the spread spectrum signal by a predetermined amount.
12. A device as claimed in claim 11 in which the test decoding signal phase adjusting means are adapted to adjust the phase of the base signal relative to the spread spectrum signal periodically by an amount such that the resulting phase angle of each of the test decoding signals is outside a range of phase angles limited by the least and the greatest of the current phase angles of the test decoding signals.
13. A device for demodulating a spread spectrum signal which has been direct sequence encoded with a predetermined pseudo noise code, comprising:
decoding signal generating means for generating a plurality of data decoding signal corresponding to the predetermined pseudo noise code, the data decoding signals being phase-shifted relative to the one another such that the data decoding signal can be simultaneously synchronized to the spread spectrum signal;
a plurality of demodulation means for spread spectrum demodulating the spread spectrum signal with a different one of the data decoding signals to produce a plurality of data signals;
combining means for producing a summation signal corresponding to the sum of the data decoding signals;
comparator means for comparing the strength of the data signals;
synchronization control means for adjusting the phase of the plurality of decoding signals relative to the spread spectrum signal so as to maintain a general synchronization between the decoding signals and the spread spectrum signal, thesynchronization control means including means responsive to the comparator meansand controlling the data signal generating means for incrementally adjusting the phase of the plurality of decoding signals relative to the spread spectrum signal such that the weakest of the data signals tends to be strengthened.
14. A device as claimed in claim 1 in which:
the data decoding signals are phase-shifted relative to one another by no more than about one-half of the duration of a chip of the data decoding signals; and, the means for incrementally adjusting the phase of the plurality of decoding signals is adapted to increment the phase angles of the data decoding signals by no more than about quarter of the duration of a chip of the data decoding signals.
CA 531531 1987-03-09 1987-03-09 Device for demodulating a spread spectrum signal Expired CA1253572A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0772813A1 (en) * 1994-07-22 1997-05-14 AETHER WIRE & LOCATION Spread spectrum localizers

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0772813A1 (en) * 1994-07-22 1997-05-14 AETHER WIRE & LOCATION Spread spectrum localizers
EP0772813A4 (en) * 1994-07-22 2002-11-13 Aether Wire & Location Spread spectrum localizers

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