CA1252236A - Variable color display device - Google Patents
Variable color display deviceInfo
- Publication number
- CA1252236A CA1252236A CA000563216A CA563216A CA1252236A CA 1252236 A CA1252236 A CA 1252236A CA 000563216 A CA000563216 A CA 000563216A CA 563216 A CA563216 A CA 563216A CA 1252236 A CA1252236 A CA 1252236A
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- color
- bus
- light
- display
- display areas
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Abstract
VARIABLE COLOR DISPLAY DEVICE
ABSTRACT OF THE DISCLOSURE
A display device, capable of selectively displaying characters in a variable color, includes a plurality of display areas with primary color light sources which are commonly coupled to primary color buses. In the first embodiment is disclosed a step variable color display device in which the primary color buses may be activated in selective combinations for illuminating the display device in a selective one of a plurality of predetermined colors.
In the second embodiment is disclosed a continuously variable color display device in which the primary color buses may be selectively activated by pulses of selective durations for controlling the color of the display device substantially continuously.
ABSTRACT OF THE DISCLOSURE
A display device, capable of selectively displaying characters in a variable color, includes a plurality of display areas with primary color light sources which are commonly coupled to primary color buses. In the first embodiment is disclosed a step variable color display device in which the primary color buses may be activated in selective combinations for illuminating the display device in a selective one of a plurality of predetermined colors.
In the second embodiment is disclosed a continuously variable color display device in which the primary color buses may be selectively activated by pulses of selective durations for controlling the color of the display device substantially continuously.
Description
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SUMMARY OF THE INVENTION
It is the principal object of this invention to provide a variable color display device.
It is another object of the invention to provide a display device in which the color of the display may be controlled in a plurality of steps.
It is further object of the invention to provide a display device in which the color of the display may be controlled substantially continuously.
It is still further object oE the invention to provi.de devices for deveLopi.ng color control signals.
In summary each display area of a variable color display device of the invention includes at least two light sources for emitting upon activation light signals of respectively different primary colors which are combined therein to obtain a composite light signal of a composite color. A-t least a first and a second primary color buses are provided to which the light sources in the display areas for emitting light signals of a first and second primary colors are respectively commonly coupled. The primary color buses may be activated either in selective combinations, for controlling the color of the display device in steps, or for selective time periods, for controlling the color of the display device substantially continuously.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings in which are shown several possible embodiments of the invention, FIG. 1 is a block diagram of 2-primary color display system.
FIG. 2 is a block diagram of 3-primary color display system.
FIG. 3 is an enlarged detail of one digit of 2-primary color digital display.
FIG. 4 is an enlarged cross-sect;onal v:iew of one dlsplay ~egment in I~IG. 3, taken along the Llne 4 - 4.
FIG. S is an enlarged detail of one digit of 3-primary color digital display.
FIG. 6 is an enlarged cross-sectional view of one display segment in FIG. 5, taken along the line 6 - 6.
FIG. 7 is a schematic diagram of one 2-primary color display element.
FIG. 8 is a schematic diagram of one 3-primary color display element.
FIG. 9 is a simplified schematic diagram, similar to FIG.
7, showing how number '7' can be displayed in three different colors.
FIG. 10 is a simplified schematic diagram, similar to FIG. 8, showing how n~lmber '1' can be displayed in seven different colors.
FIG. 11 is a block diagram of 2-primary color 4-digit display.
FIG. 12 is a block diagram of 3-primary color 4-digit ~'~ S'~ ~ 6 display.
FIG. 13 is an expanded block diagram of 2-LED color converter.
FIG. 14 is an expanded block diagram of 3-LED color converter.
FIG. 15 is a schematic diagram of a scaling circuit.
FIG. 16 is a schematic diagram of an A/D converter and memory combination of FIGS. 13 and 14.
FIG. 17 is a schematic diagram of a memory and color converter combination of FIG. 13.
FIG. 18 is a timing diagram o:E the circuit shown in FIG.
17.
FIG. 19 19 a schemat:ic diagram oE a memory and co:Lor converter combination of FIG. 14.
FIG. 20 is a timing diagram of the circuit shown in FIG.
19 .
FIG. 21 is a continuation of the timing diagram of FIG.
20.
FIG. 22 is a graphic representation of TABLE 1.
FIG. 23 is a graphic representation of TABLE 2.
FIG. 24 is a graph of the ICI chromaticity diagram.
FIG. 25 is a schematic diagram of a counter and decoder combination for developing color control signals for the display element in FIG. 7.
FIG. 26 is a chart showing the relationship between count accumulated in the counter in FIG. 25 and color of the display element in FIG. 7.
FIG. 27 is a schematic diagram of a counter and decoder combination for developing color control signals for the display element in FIG. 8.
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FIG. 28 is a chart showing the relationship between count accumulated in the counter in FIG. 27 and color of the display element in FIG. 8.
Throughout the drawings, like characters indicate like parts.
BRIEF DESCRIPTION OF THE TABLES
In the tables which show examples oE a relatlonshlp between an input voltage, memory contents, ancl resultlng color ln the color converter of the present lnvention, TABLE 1 shows the characteristic of a step variable
SUMMARY OF THE INVENTION
It is the principal object of this invention to provide a variable color display device.
It is another object of the invention to provide a display device in which the color of the display may be controlled in a plurality of steps.
It is further object of the invention to provide a display device in which the color of the display may be controlled substantially continuously.
It is still further object oE the invention to provi.de devices for deveLopi.ng color control signals.
In summary each display area of a variable color display device of the invention includes at least two light sources for emitting upon activation light signals of respectively different primary colors which are combined therein to obtain a composite light signal of a composite color. A-t least a first and a second primary color buses are provided to which the light sources in the display areas for emitting light signals of a first and second primary colors are respectively commonly coupled. The primary color buses may be activated either in selective combinations, for controlling the color of the display device in steps, or for selective time periods, for controlling the color of the display device substantially continuously.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings in which are shown several possible embodiments of the invention, FIG. 1 is a block diagram of 2-primary color display system.
FIG. 2 is a block diagram of 3-primary color display system.
FIG. 3 is an enlarged detail of one digit of 2-primary color digital display.
FIG. 4 is an enlarged cross-sect;onal v:iew of one dlsplay ~egment in I~IG. 3, taken along the Llne 4 - 4.
FIG. S is an enlarged detail of one digit of 3-primary color digital display.
FIG. 6 is an enlarged cross-sectional view of one display segment in FIG. 5, taken along the line 6 - 6.
FIG. 7 is a schematic diagram of one 2-primary color display element.
FIG. 8 is a schematic diagram of one 3-primary color display element.
FIG. 9 is a simplified schematic diagram, similar to FIG.
7, showing how number '7' can be displayed in three different colors.
FIG. 10 is a simplified schematic diagram, similar to FIG. 8, showing how n~lmber '1' can be displayed in seven different colors.
FIG. 11 is a block diagram of 2-primary color 4-digit display.
FIG. 12 is a block diagram of 3-primary color 4-digit ~'~ S'~ ~ 6 display.
FIG. 13 is an expanded block diagram of 2-LED color converter.
FIG. 14 is an expanded block diagram of 3-LED color converter.
FIG. 15 is a schematic diagram of a scaling circuit.
FIG. 16 is a schematic diagram of an A/D converter and memory combination of FIGS. 13 and 14.
FIG. 17 is a schematic diagram of a memory and color converter combination of FIG. 13.
FIG. 18 is a timing diagram o:E the circuit shown in FIG.
17.
FIG. 19 19 a schemat:ic diagram oE a memory and co:Lor converter combination of FIG. 14.
FIG. 20 is a timing diagram of the circuit shown in FIG.
19 .
FIG. 21 is a continuation of the timing diagram of FIG.
20.
FIG. 22 is a graphic representation of TABLE 1.
FIG. 23 is a graphic representation of TABLE 2.
FIG. 24 is a graph of the ICI chromaticity diagram.
FIG. 25 is a schematic diagram of a counter and decoder combination for developing color control signals for the display element in FIG. 7.
FIG. 26 is a chart showing the relationship between count accumulated in the counter in FIG. 25 and color of the display element in FIG. 7.
FIG. 27 is a schematic diagram of a counter and decoder combination for developing color control signals for the display element in FIG. 8.
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FIG. 28 is a chart showing the relationship between count accumulated in the counter in FIG. 27 and color of the display element in FIG. 8.
Throughout the drawings, like characters indicate like parts.
BRIEF DESCRIPTION OF THE TABLES
In the tables which show examples oE a relatlonshlp between an input voltage, memory contents, ancl resultlng color ln the color converter of the present lnvention, TABLE 1 shows the characteristic of a step variable
2-primary color converter.
TABLE 2 shows a rainbow-like characteristic of a continuously variable 3-prlmary color converter.
Throughout the tables, memory addresses and data are expressed in a well known hexadecimal notation.
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DESCRIPTION OF T~E PREFERRED EMBODIMENTS
Referring now, more particularly, to the drawings, in FIG. 1 is shown a block diagram of a 2-primary color display system including a display decoder 21, a variable color 2-LED display element 46, and a 2-primary color control 52.
The display decoder 21 accepts at its inputs a code representing the character to be disp:Layed and accordingly develops output drive signals to drive respective segments of display element 46. The color control 52 accepts color control signals at its inputs R (red), Y (yellow), and G
(green) and develops at its outputs drlve signals for red bus 5 and green bus 6, respectively, to :illuminate d:isplay element 46 in a selected color.
In FIG. 2 is shown a block diagram of a 3-primary color display system including a display decoder 21, a variable color 3~LED display element 47, and a 3-primary color control 53. The color control 53 accepts color control signals at its inputs R (red), Y (yellow), G (green), BG
(blue-green), B (blue), P (purple), and W (white) and develops at its outputs drive signals for red bus 5, green bus 6, and blue bus 7, respectively, to illuminate display element 47 in a selected color.
In FIG. 3, the 2-primary color display element includes seven elongated display segments a, b, c, d, e, f, and g, arranged in a conventional pattern, which may be selectively energized in different combinations to display the desired digits. Each display segment includes a pair of LEDs (light emitting diodes): red LED 2 and green LED 3, which are closely adjacent such that the light signals emitted :~5;~Z~g~
therefrom are substantially superimposed upon each other to mix the colors. To facilitate the illustration, the LEDs are designated by segment symbols, e. g.~ the red LED in the segment a is designated as 2a, etc.
In FIG. ~, red LED 2e and green LED 3e are placed on the base of a segment body 15a which is filled with a transparent light scattering material 16. When forwardly biased, LEDs 2e and 3e emit light signals of red and green colors, respectively, which are scattered within transparent material 16, thereby blending the red and green light signals into a composite light signal that emerges at the upper surEace oE segment body :l5a. rhe color oE the composite light signal may be controlled by varying the portions of the red and green light signals.
In FIG. 5, each display segment of the 3~primary color display element includes a triad of LEDs: red LED 2, green LED 3, and blue LED ~, which are closely adjacent such that the light signals emitted therefrom are substantially superimposed upon one another to mix the colors.
In FIG. 6, red LED 2e, green LED 3e, and blue LED ~e are placed on the base of a segment body l5b which is filled with a transparent light scattering material 16. Red LEDs are typically manufactured by diffusing a p-n junction into a GaAsP epitaxial layer on a GaAs substrate; green LEDs typically use a GaP epitaxial layer on a GaP substrate; blue LEDs are typically made from SiC material.
When forwardly biased, LEDs 2e, 3e, and ~le emit light signals of red, green, and blue colors, respectively, which are scattered within transparent material 16, thereby blending the red, green, and blue light signals into a ~ ~ S~ ~ ~ 6 composite light signal that emerges at the upper surface of segment body 15b. The color of the composite light signal may be controlled by varying the portions of the red, green, and blue light signals.
In FIG. 7 is shown a schematic diagram of a 2-primary color common cathodes 7-segment display element 42 which can selectively display various digital fonts in different colors on display segments a, b, c, d, e9 f, g, and DP
(Decimal Point). The anodes of all red and green LED pairs ~0 are interconnected in each display segment and are electri.cally connected to respective outputs oE a co~n~ercially we~L known common-cathode 7-segln~nt cl~coder driver 23. The cathodes of all red LEDs 2a, 2b, 2c, 2d, 2e, 2f, 2g, and 2i are interconnected to a common electric path referred to as a red bus 5. The cathodes of all green LEDs 3a, 3b, 3c, 3d, 3e, 3f, 3g, and 3i are interconnected to a like common electric path referred to as a green bus 6.
The red bus 5 is connected to the output of a tri-state inverting buffer 63a, capable of sinking sufficient current to forwardly bias all red LEDs 2a to 2i in display element 42. The green bus 6 is connected to the output of a like buffer 63b. The two buffers 63a and 63b can be simultaneously enabled by applying a low logic level signal to the input of inverter 64a, and disabled by applying a high logic level signal thereto. When buffers 63a and 63b are enabled, the conditions of red bus 5 and green bus 6 can be selectively controlled by applying suitable logic control signals to the bus control inputs RB (red bus) and GB
(green bus), to illuminate display element ~2 in a selected color. When buffers 63a and 63b are disabled, both red ~'~S'~Z~6 bus 5 and green bus 6 are effectively disconnected to cause display element 42 to be completely extinguished.
In FIG. 8 is shown a schematic diagram of a 3-primary color common anodes 7-segment display element 43 which can selectively display digital fonts in different colors.
The cathodes of all red, green, and blue LED triads in each display segment are interconnected and electrically connected to respective outputs of a commercially well known common anode 7-segment decoder driver 24. The anodes of all red LEDs 2a, 2b, 2c, 2d, 2e, 2f, and 2g are interconnected to Eorm a common electric path reEerred to as a red bus 5. The anocles of al:l green ~EDs 3a, 3b, 3c, 3d, 3e, 3E, and 3g are interconnected to form a like common electric path referred to as a green bus 6. The anodes of all blue LEDs 4a, 4b, 4c, 4d, 4e, 4f, and 4g are interconnected to form a like common electric path referred to as a blue bus 7.
The red bus 5 is connected to the output of a non-inverting tri-state buffer 62a, capable of sourcing sufficient current to illuminate all red LEDs 2a to 2g in display element 43. The green bus 6 is connected to the output of a like buffer 62b. The blue bus 7 is connected to the output of a like buffer 62c. The three buffers 62a, 62b, and 62c can be simultaneously enabled, by applying a low logic level signal to the input of inverter 64b, and disabled by applying a high logic level signal thereto.
When buffers 62a, 62b, and 62c are enabled, the conditions of red bus 5, green bus 6, and blue bus 7 can be selectively controlled by applying valid combinations of logic level signals to the bus control inputs RB (red bus), }6 GB (green bus), and BB (blue bus), to illuminate display element 43 in a selected color. When buffers 62a, 62b, and 62c are disabled, red bus 5, green bus 6, and blue bus 7 are effectively disconnected to cause display ele~ent 43 to be completely extinguished.
2'Z36 STEP VARIABLE COLOR CONTROL
The operation of display element 42 shown in FIGo 7 will be now explained by the example of illuminating a digit 171 in three different colors. A simplified schematic diagram to facilitate the explanation is shown in FIG~ 9~ ~ny digit between O and 9 can be selectively displayed by applying the appropriate BCD code to the inputs AO, Al, A2, and A3 of common-cathode 7-segment decoder driver 23. The decoder driver 23 develops at its outputs a, b, c, d, e, f, g, and DP drive signals for energizing selected groups oE the segments to thereby visually clisplay the sel.ected nwmber, in a mailLler well known ~o those having ordinary skilL :in ~he art. To display decimal number '7', a BCD cocle OLll is applied to the inputs AO, Al, A2, and A3. The decoder driver 23 develops high voltage levels at its outputs a, b, and c, to illuminate e~ually designated segments a, b, and c, and low voltage levels at all remaining outputs (not shown), to extinguish all remaining segments d, e, f, and g.
To illuminate display element ~2 in red color, the color control input R is raised to a high logic level, and the color control inputs Y and G are maintained at a low logic level. As a result, the output of OR gate 60a rises to a high logic level, thereby causing the output of buffer 63a to drop to a low logic level. The current flows from the output a of decoder driver 23, via red LED 2a and red bus 5, to current sinking output of buffer 63a. Similarly, the current flows from the output b of decoder driver 23, via red LED 2b and red bus 5, to the output of buffer 63a. The current flows from the output c of decoder driver 23, via ~ ~ S~ ~ ~ 6 red LED 2c and red bus 5, to the output of buffer 63a. As a result, segments a, b, and c illuminate in red color, thereby causing a visual impression of a character '7'. The green LEDs 3a, 3b, 3c remain extinguished because the output of buffer 63b is at a high logic level, thereby disabling green bus 6.
To illuminate display element 42 in green color, the color control input G is raised to a high logic level, while the color control inputs R and Y are maintained at a low logic level. As a result, the output of OR gate 60b rises to a high logic level, thereby causing the output of buffer 63b to drop to a low log:ic level. Tlle cur~ent El.ows frorn the output a of decoder driver 23, via green LED 3a and green bus 6, to current sinking output of buffer 63b.
Similarly, the current flows from the output b of decoder driver 23, via green LED 3b and green bus 6, to the output of buffer 63b. The current flows from the output c of decoder driver 23, via green LED 3c and green bus 6, to the output of buffer 63b. As a result, segments a, b, and c illuminate in green color. The red LEDs 2a, 2b, and 2c remain extinguished because the output of buffer 63a is at a high logic level, thereby disabling red bus 5.
To illuminate display element 42 in yellow color, the color control input Y is raised to a high logic level, while the color inputs R and G are maintained at a low logic level. As a result, the outputs of both OR gates 60a and 60b rise to a high logic level~ thereby causing the outputs of both buffers 63a and 63b to drop to a low logic level. The current flows from the output a of decoder driver 23, via red LED 2a and red bus 5, to current sinking output of ~S;2~6 buffer 63a, and, via green LED 3a and green bus 6, to current sinking output of buffer 63b. Similarly, the current flows from the output b of decoder driver 23, via red LED 2b and red bus 5, to the output of buffer 63a, and, via green LED 3b and green bus 6, to the output of buffer 63b. The current flows from the output c of decoder driver 23, via red LED 2c and red bus 5, to the output of buffer 63a, and, via green LED 3c and green bus 6, to the output of buffer 63b. As a result of blending light of red and green colors in each segment, segments a, b, and c il:luminate in substantially yellow color.
The operation oE dlsplay element ~3 shown in FlG. 8 w:ilL
be now explained by the example of illuminating a digit '1 r in seven different colors. A simplified schematic diagram to facilitate the explanation is shown in FIG. 10. To display decimal number '1', a BCD code 0001 is applied to the inputs AO, Al, A2, and A3 of common anode 7-segment decoder driver 24. The decoder driver 24 develops low voltage levels at its outputs b and c, to illuminate equally designated segments b and c, and high voltage levels at all remaining outputs (not shown), to extinguish all remaining segments a, d, e, f, and g.
To illuminate display element 43 in red color, the color control input R is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the ou-tput of OR gate 61a rises to a high logic level, thereby causing -the output of buffer 62a to rise to a high logic level. The current flows from the output of buffer 62a, via red bus 5 and red LED 2b, -to the output b of decoder driver 2~, and, via red LED 2c, to ~2~ 236 the output c of decoder driver 24. As a result, segments b and c illuminate in red color, thereby causing a visual impression of a character '1'. The green LEDs 3b, 3c and blue LEDs 4b, 4c remain extinguished because green bus 6 and blue bus 7 are disabled.
To illuminate display element 43 in green color, the color control input G is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the output of OR gate 61b rises to a high logic level, thereby causing the output of buffer 62b to rlse to a hlgh logic level. The current Elows ~rom the output o~ bufEer 62b, via green bus 6 and green LED
3b, to the output b of decoder driver 24, and, v:ia green LED
3c, to the output c of decoder driver 24. As a result, segments b and c illuminate in green color.
To illuminate display element ~3 in blue color, the color control input B is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the output oE OR gate 61c rises to a high logic level, thereby causing the output of buEfer 62c to rise to a high logic level. The current flows from the output of buffer 62c, via blue bus 7 and blue LED 4b, to the output b of decoder driver 24, and, via blue LED 4c, to the output c of decoder driver 24. As a result, segments b and c illuminate in blue color.
To illuminate display element 43 in yellow color, the color control input Y is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the outputs of OR gates 61a and 61b rise to a high logic level, thereby causing the outputs 1~
~;?,Z36 of buffers 62a and 62b to rise to a high logic level. The current flows from the output of buffer 62a, via red bus 5 and red LED 2b, to the output b of decoder driver 24 9 and, via red LED 2c, to the output c of decoder driver 24. The current also flows from the output of buffer 62b, via green bus 6 and green LED 3b, to the output b of decoder driver 24, and, via green LED 3c, to the output c of decoder driver 24. As a result of blending light of red and green colors in each segment, the segments b and c illuminate in substantially yellow color.
To illuminate clisplay element 43 in purple co:lor, the col.or con~roL inp~lt P :is raised to a high logLc LeveL, while all remaining color control inputs are maintained at a low logic level. As a result, the outputs of OR gates 61a and 61c rise to a high logic level, thereby causing the outputs of buffers 62a and 62c to rise to a high logic level. The current flows from the output of buffer 62a, via red bus 5 and red LED 2b, to the output b of decoder driver 24, and, via red LED 2c, to the output c of decoder driver 24. The current also flows from the output of buffer 62c, via blue bus 7 and blue LED 4b, to the output b of decoder driver 24, and, via blue LED 4c, to the output c of decoder driver 24. As a result of blending light of red and blue colors in each segment, segments b and c illuminate in substantially purple color.
To illuminate display element 43 in blue-green color, the color control input BG is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the outputs of OR gates 61b and 61c rise to a high logic level, thereby causing the outputs of buffers 62b and 62c to rise to a high logic level. The current flows from the output of buffer 62b, via green bus 6 and green LED 3b~ to the output b of decoder driver 24, and, via green LED 3c, to the output c of decoder driver 24. The current also flows from the output of buffer 62c, via blue bus 7 and blue LED 4b, to the output b of decoder driver 24, and, via blue LED 4c, to the output c of decoder driver 24. As a result of blending light of green and blue colors in each segment, segments b and c il:Luminate in substantially blue-green color.
To ilLuminate display element 43 in white coLor, the color co[~troL input W is raised to a high logic LeveL, while all remaining color control inputs are maintained at a low logic level. As a result, the outputs of OR gates 61a, 61b, and 61c rise to a high logic level, thereby causing the outputs of respective buffers 62a, 62b, and 62c to rise to a high logic level. The current flows from the output of buffer 62a, via red bus 5 and red LED 2b, to the output b of decoder driver 24, and, via red LED 2c, to the output c of decoder driver 24. The current also flows from the output of buffer 62b, via green bus 6 and green LED 3b, to the output b of decoder driver 24, and, via green LED 3c, to the output c of decoder driver 24. The current also flows from the output of buffer 62c, via blue bus 7 and blue LED 4b, to the output b of decoder driver 24, and, via blue LED 4c, to the output c of decoder driver 24. As a result of blending light of red, green, and blue colors in each segment, segments b and c illuminate in substantially white color.
Since the outputs of decoder driver 24 may be overloaded ~;2S2~6 by driving a triad of LEDs in parallel in display element 43, rather than a single LED in a monochromatic display 9 it would be obvious to employ suitable buffers to drive respective color display segments (not shown).
To illustrate how the present invention can be utilized in a multi-element variable color display configuration, in FIG. 11 is shown a detail of the interconnection in a 2-primary color 4-digit display having display segments la, l'b, lc, and ld arranged in a 7-segment font. The color control inputs R, Y, and G of color controls 52a, 52b, 52c, and 52d of aLl display el.ements 46a, 46'b, 46c, and 46cl are interconnecte(l, respect:ively, ancl enable inputs El, E2, E3, and E4 are used to control the conditions of respective display elements 46a, 46b, 46c, and 46d. A high logic level at the enable input E extinguishes the particular display element 46a, 46b, 46c, or 46d; a low logic level therein illuminates display element 46a, 46b, 46c, or 46d in a color determined by the instant conditions of the color control inputs R, Y, and G.
In FIG. 12 is shown a like detail of the interconnection in a 3-primary color 4-digit display having display segments la~ lb, lc, and ld arranged in a 7-segment font. Similarly, the color control inputs B, P, BG, G, Y, ~, and R of color controls 53a, 53b, 53c, and 53d of all display elements 47a, 47b, 47c, and 47d are interconnected, and the conditions of respective display elements 47a, 47b, 47c, and 47d are controlled by enable inputs El, E2, E3, and E4. A high logic level at the enable input E extinguishes the particular display element 47a, 47'b, 47c, or 47d; a low logic level therein illuminates display element 47a, 47b, ~5~6 47c, or 47d in a color determined by the instant conditions of the color control inputs B, P, BG, G, Y, W, and R.
The exemplary color control circuits described herein will cooperate equally well with a multi-element variable color display constructed either in common cathodes or in common anodes configuration.
~;~S2~6 CONTINUOUSLY VARIABLE COLOR CONVERTER
The display system shown in FIG. 13 utilizes a scaling circuit 80a which scales input analog voltage levels to a voltage range suitable for an A/D converter 74a, which in turn develops at its outputs a digital code having relation to the value of the input analog voltage. The output lines of A/D converter 74a are connected to the address inputs of a memory 76 having a plurality of addressable locations which contai.n data indicating the portions of red color for several diEEerent values of the input analog voltage. The output data oE memory 76 are appliecl to the inputs of a color converter 57 which will develop control signals for red bus 5 and green bus 6, respectively 7 of variable color display element 42.
The display system shown in FIG. 14 utilizes a scaling circuit 80b and an A/D converter 74b for converting the instant value of an input analog voltage to a digital code.
The outputs of A/D converter 74b are connected, in parallel, to the address inputs of memory 76a, which contains data lndicating the portions of red color, to the address inputs of memory 76b, which contains data indicating the portions of green color, and to the address inputs of memory 76c, which contains data indicating the portions of blue color. The output data of memory 76a are applied to red color CQnverter 59a which will develop control signals for red bus 5 of variable color display element 43. The output data of memory 76b are applied to green color converter 59b which will develop control signals for green bus 6 of display element 43. The output data of ;22;~6 memory 76c are applied to blue color converter 59c which will develop control signals for blue bus 7 of display element 43.
FIG. 15 is a schematic diagram of a scaling circuit capable of shifting and amplifying the input voltage levels.
The circuit utilizes two operational amplifiers 81a and 81b in a standard inverting configuration. The amplifier 81a is set for a unity gain by using resistors 90a and 90b of equal values; potentiometer 92a is adjusted to set a desired offset voltage. The amplifier 81b sets the gain by adjusting feedback potentiometer 92b to a desired value with respect to resistor 90c. ~s a res~Lt, an input vo:ltage, wh:icll ~lay vary between arbitrary limits Vlow and Vhigh, may be scaled and shifted to the range between 0 Volts and 9.961 Volts, to facilitate the use of a commercially available A/D
converter.
FIG. 16 is a schematic diagram of an A/D (analog-to-digital) converter 75 which is capable of converting input analog voltage, applied via resistor 90e to its input Vin~
to 8~bit digital data for addressing a memory 77. The conversion may be initiated from time to time by applying a short positive pulse 99a to the Blank and Convert input B&C.
A/D converter 75 will thereafter perform a conversion of the instant input voltage to 8-bit data indicative of its value.
When the conversion is completed, the Data Ready oukput DR drops to a low logic level, thereby indicating that the data are available at the outputs Bit :L to Bit 8, which are directly connected to respective address inputs A0 to A7 of memory 77. When the DR output drops to a low :Logic level, the Chip Select input CS of memory 77 is activatedS memory l'~S;~2~
77 is enabled, and the data, residing at the address selected by the instant output of A/D converter 75, will appear at its data outputs D0 to D7.
The description of the schematic diagram in FIG. 17 should be considered together with its accompanying timing diagram shown in FIG. 18. A clock signal 99b of a suitable frequency (e. g., 10 kHz), to provide a flicker-free display, is applied to the Clock Pulse inputs CP of 8-bit binary counters 71e and 71f to step them down. At the end :lO of each counter cycle, which takes 256 clock cycles to compLete, the Terminal Count output TC oE counter 7:Le drops to a low :Log:ic level Eor one clock cycle, to thereby indicate that the lowest count was reached. The negative pulse ~9c at the TC output of counter 71e, which is connected to the Parallel Load input PL of counter 71f, causes the instant data at the outputs of memory 76 to be loaded into counter 71f. The data at memory 76 represent the portion of red color; the portion of green color is complementary. The rising edge of the TC pulse 99c triggers flip-flop 73 into its set condition wherein its output Q
rises to a high logic level.
The counter 71f will count down, from the loaded value, until it reaches zero count, at which moment its TC output drops to a low logic level. The negative pulse at the TC
output of counter 71f, which is connected to Clear Direct input CD of flip-flop 73, causes the latter to be reset and to remain in its reset condition until it is set again at the beginning of the next 256-count cycle. It is thus obvious that the Q output of flip-flop 73 is at a high logic level for a period of time proportional to the data ~s~
initially loaded into counter 71f. The complementary output Q is at a high logic level for a complementary period of time.
The Q and Q outputs of flip-flop 73 are connected to red bus 5 and green bus 6, respectively, via suitable buffers 63a and 63b, shown in detail in FIG. 7, to respectively energize red bus 5 and green bus 6 for variable time periods, depending on the data stored in memory 76.
By referring now, more particularly 9 to the timing diagram shown in FCG. 18, in which the waveforms are compressecl to Eacilitate the llLustration, the EXA~P~t,F :L
cons:iders the memory cl~lt~l 'FD', in a stanclarcl hexaclecimal notation, to generate light of substantially red color. At the beginning of the counter cycle, pulse 99c loads data 'FD' into counter 71f. Simultaneously, flip-flop 73 is set by the rising edge of pulse 99c. The counter 71f will be thereafter stepped down by clock pulses 99b, until it reaches zero count, 2 clock cycles before the end of the counter cycle. At that instant a short negative pulse 99d is produced at its output TC to reset flip-flop 73, which will remain reset for 2 clock cycles and will be set again by pulse 99c at the beginning of the next counter cycle, which will repeat the process. It is readily apparent that flip-flop 73 was set for 254 clock cycles, or about 99% of the time, and reset for 2 clock cycles, or about 1% of the time. According]y, red bus 5 of display element 42 is energized for about 99% of the time, and green bus 6 is energized for the remaining about 1% of the time. As a result, display element 42 illuminates in substantially red color.
~ ~ 5~ Z ~ 6 The EXAMPLE 2 considers the memory data '02' (HEX~ to generate light of substantially green color. At the beginning of the counter cycle, data '02' are loaded into counter 71f, and, simultaneously, flip-flop 73 is set. The counter 71f will count down and will reach zero count after 2 clock cycles. At that instant it produces at its output TC a negative pulse 99e to reset flip-flop 73. It is readily apparent that flip-flop 73 was set for 2 clock cycles, or about 1% of the time, and reset for 254 clock cycles, or about 99% of the time. Accordingly, red bus 5 of display element 42 is energized Eor about 1 % of the time, and green bus 6 is ener~ized Eor the remaining about 99% of the time. As a result, display element ~2 illuminates in substantially green color.
The EXAMPLE 3 considers the memory data '80' ~HEX) to generate light of substantially yellow color. At the beginning of the counter cycle, data '80' are loaded into counter 71f~ and, simultaneously, flip-flop 73 is set. The counter 71f will count down and will reach zero count after 128 clock cycles. At that instant it produces at its output TC a negati~e pulse 99f to reset flip-flop 73.
It is readily apparent that flip-flop 73 was set for 128 clock cycles, or about 50% of the time, and reset for 12~
clock cycles, or about 50% of the time. Accordingly, red bus 5 of display element 42 is energized for about 50% of the time, and green bus 6 is energized for the remaining about 50% of the time. As a result of blending substantially equal portions of red and green colors, display element 42 illuminates in substantially yellow color.
The description of the schematic diagram of a 3-LED color 2~
converter in FIG. 19 should be considered together with its accompanying timing diagrams shown in FIGS. 20 and 21. A
clock signal 99b is applied to the CP inputs of counters 71d, 71a, 71b, and 71c to step them down. Every 256 counts a negative pulse 99c is generated at the TC output of counter 71d, to load data into counters 71a, 71b, and 71c from respective memories 76a, 76b, and 76c, and to set flip flops 73a, 73b, and 73c. The data in red memory 76a represent the portions of red color, the data in green memory 76b represent the portions of green color, and the data in blue memory 76c represent the portions of bl~le color to be bLended.
The counters 71a, 71b7 and 71c will count down, from the respective loaded values, until zero counts are reached.
When the respective values of the loaded data are different, the length of time of the count-down is different for each counter 71a, 71b, and 71c. When a particular counter 71a, 71b, or 71c reaches zero count, its TC output momentarily drops to a low logic level, to reset its associated flip-flop (red counter 71a resets its red flip-flop 73a, green counter 71b resets its associated green flip-flop 73b, and blue counter 71c xesets its associated blue flip-flop 73c).
Eventually, all three flip-flops 73a, 73b, and 73c will be reset. The Q outputs of flip-flops 73a, 73b, and 73c are connected to red ~us 5, green bus 6, and blue bus 7, respectively, via suitable buffers 62a, 62b, and 62c, as shown in FIG. ~, to respectively energize red bus 5, green bus 6, and blue bus 7 for variable periods of time.
By referring now more particularly to the timing diagram shown in FIGS. 20 and 21, the EXAMPLE 4 considers red ~ ~ S~ 3 6 memory data '80', green memory data lool, and blue memory data '80', all in hexadecimal notation, to generate light of substantially purple color. At the beginning of the counter cycle, the pulse 99c simultaneously loads data '80' from red memory 76a into red counter 71a, data '00' from green memory 76b into green counter 71b, and data '80' from blue memory 76c into blue counter 71c. The counters 71a, 71b, and 71c will be thereafter stepped down. The red counter 71a will reach its zero count after 128 clock cycles; green counter 71b will reach its zero count irnmediately; blue counter 71c will reach its zero count after 128 clock cycles.
~ t is reaclily apparent that red 11p-flop 73a was set for 128 clock cycles, or about 50% of the time, green flip-flop 73b was never set, and blue flip-flop 73c was set for 128 clock cycles, or about 50% of the time. Accordingly, red bus 5 of display element 43 :is energized for about 50% of the time, green bus 6 is never energized, and blue bus 7 îs energized for about 50% of the time. As a result of blending substantially equal portions of red and blue colors, display element 43 illuminates in substan-tially purple color.
The EXAMPLE 5 considers red memory data '00', green memory data '80', and blue memory data '80', to generate light of substantially blue-green color. At the beginning of the counter cycle, data '00' are loaded into red counter 71a, data '80' are loaded into green counter 71b, and data '80' are loaded into blue counter 71c. The red counter 71a will reach its zero count immediately, green counter 71b will reach its zero count after 128 clock periods, and so ~2~;~2;~6 will blue counter 71c.
The red flip-flop 73a was never set, green flip-flop 73b was set for 128 clock pulses, or about 50% of the time, and so was blue flip-flop 73c. Accordingly, green bus 6 of display element 43 is energized for about 50% of the time, and so is blue bus 7. As a result, display element 43 illuminates in substantially blue-green color.
The EXAMPLE 6 considers red memory data '40', green memory data '40', and blue memory data '80', to generate light oE substantially cyan color. At the beginning of the counter cycle, the data '40' are loaded into red counter 71a, data '40' ~re loaded into green counter 7:Lb, ancl data '80' are Loaded into blue counter 71c. The red counter 71a will reach its zero count after 64 clock cycles, and so will green counter 71b. The blue counter 71c will reach its zero count after 128 clock cycles.
The red flip-flop 73a was set for 64 clock cycles, or about 25% of the time, and so was green Elip-flop 73b.
The blue Elip-flop 73c was set for 128 clock cycles, or about 50% of the time. Accordingly, red bus 5 and green bus 6 of display element 43 are energized for about 25% of the time, and blue bus 7 is energized for about 50% of the time. As a result of blending about 50% of blue color, 25%
of red color, and 25% of green color, display element 43 illuminates in substantially cyan color.
The EXAMPLE 7 considers red memory data '80', green memory data '40', and blue memory data '40', to generate light of substantially magenta color. At the beginning of the counter cycle, the data '80' are loaded into red counter 71a, data '40' are loaded into green counter 71b, 1~52;~3~
and data '40' are loaded into blue counter 71c. The red counter 71a will reach its zero count after 128 clock cycles, green counter 71b will reach its zero count after 64 clock cycles, and so will blue counter 71c.
The red flip-flop 73a was set for 128 clock cycles, or about 50% of the time, green flip-flop 73b and blue flip-flop 73c were set for 64 clock cycles, or about 25% of the time. Accordingly, red bus 5 of display element 43 is energized for about 50% of the time, green bus 6 and blue bus 7 are energized for about 25% of the time. As a result, display element 43 illuminates in substantially magenta color.
By referring now more particularly to FIGS. 22 and 23, which are graphic representations of TABLES l and 2, respectively, the data at each memory address are digital representation of the portion of the particular primary color. All examples consider an 8-bit wide PROM
(Programmable Read Only Memory). However, the principles of the invention couLd be applied to other types of memories.
In FIG. 22, RED PORTION indicates the portion of red primary color; GREEN PORTION indicates the portion of green primary color. The RED PORTION for a particular memory address was calculated by dividing the actual value of data residing at that address by the maximum possible data 'FF' (HEX). The GREEN PORTION for the same memory address is complementary; it was obtained by subtracting the calculated value of the RED PORTION from number 1Ø
In FIG. 22 is shown the characteristic of a 2-primary color converter, defined in TABLE 1, for developing color variable in steps: pure green for input voltages less than ~25i2~
0.625 V, substantially yellow for voltages between 1.25 V
and 1.875 V, pure red for voltages between 2.5 V and 3.125 V, and of intermediate colors therebetween, this sequence being repeated three times over the voltage range.
In FIG. 23, RED PORTION indicates the portion of red primary color; GREEN PORTION indicates the portion of green primary color; BLUE PORTION indicates the portion of blue primary color. The RED PORTION for a particular memory address was calculated by dividing the value of red data residing at such address by the maximum possible data 'FF' (HEX). Similarly, the GREEN PORrrLON Eor that memory adclress was obtalnecl by clividing the value o green data by 'FF' (HEX). rrhe BLUE PORTION was obtained by dividing the value of blue data by 'FF' (HEX).
In FIG. 23 is shown the characteristic of a 3-primary color converter, defined in TABLE 2, for developing color continuously variable from pure red, through substantially orange and yellow, pure green, pure blue, to substantially purple, in a rainbow-like fashion.
In the examples of the characteristics of color converters shown in TABLE l and TABLE 2, the data values stored in red memory 76a, green memory 76b, and blue memory 76c are so designed that the sums of the red data, green data, and blue data are constant for all memory addresses, to provide uniform light intensities for all colors. It is further contemplated -that data stored in red memory 76a, green memory 76b, and blue memory 76c may be modified in order to compensate for different efficiencies of red, green, and blue LEDs. By way of an example, data values for a low efficiency LED may be proportionally incremented such ~5Z~36 that time of energization is proportionally increased, to effectively provlde equal luminances for LEDs of unequal efficiencies.
With reference to FIG. 24 there is shown the ICI
(International Committee on Illumination) chromaticity diagram designed to speciy a particular color in terms of x and y coordinates. Pure colors are located along the horseshoe-like periphery. Reference numbers along the periphery indicate wavelength in nanometers. When relative portions of three primary colors are known, the color of light prod-1ced by blending the:ir em:issions can be determined by examining tlle x and y val~les of :CC[ coorclinat~!s.
~252'~6 COLOR CONTROL SIGNALS
In FIG, 25 is shown a detail o~ a counter and decoder combination for developing color control signals to cause display element 42 to illuminate in one of three possible colors in accordance with the accumulated count. The description of the circuit should be considered together with its associated chart shown in FIG. 26. An 8-bit binary counter 95 contains internal register with outputs QO to Q7 available. Two most significant outputs Q6 and Q7 are connected to respective inputs A and B of a 3-to-8 line decoder 96; the most significant input C of decoder 96 is grounded. In response to conditions oE the co~lnter outputs Q6 ancl Q7, decoder 96 develops output signals YO, Yl, and Y2. When both counter outputs Q6 and Q7 are at a low logic level (which is typical for counts less than 63), the decoder output YO rises to a high logic level to generate active color control signal R (red). When the counter output Q6 rises to a high logic level, while the output Q7 is low (which is typical for counts between 64 and 127), the decoder output Yl rises to a high logic level to generate active color control signal Y (yellow). When the counter output Q7 rises to a high logic level and Q6 drops to a low logic level (which is typical for counts between 128 and 191), the decoder output Y2 rises to a high logic level to generate active color control signal G (green). The decoder outputs YO, Yl, and Y2 may be respectively connected to color control inputs R, Y, and G of display element 42 in FIG. 9.
Although not illustrated, it would be obvious that S2~}6 counter 95 may be incremented by applying suitable clock signals to its CLOCK input and initialized by applying a suitable signal to its CLR input. The accu~lulated count may be transferred to its internal register by applying a suitable signal to the REG CL input.
FIG. 27 is a like detail of a counter and decoder combination for developing color control signals to cause display element 43 to illuminate in one of seven possible colors, depending on the accumulated count. The associated chart is shown in FIG. 28. This circuit difEers from the one shown in F'IG. 25 in that three outputs Q5, Q6, and Q7 o~
counter 95 are connected to respective inputs A~ B, and C o~
decoder 96 to develop color control signals R, W, Y, G, BG, P, and B at respective decoder outputs Yl to Y7. When the counter output Q5 is at a high logic level and Q6, Q7 are low (which is typical for counts between 32 and 63), the decoder output Yl rises to a high logic level to generate active color control signal R (red). When the counter output Q6 is at a high logic level and Q5, Q7 are low (which is typical ~or counts between 64 and 95), the decoder output Y2 rises to a high logic level to generate active color control signal W (white). When the counter outputs Q5, Q6 are at a high logic level and Q7 is low (which is typical for counts between 96 and 127), the decoder output Y3 rises to a high logic level to generate active color control signal Y (yellow). When the counter output Q7 is at a high logic level and Q5, Q6 are low (which is typical for counts between 12~ and 159), the decoder output Y4 rises to a high logic level to generate active color contro:L signal G
(green). When the counter outputs Q5, Q7 are at a high logic level and Q6 is low (which is typical for counts between 160 and 1~1)9 the decoder output Y5 rises to a high logic level to generate active color control signal BG (blue~
green). When the counter outputs Q6, Q7 are at a high logic level and Q5 is low (which is typical for counts between 192 and 223), the decoder output Y6 rises to a high logic level to generate active color control signal P (purple).
When all counter outputs Q5, Q6, ~7 are at a high logic level (which is typical for counts higher than 224), the decoder output Y7 rises to a high logic level to generate active color control signal B (blue). The decoder outputs Y:L, Y2, Y3, Y~, Y5, Y6, and Y7 may be respectively connected to color control :inputs R, W, Y, G, BG, P, and ~3 of di~plfly element 43 in FIG. 10.
It would be obvious that the coLor sequences could be readily changed by differently interconnecting the decoder outputs Y0 to Y7 with color control inputs R to B of display element 43.
In brief summary, a variable color display device was disclosed which includes a plurality of display areas which may be selectively activated in groups to display characters. Each display area includes two light sources for emitting upon activation light signals of respectively different primary colors which are combined therein to obtain a composite light signal of a composite color. Two primary color buses are provided to which the light sources in the display areas for emitting light signals of a first and second primary colors are respectively commonly coupled.
Color control is provided for activating the primary color buses either in selective combinations, for controlling the ~S~236 color of the display device in steps, or for selective time periods, for controlling the color of the display device substantially continuously.
It would be obvious that numerous modifications can be made in the construction of the preferred embodiments shown herein, without departing from the spirit of the invention as defined in the appended claims. It is contemplated that the principles of the invention may be also applied to numerous diverse types of display devices, such are liquid crystal, plasma devices, and the like.
~2S;2Z36 CORRELATION TABLE
This is a correlation table of reference characters used in the drawings herein, their descriptions, and examples of commercially available parts.
# DESCRIPTION EXAMPLE
1 display segment 2 red LED
TABLE 2 shows a rainbow-like characteristic of a continuously variable 3-prlmary color converter.
Throughout the tables, memory addresses and data are expressed in a well known hexadecimal notation.
:~z~
DESCRIPTION OF T~E PREFERRED EMBODIMENTS
Referring now, more particularly, to the drawings, in FIG. 1 is shown a block diagram of a 2-primary color display system including a display decoder 21, a variable color 2-LED display element 46, and a 2-primary color control 52.
The display decoder 21 accepts at its inputs a code representing the character to be disp:Layed and accordingly develops output drive signals to drive respective segments of display element 46. The color control 52 accepts color control signals at its inputs R (red), Y (yellow), and G
(green) and develops at its outputs drlve signals for red bus 5 and green bus 6, respectively, to :illuminate d:isplay element 46 in a selected color.
In FIG. 2 is shown a block diagram of a 3-primary color display system including a display decoder 21, a variable color 3~LED display element 47, and a 3-primary color control 53. The color control 53 accepts color control signals at its inputs R (red), Y (yellow), G (green), BG
(blue-green), B (blue), P (purple), and W (white) and develops at its outputs drive signals for red bus 5, green bus 6, and blue bus 7, respectively, to illuminate display element 47 in a selected color.
In FIG. 3, the 2-primary color display element includes seven elongated display segments a, b, c, d, e, f, and g, arranged in a conventional pattern, which may be selectively energized in different combinations to display the desired digits. Each display segment includes a pair of LEDs (light emitting diodes): red LED 2 and green LED 3, which are closely adjacent such that the light signals emitted :~5;~Z~g~
therefrom are substantially superimposed upon each other to mix the colors. To facilitate the illustration, the LEDs are designated by segment symbols, e. g.~ the red LED in the segment a is designated as 2a, etc.
In FIG. ~, red LED 2e and green LED 3e are placed on the base of a segment body 15a which is filled with a transparent light scattering material 16. When forwardly biased, LEDs 2e and 3e emit light signals of red and green colors, respectively, which are scattered within transparent material 16, thereby blending the red and green light signals into a composite light signal that emerges at the upper surEace oE segment body :l5a. rhe color oE the composite light signal may be controlled by varying the portions of the red and green light signals.
In FIG. 5, each display segment of the 3~primary color display element includes a triad of LEDs: red LED 2, green LED 3, and blue LED ~, which are closely adjacent such that the light signals emitted therefrom are substantially superimposed upon one another to mix the colors.
In FIG. 6, red LED 2e, green LED 3e, and blue LED ~e are placed on the base of a segment body l5b which is filled with a transparent light scattering material 16. Red LEDs are typically manufactured by diffusing a p-n junction into a GaAsP epitaxial layer on a GaAs substrate; green LEDs typically use a GaP epitaxial layer on a GaP substrate; blue LEDs are typically made from SiC material.
When forwardly biased, LEDs 2e, 3e, and ~le emit light signals of red, green, and blue colors, respectively, which are scattered within transparent material 16, thereby blending the red, green, and blue light signals into a ~ ~ S~ ~ ~ 6 composite light signal that emerges at the upper surface of segment body 15b. The color of the composite light signal may be controlled by varying the portions of the red, green, and blue light signals.
In FIG. 7 is shown a schematic diagram of a 2-primary color common cathodes 7-segment display element 42 which can selectively display various digital fonts in different colors on display segments a, b, c, d, e9 f, g, and DP
(Decimal Point). The anodes of all red and green LED pairs ~0 are interconnected in each display segment and are electri.cally connected to respective outputs oE a co~n~ercially we~L known common-cathode 7-segln~nt cl~coder driver 23. The cathodes of all red LEDs 2a, 2b, 2c, 2d, 2e, 2f, 2g, and 2i are interconnected to a common electric path referred to as a red bus 5. The cathodes of all green LEDs 3a, 3b, 3c, 3d, 3e, 3f, 3g, and 3i are interconnected to a like common electric path referred to as a green bus 6.
The red bus 5 is connected to the output of a tri-state inverting buffer 63a, capable of sinking sufficient current to forwardly bias all red LEDs 2a to 2i in display element 42. The green bus 6 is connected to the output of a like buffer 63b. The two buffers 63a and 63b can be simultaneously enabled by applying a low logic level signal to the input of inverter 64a, and disabled by applying a high logic level signal thereto. When buffers 63a and 63b are enabled, the conditions of red bus 5 and green bus 6 can be selectively controlled by applying suitable logic control signals to the bus control inputs RB (red bus) and GB
(green bus), to illuminate display element ~2 in a selected color. When buffers 63a and 63b are disabled, both red ~'~S'~Z~6 bus 5 and green bus 6 are effectively disconnected to cause display element 42 to be completely extinguished.
In FIG. 8 is shown a schematic diagram of a 3-primary color common anodes 7-segment display element 43 which can selectively display digital fonts in different colors.
The cathodes of all red, green, and blue LED triads in each display segment are interconnected and electrically connected to respective outputs of a commercially well known common anode 7-segment decoder driver 24. The anodes of all red LEDs 2a, 2b, 2c, 2d, 2e, 2f, and 2g are interconnected to Eorm a common electric path reEerred to as a red bus 5. The anocles of al:l green ~EDs 3a, 3b, 3c, 3d, 3e, 3E, and 3g are interconnected to form a like common electric path referred to as a green bus 6. The anodes of all blue LEDs 4a, 4b, 4c, 4d, 4e, 4f, and 4g are interconnected to form a like common electric path referred to as a blue bus 7.
The red bus 5 is connected to the output of a non-inverting tri-state buffer 62a, capable of sourcing sufficient current to illuminate all red LEDs 2a to 2g in display element 43. The green bus 6 is connected to the output of a like buffer 62b. The blue bus 7 is connected to the output of a like buffer 62c. The three buffers 62a, 62b, and 62c can be simultaneously enabled, by applying a low logic level signal to the input of inverter 64b, and disabled by applying a high logic level signal thereto.
When buffers 62a, 62b, and 62c are enabled, the conditions of red bus 5, green bus 6, and blue bus 7 can be selectively controlled by applying valid combinations of logic level signals to the bus control inputs RB (red bus), }6 GB (green bus), and BB (blue bus), to illuminate display element 43 in a selected color. When buffers 62a, 62b, and 62c are disabled, red bus 5, green bus 6, and blue bus 7 are effectively disconnected to cause display ele~ent 43 to be completely extinguished.
2'Z36 STEP VARIABLE COLOR CONTROL
The operation of display element 42 shown in FIGo 7 will be now explained by the example of illuminating a digit 171 in three different colors. A simplified schematic diagram to facilitate the explanation is shown in FIG~ 9~ ~ny digit between O and 9 can be selectively displayed by applying the appropriate BCD code to the inputs AO, Al, A2, and A3 of common-cathode 7-segment decoder driver 23. The decoder driver 23 develops at its outputs a, b, c, d, e, f, g, and DP drive signals for energizing selected groups oE the segments to thereby visually clisplay the sel.ected nwmber, in a mailLler well known ~o those having ordinary skilL :in ~he art. To display decimal number '7', a BCD cocle OLll is applied to the inputs AO, Al, A2, and A3. The decoder driver 23 develops high voltage levels at its outputs a, b, and c, to illuminate e~ually designated segments a, b, and c, and low voltage levels at all remaining outputs (not shown), to extinguish all remaining segments d, e, f, and g.
To illuminate display element ~2 in red color, the color control input R is raised to a high logic level, and the color control inputs Y and G are maintained at a low logic level. As a result, the output of OR gate 60a rises to a high logic level, thereby causing the output of buffer 63a to drop to a low logic level. The current flows from the output a of decoder driver 23, via red LED 2a and red bus 5, to current sinking output of buffer 63a. Similarly, the current flows from the output b of decoder driver 23, via red LED 2b and red bus 5, to the output of buffer 63a. The current flows from the output c of decoder driver 23, via ~ ~ S~ ~ ~ 6 red LED 2c and red bus 5, to the output of buffer 63a. As a result, segments a, b, and c illuminate in red color, thereby causing a visual impression of a character '7'. The green LEDs 3a, 3b, 3c remain extinguished because the output of buffer 63b is at a high logic level, thereby disabling green bus 6.
To illuminate display element 42 in green color, the color control input G is raised to a high logic level, while the color control inputs R and Y are maintained at a low logic level. As a result, the output of OR gate 60b rises to a high logic level, thereby causing the output of buffer 63b to drop to a low log:ic level. Tlle cur~ent El.ows frorn the output a of decoder driver 23, via green LED 3a and green bus 6, to current sinking output of buffer 63b.
Similarly, the current flows from the output b of decoder driver 23, via green LED 3b and green bus 6, to the output of buffer 63b. The current flows from the output c of decoder driver 23, via green LED 3c and green bus 6, to the output of buffer 63b. As a result, segments a, b, and c illuminate in green color. The red LEDs 2a, 2b, and 2c remain extinguished because the output of buffer 63a is at a high logic level, thereby disabling red bus 5.
To illuminate display element 42 in yellow color, the color control input Y is raised to a high logic level, while the color inputs R and G are maintained at a low logic level. As a result, the outputs of both OR gates 60a and 60b rise to a high logic level~ thereby causing the outputs of both buffers 63a and 63b to drop to a low logic level. The current flows from the output a of decoder driver 23, via red LED 2a and red bus 5, to current sinking output of ~S;2~6 buffer 63a, and, via green LED 3a and green bus 6, to current sinking output of buffer 63b. Similarly, the current flows from the output b of decoder driver 23, via red LED 2b and red bus 5, to the output of buffer 63a, and, via green LED 3b and green bus 6, to the output of buffer 63b. The current flows from the output c of decoder driver 23, via red LED 2c and red bus 5, to the output of buffer 63a, and, via green LED 3c and green bus 6, to the output of buffer 63b. As a result of blending light of red and green colors in each segment, segments a, b, and c il:luminate in substantially yellow color.
The operation oE dlsplay element ~3 shown in FlG. 8 w:ilL
be now explained by the example of illuminating a digit '1 r in seven different colors. A simplified schematic diagram to facilitate the explanation is shown in FIG. 10. To display decimal number '1', a BCD code 0001 is applied to the inputs AO, Al, A2, and A3 of common anode 7-segment decoder driver 24. The decoder driver 24 develops low voltage levels at its outputs b and c, to illuminate equally designated segments b and c, and high voltage levels at all remaining outputs (not shown), to extinguish all remaining segments a, d, e, f, and g.
To illuminate display element 43 in red color, the color control input R is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the ou-tput of OR gate 61a rises to a high logic level, thereby causing -the output of buffer 62a to rise to a high logic level. The current flows from the output of buffer 62a, via red bus 5 and red LED 2b, -to the output b of decoder driver 2~, and, via red LED 2c, to ~2~ 236 the output c of decoder driver 24. As a result, segments b and c illuminate in red color, thereby causing a visual impression of a character '1'. The green LEDs 3b, 3c and blue LEDs 4b, 4c remain extinguished because green bus 6 and blue bus 7 are disabled.
To illuminate display element 43 in green color, the color control input G is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the output of OR gate 61b rises to a high logic level, thereby causing the output of buffer 62b to rlse to a hlgh logic level. The current Elows ~rom the output o~ bufEer 62b, via green bus 6 and green LED
3b, to the output b of decoder driver 24, and, v:ia green LED
3c, to the output c of decoder driver 24. As a result, segments b and c illuminate in green color.
To illuminate display element ~3 in blue color, the color control input B is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the output oE OR gate 61c rises to a high logic level, thereby causing the output of buEfer 62c to rise to a high logic level. The current flows from the output of buffer 62c, via blue bus 7 and blue LED 4b, to the output b of decoder driver 24, and, via blue LED 4c, to the output c of decoder driver 24. As a result, segments b and c illuminate in blue color.
To illuminate display element 43 in yellow color, the color control input Y is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the outputs of OR gates 61a and 61b rise to a high logic level, thereby causing the outputs 1~
~;?,Z36 of buffers 62a and 62b to rise to a high logic level. The current flows from the output of buffer 62a, via red bus 5 and red LED 2b, to the output b of decoder driver 24 9 and, via red LED 2c, to the output c of decoder driver 24. The current also flows from the output of buffer 62b, via green bus 6 and green LED 3b, to the output b of decoder driver 24, and, via green LED 3c, to the output c of decoder driver 24. As a result of blending light of red and green colors in each segment, the segments b and c illuminate in substantially yellow color.
To illuminate clisplay element 43 in purple co:lor, the col.or con~roL inp~lt P :is raised to a high logLc LeveL, while all remaining color control inputs are maintained at a low logic level. As a result, the outputs of OR gates 61a and 61c rise to a high logic level, thereby causing the outputs of buffers 62a and 62c to rise to a high logic level. The current flows from the output of buffer 62a, via red bus 5 and red LED 2b, to the output b of decoder driver 24, and, via red LED 2c, to the output c of decoder driver 24. The current also flows from the output of buffer 62c, via blue bus 7 and blue LED 4b, to the output b of decoder driver 24, and, via blue LED 4c, to the output c of decoder driver 24. As a result of blending light of red and blue colors in each segment, segments b and c illuminate in substantially purple color.
To illuminate display element 43 in blue-green color, the color control input BG is raised to a high logic level, while all remaining color control inputs are maintained at a low logic level. As a result, the outputs of OR gates 61b and 61c rise to a high logic level, thereby causing the outputs of buffers 62b and 62c to rise to a high logic level. The current flows from the output of buffer 62b, via green bus 6 and green LED 3b~ to the output b of decoder driver 24, and, via green LED 3c, to the output c of decoder driver 24. The current also flows from the output of buffer 62c, via blue bus 7 and blue LED 4b, to the output b of decoder driver 24, and, via blue LED 4c, to the output c of decoder driver 24. As a result of blending light of green and blue colors in each segment, segments b and c il:Luminate in substantially blue-green color.
To ilLuminate display element 43 in white coLor, the color co[~troL input W is raised to a high logic LeveL, while all remaining color control inputs are maintained at a low logic level. As a result, the outputs of OR gates 61a, 61b, and 61c rise to a high logic level, thereby causing the outputs of respective buffers 62a, 62b, and 62c to rise to a high logic level. The current flows from the output of buffer 62a, via red bus 5 and red LED 2b, to the output b of decoder driver 24, and, via red LED 2c, to the output c of decoder driver 24. The current also flows from the output of buffer 62b, via green bus 6 and green LED 3b, to the output b of decoder driver 24, and, via green LED 3c, to the output c of decoder driver 24. The current also flows from the output of buffer 62c, via blue bus 7 and blue LED 4b, to the output b of decoder driver 24, and, via blue LED 4c, to the output c of decoder driver 24. As a result of blending light of red, green, and blue colors in each segment, segments b and c illuminate in substantially white color.
Since the outputs of decoder driver 24 may be overloaded ~;2S2~6 by driving a triad of LEDs in parallel in display element 43, rather than a single LED in a monochromatic display 9 it would be obvious to employ suitable buffers to drive respective color display segments (not shown).
To illustrate how the present invention can be utilized in a multi-element variable color display configuration, in FIG. 11 is shown a detail of the interconnection in a 2-primary color 4-digit display having display segments la, l'b, lc, and ld arranged in a 7-segment font. The color control inputs R, Y, and G of color controls 52a, 52b, 52c, and 52d of aLl display el.ements 46a, 46'b, 46c, and 46cl are interconnecte(l, respect:ively, ancl enable inputs El, E2, E3, and E4 are used to control the conditions of respective display elements 46a, 46b, 46c, and 46d. A high logic level at the enable input E extinguishes the particular display element 46a, 46b, 46c, or 46d; a low logic level therein illuminates display element 46a, 46b, 46c, or 46d in a color determined by the instant conditions of the color control inputs R, Y, and G.
In FIG. 12 is shown a like detail of the interconnection in a 3-primary color 4-digit display having display segments la~ lb, lc, and ld arranged in a 7-segment font. Similarly, the color control inputs B, P, BG, G, Y, ~, and R of color controls 53a, 53b, 53c, and 53d of all display elements 47a, 47b, 47c, and 47d are interconnected, and the conditions of respective display elements 47a, 47b, 47c, and 47d are controlled by enable inputs El, E2, E3, and E4. A high logic level at the enable input E extinguishes the particular display element 47a, 47'b, 47c, or 47d; a low logic level therein illuminates display element 47a, 47b, ~5~6 47c, or 47d in a color determined by the instant conditions of the color control inputs B, P, BG, G, Y, W, and R.
The exemplary color control circuits described herein will cooperate equally well with a multi-element variable color display constructed either in common cathodes or in common anodes configuration.
~;~S2~6 CONTINUOUSLY VARIABLE COLOR CONVERTER
The display system shown in FIG. 13 utilizes a scaling circuit 80a which scales input analog voltage levels to a voltage range suitable for an A/D converter 74a, which in turn develops at its outputs a digital code having relation to the value of the input analog voltage. The output lines of A/D converter 74a are connected to the address inputs of a memory 76 having a plurality of addressable locations which contai.n data indicating the portions of red color for several diEEerent values of the input analog voltage. The output data oE memory 76 are appliecl to the inputs of a color converter 57 which will develop control signals for red bus 5 and green bus 6, respectively 7 of variable color display element 42.
The display system shown in FIG. 14 utilizes a scaling circuit 80b and an A/D converter 74b for converting the instant value of an input analog voltage to a digital code.
The outputs of A/D converter 74b are connected, in parallel, to the address inputs of memory 76a, which contains data lndicating the portions of red color, to the address inputs of memory 76b, which contains data indicating the portions of green color, and to the address inputs of memory 76c, which contains data indicating the portions of blue color. The output data of memory 76a are applied to red color CQnverter 59a which will develop control signals for red bus 5 of variable color display element 43. The output data of memory 76b are applied to green color converter 59b which will develop control signals for green bus 6 of display element 43. The output data of ;22;~6 memory 76c are applied to blue color converter 59c which will develop control signals for blue bus 7 of display element 43.
FIG. 15 is a schematic diagram of a scaling circuit capable of shifting and amplifying the input voltage levels.
The circuit utilizes two operational amplifiers 81a and 81b in a standard inverting configuration. The amplifier 81a is set for a unity gain by using resistors 90a and 90b of equal values; potentiometer 92a is adjusted to set a desired offset voltage. The amplifier 81b sets the gain by adjusting feedback potentiometer 92b to a desired value with respect to resistor 90c. ~s a res~Lt, an input vo:ltage, wh:icll ~lay vary between arbitrary limits Vlow and Vhigh, may be scaled and shifted to the range between 0 Volts and 9.961 Volts, to facilitate the use of a commercially available A/D
converter.
FIG. 16 is a schematic diagram of an A/D (analog-to-digital) converter 75 which is capable of converting input analog voltage, applied via resistor 90e to its input Vin~
to 8~bit digital data for addressing a memory 77. The conversion may be initiated from time to time by applying a short positive pulse 99a to the Blank and Convert input B&C.
A/D converter 75 will thereafter perform a conversion of the instant input voltage to 8-bit data indicative of its value.
When the conversion is completed, the Data Ready oukput DR drops to a low logic level, thereby indicating that the data are available at the outputs Bit :L to Bit 8, which are directly connected to respective address inputs A0 to A7 of memory 77. When the DR output drops to a low :Logic level, the Chip Select input CS of memory 77 is activatedS memory l'~S;~2~
77 is enabled, and the data, residing at the address selected by the instant output of A/D converter 75, will appear at its data outputs D0 to D7.
The description of the schematic diagram in FIG. 17 should be considered together with its accompanying timing diagram shown in FIG. 18. A clock signal 99b of a suitable frequency (e. g., 10 kHz), to provide a flicker-free display, is applied to the Clock Pulse inputs CP of 8-bit binary counters 71e and 71f to step them down. At the end :lO of each counter cycle, which takes 256 clock cycles to compLete, the Terminal Count output TC oE counter 7:Le drops to a low :Log:ic level Eor one clock cycle, to thereby indicate that the lowest count was reached. The negative pulse ~9c at the TC output of counter 71e, which is connected to the Parallel Load input PL of counter 71f, causes the instant data at the outputs of memory 76 to be loaded into counter 71f. The data at memory 76 represent the portion of red color; the portion of green color is complementary. The rising edge of the TC pulse 99c triggers flip-flop 73 into its set condition wherein its output Q
rises to a high logic level.
The counter 71f will count down, from the loaded value, until it reaches zero count, at which moment its TC output drops to a low logic level. The negative pulse at the TC
output of counter 71f, which is connected to Clear Direct input CD of flip-flop 73, causes the latter to be reset and to remain in its reset condition until it is set again at the beginning of the next 256-count cycle. It is thus obvious that the Q output of flip-flop 73 is at a high logic level for a period of time proportional to the data ~s~
initially loaded into counter 71f. The complementary output Q is at a high logic level for a complementary period of time.
The Q and Q outputs of flip-flop 73 are connected to red bus 5 and green bus 6, respectively, via suitable buffers 63a and 63b, shown in detail in FIG. 7, to respectively energize red bus 5 and green bus 6 for variable time periods, depending on the data stored in memory 76.
By referring now, more particularly 9 to the timing diagram shown in FCG. 18, in which the waveforms are compressecl to Eacilitate the llLustration, the EXA~P~t,F :L
cons:iders the memory cl~lt~l 'FD', in a stanclarcl hexaclecimal notation, to generate light of substantially red color. At the beginning of the counter cycle, pulse 99c loads data 'FD' into counter 71f. Simultaneously, flip-flop 73 is set by the rising edge of pulse 99c. The counter 71f will be thereafter stepped down by clock pulses 99b, until it reaches zero count, 2 clock cycles before the end of the counter cycle. At that instant a short negative pulse 99d is produced at its output TC to reset flip-flop 73, which will remain reset for 2 clock cycles and will be set again by pulse 99c at the beginning of the next counter cycle, which will repeat the process. It is readily apparent that flip-flop 73 was set for 254 clock cycles, or about 99% of the time, and reset for 2 clock cycles, or about 1% of the time. According]y, red bus 5 of display element 42 is energized for about 99% of the time, and green bus 6 is energized for the remaining about 1% of the time. As a result, display element 42 illuminates in substantially red color.
~ ~ 5~ Z ~ 6 The EXAMPLE 2 considers the memory data '02' (HEX~ to generate light of substantially green color. At the beginning of the counter cycle, data '02' are loaded into counter 71f, and, simultaneously, flip-flop 73 is set. The counter 71f will count down and will reach zero count after 2 clock cycles. At that instant it produces at its output TC a negative pulse 99e to reset flip-flop 73. It is readily apparent that flip-flop 73 was set for 2 clock cycles, or about 1% of the time, and reset for 254 clock cycles, or about 99% of the time. Accordingly, red bus 5 of display element 42 is energized Eor about 1 % of the time, and green bus 6 is ener~ized Eor the remaining about 99% of the time. As a result, display element ~2 illuminates in substantially green color.
The EXAMPLE 3 considers the memory data '80' ~HEX) to generate light of substantially yellow color. At the beginning of the counter cycle, data '80' are loaded into counter 71f~ and, simultaneously, flip-flop 73 is set. The counter 71f will count down and will reach zero count after 128 clock cycles. At that instant it produces at its output TC a negati~e pulse 99f to reset flip-flop 73.
It is readily apparent that flip-flop 73 was set for 128 clock cycles, or about 50% of the time, and reset for 12~
clock cycles, or about 50% of the time. Accordingly, red bus 5 of display element 42 is energized for about 50% of the time, and green bus 6 is energized for the remaining about 50% of the time. As a result of blending substantially equal portions of red and green colors, display element 42 illuminates in substantially yellow color.
The description of the schematic diagram of a 3-LED color 2~
converter in FIG. 19 should be considered together with its accompanying timing diagrams shown in FIGS. 20 and 21. A
clock signal 99b is applied to the CP inputs of counters 71d, 71a, 71b, and 71c to step them down. Every 256 counts a negative pulse 99c is generated at the TC output of counter 71d, to load data into counters 71a, 71b, and 71c from respective memories 76a, 76b, and 76c, and to set flip flops 73a, 73b, and 73c. The data in red memory 76a represent the portions of red color, the data in green memory 76b represent the portions of green color, and the data in blue memory 76c represent the portions of bl~le color to be bLended.
The counters 71a, 71b7 and 71c will count down, from the respective loaded values, until zero counts are reached.
When the respective values of the loaded data are different, the length of time of the count-down is different for each counter 71a, 71b, and 71c. When a particular counter 71a, 71b, or 71c reaches zero count, its TC output momentarily drops to a low logic level, to reset its associated flip-flop (red counter 71a resets its red flip-flop 73a, green counter 71b resets its associated green flip-flop 73b, and blue counter 71c xesets its associated blue flip-flop 73c).
Eventually, all three flip-flops 73a, 73b, and 73c will be reset. The Q outputs of flip-flops 73a, 73b, and 73c are connected to red ~us 5, green bus 6, and blue bus 7, respectively, via suitable buffers 62a, 62b, and 62c, as shown in FIG. ~, to respectively energize red bus 5, green bus 6, and blue bus 7 for variable periods of time.
By referring now more particularly to the timing diagram shown in FIGS. 20 and 21, the EXAMPLE 4 considers red ~ ~ S~ 3 6 memory data '80', green memory data lool, and blue memory data '80', all in hexadecimal notation, to generate light of substantially purple color. At the beginning of the counter cycle, the pulse 99c simultaneously loads data '80' from red memory 76a into red counter 71a, data '00' from green memory 76b into green counter 71b, and data '80' from blue memory 76c into blue counter 71c. The counters 71a, 71b, and 71c will be thereafter stepped down. The red counter 71a will reach its zero count after 128 clock cycles; green counter 71b will reach its zero count irnmediately; blue counter 71c will reach its zero count after 128 clock cycles.
~ t is reaclily apparent that red 11p-flop 73a was set for 128 clock cycles, or about 50% of the time, green flip-flop 73b was never set, and blue flip-flop 73c was set for 128 clock cycles, or about 50% of the time. Accordingly, red bus 5 of display element 43 :is energized for about 50% of the time, green bus 6 is never energized, and blue bus 7 îs energized for about 50% of the time. As a result of blending substantially equal portions of red and blue colors, display element 43 illuminates in substan-tially purple color.
The EXAMPLE 5 considers red memory data '00', green memory data '80', and blue memory data '80', to generate light of substantially blue-green color. At the beginning of the counter cycle, data '00' are loaded into red counter 71a, data '80' are loaded into green counter 71b, and data '80' are loaded into blue counter 71c. The red counter 71a will reach its zero count immediately, green counter 71b will reach its zero count after 128 clock periods, and so ~2~;~2;~6 will blue counter 71c.
The red flip-flop 73a was never set, green flip-flop 73b was set for 128 clock pulses, or about 50% of the time, and so was blue flip-flop 73c. Accordingly, green bus 6 of display element 43 is energized for about 50% of the time, and so is blue bus 7. As a result, display element 43 illuminates in substantially blue-green color.
The EXAMPLE 6 considers red memory data '40', green memory data '40', and blue memory data '80', to generate light oE substantially cyan color. At the beginning of the counter cycle, the data '40' are loaded into red counter 71a, data '40' ~re loaded into green counter 7:Lb, ancl data '80' are Loaded into blue counter 71c. The red counter 71a will reach its zero count after 64 clock cycles, and so will green counter 71b. The blue counter 71c will reach its zero count after 128 clock cycles.
The red flip-flop 73a was set for 64 clock cycles, or about 25% of the time, and so was green Elip-flop 73b.
The blue Elip-flop 73c was set for 128 clock cycles, or about 50% of the time. Accordingly, red bus 5 and green bus 6 of display element 43 are energized for about 25% of the time, and blue bus 7 is energized for about 50% of the time. As a result of blending about 50% of blue color, 25%
of red color, and 25% of green color, display element 43 illuminates in substantially cyan color.
The EXAMPLE 7 considers red memory data '80', green memory data '40', and blue memory data '40', to generate light of substantially magenta color. At the beginning of the counter cycle, the data '80' are loaded into red counter 71a, data '40' are loaded into green counter 71b, 1~52;~3~
and data '40' are loaded into blue counter 71c. The red counter 71a will reach its zero count after 128 clock cycles, green counter 71b will reach its zero count after 64 clock cycles, and so will blue counter 71c.
The red flip-flop 73a was set for 128 clock cycles, or about 50% of the time, green flip-flop 73b and blue flip-flop 73c were set for 64 clock cycles, or about 25% of the time. Accordingly, red bus 5 of display element 43 is energized for about 50% of the time, green bus 6 and blue bus 7 are energized for about 25% of the time. As a result, display element 43 illuminates in substantially magenta color.
By referring now more particularly to FIGS. 22 and 23, which are graphic representations of TABLES l and 2, respectively, the data at each memory address are digital representation of the portion of the particular primary color. All examples consider an 8-bit wide PROM
(Programmable Read Only Memory). However, the principles of the invention couLd be applied to other types of memories.
In FIG. 22, RED PORTION indicates the portion of red primary color; GREEN PORTION indicates the portion of green primary color. The RED PORTION for a particular memory address was calculated by dividing the actual value of data residing at that address by the maximum possible data 'FF' (HEX). The GREEN PORTION for the same memory address is complementary; it was obtained by subtracting the calculated value of the RED PORTION from number 1Ø
In FIG. 22 is shown the characteristic of a 2-primary color converter, defined in TABLE 1, for developing color variable in steps: pure green for input voltages less than ~25i2~
0.625 V, substantially yellow for voltages between 1.25 V
and 1.875 V, pure red for voltages between 2.5 V and 3.125 V, and of intermediate colors therebetween, this sequence being repeated three times over the voltage range.
In FIG. 23, RED PORTION indicates the portion of red primary color; GREEN PORTION indicates the portion of green primary color; BLUE PORTION indicates the portion of blue primary color. The RED PORTION for a particular memory address was calculated by dividing the value of red data residing at such address by the maximum possible data 'FF' (HEX). Similarly, the GREEN PORrrLON Eor that memory adclress was obtalnecl by clividing the value o green data by 'FF' (HEX). rrhe BLUE PORTION was obtained by dividing the value of blue data by 'FF' (HEX).
In FIG. 23 is shown the characteristic of a 3-primary color converter, defined in TABLE 2, for developing color continuously variable from pure red, through substantially orange and yellow, pure green, pure blue, to substantially purple, in a rainbow-like fashion.
In the examples of the characteristics of color converters shown in TABLE l and TABLE 2, the data values stored in red memory 76a, green memory 76b, and blue memory 76c are so designed that the sums of the red data, green data, and blue data are constant for all memory addresses, to provide uniform light intensities for all colors. It is further contemplated -that data stored in red memory 76a, green memory 76b, and blue memory 76c may be modified in order to compensate for different efficiencies of red, green, and blue LEDs. By way of an example, data values for a low efficiency LED may be proportionally incremented such ~5Z~36 that time of energization is proportionally increased, to effectively provlde equal luminances for LEDs of unequal efficiencies.
With reference to FIG. 24 there is shown the ICI
(International Committee on Illumination) chromaticity diagram designed to speciy a particular color in terms of x and y coordinates. Pure colors are located along the horseshoe-like periphery. Reference numbers along the periphery indicate wavelength in nanometers. When relative portions of three primary colors are known, the color of light prod-1ced by blending the:ir em:issions can be determined by examining tlle x and y val~les of :CC[ coorclinat~!s.
~252'~6 COLOR CONTROL SIGNALS
In FIG, 25 is shown a detail o~ a counter and decoder combination for developing color control signals to cause display element 42 to illuminate in one of three possible colors in accordance with the accumulated count. The description of the circuit should be considered together with its associated chart shown in FIG. 26. An 8-bit binary counter 95 contains internal register with outputs QO to Q7 available. Two most significant outputs Q6 and Q7 are connected to respective inputs A and B of a 3-to-8 line decoder 96; the most significant input C of decoder 96 is grounded. In response to conditions oE the co~lnter outputs Q6 ancl Q7, decoder 96 develops output signals YO, Yl, and Y2. When both counter outputs Q6 and Q7 are at a low logic level (which is typical for counts less than 63), the decoder output YO rises to a high logic level to generate active color control signal R (red). When the counter output Q6 rises to a high logic level, while the output Q7 is low (which is typical for counts between 64 and 127), the decoder output Yl rises to a high logic level to generate active color control signal Y (yellow). When the counter output Q7 rises to a high logic level and Q6 drops to a low logic level (which is typical for counts between 128 and 191), the decoder output Y2 rises to a high logic level to generate active color control signal G (green). The decoder outputs YO, Yl, and Y2 may be respectively connected to color control inputs R, Y, and G of display element 42 in FIG. 9.
Although not illustrated, it would be obvious that S2~}6 counter 95 may be incremented by applying suitable clock signals to its CLOCK input and initialized by applying a suitable signal to its CLR input. The accu~lulated count may be transferred to its internal register by applying a suitable signal to the REG CL input.
FIG. 27 is a like detail of a counter and decoder combination for developing color control signals to cause display element 43 to illuminate in one of seven possible colors, depending on the accumulated count. The associated chart is shown in FIG. 28. This circuit difEers from the one shown in F'IG. 25 in that three outputs Q5, Q6, and Q7 o~
counter 95 are connected to respective inputs A~ B, and C o~
decoder 96 to develop color control signals R, W, Y, G, BG, P, and B at respective decoder outputs Yl to Y7. When the counter output Q5 is at a high logic level and Q6, Q7 are low (which is typical for counts between 32 and 63), the decoder output Yl rises to a high logic level to generate active color control signal R (red). When the counter output Q6 is at a high logic level and Q5, Q7 are low (which is typical ~or counts between 64 and 95), the decoder output Y2 rises to a high logic level to generate active color control signal W (white). When the counter outputs Q5, Q6 are at a high logic level and Q7 is low (which is typical for counts between 96 and 127), the decoder output Y3 rises to a high logic level to generate active color control signal Y (yellow). When the counter output Q7 is at a high logic level and Q5, Q6 are low (which is typical for counts between 12~ and 159), the decoder output Y4 rises to a high logic level to generate active color contro:L signal G
(green). When the counter outputs Q5, Q7 are at a high logic level and Q6 is low (which is typical for counts between 160 and 1~1)9 the decoder output Y5 rises to a high logic level to generate active color control signal BG (blue~
green). When the counter outputs Q6, Q7 are at a high logic level and Q5 is low (which is typical for counts between 192 and 223), the decoder output Y6 rises to a high logic level to generate active color control signal P (purple).
When all counter outputs Q5, Q6, ~7 are at a high logic level (which is typical for counts higher than 224), the decoder output Y7 rises to a high logic level to generate active color control signal B (blue). The decoder outputs Y:L, Y2, Y3, Y~, Y5, Y6, and Y7 may be respectively connected to color control :inputs R, W, Y, G, BG, P, and ~3 of di~plfly element 43 in FIG. 10.
It would be obvious that the coLor sequences could be readily changed by differently interconnecting the decoder outputs Y0 to Y7 with color control inputs R to B of display element 43.
In brief summary, a variable color display device was disclosed which includes a plurality of display areas which may be selectively activated in groups to display characters. Each display area includes two light sources for emitting upon activation light signals of respectively different primary colors which are combined therein to obtain a composite light signal of a composite color. Two primary color buses are provided to which the light sources in the display areas for emitting light signals of a first and second primary colors are respectively commonly coupled.
Color control is provided for activating the primary color buses either in selective combinations, for controlling the ~S~236 color of the display device in steps, or for selective time periods, for controlling the color of the display device substantially continuously.
It would be obvious that numerous modifications can be made in the construction of the preferred embodiments shown herein, without departing from the spirit of the invention as defined in the appended claims. It is contemplated that the principles of the invention may be also applied to numerous diverse types of display devices, such are liquid crystal, plasma devices, and the like.
~2S;2Z36 CORRELATION TABLE
This is a correlation table of reference characters used in the drawings herein, their descriptions, and examples of commercially available parts.
# DESCRIPTION EXAMPLE
1 display segment 2 red LED
3 green LED
4 blue LED
red bus 6 green bus 7 blue bus 15 segment body 16 light scattering material 21 display decoder 23 common cathode 7-segment decoder driver 74LS49 24 common anode 7-segment decoder driver 74LS47 40 variable color display 42 variab].e color 7-segment display element (2 LEDs~
43 variable color 7-segment display element (3 LEDs) 46 variable color display element (2 LEDs) 47 variable color display element (3 LEDs) coLor control 51 step variable color control 52 color control (2 LEDs) 53 color control (3 LEDs) 56 continuously variable color converter ~L~S;2~36 # DESCRIPTION EXAMPLE
57 2-primary color converter 59 single color converter 2-input OR gate 74HC32 61 4-input OR gate 4072 62 non-inverting buffer 74LS244 63 inverting buffer 74LS240 64 inverter part of 74LS240,4 71 8-bit counter 74F579 73 D type flip-flop 74HC74 74 A/D converter 75 8-bit A/D converter AD570 76 memory 77 2k x 8 bit PROM 2716 80 scaling circuit 81 op amp LM741 90 resistor 92 potentiometer 95 8-bit counter with register 74HC590 96 3-to-8 line decoder 74HC237 99 pulse ~2~2~6 DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 0.0 00 00 0.0 1.0 0.039 01 00 0.0 1.0 0.078 02 00 0.0 1.0 0.1.17 03 00 0.0 1.0 0.156 04 00 0.0 1.0 0.195 05 00 0.0 1.0 0.234 06 00 0.0 1.0 0.273 07 00 0.0 1.0 0.312 08 00 0.0 1.0 0.352 09 00 0.0 1.0 0.391 0A 00 0.0 1.0 0.430 0B 00 0.0 1.0 0.469 0C 00 0.0 1.0 0.508 OD 00 0.0 1.0 0.547 OE 00 0.0 1.0 0.586 OF 00 0.0 1.0 ~:S22~6 DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 0.625 10 40 0.25 0.75 0.664 1~ 40 0.25 0.75 ().703 12 40 0.25 0.75 0.7~2 13 40 0.25 0.75 0.781 14 40 0.25 0.75 0.820 ~5 40 0.25 0.75 0.859 16 40 0.25 0.75 0.898 17 40 0.25 0.75 0.937 18 40 0.25 0.75 0.977 19 40 0.25 0.75 1.016 lA 40 0.25 0.75 1.055 lB 40 0.25 0.75 1.094 lC 40 0.25 0.75 1.133 lD 40 0.25 0.75 1.172 lE 40 0.25 0.75 1.211 lF 40 0.25 0.75 ~2~
DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex~
1.250 20 80 0.5 O.S
1.289 21 80 0.5 0.5 1.328 22 80 0.5 0.5 ~.367 23 80 0.5 0.5 10 1.406 24 80 0.5 0.5 1.445 25 80 0.5 0.5 1.484 26 80 0.5 0.5 1.523 27 80 0.5 0.5 1.562 28 80 0.5 0.5 1.~02 29 80 0.5 0.5 1.641 2A 80 0.5 0.5 1.680 2B 80 0.5 0.5 1.719 2C 80 0.5 0.5 1.758 2D 80 0~5 0.5 20 1.797 2E 80 0.5 0.5 1.836 2F 80 0.5 0.5 ~ZS2~
DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 1.875 30 CO 0.75 0.25 1.914 3~ CO 0.75 0.25 1.953 32 CO 0.75 0.25 1.992 33 CO 0.75 0.25 2.031 34 CO 0.75 0.25 2.070 35 CO 0.75 0.25 2.109 36 CO 0.75 ~.25 2.148 37 CO 0.75 0.25 2.187 38 CO 0.75 0.25 2.227 39 CO 0.75 0.25 2.266 3A CO 0.75 0.25 2.305 3B CO 0.75 0.25 2.344 3C CO 0.75 0.25 2.389 3D CO 0.75 0.25 2.422 3E CO 0.75 0.25 2.461 3F CO 0.75 0.25 ~L;2S;22;:~
DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 2.500 40 FF 1.0 0.0 2.539 41 FF 1.0 0.0 2.578 42 FF 1.0 0.0 2.617 43 FF 1.0 0.0 2.656 44 FF 1.0 0.0 2.695 45 FF 1.0 0.0 2.734 46 FF 1.0 0.0 2.773 47 FF 1.0 0.0 2.812 48 FF 1.0 0.0 2.852 49 FF 1.0 0.0 2.891 4A FF 1.0 0.0 2.930 4B FF 1.0 0.0 2.969 4C FF 1.0 0.0 3.008 4D FF 1.0 0.0 3.047 4E FF 1.0 0.0 3.086 4F FF 1.0 0.0 23~
DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 3.125 50 00 0.0 1.0 3.164 51 00 O.Q 1.0 3.203 52 00 0.0 1.0 3.2~2 53 00 0.0 1.0 3.281 54 00 0.0 1.0 3.320 55 00 0.0 1.0 3.359 56 00 0.0 1.0 3.398 57 00 0.0 1.0 3.437 58 00 0.0 1.0 3.477 59 00 0.0 1.0 3.516 5A 00 0.0 1.0 3.555 5B 00 0.0 1.0 3.59~ 5~ 00 0.0 1.0 3.633 5D 00 0.0 1.0 3.672 5E OO O.O 1.0 3.711 5F 00 0.0 1.0 ~1 ~2S2Z~6 DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 3.750 60 40 0.25 0.75 3.789 61 40 0.25 0.75 3.8~8 62 40 0.25 0.75 3.867 63 40 0.25 0.75 3.906 6~ 40 0.25 0.75 3.945 65 40 0.25 0.75 3.984 66 40 0.25 0.75 4.023 67 40 0.25 0.75 4.062 68 40 0.25 0.75 4.102 69 40 0.25 0.75 4.141 6A 40 0.25 0.75 4.178 6B 40 0.25 0.75 4.219 6C 40 0.25 0.75 4.258 6D 40 0.25 0.75 4.299 6E 40 0.25 0.75 4.336 6F 40 0.25 0.75 ~;252;~6 DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex~ (Hex~
4.375 70 80 0.5 0.5 4.414 71 80 0.5 0.5 ~.4S3 7~ 80 0.5 0.5 4.~92 73 80 0.5 0.5 4.531 74 80 0.5 0.5 4.570 75 80 0.5 0.5 4.609 76 80 0.5 0.5 4.648 77 80 0.5 0.5 4.687 78 80 0.5 0.5 ~.727 79 80 0.5 0.5 4.766 7A 80 0.5 0.5 4.805 7B 80 0.5 0.5 4.844 7C 80 0.5 0.5 4.883 7D 80 0.5 0.5 4.922 7E 80 0.5 0.5 4.961 7F 80 0.5 0.5 ~2~ 6 DATA PORTIONS
Input PROM 'Red 7 red green Voltage Address PROM
(Volts) (Hex) ~Hex)
red bus 6 green bus 7 blue bus 15 segment body 16 light scattering material 21 display decoder 23 common cathode 7-segment decoder driver 74LS49 24 common anode 7-segment decoder driver 74LS47 40 variable color display 42 variab].e color 7-segment display element (2 LEDs~
43 variable color 7-segment display element (3 LEDs) 46 variable color display element (2 LEDs) 47 variable color display element (3 LEDs) coLor control 51 step variable color control 52 color control (2 LEDs) 53 color control (3 LEDs) 56 continuously variable color converter ~L~S;2~36 # DESCRIPTION EXAMPLE
57 2-primary color converter 59 single color converter 2-input OR gate 74HC32 61 4-input OR gate 4072 62 non-inverting buffer 74LS244 63 inverting buffer 74LS240 64 inverter part of 74LS240,4 71 8-bit counter 74F579 73 D type flip-flop 74HC74 74 A/D converter 75 8-bit A/D converter AD570 76 memory 77 2k x 8 bit PROM 2716 80 scaling circuit 81 op amp LM741 90 resistor 92 potentiometer 95 8-bit counter with register 74HC590 96 3-to-8 line decoder 74HC237 99 pulse ~2~2~6 DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 0.0 00 00 0.0 1.0 0.039 01 00 0.0 1.0 0.078 02 00 0.0 1.0 0.1.17 03 00 0.0 1.0 0.156 04 00 0.0 1.0 0.195 05 00 0.0 1.0 0.234 06 00 0.0 1.0 0.273 07 00 0.0 1.0 0.312 08 00 0.0 1.0 0.352 09 00 0.0 1.0 0.391 0A 00 0.0 1.0 0.430 0B 00 0.0 1.0 0.469 0C 00 0.0 1.0 0.508 OD 00 0.0 1.0 0.547 OE 00 0.0 1.0 0.586 OF 00 0.0 1.0 ~:S22~6 DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 0.625 10 40 0.25 0.75 0.664 1~ 40 0.25 0.75 ().703 12 40 0.25 0.75 0.7~2 13 40 0.25 0.75 0.781 14 40 0.25 0.75 0.820 ~5 40 0.25 0.75 0.859 16 40 0.25 0.75 0.898 17 40 0.25 0.75 0.937 18 40 0.25 0.75 0.977 19 40 0.25 0.75 1.016 lA 40 0.25 0.75 1.055 lB 40 0.25 0.75 1.094 lC 40 0.25 0.75 1.133 lD 40 0.25 0.75 1.172 lE 40 0.25 0.75 1.211 lF 40 0.25 0.75 ~2~
DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex~
1.250 20 80 0.5 O.S
1.289 21 80 0.5 0.5 1.328 22 80 0.5 0.5 ~.367 23 80 0.5 0.5 10 1.406 24 80 0.5 0.5 1.445 25 80 0.5 0.5 1.484 26 80 0.5 0.5 1.523 27 80 0.5 0.5 1.562 28 80 0.5 0.5 1.~02 29 80 0.5 0.5 1.641 2A 80 0.5 0.5 1.680 2B 80 0.5 0.5 1.719 2C 80 0.5 0.5 1.758 2D 80 0~5 0.5 20 1.797 2E 80 0.5 0.5 1.836 2F 80 0.5 0.5 ~ZS2~
DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 1.875 30 CO 0.75 0.25 1.914 3~ CO 0.75 0.25 1.953 32 CO 0.75 0.25 1.992 33 CO 0.75 0.25 2.031 34 CO 0.75 0.25 2.070 35 CO 0.75 0.25 2.109 36 CO 0.75 ~.25 2.148 37 CO 0.75 0.25 2.187 38 CO 0.75 0.25 2.227 39 CO 0.75 0.25 2.266 3A CO 0.75 0.25 2.305 3B CO 0.75 0.25 2.344 3C CO 0.75 0.25 2.389 3D CO 0.75 0.25 2.422 3E CO 0.75 0.25 2.461 3F CO 0.75 0.25 ~L;2S;22;:~
DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 2.500 40 FF 1.0 0.0 2.539 41 FF 1.0 0.0 2.578 42 FF 1.0 0.0 2.617 43 FF 1.0 0.0 2.656 44 FF 1.0 0.0 2.695 45 FF 1.0 0.0 2.734 46 FF 1.0 0.0 2.773 47 FF 1.0 0.0 2.812 48 FF 1.0 0.0 2.852 49 FF 1.0 0.0 2.891 4A FF 1.0 0.0 2.930 4B FF 1.0 0.0 2.969 4C FF 1.0 0.0 3.008 4D FF 1.0 0.0 3.047 4E FF 1.0 0.0 3.086 4F FF 1.0 0.0 23~
DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 3.125 50 00 0.0 1.0 3.164 51 00 O.Q 1.0 3.203 52 00 0.0 1.0 3.2~2 53 00 0.0 1.0 3.281 54 00 0.0 1.0 3.320 55 00 0.0 1.0 3.359 56 00 0.0 1.0 3.398 57 00 0.0 1.0 3.437 58 00 0.0 1.0 3.477 59 00 0.0 1.0 3.516 5A 00 0.0 1.0 3.555 5B 00 0.0 1.0 3.59~ 5~ 00 0.0 1.0 3.633 5D 00 0.0 1.0 3.672 5E OO O.O 1.0 3.711 5F 00 0.0 1.0 ~1 ~2S2Z~6 DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 3.750 60 40 0.25 0.75 3.789 61 40 0.25 0.75 3.8~8 62 40 0.25 0.75 3.867 63 40 0.25 0.75 3.906 6~ 40 0.25 0.75 3.945 65 40 0.25 0.75 3.984 66 40 0.25 0.75 4.023 67 40 0.25 0.75 4.062 68 40 0.25 0.75 4.102 69 40 0.25 0.75 4.141 6A 40 0.25 0.75 4.178 6B 40 0.25 0.75 4.219 6C 40 0.25 0.75 4.258 6D 40 0.25 0.75 4.299 6E 40 0.25 0.75 4.336 6F 40 0.25 0.75 ~;252;~6 DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex~ (Hex~
4.375 70 80 0.5 0.5 4.414 71 80 0.5 0.5 ~.4S3 7~ 80 0.5 0.5 4.~92 73 80 0.5 0.5 4.531 74 80 0.5 0.5 4.570 75 80 0.5 0.5 4.609 76 80 0.5 0.5 4.648 77 80 0.5 0.5 4.687 78 80 0.5 0.5 ~.727 79 80 0.5 0.5 4.766 7A 80 0.5 0.5 4.805 7B 80 0.5 0.5 4.844 7C 80 0.5 0.5 4.883 7D 80 0.5 0.5 4.922 7E 80 0.5 0.5 4.961 7F 80 0.5 0.5 ~2~ 6 DATA PORTIONS
Input PROM 'Red 7 red green Voltage Address PROM
(Volts) (Hex) ~Hex)
5.000 80 CO 0.75 0.25 5.039 81 CO 0.75 0.25 5.078 ~2 CO 0.75 0~25 5.117 83 CO 0.75 0.25 10 5.156 84 CO 0.75 0.25 5.195 85 CO 0.75 0.25 5.234 86 CO 0.75 0.25 5.273 87 CO 0.75 0.25 5.312 88 CO 0.75 0.25 5.352 89 CO 0.75 0.25 5.391 8A CO 0.75 0.25 5.430 8B CO 0.75 0.25 5.469 8C CO 0.75 0.25 5.508 8D CO 0.75 0.25 20 5.547 8E CO 0.75 0.25 5.586 8F CO 0.75 0.25 4~
~L~S22;:~6 DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 5.625 90 FF L.O 0.0 5.664 9:L FF 1.0 0.0 5.703 92 FF l.. O 0.0 5.742 93 FF 1.0 0.0 10 5.781 94 FF 1.0 0.0 5.820 95 FF 1.0 0.0 5.859 96 FF 1.0 0.0 5.898 97 FF 1.0 0.0 5.937 98 FF 1.0 0.0 5.977 99 FF 1.0 0.0
~L~S22;:~6 DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 5.625 90 FF L.O 0.0 5.664 9:L FF 1.0 0.0 5.703 92 FF l.. O 0.0 5.742 93 FF 1.0 0.0 10 5.781 94 FF 1.0 0.0 5.820 95 FF 1.0 0.0 5.859 96 FF 1.0 0.0 5.898 97 FF 1.0 0.0 5.937 98 FF 1.0 0.0 5.977 99 FF 1.0 0.0
6.016 9A FF 1.0 0.0 6.055 9B FF 1.0 0.0 6.094 9C FF 1.0 0.0 6.133 9D FF 1.0 0.0 20 6.172 9E FF 1.0 0.0 6.211 9F FF 1.0 0.0 S~6 DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 6.250 AO 00 0.0 1.0 6.289 Al 00 0.0 1.0 6.328 A2 00 0.0 1.0 6.367 ~3 00 0.0 1.0 6.406 A4 00 0.0 1.0 6.445 A5 00 0.0 1.0 6.484 A6 00 0.0 1.0 6.524 A7 00 0.0 1.0 6.562 A8 00 0.0 1.0 6.602 A9 00 0.0 1.0 6.641 AA 00 0.0 1.0 6.680 AB 00 0.0 1.0 6.719 AC 00 0.0 1.0 6.758 AD 00 0.0 1.0 6.797 AE 00 0.0 1.0 6~836 AF 00 0.0 1.0 ~5~6 DATA PORTIO~S
Input PROM 'P~ed' red green Voltage Address PROM
(Volts) (Hex) (Hex) 6.875 BO 40 0.25 0.75 6.914 Bl 40 0.25 0.75 6.953 B2 40 0.25 0.75 6.992 B3 ~0 0.25 0.75 10 7.031 B4 40 0.25 0.75
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 6.250 AO 00 0.0 1.0 6.289 Al 00 0.0 1.0 6.328 A2 00 0.0 1.0 6.367 ~3 00 0.0 1.0 6.406 A4 00 0.0 1.0 6.445 A5 00 0.0 1.0 6.484 A6 00 0.0 1.0 6.524 A7 00 0.0 1.0 6.562 A8 00 0.0 1.0 6.602 A9 00 0.0 1.0 6.641 AA 00 0.0 1.0 6.680 AB 00 0.0 1.0 6.719 AC 00 0.0 1.0 6.758 AD 00 0.0 1.0 6.797 AE 00 0.0 1.0 6~836 AF 00 0.0 1.0 ~5~6 DATA PORTIO~S
Input PROM 'P~ed' red green Voltage Address PROM
(Volts) (Hex) (Hex) 6.875 BO 40 0.25 0.75 6.914 Bl 40 0.25 0.75 6.953 B2 40 0.25 0.75 6.992 B3 ~0 0.25 0.75 10 7.031 B4 40 0.25 0.75
7.070 B5 40 0.25 0.75 7.109 B6 40 0.25 0.75 7.148 B7 40 0.25 0.75 7.187 B8 40 0.25 0.75 7.227 B9 40 0.25 0.75 7.266 BA 40 0.25 0.75 7.305 BB 40 0.25 0.75 7.344 BC 40 0.25 0.75 7.383 BD 40 0.25 0.75 20 7.422 BE 40 0.25 0.75 7.461 BF 40 0.25 0.75 ~L~S2Z;~i DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 7.500 CO 80 0.5 0.5 7.539 Cl 80 0.5 0.5 7.587 C2 80 0.5 0.5 7.617 C3 80 0.5 0.5 ~0 7.656 C~ 80 0.5 0.5 7.695 C5 80 0.5 0.5 7.734 C6 80 0.5 0.5 7.773 C7 80 0.5 0.5 7.812 C8 80 0.5 0.5 7.852 C9 80 0.5 0.5 7.891 CA 80 0.5 0.5 7.930 CB 80 0.5 0.5 7.969 CC 80 0.5 0.5
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 7.500 CO 80 0.5 0.5 7.539 Cl 80 0.5 0.5 7.587 C2 80 0.5 0.5 7.617 C3 80 0.5 0.5 ~0 7.656 C~ 80 0.5 0.5 7.695 C5 80 0.5 0.5 7.734 C6 80 0.5 0.5 7.773 C7 80 0.5 0.5 7.812 C8 80 0.5 0.5 7.852 C9 80 0.5 0.5 7.891 CA 80 0.5 0.5 7.930 CB 80 0.5 0.5 7.969 CC 80 0.5 0.5
8.008 CD 80 0.5 0.5 8.047 CE 80 0.5 0.5 8.086 CF 80 0.5 0.5 ~5~2~
DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 8.125 DO CO 0.75 0.25 8.164 Dl. C0 0.75 0.25 8.203 D2 C0 0.75 0.25 8.242 D3 C0 0.75 0.25 10 8.281 D4 C0 0.75 0.25 8.320 D5 CO 0.75 0.25 8.359 D6 CO 0.75 0.25 8.398 D7 CO 0.75 0.25 8.437 D8 C0 0.75 0.25 8.477 D9 C0 0.75 0.25 8.516 DA C0 0.75 0.25 8.555 DB C0 0.75 0.25 8.594 DC CO 0.75 0.25 8.633 DD C0 0.75 0.25 20 8.672 DE C0 0.75 0.25 8.711 DF CO 0.75 0.25 ~s~
DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 8.750 EO FF 1.0 0.0 8.789 El FF 1.0 0.0 8.828 E2 ~FF l.O 0.0 8.867 E3 FF 1.0 0.0 8.906 E4 FF 1.0 0.0 8.945 E5 FF 1.0 0.0 8.984 E6 FF 1.0 0.0
DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 8.125 DO CO 0.75 0.25 8.164 Dl. C0 0.75 0.25 8.203 D2 C0 0.75 0.25 8.242 D3 C0 0.75 0.25 10 8.281 D4 C0 0.75 0.25 8.320 D5 CO 0.75 0.25 8.359 D6 CO 0.75 0.25 8.398 D7 CO 0.75 0.25 8.437 D8 C0 0.75 0.25 8.477 D9 C0 0.75 0.25 8.516 DA C0 0.75 0.25 8.555 DB C0 0.75 0.25 8.594 DC CO 0.75 0.25 8.633 DD C0 0.75 0.25 20 8.672 DE C0 0.75 0.25 8.711 DF CO 0.75 0.25 ~s~
DATA PORTIONS
Input PROM 'Red' red green Voltage Address PROM
(Volts) (Hex) (Hex) 8.750 EO FF 1.0 0.0 8.789 El FF 1.0 0.0 8.828 E2 ~FF l.O 0.0 8.867 E3 FF 1.0 0.0 8.906 E4 FF 1.0 0.0 8.945 E5 FF 1.0 0.0 8.984 E6 FF 1.0 0.0
9.023 E7 FF 1.0 0.0 9.062 E8 FF 1.0 0.0 9.102 E9 FF 1.0 0.0 9.141 EA FF 1.0 0.0 9.180 EB FF 1.0 0.0 9.219 EC FF 1.0 0.0 9.258 ED FF 1.0 0.0 9.299 EE FF 1.0 0.0 9.336 EF FF 1.0 0.0 ~S2~
TABLE l DATA PORTIONS
Input PROM iRed' red green Voltage Address PROM
(Volts) (Hex) (Hex) 9.375 FO 00 0.0 l.O
9.414 Fl 00 0.0 l.O
9,~153 F2 00 0.0 l.O
9.492 1i'3 00 0.0 l.O
9.531 F4 00 0.0 l.O
9.570 F5 00 0.0 l.O
9.609 F6 00 0.0 l.O
9.648 F7 00 0.0 l.O
9.687 F8 00 0.0 l.O
9.727 F9 00 0.0 l.O
9.766 FA 00 0.0 l.O
9.805 FB 00 0.0 l.O
9.844 FC 00 0.0 l.O
9.883 FD 00 0~0 l.O
9.922 FE 00 000 l.O
9.961 FF 00 0.0 l.O
~;2S22~
DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green blue Voltage Address PROM PROM PROM
(Volts) (Hex) (Hex) (Hex) (Hex) 0.0 00 FF 00 00 1.0 0.0 0.0 0.039 0l FE 02 00 0.992 0.008 0.0 0.078 02 E'C 04 00 0.984 0.016 0.0 0.117 03 FA 06 00 0.976 0.024 O.O
TABLE l DATA PORTIONS
Input PROM iRed' red green Voltage Address PROM
(Volts) (Hex) (Hex) 9.375 FO 00 0.0 l.O
9.414 Fl 00 0.0 l.O
9,~153 F2 00 0.0 l.O
9.492 1i'3 00 0.0 l.O
9.531 F4 00 0.0 l.O
9.570 F5 00 0.0 l.O
9.609 F6 00 0.0 l.O
9.648 F7 00 0.0 l.O
9.687 F8 00 0.0 l.O
9.727 F9 00 0.0 l.O
9.766 FA 00 0.0 l.O
9.805 FB 00 0.0 l.O
9.844 FC 00 0.0 l.O
9.883 FD 00 0~0 l.O
9.922 FE 00 000 l.O
9.961 FF 00 0.0 l.O
~;2S22~
DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green blue Voltage Address PROM PROM PROM
(Volts) (Hex) (Hex) (Hex) (Hex) 0.0 00 FF 00 00 1.0 0.0 0.0 0.039 0l FE 02 00 0.992 0.008 0.0 0.078 02 E'C 04 00 0.984 0.016 0.0 0.117 03 FA 06 00 0.976 0.024 O.O
10 0.156 04 F8 08 00 0.969 0.031 0.0 0.195 05 F6 OA 00 0.961 0.039 O.0 0.234 06 F4 OC 00 0.953 0.047 0.0 0.273 07 F2 OE 00 0.945 0.055 0.0 0.312 08 F0 10 00 0.937 0.063 0.0 0.352 09 EE 12 00 0.930 0.070 0.0 0.391 0A EC 14 00 0.922 0.078 0.0 0.430 OB EA 16 OO 0.914 0.086 0.0 0.469 0C E8 18 00 0.906 0.094 0.0 0.508 OD E6 lA OO 0.899 0.101 O.O
20 0.547 0E E4 lC 00 0.891 0.109 O.O
; 0.586 OF E2 lE 00 0.883 0.117 0.0 2~i DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green blue Voltage Address PROM PROM PROM
(Volts) (Hex) (Hex) (Hex) (Hex) 0.625 10 E0 20 00 0.875 0.125 0.0 0.664 lL D~ 22 00 0.867 0.133 0.0 0.703 12 DC 24 00 0.859 O.:L4:l 0.0 0.742 :L3 DA 26 00 0.851 0.149 0.0 0.781 14 D8 28 00 0.844 0.156 0.0 0.820 15 D6 2A OO 0.836 0.164 0.0 0.859 16 D4 2C 00 0.828 0.172 0.0 0.898 17 D2 2E 00 0.820 0.180 0.0 0.937 18 DO 30 00 0.812 0.188 0.0 0.977 19 CE 32 00 0.804 0.196 0.0 1.016 lA CC 34 00 0.796 0.204 0.0 1.055 lB CA 36 00 0.788 0.212 0.0 1.094 lC C8 38 OO 0.781 0.219 0.0 1.133 lD C6 3A 00 0.773 0.227 0.0 1.172 lE C4 3C 00 0.766 0.234 0.0 1.211 lF C2 3E 00 0.758 0.242 O.O
~5~
DATA PORTIONS
Inpu~ PROM 'Red' 'Green' 'Blue' red green blue Voltage Address PROM PROM PR~M
(~olts) (Hex) (Hex) (Hex) (Hex) 1.250 20 CO 40 00 0.75 0.25 0.0 1.289 21 BE 42 00 0.742 0.258 0.0 1.328 22 ~C ~4 00 0.734 0.266 0.0 1.367 23 BA 46 00 0.726 0.274 0.0 10 1.406 24 B8 48 00 0.719 0.281 0.0 1.445 25 B6 4A 00 0.711 0.289 0.0 1.484 26 B4 4C 00 0.703 0.297 0.0 1.523 27 B2 4E 00 0.695 0.305 0.0 1.562 28 BO 50 00 0.687 0.313 0.0 1.602 29 AE 52 00 0.680 0.320 0.0 1.641 2A AC 54 00 0.672 0.328 0.0 1.680 2B AA 56 00 0.664 0.336 0.0 1.719 2C A8 58 00 0.656 0.344 0.0 1.758 2D A6 5A 00 0.648 0.352 0.0 20 1.797 2E A4 5C 00 0.641 0.359 0.0 1~836 2F A2 5E 00 0.633 0.367 0.0 ~52~6 DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green blue Voltage Address PROM PROM PROM
(Volts) (Hex) (Hex) (Hex) (Hex) 1.875 30 A0 60 O0 0.625 0.375 0.0 1.914 31 9E 62 00 0.6:l3 0.383 0.0 .953 32 9C 6~ 00 0.609 0.39l 0.0 1.992 33 9A 66 00 0.602 0.398 0.0 102.031 34 98 68 00 0.594 0.~06 0.0 2.070 35 96 6A 00 0.586 0.414 0.0 2.109 36 94 6C 00 0.578 0.422 0.0 2.148 37 92 6E 00 0.570 0.430 0.0 2.187 38 90 70 00 0.562 0.438 0.0 2.227 39 8E 72 00 0.554 0.446 0.0 2.266 3A 8C 74 00 0.547 0.453 0.0 2.305 3B 8A 76 00 0.539 0.461 O.0 2.34~ 3C 88 78 00 0.531 0.469 0.0 2.389 3D 86 7A 00 0.524 0.476 0.0 202.422 3E 84 7C 00 0.516 0.484 0.0 2.461 3F 82 7E 00 0.508 0.492 0.0 ~;~5~
DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green blue Voltage Address PROM PROM PROM
(Volts) (Hex) (Hex) (Hex) (Hex) 2.500 40 80 80 00 0.5 0.5 0.0 2.539 4L 7C 84 00 0.484 0.516 0.0 2.578 ~2 78 88 00 0.~i69 0.531 0.0 2.617 43 74 8C 00 0.~53 0.547 0.0 10 2.656 44 70 90 00 0.437 0.563 0.0 2.695 45 6C 94 00 0.422 0.578 0.0 2.734 46 68 98 00 0.406 0.594 0.0 2.773 47 64 9C 00 0.391 0.609 0.0 2.812 48 60 A0 00 0.375 0.625 0.0 2.852 49 5C A4 00 0.359 0.641 0.0 2.891 4A 58 A8 00 0.344 0.656 0.0 2.930 4B 54 AC 00 0.328 0.672 0.0 2.969 4C 50 B0 00 0.312 0.688 0.0 3.008 4D 4C B4 00 0.297 0.703 0.0 20 3.047 4E 48 B8 00 0.281 0.719 0.0 3.086 4F 44 BC 00 0.266 0.734 0.0 S;~2~6 DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green blue Voltage Address PROM PROM PROM
(Vol~s) (Hex) (Hex) (Hex) (Hex) 3.125 50 40 CO 00 0.25 0.75 0.0 3.~64 51 3C C4 00 0.23~ 0.766 0.0 3.203 52 38 C~ 00 0.2L9 0.78:l 0.0 3.242 53 3~ CC 00 0.203 0.797 0.0 3.281 54 30 DO 00 0.187 0.813 0.0 3.320 55 2C D4 00 0.172 0.828 0.0 3.359 56 28 D8 00 0.156 0.844 0.0 3.398 57 24 DC 00 0.141 0.859 0.0 3.437 58 20 EO 00 0.125 0.875 0.0 3.477 59 lC E4 00 0.109 0.891 0.0 3.516 5A 18 E8 00 0.094 0.906 0.0 3.555 5B 14 EC 00 0.078 0.922 0.0 3.594 5C 10 FO 00 0.062 0.938 0.0 3.633 5D OC F4 00 0.047 0.953 0.0 3.672 5E 08 F8 00 0.031 0.967 0.0 3.711 5F 04 FC 00 0.016 0.984 0.0 ~ ~ 5~ ~ ~ 6 DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green blue Voltage Address PROM PROM PROM
(Volts) (Hex~ (Hex) (Hex) (Hex) 3.750 60 00 FF 00 0.0 1.0 0.0 3.789 61 00 F8 08 0.0 0.969 0.03l 3.828 62 00 F0 L0 0.0 0.937 0.063 3.867 63 00 E8 18 0.0 0.906 0.094 ` 10 3.906 64 00 EO 20 0.0 0.875 0.125 3.945 65 00 D8 28 0.0 0.844 0.156 3.984 66 00 D0 30 0.0 0.812 0.188 4.023 67 00 C8 38 0.0 0.781 0.219 4.062 68 00 C0 40 0.0 0.75 0.25 4.102 69 00 B8 48 0.0 0.719 0.281 4.141 6A 00 B0 50 0.0 0.687 0.313 4.178 6B 00 A8 58 0.0 0.656 0.344 4.219 6C 00 A0 60 0.0 0.625 0O375 4.258 6D 00 98 68 0.0 0.594 0.406 20 4.299 6E 00 90 70 0.0 0.562 0.438 4.336 6F' 00 88 78 0.0 0.531 0.469 ~ ;~52Z~6 DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green blue Voltage Address PROM PROM PROM
(Volts) (Hex) (Hex) (~ex) (Hex) 4.375 70 00 80 80 0.0 0.5 0.5 71 00 78 88 0.0 ().~69 0.531 ~ 53 72 00 70 90 0.0 ().~37 0.563 4.492 73 00 68 98 0.0 0.406 0.594 10 4.531 74 00 60 AO 0.0 0.375 0.625 4.570 75 00 58 A8 0.0 0.344 0.656 4.609 76 00 50 BO 0.0 0.312 0.688 4.648 77 00 48 B8 0.0 0.281 0.719 4.687 78 00 40 CO 0.0 0.25 0.75 4.727 79 00 38 C8 0.0 0.219 0.781 4.766 7A 00 30 DQ 0.0 0.187 0.813 4.805 7B 00 28 D8 0.0 0.156 0.844 4.844 7C 00 20 EO 0.0 0.125 0.875 4.883 7D 00 18 E8 0.0 0.094 0.906 20 4.922 7E 00 10 FO 0.0 0.062 0.938 4.961 7F 00 08 F8 0.0 0.031 0.967 ~'~S2~6 DATA PORTIONS
Input PROM 'Redl 'Green' 'Blue' red green ~lue Voltage Address PROM PROM PROM
(Volts) (Hex) (Hex) (Hex) (Hex) 5.000 80 00 00 FF 0.0 0.0 1.0 5.039 8:L 04 00 FC 0.0l6 0.0 0.984 5.078 82 08 00 F8 0.031 0.0 0.969 5.117 83 0C 00 F4 0.047 0.0 0~953 10 5.156 84 10 00 F0 0.063 0.0 0.937 5.195 85 14 00 EC 0.078 0.0 0.922 5.234 86 18 00 E8 0.094 0.0 0.906 5.273 87 lC 00 E4 0.109 0.0 0.891 5.312 88 20 00 E0 0.125 0.0 0.875 5.352 89 24 00 DC 0.141 0.0 0.859 5.391 8A 28 00 D8 0.156 0.0 0.844 5.430 8B 2C 00 D4 0.172 0.0 0.828 5.469 8C 30 00 D0 0.188 0.0 0.812 5.508 8D 34 00 CC 0.2 0.0 0.8 20 5.547 8E 38 00 C8 0.219 0.0 0.781 5.586 8F 3C 00 C4 0.234 0.0 0.766 ~5;~
DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green ~lue Voltage Address PROM PROM PROM
(Volts) (Hex) (Hex) (Hex) (Hex) 5.625 90 40 00 CO 0.25 0.0 0.75 5.664 91 44 00 BC 0.266 0.0 0.734 5.703 92 48 00 B8 0.28:L 0.0 0.719 5.742 93 4C 00 B4 0.297 0.0 0.703 5.781 94 50 00 BO 0.313 0.0 0.687 5.820 95 54 00 AC 0.328 0.0 0.672 5.859 96 58 00 A8 0.344 0.0 0.656 5.898 97 5C 00 A4 0.359 0.0 0.641 5.937 98 60 00 AO 0.375 0.0 0.625 5.977 99 64 00 9C 0.391 0.0 0.609 6.016 9A 68 00 98 0.406 0.0 0.594 6.055 9B 6C 00 94 0.422 0.0 0.578 6.094 9C 70 00 90 0.438 0.0 0.562 6.133 9D 74 00 8C 0.453 0.0 0.547 6.172 9E 78 00 88 0.469 0.0 0.531 6.211 9F 7C 00 84 0.484 0.0 0.516 ~Z~ 6 DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green blue Voltage Address PROM PROM PROM
(Volts) (Hex) (Hex) (Hex) (Hex) 6.250 A0 80 00 80 0.5 0.0 0.5 6.289 Al 84 00 7C 0.5:L6 0.0 0.484 6.328 A2 88 00 78 0.531 0.0 0.469 6.367 A3 8C 00 74 0.547 0.0 0.453 10 6.406 A4 90 00 70 0.563 0.0 0.437 6.445 A5 94 00 6C 0.578 0.0 0.422 6.484 A6 98 00 68 0.594 0.0 0.406 6.524 A7 9C 00 64 0.609 0.0 0.391 6.562 A8 A0 00 60 0.625 0.0 0.375 6.602 A9 A4 00 5C 0.641 0.0 0.359 6.641 AA A8 00 58 0.656 0.0 0.344 6.680 AB AC 00 54 0.672 0.0 0.328 6.719 AC B0 00 50 0.688 0.0 0.312 6.758 AD B4 00 4C 0.703 0.0 0.297 20 6.797 AE B8 00 48 0.719 0.0 0.281 6.836 AF BC 00 44 0.734 0.0 0.266 ~2;2~6 DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green blue ; Voltage Address PROM PROM PROM
(Volts) (Hex) (Hex) (Hex) (Hex) 6.875 B0 C0 00 40 0.75 0.0 0.25 6.914 Bl C4 00 3C 0.766 0.0 0.234 6.953 B2 C8 00 38 0.781 0.0 0.219 6.992 B3 CC 00 3ll 0.797 0.0 0.203 10 7.031 B4 D0 00 30 0.813 0.0 0.187 7.070 B5 D4 00 2C 0.828 0.0 0.172 7.109 B6 D8 00 28 0.844 0.0 0.156 7.148 B7 DC 00 24 0.859 0.0 0.141 7.187 B8 E0 00 20 0.875 0.0 0.125 7.227 B9 E4 00 lC 0.891 0.0 0.109 7.266 BA E8 00 18 0.906 0.0 0.094 7.305 BB EC 00 14 0.922 0O0 0.078 7.344 BC F0 00 10 0.938 0.0 0.062 7.383 BD F4 00 0C 0.953 0.0 0.047 20 7.422 BE F8 00 08 0.967 0.0 0.031 7.461 BF FC 00 04 0.984 0.0 0.016
20 0.547 0E E4 lC 00 0.891 0.109 O.O
; 0.586 OF E2 lE 00 0.883 0.117 0.0 2~i DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green blue Voltage Address PROM PROM PROM
(Volts) (Hex) (Hex) (Hex) (Hex) 0.625 10 E0 20 00 0.875 0.125 0.0 0.664 lL D~ 22 00 0.867 0.133 0.0 0.703 12 DC 24 00 0.859 O.:L4:l 0.0 0.742 :L3 DA 26 00 0.851 0.149 0.0 0.781 14 D8 28 00 0.844 0.156 0.0 0.820 15 D6 2A OO 0.836 0.164 0.0 0.859 16 D4 2C 00 0.828 0.172 0.0 0.898 17 D2 2E 00 0.820 0.180 0.0 0.937 18 DO 30 00 0.812 0.188 0.0 0.977 19 CE 32 00 0.804 0.196 0.0 1.016 lA CC 34 00 0.796 0.204 0.0 1.055 lB CA 36 00 0.788 0.212 0.0 1.094 lC C8 38 OO 0.781 0.219 0.0 1.133 lD C6 3A 00 0.773 0.227 0.0 1.172 lE C4 3C 00 0.766 0.234 0.0 1.211 lF C2 3E 00 0.758 0.242 O.O
~5~
DATA PORTIONS
Inpu~ PROM 'Red' 'Green' 'Blue' red green blue Voltage Address PROM PROM PR~M
(~olts) (Hex) (Hex) (Hex) (Hex) 1.250 20 CO 40 00 0.75 0.25 0.0 1.289 21 BE 42 00 0.742 0.258 0.0 1.328 22 ~C ~4 00 0.734 0.266 0.0 1.367 23 BA 46 00 0.726 0.274 0.0 10 1.406 24 B8 48 00 0.719 0.281 0.0 1.445 25 B6 4A 00 0.711 0.289 0.0 1.484 26 B4 4C 00 0.703 0.297 0.0 1.523 27 B2 4E 00 0.695 0.305 0.0 1.562 28 BO 50 00 0.687 0.313 0.0 1.602 29 AE 52 00 0.680 0.320 0.0 1.641 2A AC 54 00 0.672 0.328 0.0 1.680 2B AA 56 00 0.664 0.336 0.0 1.719 2C A8 58 00 0.656 0.344 0.0 1.758 2D A6 5A 00 0.648 0.352 0.0 20 1.797 2E A4 5C 00 0.641 0.359 0.0 1~836 2F A2 5E 00 0.633 0.367 0.0 ~52~6 DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green blue Voltage Address PROM PROM PROM
(Volts) (Hex) (Hex) (Hex) (Hex) 1.875 30 A0 60 O0 0.625 0.375 0.0 1.914 31 9E 62 00 0.6:l3 0.383 0.0 .953 32 9C 6~ 00 0.609 0.39l 0.0 1.992 33 9A 66 00 0.602 0.398 0.0 102.031 34 98 68 00 0.594 0.~06 0.0 2.070 35 96 6A 00 0.586 0.414 0.0 2.109 36 94 6C 00 0.578 0.422 0.0 2.148 37 92 6E 00 0.570 0.430 0.0 2.187 38 90 70 00 0.562 0.438 0.0 2.227 39 8E 72 00 0.554 0.446 0.0 2.266 3A 8C 74 00 0.547 0.453 0.0 2.305 3B 8A 76 00 0.539 0.461 O.0 2.34~ 3C 88 78 00 0.531 0.469 0.0 2.389 3D 86 7A 00 0.524 0.476 0.0 202.422 3E 84 7C 00 0.516 0.484 0.0 2.461 3F 82 7E 00 0.508 0.492 0.0 ~;~5~
DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green blue Voltage Address PROM PROM PROM
(Volts) (Hex) (Hex) (Hex) (Hex) 2.500 40 80 80 00 0.5 0.5 0.0 2.539 4L 7C 84 00 0.484 0.516 0.0 2.578 ~2 78 88 00 0.~i69 0.531 0.0 2.617 43 74 8C 00 0.~53 0.547 0.0 10 2.656 44 70 90 00 0.437 0.563 0.0 2.695 45 6C 94 00 0.422 0.578 0.0 2.734 46 68 98 00 0.406 0.594 0.0 2.773 47 64 9C 00 0.391 0.609 0.0 2.812 48 60 A0 00 0.375 0.625 0.0 2.852 49 5C A4 00 0.359 0.641 0.0 2.891 4A 58 A8 00 0.344 0.656 0.0 2.930 4B 54 AC 00 0.328 0.672 0.0 2.969 4C 50 B0 00 0.312 0.688 0.0 3.008 4D 4C B4 00 0.297 0.703 0.0 20 3.047 4E 48 B8 00 0.281 0.719 0.0 3.086 4F 44 BC 00 0.266 0.734 0.0 S;~2~6 DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green blue Voltage Address PROM PROM PROM
(Vol~s) (Hex) (Hex) (Hex) (Hex) 3.125 50 40 CO 00 0.25 0.75 0.0 3.~64 51 3C C4 00 0.23~ 0.766 0.0 3.203 52 38 C~ 00 0.2L9 0.78:l 0.0 3.242 53 3~ CC 00 0.203 0.797 0.0 3.281 54 30 DO 00 0.187 0.813 0.0 3.320 55 2C D4 00 0.172 0.828 0.0 3.359 56 28 D8 00 0.156 0.844 0.0 3.398 57 24 DC 00 0.141 0.859 0.0 3.437 58 20 EO 00 0.125 0.875 0.0 3.477 59 lC E4 00 0.109 0.891 0.0 3.516 5A 18 E8 00 0.094 0.906 0.0 3.555 5B 14 EC 00 0.078 0.922 0.0 3.594 5C 10 FO 00 0.062 0.938 0.0 3.633 5D OC F4 00 0.047 0.953 0.0 3.672 5E 08 F8 00 0.031 0.967 0.0 3.711 5F 04 FC 00 0.016 0.984 0.0 ~ ~ 5~ ~ ~ 6 DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green blue Voltage Address PROM PROM PROM
(Volts) (Hex~ (Hex) (Hex) (Hex) 3.750 60 00 FF 00 0.0 1.0 0.0 3.789 61 00 F8 08 0.0 0.969 0.03l 3.828 62 00 F0 L0 0.0 0.937 0.063 3.867 63 00 E8 18 0.0 0.906 0.094 ` 10 3.906 64 00 EO 20 0.0 0.875 0.125 3.945 65 00 D8 28 0.0 0.844 0.156 3.984 66 00 D0 30 0.0 0.812 0.188 4.023 67 00 C8 38 0.0 0.781 0.219 4.062 68 00 C0 40 0.0 0.75 0.25 4.102 69 00 B8 48 0.0 0.719 0.281 4.141 6A 00 B0 50 0.0 0.687 0.313 4.178 6B 00 A8 58 0.0 0.656 0.344 4.219 6C 00 A0 60 0.0 0.625 0O375 4.258 6D 00 98 68 0.0 0.594 0.406 20 4.299 6E 00 90 70 0.0 0.562 0.438 4.336 6F' 00 88 78 0.0 0.531 0.469 ~ ;~52Z~6 DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green blue Voltage Address PROM PROM PROM
(Volts) (Hex) (Hex) (~ex) (Hex) 4.375 70 00 80 80 0.0 0.5 0.5 71 00 78 88 0.0 ().~69 0.531 ~ 53 72 00 70 90 0.0 ().~37 0.563 4.492 73 00 68 98 0.0 0.406 0.594 10 4.531 74 00 60 AO 0.0 0.375 0.625 4.570 75 00 58 A8 0.0 0.344 0.656 4.609 76 00 50 BO 0.0 0.312 0.688 4.648 77 00 48 B8 0.0 0.281 0.719 4.687 78 00 40 CO 0.0 0.25 0.75 4.727 79 00 38 C8 0.0 0.219 0.781 4.766 7A 00 30 DQ 0.0 0.187 0.813 4.805 7B 00 28 D8 0.0 0.156 0.844 4.844 7C 00 20 EO 0.0 0.125 0.875 4.883 7D 00 18 E8 0.0 0.094 0.906 20 4.922 7E 00 10 FO 0.0 0.062 0.938 4.961 7F 00 08 F8 0.0 0.031 0.967 ~'~S2~6 DATA PORTIONS
Input PROM 'Redl 'Green' 'Blue' red green ~lue Voltage Address PROM PROM PROM
(Volts) (Hex) (Hex) (Hex) (Hex) 5.000 80 00 00 FF 0.0 0.0 1.0 5.039 8:L 04 00 FC 0.0l6 0.0 0.984 5.078 82 08 00 F8 0.031 0.0 0.969 5.117 83 0C 00 F4 0.047 0.0 0~953 10 5.156 84 10 00 F0 0.063 0.0 0.937 5.195 85 14 00 EC 0.078 0.0 0.922 5.234 86 18 00 E8 0.094 0.0 0.906 5.273 87 lC 00 E4 0.109 0.0 0.891 5.312 88 20 00 E0 0.125 0.0 0.875 5.352 89 24 00 DC 0.141 0.0 0.859 5.391 8A 28 00 D8 0.156 0.0 0.844 5.430 8B 2C 00 D4 0.172 0.0 0.828 5.469 8C 30 00 D0 0.188 0.0 0.812 5.508 8D 34 00 CC 0.2 0.0 0.8 20 5.547 8E 38 00 C8 0.219 0.0 0.781 5.586 8F 3C 00 C4 0.234 0.0 0.766 ~5;~
DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green ~lue Voltage Address PROM PROM PROM
(Volts) (Hex) (Hex) (Hex) (Hex) 5.625 90 40 00 CO 0.25 0.0 0.75 5.664 91 44 00 BC 0.266 0.0 0.734 5.703 92 48 00 B8 0.28:L 0.0 0.719 5.742 93 4C 00 B4 0.297 0.0 0.703 5.781 94 50 00 BO 0.313 0.0 0.687 5.820 95 54 00 AC 0.328 0.0 0.672 5.859 96 58 00 A8 0.344 0.0 0.656 5.898 97 5C 00 A4 0.359 0.0 0.641 5.937 98 60 00 AO 0.375 0.0 0.625 5.977 99 64 00 9C 0.391 0.0 0.609 6.016 9A 68 00 98 0.406 0.0 0.594 6.055 9B 6C 00 94 0.422 0.0 0.578 6.094 9C 70 00 90 0.438 0.0 0.562 6.133 9D 74 00 8C 0.453 0.0 0.547 6.172 9E 78 00 88 0.469 0.0 0.531 6.211 9F 7C 00 84 0.484 0.0 0.516 ~Z~ 6 DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green blue Voltage Address PROM PROM PROM
(Volts) (Hex) (Hex) (Hex) (Hex) 6.250 A0 80 00 80 0.5 0.0 0.5 6.289 Al 84 00 7C 0.5:L6 0.0 0.484 6.328 A2 88 00 78 0.531 0.0 0.469 6.367 A3 8C 00 74 0.547 0.0 0.453 10 6.406 A4 90 00 70 0.563 0.0 0.437 6.445 A5 94 00 6C 0.578 0.0 0.422 6.484 A6 98 00 68 0.594 0.0 0.406 6.524 A7 9C 00 64 0.609 0.0 0.391 6.562 A8 A0 00 60 0.625 0.0 0.375 6.602 A9 A4 00 5C 0.641 0.0 0.359 6.641 AA A8 00 58 0.656 0.0 0.344 6.680 AB AC 00 54 0.672 0.0 0.328 6.719 AC B0 00 50 0.688 0.0 0.312 6.758 AD B4 00 4C 0.703 0.0 0.297 20 6.797 AE B8 00 48 0.719 0.0 0.281 6.836 AF BC 00 44 0.734 0.0 0.266 ~2;2~6 DATA PORTIONS
Input PROM 'Red' 'Green' 'Blue' red green blue ; Voltage Address PROM PROM PROM
(Volts) (Hex) (Hex) (Hex) (Hex) 6.875 B0 C0 00 40 0.75 0.0 0.25 6.914 Bl C4 00 3C 0.766 0.0 0.234 6.953 B2 C8 00 38 0.781 0.0 0.219 6.992 B3 CC 00 3ll 0.797 0.0 0.203 10 7.031 B4 D0 00 30 0.813 0.0 0.187 7.070 B5 D4 00 2C 0.828 0.0 0.172 7.109 B6 D8 00 28 0.844 0.0 0.156 7.148 B7 DC 00 24 0.859 0.0 0.141 7.187 B8 E0 00 20 0.875 0.0 0.125 7.227 B9 E4 00 lC 0.891 0.0 0.109 7.266 BA E8 00 18 0.906 0.0 0.094 7.305 BB EC 00 14 0.922 0O0 0.078 7.344 BC F0 00 10 0.938 0.0 0.062 7.383 BD F4 00 0C 0.953 0.0 0.047 20 7.422 BE F8 00 08 0.967 0.0 0.031 7.461 BF FC 00 04 0.984 0.0 0.016
Claims (19)
1. A variable color display device comprising:
a plurality of variable color display areas arranged in a pattern, each said display area including a first light source for emitting upon activation light signals of a first color, a second light source for emitting upon activation light signals of a second color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a first bus to which the first light sources are commonly coupled for enabling, upon activation of said first bus, the first light sources in the display areas activated by said decoder to be illuminated in said first color;
a second bus to which the second light sources are commonly coupled for enabling, upon activation of said second bus, the second light sources in the display areas activated by said decoder to be illuminated in said second color; and a color control including an input for receiving a color control signal and outputs for developing output control signals for simultaneously activating, in response to said color control signal, said first bus and said second bus, to illuminate the exhibited display unit in said composite color.
a plurality of variable color display areas arranged in a pattern, each said display area including a first light source for emitting upon activation light signals of a first color, a second light source for emitting upon activation light signals of a second color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a first bus to which the first light sources are commonly coupled for enabling, upon activation of said first bus, the first light sources in the display areas activated by said decoder to be illuminated in said first color;
a second bus to which the second light sources are commonly coupled for enabling, upon activation of said second bus, the second light sources in the display areas activated by said decoder to be illuminated in said second color; and a color control including an input for receiving a color control signal and outputs for developing output control signals for simultaneously activating, in response to said color control signal, said first bus and said second bus, to illuminate the exhibited display unit in said composite color.
2. A variable color display device comprising:
a plurality of variable color display areas arranged in a pattern, each said display area including a first light source for emitting upon activation light signals of a first color, a second light source for emitting upon activation light signals of a second color, a third light source for emitting upon activation light signals of a third color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a first bus to which the first light sources are commonly coupled for enabling, upon activation of said first bus, the first light sources in the display areas activated by said decoder to be illuminated in said first color;
a second bus to which the second light sources are commonly coupled for enabling, upon activation of said second bus, the second light sources in the display areas activated by said decoder to be illuminated in said second color;
a third bus to which the third light sources are commonly coupled for enabling, upon activation of said third bus, the third light sources in the display areas activated by said decoder to be illuminated in said third color; and a color control including an input for receiving a color control signal and outputs for developing output control signals for simultaneously activating, in response to said color control signal, a predetermined combination of said first bus, said second bus, and said third bus, to illuminate the exhibited display unit in a predetermined composite color.
a plurality of variable color display areas arranged in a pattern, each said display area including a first light source for emitting upon activation light signals of a first color, a second light source for emitting upon activation light signals of a second color, a third light source for emitting upon activation light signals of a third color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a first bus to which the first light sources are commonly coupled for enabling, upon activation of said first bus, the first light sources in the display areas activated by said decoder to be illuminated in said first color;
a second bus to which the second light sources are commonly coupled for enabling, upon activation of said second bus, the second light sources in the display areas activated by said decoder to be illuminated in said second color;
a third bus to which the third light sources are commonly coupled for enabling, upon activation of said third bus, the third light sources in the display areas activated by said decoder to be illuminated in said third color; and a color control including an input for receiving a color control signal and outputs for developing output control signals for simultaneously activating, in response to said color control signal, a predetermined combination of said first bus, said second bus, and said third bus, to illuminate the exhibited display unit in a predetermined composite color.
3. A variable color display device comprising:
a plurality of variable color display areas arranged in a pattern, each said display area including a first light source for emitting upon activation light signals of a first color, a second light source for emitting upon activation light signals of a second color, a third light source for emitting upon activation light signals of a third color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a first bus to which the first light sources are commonly coupled for enabling, upon activation of said first bus, the first light sources in the display areas activated by said decoder to be illuminated in said first color;
a second bus to which the second light sources are commonly coupled for enabling, upon activation of said second bus, the second light sources in the display areas activated by said decoder to be illuminated in said second color;
a third bus to which the third light sources are commonly coupled for enabling, upon activation of said third bus, the third light sources in the display areas activated by said decoder to be illuminated in said third color; and a color control including four inputs for respectively receiving a first color control signal, a second color control signal, a third color control signal and a fourth color control signal, and outputs for developing output control signals for simultaneously activating said first bus and said second bus in response to said first color control signal, for simultaneously activating said first bus and said third bus in response to said second color control signal, for simultaneously activating said second bus and said third bus in response to said third color control signal, and for simultaneously activating said first bus, said second bus, and said third bus in response to said fourth color control signal, to illuminate the exhibited display unit in one of four predetermined composite colors.
a plurality of variable color display areas arranged in a pattern, each said display area including a first light source for emitting upon activation light signals of a first color, a second light source for emitting upon activation light signals of a second color, a third light source for emitting upon activation light signals of a third color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a first bus to which the first light sources are commonly coupled for enabling, upon activation of said first bus, the first light sources in the display areas activated by said decoder to be illuminated in said first color;
a second bus to which the second light sources are commonly coupled for enabling, upon activation of said second bus, the second light sources in the display areas activated by said decoder to be illuminated in said second color;
a third bus to which the third light sources are commonly coupled for enabling, upon activation of said third bus, the third light sources in the display areas activated by said decoder to be illuminated in said third color; and a color control including four inputs for respectively receiving a first color control signal, a second color control signal, a third color control signal and a fourth color control signal, and outputs for developing output control signals for simultaneously activating said first bus and said second bus in response to said first color control signal, for simultaneously activating said first bus and said third bus in response to said second color control signal, for simultaneously activating said second bus and said third bus in response to said third color control signal, and for simultaneously activating said first bus, said second bus, and said third bus in response to said fourth color control signal, to illuminate the exhibited display unit in one of four predetermined composite colors.
4. A variable color display device comprising:
a plurality of variable color display areas arranged in a pattern, each said display area including a red light source for emitting upon activation light signals of red color, a green light source for emitting upon activation light signals of green color, a blue light source for emitting upon activation light signals of blue color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a red bus to which the red light sources are commonly coupled for enabling, upon activation of said red bus, the red light sources in the display areas activated by said decoder to be illuminated in red color;
a green bus to which the green light sources are commonly coupled for enabling, upon activation of said green bus, the green light sources in the display areas activated by said decoder to be illuminated in green color;
a blue bus to which the blue light sources are commonly coupled for enabling, upon activation of said blue bus, the blue light sources in the display areas activated by said decoder to be illuminated in blue color; and a color control including seven inputs for respectively receiving a red color control signal, a green color control signal, a blue color control signal, a yellow color control signal, a blue-green color control signal, a purple color control signal and a white color control signal, and outputs for developing output control signals for activating said red bus in response to said red color control signal, to illuminate the exhibited display unit in red color, for activating said green bus in response to said green color control signal, to illuminate the exhibited display unit in green color, for activating said blue bus in response to said blue color control signal, to illuminate the exhibited display unit in blue color, for simultaneously activating said red bus and said green bus in response to said yellow color control signal, to illuminate the exhibited display unit in yellow color, for simultaneously activating said green bus and said blue bus in response to said blue-green color control signal, to illuminate the exhibited display unit in blue-green color, for simultaneously activating said red bus and said blue bus in response to said purple color control signal, to illuminate the exhibited display unit in purple color, and for simultaneously activating said red bus, said green bus, and said blue bus in response to said white color control signal, to illuminate the exhibited display unit in white color.
a plurality of variable color display areas arranged in a pattern, each said display area including a red light source for emitting upon activation light signals of red color, a green light source for emitting upon activation light signals of green color, a blue light source for emitting upon activation light signals of blue color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a red bus to which the red light sources are commonly coupled for enabling, upon activation of said red bus, the red light sources in the display areas activated by said decoder to be illuminated in red color;
a green bus to which the green light sources are commonly coupled for enabling, upon activation of said green bus, the green light sources in the display areas activated by said decoder to be illuminated in green color;
a blue bus to which the blue light sources are commonly coupled for enabling, upon activation of said blue bus, the blue light sources in the display areas activated by said decoder to be illuminated in blue color; and a color control including seven inputs for respectively receiving a red color control signal, a green color control signal, a blue color control signal, a yellow color control signal, a blue-green color control signal, a purple color control signal and a white color control signal, and outputs for developing output control signals for activating said red bus in response to said red color control signal, to illuminate the exhibited display unit in red color, for activating said green bus in response to said green color control signal, to illuminate the exhibited display unit in green color, for activating said blue bus in response to said blue color control signal, to illuminate the exhibited display unit in blue color, for simultaneously activating said red bus and said green bus in response to said yellow color control signal, to illuminate the exhibited display unit in yellow color, for simultaneously activating said green bus and said blue bus in response to said blue-green color control signal, to illuminate the exhibited display unit in blue-green color, for simultaneously activating said red bus and said blue bus in response to said purple color control signal, to illuminate the exhibited display unit in purple color, and for simultaneously activating said red bus, said green bus, and said blue bus in response to said white color control signal, to illuminate the exhibited display unit in white color.
5. A variable color display device comprising:
a plurality of variable color display areas arranged in a pattern, each said display area including a first light emitting diode for emitting when forwardly biased light signals of a first color, a second light emitting diode for emitting when forwardly biased light signals of a second color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a first bus to which the first light emitting diodes are commonly coupled for forwardly biasing, upon activation of said first bus, the first light emitting diodes in the display areas activated by said decoder to be illuminated in said first color;
a second bus to which the second light emitting diodes are commonly coupled for forwardly biasing, upon activation of said second bus, the second light emitting diodes in the display areas activated by said decoder to be illuminated in said second color; and a color control including a first OR gate having a first input, a second input and an output and a second OR gate having a first input, a second input, and an output, the output of said first OR gate being coupled to activate said first bus, the output of said second OR gate being coupled to activate said second bus, the second input of said first OR gate and the second input of said second OR gate being commonly coupled;
whereby both said first bus and said second bus are activated when a high level signal is applied to the coupled inputs of said first OR gate and said second OR gate, for illuminating in said composite color the display areas activated by said decoder.
a plurality of variable color display areas arranged in a pattern, each said display area including a first light emitting diode for emitting when forwardly biased light signals of a first color, a second light emitting diode for emitting when forwardly biased light signals of a second color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a first bus to which the first light emitting diodes are commonly coupled for forwardly biasing, upon activation of said first bus, the first light emitting diodes in the display areas activated by said decoder to be illuminated in said first color;
a second bus to which the second light emitting diodes are commonly coupled for forwardly biasing, upon activation of said second bus, the second light emitting diodes in the display areas activated by said decoder to be illuminated in said second color; and a color control including a first OR gate having a first input, a second input and an output and a second OR gate having a first input, a second input, and an output, the output of said first OR gate being coupled to activate said first bus, the output of said second OR gate being coupled to activate said second bus, the second input of said first OR gate and the second input of said second OR gate being commonly coupled;
whereby both said first bus and said second bus are activated when a high level signal is applied to the coupled inputs of said first OR gate and said second OR gate, for illuminating in said composite color the display areas activated by said decoder.
6. A variable color display device comprising:
a plurality of variable color display areas arranged in a pattern, each said display area including a first light emitting diode for emitting when forwardly biased light signals of a first color, a second light emitting diode for emitting when forwardly biased light signals of a second color, a third light emitting diode for emitting when forwardly biased light signals of a third color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a first bus to which the first light emitting diodes are commonly coupled for forwardly biasing, upon activation of said first bus, the first light emitting diodes in the display areas activated by said decoder to be illuminated in said first color;
a second bus to which the second light emitting diodes are commonly coupled for forwardly biasing, upon activation of said second bus, the second light emitting diodes in the display areas activated by said decoder to be illuminated in said second color;
a third bus to which the third light emitting diodes are commonly coupled for forwardly biasing, upon activation of said third bus, the third light emitting diodes in the display areas activated by said decoder to be illuminated in said third color; and a color control including a first OR gate having a plurality of inputs and an output, a second OR gate having a plurality of inputs and an output, and a third OR gate having a plurality of inputs and an output, the output of said first OR gate being coupled to activate said first bus, the output of said second OR gate being coupled to activate said second bus, and the output of said third OR gate being coupled to activate said third bus, the inputs of said first OR gate, said second OR gate, and said third OR gate being coupled according to a predetermined system such that color control signals may be applied thereto;
whereby a predetermined combination of said first bus, said second bus, and said third bus may be activated in response to color control signals applied to the coupled inputs of said first OR gate, said second OR gate, and said third OR gate, for illuminating in a selective one of a plurality of predetermined composite colors the display areas activated by said decoder.
a plurality of variable color display areas arranged in a pattern, each said display area including a first light emitting diode for emitting when forwardly biased light signals of a first color, a second light emitting diode for emitting when forwardly biased light signals of a second color, a third light emitting diode for emitting when forwardly biased light signals of a third color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a first bus to which the first light emitting diodes are commonly coupled for forwardly biasing, upon activation of said first bus, the first light emitting diodes in the display areas activated by said decoder to be illuminated in said first color;
a second bus to which the second light emitting diodes are commonly coupled for forwardly biasing, upon activation of said second bus, the second light emitting diodes in the display areas activated by said decoder to be illuminated in said second color;
a third bus to which the third light emitting diodes are commonly coupled for forwardly biasing, upon activation of said third bus, the third light emitting diodes in the display areas activated by said decoder to be illuminated in said third color; and a color control including a first OR gate having a plurality of inputs and an output, a second OR gate having a plurality of inputs and an output, and a third OR gate having a plurality of inputs and an output, the output of said first OR gate being coupled to activate said first bus, the output of said second OR gate being coupled to activate said second bus, and the output of said third OR gate being coupled to activate said third bus, the inputs of said first OR gate, said second OR gate, and said third OR gate being coupled according to a predetermined system such that color control signals may be applied thereto;
whereby a predetermined combination of said first bus, said second bus, and said third bus may be activated in response to color control signals applied to the coupled inputs of said first OR gate, said second OR gate, and said third OR gate, for illuminating in a selective one of a plurality of predetermined composite colors the display areas activated by said decoder.
7. A method of controlling a color of a variable color display device which comprises a plurality of display areas arranged in a pattern for selectively exhibiting a plurality of display units, each said display area including a plurality of light sources for emitting upon activation light signals of respectively different primary colors and means for combining said light signals to obtain a composite light signal of a composite color, by exhibiting a selected display unit by repeatedly substantially simultaneously activating the light sources in selected display areas for brief time intervals to cause the light sources to emit light signals of said primary colors, and by selectively controlling the durations of the time intervals of activation of the light sources in the selected display areas to control the portions of the primary color light signals emitted therefrom, to thereby control the color of the exhibited display unit.
8. A variable color display device comprising:
a plurality of variable color display areas arranged in a pattern for selectively exhibiting a plurality of display units, each said display area including a plurality of light sources for emitting upon activation light signals of respectively different primary colors and means for combining said light signals to obtain a composite light signal of a composite color;
means for exhibiting a selected display unit by repeatedly substantially simultaneously activating the light sources in selected display areas by pulses of a substantially constant amplitude for causing the light sources to emit light signals of said primary colors; and color control means for selectively controlling the durations of the pulses applied to the light sources in the selected display areas to control the portions of the primary color light signals emitted therefrom, to thereby control the color of the exhibited display unit.
a plurality of variable color display areas arranged in a pattern for selectively exhibiting a plurality of display units, each said display area including a plurality of light sources for emitting upon activation light signals of respectively different primary colors and means for combining said light signals to obtain a composite light signal of a composite color;
means for exhibiting a selected display unit by repeatedly substantially simultaneously activating the light sources in selected display areas by pulses of a substantially constant amplitude for causing the light sources to emit light signals of said primary colors; and color control means for selectively controlling the durations of the pulses applied to the light sources in the selected display areas to control the portions of the primary color light signals emitted therefrom, to thereby control the color of the exhibited display unit.
9. A method of controlling a color of a variable color display device which comprises a plurality of display areas arranged in a pattern for selectively exhibiting a plurality of display units, each said display area including a plurality of light emitting diodes for emitting when forwardly biased light signals of respectively different primary colors and means for combining said light signals to obtain a composite light signal of a composite color, by exhibiting a selected display unit by repeatedly substantially simultaneously forwardly biasing the light emitting diodes in selected display areas for brief time intervals to cause the light emitting diodes to emit light signals of said primary colors, and by selectively controlling the durations of the time intervals of forward biasing of the light emitting diodes in the selected display areas to control the portions of the primary color light signals emitted therefrom, to thereby control the color of the exhibited display unit.
10. A variable color display device comprising:
a plurality of variable color display areas arranged in a pattern for selectively exhibiting a plurality of display units, each said display area including a plurality of light emitting diodes for emitting when forwardly biased light signals of respectively different primary colors and means for combining said light signals to obtain a composite light signal of a composite color;
means for exhibiting a selected display unit by repeatedly substantially simultaneously forwardly biasing said light emitting diodes in selected display areas by pulses of a substantially constant voltage amplitude for causing the light emitting diodes to emit light signals of said primary colors; and color control means for selectively controlling the durations of the pulses applied to the light emitting diodes in the selected display areas to control the portions of the primary color light signals emitted therefrom, to thereby control the color of the exhibited display unit.
a plurality of variable color display areas arranged in a pattern for selectively exhibiting a plurality of display units, each said display area including a plurality of light emitting diodes for emitting when forwardly biased light signals of respectively different primary colors and means for combining said light signals to obtain a composite light signal of a composite color;
means for exhibiting a selected display unit by repeatedly substantially simultaneously forwardly biasing said light emitting diodes in selected display areas by pulses of a substantially constant voltage amplitude for causing the light emitting diodes to emit light signals of said primary colors; and color control means for selectively controlling the durations of the pulses applied to the light emitting diodes in the selected display areas to control the portions of the primary color light signals emitted therefrom, to thereby control the color of the exhibited display unit.
11. A variable color display device comprising:
a plurality of variable color display areas arranged in a pattern for selectively exhibiting a plurality of display units, each said display area including a first light source for emitting upon activation light signals of a first color, a second light source for emitting upon activation light signals of a second color, a third light source for emitting upon activation light signals of a third color, and means for combining said light signals of said first color, said second color, and said third color to obtain a composite light signal of a composite color;
means for exhibiting a selected display unit by repeatedly activating first light sources in selected display areas by a first pulse of a substantially constant amplitude for causing the first light sources to emit light signals of said first color, by repeatedly activating second light sources in the selected display areas by a second pulse of a substantially constant amplitude for causing the second light sources to emit light signals of said second color, and by repeatedly activating third light sources in the selected display areas by a third pulse of a substantially constant amplitude for causing the third light sources to emit light signals of said third color;
said first pulse, said second pulse, and said third pulse starting substantially simultaneously; and color control means for selectively terminating said first pulse, said second pulse, and said third pulse to control their respective durations, to control the portions of the light signals of said first color, of said second color, and of said third color emitted from the selected display areas, to thereby control the color of the exhibited display unit.
a plurality of variable color display areas arranged in a pattern for selectively exhibiting a plurality of display units, each said display area including a first light source for emitting upon activation light signals of a first color, a second light source for emitting upon activation light signals of a second color, a third light source for emitting upon activation light signals of a third color, and means for combining said light signals of said first color, said second color, and said third color to obtain a composite light signal of a composite color;
means for exhibiting a selected display unit by repeatedly activating first light sources in selected display areas by a first pulse of a substantially constant amplitude for causing the first light sources to emit light signals of said first color, by repeatedly activating second light sources in the selected display areas by a second pulse of a substantially constant amplitude for causing the second light sources to emit light signals of said second color, and by repeatedly activating third light sources in the selected display areas by a third pulse of a substantially constant amplitude for causing the third light sources to emit light signals of said third color;
said first pulse, said second pulse, and said third pulse starting substantially simultaneously; and color control means for selectively terminating said first pulse, said second pulse, and said third pulse to control their respective durations, to control the portions of the light signals of said first color, of said second color, and of said third color emitted from the selected display areas, to thereby control the color of the exhibited display unit.
12. A variable color display device comprising:
a plurality of variable color display areas arranged in a pattern for selectively exhibiting a plurality of display units, each said display area including a first light emitting diode for emitting when forwardly biased light signals of a first color, a second light emitting diode for emitting when forwardly biased light signals of a second color, a third light emitting diode for emitting when forwardly biased light signals of a third color, and means for combining said light signals of said first color, said second color, and said third color to obtain a composite light signal of a composite color;
means for exhibiting a selected display unit by repeatedly forwardly biasing first light emitting diodes in selected display areas by a first pulse of a substantially constant voltage amplitude for causing the first light emitting diodes to emit light signals of said first color, by repeatedly forwardly biasing second light emitting diodes in the selected display areas by a second pulse of a substantially constant voltage amplitude for causing the second light emitting diodes to emit light signals of said second color, and by repeatedly forwardly biasing third light emitting diodes in the selected display areas by a third pulse of a substantially constant voltage amplitude for causing the third light emitting diodes to emit light signals of said third color;
said first pulse, said second pulse, and said third pulse starting substantially simultaneously; and color control means for selectively terminating said first pulse, said second pulse, and said third pulse to control their respective durations, to control the portions of the light signals of said first color, of said second color, and of said third color emitted from the selected display areas, to thereby control the color of the exhibited display unit.
a plurality of variable color display areas arranged in a pattern for selectively exhibiting a plurality of display units, each said display area including a first light emitting diode for emitting when forwardly biased light signals of a first color, a second light emitting diode for emitting when forwardly biased light signals of a second color, a third light emitting diode for emitting when forwardly biased light signals of a third color, and means for combining said light signals of said first color, said second color, and said third color to obtain a composite light signal of a composite color;
means for exhibiting a selected display unit by repeatedly forwardly biasing first light emitting diodes in selected display areas by a first pulse of a substantially constant voltage amplitude for causing the first light emitting diodes to emit light signals of said first color, by repeatedly forwardly biasing second light emitting diodes in the selected display areas by a second pulse of a substantially constant voltage amplitude for causing the second light emitting diodes to emit light signals of said second color, and by repeatedly forwardly biasing third light emitting diodes in the selected display areas by a third pulse of a substantially constant voltage amplitude for causing the third light emitting diodes to emit light signals of said third color;
said first pulse, said second pulse, and said third pulse starting substantially simultaneously; and color control means for selectively terminating said first pulse, said second pulse, and said third pulse to control their respective durations, to control the portions of the light signals of said first color, of said second color, and of said third color emitted from the selected display areas, to thereby control the color of the exhibited display unit.
13. A variable color display device comprising:
a plurality of variable color display areas arranged in a pattern, each said display area including a first light source for emitting upon activation light signals of a first primary color, a second light source for emitting upon activation light signals of a second primary color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a first bus to which the first light sources are commonly coupled for enabling, upon activation of said first bus, the first light sources in the display areas activated by said decoder to be illuminated in said first color;
a second bus to which the second light sources are commonly coupled for enabling, upon activation of said second bus, the second light sources in the display areas activated by said decoder to be illuminated in said second color;
means for repeatedly activating said first bus and said second bus by substantially simultaneously applying thereto pulses of a substantially constant amplitude, respectively, for causing the light sources in the display areas activated by said decoder to emit light signals of said primary colors; and color control means for selectively controlling the durations of the pulses respectively applied to said first bus and to said second bus for controlling the portions of said primary colors, to thereby control the color of the exhibited display unit.
a plurality of variable color display areas arranged in a pattern, each said display area including a first light source for emitting upon activation light signals of a first primary color, a second light source for emitting upon activation light signals of a second primary color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a first bus to which the first light sources are commonly coupled for enabling, upon activation of said first bus, the first light sources in the display areas activated by said decoder to be illuminated in said first color;
a second bus to which the second light sources are commonly coupled for enabling, upon activation of said second bus, the second light sources in the display areas activated by said decoder to be illuminated in said second color;
means for repeatedly activating said first bus and said second bus by substantially simultaneously applying thereto pulses of a substantially constant amplitude, respectively, for causing the light sources in the display areas activated by said decoder to emit light signals of said primary colors; and color control means for selectively controlling the durations of the pulses respectively applied to said first bus and to said second bus for controlling the portions of said primary colors, to thereby control the color of the exhibited display unit.
14. A variable color display device comprising:
a plurality of variable color display areas arranged in a pattern, each said display area including a first light source for emitting upon activation light signals of a first primary color, a second light source for emitting upon activation light signals of a second primary color, a third light source for emitting upon activation light signals of a third primary color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a first bus to which the first light sources are commonly coupled for enabling, upon activation of said first bus, the first light sources in the display areas activated by said decoder to be illuminated in said first color;
a second bus to which the second light sources are commonly coupled for enabling, upon activation of said second bus, the second light sources in the display areas activated by said decoder to be illuminated in said second color;
a third bus to which the third light sources are commonly coupled for enabling, upon activation of said third bus, the third light sources in the display areas activated by said decoder to be illuminated in said third color;
means for repeatedly activating said first bus, said second bus, and said third bus by substantially simultaneously applying thereto pulses of a substantially constant amplitude, respectively, for causing the light sources in the display areas activated by said decoder to emit light signals of said primary colors; and color control means for selectively controlling the durations of the pulses respectively applied to said first bus, to said second bus, and to said third bus for controlling the portions of said primary colors, to thereby control the color of the exhibited display unit.
a plurality of variable color display areas arranged in a pattern, each said display area including a first light source for emitting upon activation light signals of a first primary color, a second light source for emitting upon activation light signals of a second primary color, a third light source for emitting upon activation light signals of a third primary color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a first bus to which the first light sources are commonly coupled for enabling, upon activation of said first bus, the first light sources in the display areas activated by said decoder to be illuminated in said first color;
a second bus to which the second light sources are commonly coupled for enabling, upon activation of said second bus, the second light sources in the display areas activated by said decoder to be illuminated in said second color;
a third bus to which the third light sources are commonly coupled for enabling, upon activation of said third bus, the third light sources in the display areas activated by said decoder to be illuminated in said third color;
means for repeatedly activating said first bus, said second bus, and said third bus by substantially simultaneously applying thereto pulses of a substantially constant amplitude, respectively, for causing the light sources in the display areas activated by said decoder to emit light signals of said primary colors; and color control means for selectively controlling the durations of the pulses respectively applied to said first bus, to said second bus, and to said third bus for controlling the portions of said primary colors, to thereby control the color of the exhibited display unit.
15. A variable color display device comprising:
a plurality of variable color display areas arranged in a pattern, each said display area including a first light emitting diode for emitting when forwardly biased light signals of a first primary color, a second light emitting diode for emitting when forwardly biased light signals of a second primary color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a first bus to which the first light emitting diodes are commonly coupled for forwardly biasing, upon activation of said first bus, the first light emitting diodes in the display areas activated by said decoder to be illuminated in said first color;
a second bus to which the second light emitting diodes are commonly coupled for forwardly biasing, upon activation of said second bus, the second light emitting diodes in the display areas activated by said decoder to be illuminated in said second color;
means for repeatedly activating said first bus and said second bus by substantially simultaneously applying thereto pulses of a substantially constant amplitude, respectively, for causing the light emitting diodes in the display areas activated by said decoder to emit light signals of said primary colors; and color control means for selectively controlling the durations of the pulses respectively applied to said first bus and to said second bus for controlling the portions of said primary colors, to thereby control the color of the exhibited display unit.
a plurality of variable color display areas arranged in a pattern, each said display area including a first light emitting diode for emitting when forwardly biased light signals of a first primary color, a second light emitting diode for emitting when forwardly biased light signals of a second primary color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a first bus to which the first light emitting diodes are commonly coupled for forwardly biasing, upon activation of said first bus, the first light emitting diodes in the display areas activated by said decoder to be illuminated in said first color;
a second bus to which the second light emitting diodes are commonly coupled for forwardly biasing, upon activation of said second bus, the second light emitting diodes in the display areas activated by said decoder to be illuminated in said second color;
means for repeatedly activating said first bus and said second bus by substantially simultaneously applying thereto pulses of a substantially constant amplitude, respectively, for causing the light emitting diodes in the display areas activated by said decoder to emit light signals of said primary colors; and color control means for selectively controlling the durations of the pulses respectively applied to said first bus and to said second bus for controlling the portions of said primary colors, to thereby control the color of the exhibited display unit.
16. A variable color display device comprising:
a plurality of variable color display areas arranged in a pattern, each said display area including a first light emitting diode for emitting when forwardly biased light signals of a first primary color, a second light emitting diode for emitting when forwardly biased light signals of a second primary color, a third light emitting diode for emitting when forwardly biased light signals of a third primary color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a first bus to which the first light emitting diodes are commonly coupled for forwardly biasing, upon activation of said first bus, the first light emitting diodes in the display areas activated by said decoder to be illuminated in said first color;
a second bus to which the second light emitting diodes are commonly coupled for forwardly biasing, upon activation of said second bus, the second light emitting diodes in the display areas activated by said decoder to be illuminated in said second color;
a third bus to which the third light emitting diodes are commonly coupled for forwardly biasing, upon activation of said third bus, the third light emitting diodes in the display areas activated by said decoder to be illuminated in said third color;
means for repeatedly activating said first bus, said second bus, and said third bus by substantially simultaneously applying thereto pulses of a substantially constant amplitude, respectively, for causing the light emitting diodes in the display areas activated by said decoder to emit light signals of said primary colors; and color control means for selectively controlling the durations of the pulses respectively applied to said first bus, to said second bus, and to said third bus for controlling the portions of said primary colors, to thereby control the color of the exhibited display unit.
a plurality of variable color display areas arranged in a pattern, each said display area including a first light emitting diode for emitting when forwardly biased light signals of a first primary color, a second light emitting diode for emitting when forwardly biased light signals of a second primary color, a third light emitting diode for emitting when forwardly biased light signals of a third primary color, and means for combining said light signals in each said display area to obtain a composite light signal of a composite color;
a decoder for selectively activating groups of said display areas to exhibit one of a plurality of display units;
a first bus to which the first light emitting diodes are commonly coupled for forwardly biasing, upon activation of said first bus, the first light emitting diodes in the display areas activated by said decoder to be illuminated in said first color;
a second bus to which the second light emitting diodes are commonly coupled for forwardly biasing, upon activation of said second bus, the second light emitting diodes in the display areas activated by said decoder to be illuminated in said second color;
a third bus to which the third light emitting diodes are commonly coupled for forwardly biasing, upon activation of said third bus, the third light emitting diodes in the display areas activated by said decoder to be illuminated in said third color;
means for repeatedly activating said first bus, said second bus, and said third bus by substantially simultaneously applying thereto pulses of a substantially constant amplitude, respectively, for causing the light emitting diodes in the display areas activated by said decoder to emit light signals of said primary colors; and color control means for selectively controlling the durations of the pulses respectively applied to said first bus, to said second bus, and to said third bus for controlling the portions of said primary colors, to thereby control the color of the exhibited display unit.
17. A variable color display device comprising:
variable color display means for providing a display indication in a single selective color;
an N-bit counter for accumulating a count, where N is an integer having value at least 2, said counter having counter outputs indicative of the value of the accumulated count;
a converter responsive to said counter outputs for converting said value of the accumulated count to color control signals, said converter developing a first color control signal for said value of the accumulated count being less than a predetermined low count, a second color control signal for said value of the accumulated count being between the predetermined low count and a predetermined high count, and a third color control signal for said value of the accumulated count being greater than the predetermined high count; and color control means responsive to said color control signals for causing said display means to illuminate in a first color in response to said first color control signal, in a second color in response to said second color control signal, and in a third color in response to said third color control signal.
variable color display means for providing a display indication in a single selective color;
an N-bit counter for accumulating a count, where N is an integer having value at least 2, said counter having counter outputs indicative of the value of the accumulated count;
a converter responsive to said counter outputs for converting said value of the accumulated count to color control signals, said converter developing a first color control signal for said value of the accumulated count being less than a predetermined low count, a second color control signal for said value of the accumulated count being between the predetermined low count and a predetermined high count, and a third color control signal for said value of the accumulated count being greater than the predetermined high count; and color control means responsive to said color control signals for causing said display means to illuminate in a first color in response to said first color control signal, in a second color in response to said second color control signal, and in a third color in response to said third color control signal.
18. A variable color display device comprising:
variable color display means for providing a display indication in a single selective color;
an 8-bit binary counter for accumulating a count, said counter having counter outputs indicative of the value of the accumulated count;
a decoder responsive to said counter outputs for decoding said value of the accumulated count to color control signals, said decoder developing a first color control signal for said value of the accumulated count being less than 63, a second color control signal for said value of the accumulated count being between 64 and 127, and a third color control signal for said value of the accumulated count being between 128 and 191; and color control means responsive to said color control signals for causing said display means to illuminate in red color in response to said first color control signal, in yellow color in response to said second color control signal, and in green color in response to said third color control signal.
variable color display means for providing a display indication in a single selective color;
an 8-bit binary counter for accumulating a count, said counter having counter outputs indicative of the value of the accumulated count;
a decoder responsive to said counter outputs for decoding said value of the accumulated count to color control signals, said decoder developing a first color control signal for said value of the accumulated count being less than 63, a second color control signal for said value of the accumulated count being between 64 and 127, and a third color control signal for said value of the accumulated count being between 128 and 191; and color control means responsive to said color control signals for causing said display means to illuminate in red color in response to said first color control signal, in yellow color in response to said second color control signal, and in green color in response to said third color control signal.
19. A variable color display device comprising:
variable color display means for providing a display indication in a single selective color;
an 8-bit binary counter for accumulating a count, said counter having counter outputs indicative of the value of the accumulated count;
a decoder responsive to said counter outputs for decoding said value of the accumulated count to color control signals, said decoder developing a first color control signal for said value of the accumulated count being between 32 and 63, a second color control signal for said value of the accumulated count being between 64 and 95, a third color control signal for said value of the accumulated count being between 96 and 127, a fourth color control signal for said value of the accumulated count being between 128 and 159, a fifth color control signal for said value of the accumulated count being between 160 and 191, a sixth color control signal for said value of the accumulated count being between 192 and 223, and a seventh color control signal for said value of the accumulated count being over 224; and color control means responsive to said color control signals for causing said display means to illuminate in red color in response to said first color control signal, in white color in response to said second color control signal, in yellow color in response to said third color control signal, in green color in response to said fourth color control signal, in blue-green color in response to said fifth color control signal, in purple color in response to said sixth color control signal, and in blue color in response to said seventh color control signal.
variable color display means for providing a display indication in a single selective color;
an 8-bit binary counter for accumulating a count, said counter having counter outputs indicative of the value of the accumulated count;
a decoder responsive to said counter outputs for decoding said value of the accumulated count to color control signals, said decoder developing a first color control signal for said value of the accumulated count being between 32 and 63, a second color control signal for said value of the accumulated count being between 64 and 95, a third color control signal for said value of the accumulated count being between 96 and 127, a fourth color control signal for said value of the accumulated count being between 128 and 159, a fifth color control signal for said value of the accumulated count being between 160 and 191, a sixth color control signal for said value of the accumulated count being between 192 and 223, and a seventh color control signal for said value of the accumulated count being over 224; and color control means responsive to said color control signals for causing said display means to illuminate in red color in response to said first color control signal, in white color in response to said second color control signal, in yellow color in response to said third color control signal, in green color in response to said fourth color control signal, in blue-green color in response to said fifth color control signal, in purple color in response to said sixth color control signal, and in blue color in response to said seventh color control signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000563216A CA1252236A (en) | 1986-01-15 | 1988-04-05 | Variable color display device |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/819,111 | 1986-01-15 | ||
| US06/819,111 US4794383A (en) | 1986-01-15 | 1986-01-15 | Variable color digital multimeter |
| CA000527374A CA1261923A (en) | 1986-01-15 | 1987-01-15 | Variable color digital multimeter |
| CA000563216A CA1252236A (en) | 1986-01-15 | 1988-04-05 | Variable color display device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000527374A Division CA1261923A (en) | 1986-01-15 | 1987-01-15 | Variable color digital multimeter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1252236A true CA1252236A (en) | 1989-04-04 |
Family
ID=25671199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000563216A Expired CA1252236A (en) | 1986-01-15 | 1988-04-05 | Variable color display device |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1252236A (en) |
-
1988
- 1988-04-05 CA CA000563216A patent/CA1252236A/en not_active Expired
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