CA1244088A - Fault simulation for differential cascode voltage switches - Google Patents

Fault simulation for differential cascode voltage switches

Info

Publication number
CA1244088A
CA1244088A CA000499773A CA499773A CA1244088A CA 1244088 A CA1244088 A CA 1244088A CA 000499773 A CA000499773 A CA 000499773A CA 499773 A CA499773 A CA 499773A CA 1244088 A CA1244088 A CA 1244088A
Authority
CA
Canada
Prior art keywords
switch
output
gate
tree
boolean
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000499773A
Other languages
English (en)
French (fr)
Inventor
Zeev Barazilai
Vijay S. Iyengar
Barry K. Rosen
Gabriel M. Silberman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1244088A publication Critical patent/CA1244088A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
CA000499773A 1985-03-08 1986-01-17 Fault simulation for differential cascode voltage switches Expired CA1244088A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/709,612 US4727313A (en) 1985-03-08 1985-03-08 Fault simulation for differential cascode voltage switches
US6-709612 1985-03-08

Publications (1)

Publication Number Publication Date
CA1244088A true CA1244088A (en) 1988-11-01

Family

ID=24850590

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000499773A Expired CA1244088A (en) 1985-03-08 1986-01-17 Fault simulation for differential cascode voltage switches

Country Status (5)

Country Link
US (1) US4727313A (de)
EP (1) EP0193811B1 (de)
JP (1) JPH087253B2 (de)
CA (1) CA1244088A (de)
DE (1) DE3688437T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4935646A (en) * 1989-02-22 1990-06-19 International Business Machines Corporation Fully static CMOS cascode voltage switch logic systems
EP0508620B1 (de) * 1991-04-11 1998-05-20 Hewlett-Packard Company Verfahren und System zur automatischen Bestimmung der logischen Funktion einer Schaltung
US5260952A (en) * 1991-04-30 1993-11-09 Ibm Corporation Fault tolerant logic system
US5299136A (en) * 1991-06-05 1994-03-29 International Business Machines Corp. Fully testable DCVS circuits with single-track global wiring
US5815687A (en) * 1996-09-19 1998-09-29 International Business Machines Corporation Apparatus and method for simulating domino logic circuits using a special machine cycle to validate pre-charge
DE19710463C2 (de) * 1997-03-13 1999-02-25 Siemens Ag Verfahren zur automatischen Differentiation auf einem Rechner insbesondere zur Simulation elektronischer Schaltungen
US6012157A (en) * 1997-12-03 2000-01-04 Lsi Logic Corporation System for verifying the effectiveness of a RAM BIST controller's ability to detect faults in a RAM memory using states indicating by fault severity information

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3715573A (en) * 1971-04-14 1973-02-06 Ibm Failure activity determination technique in fault simulation
US4204633A (en) * 1978-11-20 1980-05-27 International Business Machines Corporation Logic chip test system with path oriented decision making test pattern generator
DE3221819A1 (de) * 1982-06-09 1984-02-23 Siemens AG, 1000 Berlin und 8000 München Vorrichtung zur simulation eines schaltwerks mit hilfe eines rechners

Also Published As

Publication number Publication date
EP0193811B1 (de) 1993-05-19
EP0193811A2 (de) 1986-09-10
JPH087253B2 (ja) 1996-01-29
JPS61207976A (ja) 1986-09-16
US4727313A (en) 1988-02-23
DE3688437D1 (de) 1993-06-24
EP0193811A3 (en) 1989-04-26
DE3688437T2 (de) 1993-12-23

Similar Documents

Publication Publication Date Title
Wadsack Fault modeling and logic simulation of CMOS and MOS integrated circuits
EP0229975B1 (de) Verfahren zur Modellierung und zur Fehlersimulation von komplementären Metalloxidhalbleiterschaltungen
Jain et al. Test generation for MOS circuits using D-algorithm
Hayes Fault modeling.
Hayes A unified switching theory with applications to VLSI design
Reddy et al. A gate level model for CMOS combinational logic circuits with application to fault detection
Ke et al. Synthesis of delay-verifiable combinational circuits
Ma et al. A comparison of bridging fault simulation methods
Bose et al. A fault simulator for MOS LSI circuits
CA1244088A (en) Fault simulation for differential cascode voltage switches
JP2715956B2 (ja) Ｉｄｄｑを用いたＣＭＯＳ論理回路の故障箇所の絞り込み方法
Ruiz et al. Switch-level fault detection and diagnosis environment for MOS digital circuits using spectral techniques
Shih et al. Transistor-level test generation for physical failures in CMOS circuits
Alt et al. Simulation of non-classical faults on the gate level-fault modeling
Ramachandran An improved switch-level simulator for MOS circuits
US5341314A (en) Method for generating a test to detect differences between integrated circuits
Favalli et al. Modeling of broken connections faults in CMOS ICs
Favalli et al. Fault simulation for general FCMOS ICs
Zhang et al. A neural network algorithm for testing stuck-open faults in CMOS combinational circuits
Giambiasi et al. SILOG: a practical tool for large digital network simulation
Ferguson Detection of multiple faults in MOS circuits
Rubio et al. An approach to the analysis and test of crosstalk faults in digital VLSI circuits
Menon et al. Fault modeling and testable design of 2-level complex ECL gates
Lala et al. Design of a fault-tolerant universal cell
GAULT The application of fault indistinguishability in combinational networks

Legal Events

Date Code Title Description
MKEX Expiry