CA1221461A - Document processing system and equipment - Google Patents

Abstract

DOCUMENT PROCESSING SYSTEM END EQUIPMENT
ABSTRACT
A document processing system including a digital image capture system, character recognition circuitry, document encoding systems, endorsers, audit trail printers and an in-line microfilm record system enable documents to be read, endorsed, encoded, digitally imaged, filmed and sorted in a single continuous pass through the document processor by way of a modular transport system.
The encoding of the continuously moving documents is accomplished by a plurality of fixed dies, electronically controlled hammers, and an ink bearing ribbon interposed between the documents and the fixed dies, the ribbon being momentarily transported at the same velocity as the documents.
Scanning and digitizing of the documents is effected by continuously transporting the documents across the focal plane of a stationary scanner where the documents are repetitively scanned in a single axis, two scanners being employed to permit scanning and digitization of both sides of a particular document in a single pass through the transport mechanism. Circuitry is included in the scanner which permits the presence or absence of a document to be detected and allows dynamic adjustment of threshold levels, thereby accomodating documents which utilize shaded backgrounds.
The system includes apparatus for visually displaying an image which corresponds to a plurality of stored digital values, the apparatus including an image memory and circuitry enabling the display to be partitioned into discrete portions of variable sizes, each portion of which may be utilized either to display a selected portion of the image within the image memory or to display a plurality of alphanumeric characters. Additionally, circuitry is provided which allows image rotation, mirror imaging and discrete video attribute selection within each portion of the display.

Video data compression apparatus and method are employed for use in minimizing the amount of data necessary to store and recall a black and white video image. An image initially obtained by vertically scanning a selected document is represented by a series of consecutive vertical scans identifying particular sections or cells of the image as black or white.
A plurality of consecutive scans are then temporarily stored and analyzed horizontally, analysis circuitry being utilized to identify certain consecutive black or white sections of the image, repetitions of previous sections of the image or repetitions of certain selectable patterns within the image.
The coded output of the analysis circuitry is then stored and utilized to reconstruct the image.

Description

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!j 13ACKGRO~ND OF T1113 II~V~Nri'ION
This invention relates to document processing systerns in general, more particularly to document processing systerns I aclapted to be utilized in the processing of f:inancia]. documents such as checks, invoices, payment advices, vouchers, dra~ts, credit card charges and the'like, and even more particularly to improved document encoders, scanners, digital image processors, and video image data compressors particularly useful in the l document processing system.
¦ Document processors which read and sort financial documents have been in common use for some time; however, ¦ various other functions which are necessary to most financial operations have been relegated to separate sub-systems or Il specialized processors to prevent major bottlenecks in the 1¦ document processing system. Among the peripheral functions ¦l which have not, in the past, been accomplished by the primary ¦¦ document processor are encoding with magnetic ink, microfilming ¦ and endorsing. Additionally, state of the art document pro-1~ cessors utilizing digital imaging still require manual transfer 1l of documents to other processors to accomplish traditionally ¦l slower speed operations such as encoding, thus resulting in I . - , ;
¦ lower e~ficiency in processing and increased probabil.ity of ! errors, I An effective document processing system desirably 1 utilizes an effective document encoder. State of the art encoders typically fall into two general categories. The first category of encoders includes those encoders which utilize , a step function to position the document to be encoded at ! a particular point. Such encoders function in a manner typically associated,with ty~ewriters or other mechanical printers and are not generally compatible with high speed document processors. A second category of document encoders, including laser printers and ink jet printers, while capable , , of encoding continuously moving documents is nonetheless incom-,, patible for use with modern financial document processors.
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j Document processing systems also desirably re~uire efEective means of image s-torage. Early atternpts a~ image storage utilized so-called "hard copy" image ~torage such as microficlle, microfilm or reduced photocopies. More recently, I document images have been obtained utiliæing electronic video equipment, and still more recently, utilizing digital elec-I tronic video equipment.
,¦ Typically, in a digital document image capture system, Il a moving document is repetitively scanned in one axis and ~ individual sections of the documents are assigned a value as either a "black" or "white" section, as a result of a comparison with an arbitrarily assigned reference valueO This simplistic il approach to rendering a document image into a series of "black"
Ii or "white" sections is sufficient for many applications;
!! however, if the system must operate upon multihued documents, ¦l such as personal checks, it is possible that the background ¦i color of a particular document may exceed the reference value, il and therefore may result in the entire image undesirably being j, classified as "black".
I Further, an optical sensor is typically utilized to !i detect the presence of a document prior to the initiation of il digitization in such known systems. This additional piece of Il electronic equipment provides a possible source of error, in ¦l that a malfunction of the optical sensor may result in a il document passing through the system without being scanned.
Digital image processing for creating visual images from digital data is known. Typically, state of the art systems display an entire image corresponding to the digital Il values stored in memory. More sophisticated systems utilize 1l video displays with permanently established boundaries between two sections oE-a display and separate images assigned to each ,¦ section, in order to visually compare one image to another.
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I ~s the compl~xity oE such sys-tems increases and ~he c1em.ll)(1s ¦1 upon digital image processors grow to include such state o~ the ~1 art devices as laser printers, the need continues to exist ¦¦ ~or more sophisticated and ~lexible digitAl imagQ proce~ing 1I systems, particularly in ~inancial document processor systems.
I! An effective document processor desirably includes video image data compression apparatus. Specifically, in circumstances in which it is desired to store or recall a ', plurality of video images, the ma~nitude of data required for , each individual image makes data compression a highly desired ¦¦ feature. ~
¦ Known data compression schemes which are utilized in conjunction with black and white document images typically 1 involve a scan which is perpendicular to the direction of j document travel. Scan data is then analyzed and long consecu-tive black or white sections are removed and replaced with coded substitutes. In more sophisticated data compression schemes t scan data is analyzed and repetitive patterns ,j containing both black and white sections may be encoded and , removèd. Present apparatus, however, is not completely acceptable, particularly for an effective document processor i! system.

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SUM~ Y OF 'IIIE INV~NTION
~1 ~ccordingly, it is a principal object o~ ~he present ¦¦ invention to provide an improved financial document processor.
ll It is another ob~ect oE the present invention to 1' provide an improved financial document processor which utilizes a modular transport system and combines all required operations ¦ into a single document processor.
j! It is yet another object of the present invention to provide an improved document encoder capable of encoding 0 l1 continuously moving documents. I

il It is another object of the present invention to provide ¦
an improved digital document image scanning system with a variable reference value being utilized for blac~/white decisionsl l It is another object of the present invention to provide ¦
!1 an improved digital image processing system.
I¦ It is another object of the present invention to provide a video data compression system which provides a higher degree of data compression than known systems. I
,l In accordance with these and other objects, the inven- , 20 1l tion, briefly described, is directed to a document processing system which comprises a modular transport system including a digital image capture system, character recognition circuitry, !
document encoding systems, document endorsing systems, audit !i trail printers, an in-line microfilm record system and a high 25 1i speed document sorter. Associated video terminals and non-1ll impact printers such as laser printers are utilized to provide ¦! visual images of documents processed by the system. Selected documents may be read, endorsed, encoded, annotated with an Il audit trail indicia, digitally imaged, filmed and sorted in a 30 ¦¦ single continuous pass through the document processing system ¦l of the present invention. I

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For encodillcJ, the documcn~s are transported between a plurality of ~ixed dies and a plurality of electronically controllecl hammers. A ma~3entic ink bearing ribbon is interposed Il between the documents and thc fixed dies and i5 transpo~ted at 5 1I the same velocity as the documents. As the documents itraverse j the plurality of fixed dies, the electronically controlled hammers are cycled, in a selected sequence and at selected positions. In thos applications in which the cycle time of the ,1 electronically controlled hammer is too slow to allow identical il encoding in adjacent positions, a second plurality o fixed ¦' Il dies and associated electronically controlled hammers may be ¦¦ located adjacent to the first 'plurality or interspersed ¦ among the first plurality of fixed dies.
¦ As further described, the documents are continually 1 transported across the focal plane of a stationary scanner, ' ¦l and repetitively scanned in' a single axis. Circuitry is 1, included in the digital scanner which permits the presence or il absence of a document to be detected by means of an evaluation 1 of the output of the digital scanner. Additional circuitry in '! the digital scanner allows a dynamic adjustment of reference levels, thereby 'accommodating multihued documents which may 1, utilize shaded backgrounds.
i, A digital image processing system includes an image !l memory and circuitry enabling the display to be partitioned - 25 1 into discrete portions of variable sizes, each portion of which ! may be utilized either to display a selected portion of the ' image within the image memory or to display a plurality of Il alphanumeric characters. During alphanumeric character mode, 1~ coded representations of each alphanumeric character are 30 li stored in the image memory, in an appropriate section.
Alternately, selected portions of one document image may be visually compared to selected portions of a second document image by u~ilizing this display partitioning feature. Addi-tionally, circuitry is provided which allows image rotation, 35 , mirror imaging ancl discrete video attribute selection ~ithin I each portion of the display.

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, In accordance with an improved dat~ comyr~s,sion scllerrle, Ij an image is obtained by vertically scannin~ a selected document. , 1, j~ The image is then represented by a series o~ consecutive verti-¦l cal scans identifying particular sections or cells of the irnage ~j as either black or white. A plurali-ty of consecutive scans t are then temporarily stored and analyzed hori~ontally, Analysis ' circuitry is utilized to identify certain consecutive white or black sections of the image, repetition of previous sections of jl the image, or repetition of certain selectable patterns within 1i the image. The coded output of the allalysis circuitry is then stored and may be utilized to reconstruct the image of the ¦ financial document.
According to one broad aspect of the invention~ it comprises an apparàtus for processing documents comprising:
' means for transporting a series of continuously moving documents along a selected track; means disposed adjacent to said selected track for selectively encoding machine readable data upon selected ones of said documents; means disposed adjacent to said selected track for reading machlne readable ` data encoded upon selected ones of said documents; and means , disposed at l~e cnd of said track for sorting sald d~cuments.

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Another broad aspect of:the invention is a digital document scanning system comprising: cligital scanning means including a fixed array of photoelectric transducers arranged to scan in a selected axis alony a fixed focal plane; transport means for transporting a continuously moving series of variegated documents along said fixed focal plane; means for generating a first output signal when a selected output of said fixed array of photoelectric transducers is above a reference level and a second output,signal when said selected output of said fixed array of photoelectric~ transducers is below said reference levelj and means responsive to the outputs of said fixed array of photoelectric transducers for adjusting said reference level.

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,, !~BRIEF D~.SCRIPTION OF TIIE D~W'LNGS
The novel ~eatures believed characteristic of the invention are set forth in the appended claims. The inven-. I tion itself; however, as well as a preferred mode of use, ¦Ifurther objects and advantages thereof, will best be under-¦~stood by reference to the following detailed descr.iption of an illustrative embodiment when read'in conjunction with the ,accompanying drawings, wherein:
I¦ Figures la and lb form a general block diagram oE
ilthe document processing sy'stem of the present invention;
Figure 2 depicts a diagrammatic view of the docu-¦ment transport of the document processing system of the ~present invention;
Il Figure 3a depicts a block diagram of the encbder llof the document processing $ystem of the present invention;
Figure 3b depicts a diagrammatic view of'the ¦encoder of the document processing system of the present ,linvention;
¦1 ' Figure 4 depicts a diagrammatic Vie~ of the en-1i dorser of the document processing system of the present invention;
Figure 5 depicts a diagrammatic view of the camera ,¦system of the document processor of the present inVention;
Ij Figures 6a-6i depict a schematic view of the llcomponent,s of the camera buffer and interf~ce circuitry of the document processor of the present invention;

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i i Figures 7a-70 and Figures 8a~80 depict a schematic view of ~he component6 oE the data compress.ion sys~em o~ the i document processor of the pre~ent invention;
. I Figures 9a-9b depict a block diagram o~ the major !5 1¦ components o~ the data expansion system of the doeument processor of the present invention;
Figure 10 depicts a detaile'd block diagram of the ! video terminal subsystem o the document processor of the l present invention; and 10¦ . Figures lla-llo and Figures 12a-12q depict a ~¦schematic view of the video formatter of the doeument ¦jprocessor of the present invention.
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Il GENERAL SYSTEM DESCRIPTION
1 Referring to Figures la and lb, there is depicted a general block diagram of the various subsystems comprising the document processing,system whieh embodies.,the present invention. ~, l The document processing system is'controlled by 20j digital computer 100. Digital eomputer lOO coordinates the storage and retrieval of digitized document images and l associated data which are stored, in the disclosed embodi-.1 ment, in magnetic disk storage. Disk controller 102 con-. ¦ trols the actual access o digitized document images via 251 disk drives 104, 106, and 108. Additional data, accounting information or program data may be accessed by'digital ¦computer lOO hro~gh t-pe controller llO which controls ' ; . , , ~ , '. I
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magne-tic tape drives 112 and 114. It will be appreciated by those ski.lled in the art that disk controller 102 and tape controller 110 may control an increased or decreased number of disk or tape drives, as a matter o design choice.
¦IDigi~.al computer 100 may selectively access either magnetic disk storage or magnetic tape skorage through channel se-lector 116.
Digital computer 100, in the embodiment disclosed, interfaces with a local operator via the computer I/O bus 1 and prin-ter interface 118. Printer interface 11~ controls ¦ line printer 120. In alternate modes of operation wherein I remote communication with digital computer 100 is desired, a ¦ modem and appropriate interface circuitry may be utilized.
¦ Digital computer lOO also controls the operation 1 of laser printer subsystem 124, through laser printer inter-¦ face 122. Laser printer subsystem 124 is utilized to provide hard copy of selected digital images and may be utilized to ¦generate account statements, billing statements, or other l¦correspondence comprising any combination of alphanumeric ¦¦ characters and images. The operation of laser subsystem 124 ¦is described in greater detail herein.
Video terminal subsystem 136 is utilized in the document processing system of the present invention to provide a real time, controllable video display of selected l¦documents and alphanumeric information. The display is utilized to facilitate processing of information on each document. Digital computer 100 controls the operation of l .
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¦Ivideo terminal subsystem 136 through buffer interEace 144 and synchronous data lin]c control master 146. A plurality of video display termi'nals may be utili~ed with each SDLC
l master, in a manner which will be explained in detail below.
I High speed transport subsystem 1~8 is utilized to transport individual documents through imaye capture sta-tions, machine readers, encoders and sorters.' A plurality of high speed transports may be utilized within each docu-l ment processing system, thereby increasing the capacity of 1 an individual system. High speed transport system 148 is controlled utilizing buffer interface 156 and synchronous data link control master 15~. High speed transport system 148 will be explained in greater detail with respect to Figure 2.
1l Digital image data obtained from the digital camera or cameras installed in each high speed transport is , transferred to camera interface 160. Camera interface 160 is described in detail ~ith reference to Figures 6a through I 6i and is utilized to couple the image data to digital image I compactor 162. Digital image compactor 162 is utilized to ' remove any redundancies contained in a selected image and to encode the remaining data. In addition to the specific algorithm taught in the disclosed embodiment, the document l processing system of the,present invention will function I with other known data compaction algorithms, such as, for example, the CCITT standard algorithm. The thus compacted digital image will require substantially less storage space . 1.
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in tl~e docunl~nt processing syste3n. The compacte~ im~ge d3ata may ~e tr~ns~err~d to storage via multiplexe~ dir~ct melllt)~y access lG4 and 3nultiplexed direct melnory access 1~6. T~JO ¦ :
,direct memory systems are utilized in order to'provi(~ , compatible interfaces between the local X bus and the direct memory access interface bus of digital computer 100.
~ Retrieval and display of a compacted digital image may take place i~ several ways. A compacted image is trans-j ferred to the local X.bus via'direct memory access 1~4 and .
direct memory access 166, The compacted image is apyl.ied to ;digital image expander 168. The redundancies present in the ,original image are restored and the subsequent image is transferred via X bus distributor 170 or X bus distributor 172 to either laser printer subsystem 124 or video terminal jsubsystem 136 for reproduction of a hard copy or an elec-tronic image.

DIGITAL COMP~TER
The document processing system of the preferred embodiment of the present invention utilizes' a digital computer 100, Figure l, to control the operation of the system and coordinate the storage and retrieval of document images. In a preferred embodiment of the present invention, digital computer 100 was actually constructed utilizing a .
.;Series 3200 minicomputer, manufacture~ by the Perkin-Elmer .
Compater Syst~ms Division of Oceanport, Wew Jersey.
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l'he Model 3242 minicomputer utilizes 32-bit - l¦architecture and a 32-bit operating system. The main memory ;¦storage, in the embodiment disclosed, contains lS36 kilobytes l¦of 150 nanosecond MOS memory. Supplementing the computer's main memory store are disc drives 104; 106 and 108, Figure l 1, Model 9775 manufactured by Control Data Corporation of I Minneapolis, Minnesota, and tape drives 112 and 114, Figure 1, Model TPAC 4516, manufactured by Perkin-Elmer of Ocean-~lport, New Jersey.
Digital computer 100 also includes a rechargeable ,Ibattery backup system ~not shown) to sustain the main memory jin the event of a power failure. The preferred embodiment jlof digital computer 100 utilizes a battery rated at 320 megabyte minutes, which is capable of maintaining the memory l¦integrity of 16 megabytes for twenty minutes.
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j DOCVMENT TRANSPORT
,j Referring now~to Figure 2, there is depicted a ildiagrammatic plan view of document transport 200. Document 1 20 ''transport 200, in a preferred embodiment, is a specially ¦built transport which may be modified to include additional ' equipment or to exclude undesired capabilities. The trans- ¦
- ¦Iport constructed and depicted in Figure 2 utilizes high ¦speed endless belts which are driven by pinch rollers in the ¦Imanner well known in the art. The pinch rollers are driven by syncl-ronous AC motors at a nominal speed of 52 inches per !l ' Il .
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second in the disclosed embodiment. Sect:ions of the trans-port may be driven at different speeds in a manner described below.
Documents are loaded into document transpork 200 by means o~ ~ocument hopper 202. Single documents are loaded from document hopper 202 via feed drum 204. 'I'he documents are then passed along document transport 200 between rollers and the endless belts (not shown).
~ The first seetion of document transport 200, l¦ reader section 206, includes an optical character reader 208 and a magnetic ink eharacter reader 210. Those skilled in i the art will appreciate that a single model optieal reader, i such as the 30-250 ips read head manufaetured by Input ~usiness Maehines, Incorporated of Rockvilla, Maryiand, can , Eunction as either an OCR reader or may be utilized to op-i tically read MICR charaeters with appropriate eontrol elec-¦ tronies. OCR reader 208 may be utilized in the applications ¦ wherein the amount field or other information is printed in I an OCR format.
O I The next seetion of doeument transpor~ 200 is eneoder seetion 212. Eneoder seetion 212 includes hammer bank assembly 214 and die and ribbon assembly 216 and is utilized to eneode seleeted doeuments with seleetable indicia, while the doeument is traversing document transport 200. The operation o~ the eneoder section will be explained in greater detail with reference to Figure 3.
Section 218 of document transport 200 is the endorser section. Endorser section 218 eontains ink jet l -10-~ Z1~61 llprlnters 220 and 2~2 and endorser 224. Ink jet printers 220 I! and 222 are standard state of the art ink jet printer~ that ~ImaY be utilized, in the disclosed embodiment, to print llselected indicia upon each document which passes through ll document transport 200. The selected indicia may be util-l¦ized to assist in audit trail functions or in any other ,¦function desired. Endorser 224 is utilized to endorse ! documents such as chec~s. The structure and o~eration of l¦endorser 224 will be explained in greater detail with l¦respect to Figure 4.
~j The next section in document transport 200, through ! which each document is transported, is camera section 226.
¦ Camera section 226 contains, in the embodiment disclosed, l two digital video cameras, 228 and 234 and two illumination l¦ sources, 230 and 232. Each document which passes through '¦camera section 226 is scanned on both sides utilizing video llcameras 228 and 234. The operation of camera section 226 is ,jexplained below with refcrence to Figures 5 and 6.
- ,j The penultimat~ section of document transport 200, ,Imicrofilm se.ction 236, contalns a microprocessor controlled - ''microfilm recorder 238. Microfilm recorder 238 is described ;in greater detail below, and is utilized to provide hard - jlcopy of selected documents which have been processed by the llsystem of this invention. Microfilm recorder 238 is capable 11 f accurately recording documents traveling at greatex rates ¦f speed than that.present in earlier sections of document Itransport 200, and as a consequence, the transport speed is ' ' ' l .

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i ¦lincreased in microfilm section 236 to a nominal speed of 100 inches per second. This l:ransition is accomplished by I utilizing a slipping drive at the interface between micro-l film section 236 and camera section 226. Thus, while a j portion of a document is still traveling at a nominal speed of 52 inches per second in camera ssction 226, the slipping drive (not shown) in micro~ilm sectio~ 236 allows the lldocument to slip until fully released.
¦¦ The final section o document transport 200 is 1 stacker section 240. Stacker section 240, in any manner well known in the art, sorts the documents processed through ¦document transport 200 into one of several pockets. The ¦¦number of pockets is, of course a design choice wholly !¦ dependent upon the application desired. ! .
!1 As those skilled in the art will appreciate the ! modularity of design employed in document transport 200 will allow great flexibility in many applications. Whole sections l1f document transport 200 may be deleted or rearranged to ilpermit a wide variety of custom applications. Further, the I number and type of devices within each module may be increased ¦or decreased as a matter of design choice.

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¦ ENCODER
Il With reference now to Figure 3a, there is depicted ! a schematic view of encoder 300 of the present in~ention.
IlAn important feature of the present invention is an ability ilto encode continuously moving documents. In known document .1 ~

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l i processing systems document encocling proves to be the major ¦ bottleneck to high speed processing. Typical solu~ions have ¦lincluded a scparate slower portion of the document processor ¦~in which a document is stepped through an encoder, or a I separate off-line encoder. Document encoder 300 is capable ¦ of encoding documents which are continuously moving at the i rate of the documen-t processing system o~ the present inven-tion.
Document encoder 300 utilizes, in the illustrated llembodiment of the present invention, two identical electro-magnetic hammer banks, hammer bank 302 and hamMer bank 304.
It will be apparent, however, upon reference to the fore-going explanation, that a fewer or greater number of ha~ner l banks may be utilized in systems wherein slower or faster , transport speeds are desired. Hammer banks 302 and 304 are ¦ electromagnetic hammers such as part no. CCE-05-306 manu-factured by Dataproducts, Woodland Hills, California. Each hammer bank is controlled by a hammer driver~ In the dis-l closed embodiment, hammer driver 306 controls hammer bank ¦ 302 and hammer driver 308 controls hammer bank 304. Hammer ! power supply 310 provides operating power for all hammer drivers alld hammer banks.
Positioned opposite each hammer bank is an ap-l propriately encoded die. The selection of characters util-! ized in a particular application is strictly a design choice and may include OCR characters, MICR characters or any other ¦ desired cl~ racter pattern. The illustrated emoodiment ' ' , '' '' '.
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¦¦.includes two substantially identical die sets, die set 312 ¦¦and die set 314. Ilowever, as a matter of design choice, a ilsingle die set may be utilized. A1BO included in the illus-¦trated embodiment is microprocessor control 316, which ~provides control si.gnals to hammer drivers 306 and 308 in ¦IresPonse to signals from optical sensor 318. Optical sensor 318 is utilized to detect the presence of a document along . document path 320. Ribbon mechanism 322 is also depicted in .1 Figure 3a, and will be explained in greater detail with 1 reference to Figure 3b.
Figure 3b depicts a partially diagrammatic view of ¦ the major components of document encoder 300. AS explained above, hammer banks 302 and.304 selectively strike portions l~of die sets 312 and 314, upon receipt of control signa~s ¦Igenerated by a microprocessor control 316 (see Figure 3al, I! in conjunction with an item presence signal generated by ¦optical sensor 318.
,¦ Ribbon mechanism 322 (Figure 3a) is shown in il~reater detail in Figure.3b and includes a ribbon supply lireel 324, ribbon takeup reel 326, ribbon tensioning arms 333 and 332 and ribbon capstan 338. Ribbon supply reel 324 provides a fresh supply of magnetic ink ribbon 340. Such ! magnetic ink ribbons are typically single strike ribbons, Ithat is to say the magnetic ink associated with each char-lacter is totally removed from the ribbon during the printing ~f that character.and further attempts to print utilizing the same section of ribbon.340 will result in in~alid ., . . .

magnetic signatures. There~ore, it is necess~ry to advance l maynetic ink ribbon 340 aft~r each character is printed, and ¦lit is advantageous, from an economy standpoint, to advance ¦ ribbon 340 only while a document i5 present in encoder 300.
! This is accomplished utilizing ribbon capstan 338 which is ¦ electronically controlled by microprocessor control 316 l during those periods when a document is detected by optical I sensor 318. For reasons which will be explained below, I ribbon 340 is driven by ribbon capstan 338 at the same speed ¦ as documents on the transport. The rapid acceleration of l ribbon 340 to transport speed is accomplished without ¦ damage to ribbon 340 utilizlng ribbon tensioning a~ms 330 I and 332. Ribbon tensioning arms 330 and 33Z are pivotally ! mounted at point 342 and resiliently biased utllizing!
l¦springs 334 and 336. A rapid acceleration of ribbon 340 is 'I then absorbed by ribbon tensioning arms 330 and 332 until ¦I ribbon supply reel 324 and ribbon takeup reel 326 can 1l compensate. ~ j 'I In operation, encoder 300 utilizes two character il sets to compensate for the duty cycle of the hammex bank i1 utilized. Each individual hammer within hammer banks 306 Ij and 308 has a duty cycle of approximately .004 seconds.
jl Document encoding standards for MICR require individual I characters to be encoded approximately one eighth inch ! apart, or one-tenth inch spacing for OCR. At a nominal I transport speed of SZ inches per second, a document will travel one-eighth iAch in approxim-tely .0024 eFonds. It 1, , ' . .

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should therefore be apparent that with a duty cycle of .00~
seconds, a single hammer and die combination will be unable l to repetitively strike a single character at one-eighth inch ¦ intervals. Thus, the use of multiple hammers and substan ;Itially identical character sets will allow full encodi'ng at the present duty cycle. Consider a possible worse case ~ analysis, a desired encoding of eight consecutive identical ! characters. Those skilled in the art will appreciate that a lisingle hammer and die will be able to encode alternate digit ,Ipositions at the stated speed of operation. The second ' groùp of hammers and characters allows encoder 300 to fill in the missing digits. More specifically, hammer bank 3Q6 and die set 312 may encode the odd'digit positions in a ldesired field, and hammer bank 308 and die set 314 may!
;lencode the even digit positions. Thus, it should be appar-¦ent that increased or decreased transport speeds may be ~laccommodated by utilizing'a greater or fewer number of ,Ihammer banks and die sets, without requiring a faster duty ,¦cycle for individual hammers. It should also be apparent j~that since certain portions of a particular diglt field may be encoded by one hammer bank while other postions may be encoded by a second hammer bank, it will be advantageous to maintain ribbon 340 at the same speed as the documents l passing through encoder 30Q. By so doing, the'used portion 1 of ribbon '340 associated With a p~rticular c~aracter'will 'Imaintain its relative position directly above that partic-¦¦ular character on the ocument.

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ll ~NDORSER
l Referring now to Fig~re 4, a cutaway view of the I major components of endorser mechanism 400 is depicted. A
ilsection of a document 402 is shown on document path 404.
ll The belt drive mechanism which transports document 402 along ¦document path 404 is not shown.
Il Ink roller 406 is mounted in bracket 408, which ¦Imay be pivoted upward at pivot point 410 to allow replace-l¦ment of ink roller 406. Additionally, pressure adjuster 412 , may be utilized to adjust the amount of pressure exerted by ! ink roller 406 upon transfer roller 414.
! Transfer roller 414 is mounted in tangential - !Iproximity to endorser plate 416 and is utilized to transfer ¦¦ink to endorser plate 416 from ink roller 406. Transfer 1¦ roller 414, endorser plate 416 and platen 418 are all driven ilby belt 420 and belt 422 and drive pulley 424; however, ¦lelectronically controlled clutch 426 is utilized to selec-itively engage endorser plate 416. Thus, when it IS desired ! to endorse a sèlected document, ink is transferred to en~
li dorser plate 416 and electronic clutch 426 is energized, urging endorser plate 416 into contact with platen 418 and rotating endorser plate 416 and platen 418 at an apprQpriate speed.

! Electronic clutch 426 is controlled, in a pre-¦ ferred emhodiment, utilizing an appropriately programmed microproce sor type device. Tlerefore, doc~ments may be 1 . ' " '. ' " ' .
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I¦ VIDEO CAMERA
~ Figure 5 depicts a diagrammatic view of a system utilizing two video cameras 500 and illumination sources 502 whereby the image on both sides of a ~ocument may be cap-tured. Each illumination source 502 is comprised of two 500 llwatt tungsten halogen bulbs, encased in a housing having ,~cooling means and an optical focus assembly 504. Optical ¦¦focus assembly 504 comprises à plurality of lenses arranged, ¦in any manner well known in the art, to focus a vertical bar ¦of intense light onto document plane 506. In the embodiment ¦disclosed, the vertical bar is generally rectangular in ¦Ishape and is approximately six inches tall and one tenth of l~
~! an inch wide. As discussed above, documents are transported laterally across this illuminated portion to enable video ¦image capture. , I The light reflected from each document passes 2G il through each eamera lens assembly 508 and is focused on line , scanner 510. Camera lens assembly 508 is a fixed magniri- ¦
cation ratio lens typically utilized in fixed working dis-~¦tance applications such as photographic enlargers. Line llscanner 510 is a solid state line scanner such as those !I commercially available from the Reticon Corporation of ! Sunnyvale, California. Line scanner 510 is a high ~ensity, ,¦monolithic, linear array of silicon photodiodes with ,1 . ' . '' '/ . ' .
!! , . . .
I '' ',, '''' ~

il - 1 8 -l~Z1~6~

l lntegrated scanning circuits for serial readout. The array, t in the embodimen~ disclosed, conaists of a row of 768 silicon photodiodes, having a storage capacitor associated therewith Ilupon which may be integrated the photocurrent r and a tran-jisistor switch for periodic readout via an integrated scan-ning circuit. The individual photodlodes of line scanner 510 are one mil square and are spaced center-to-center, one mil apart. ' l During image capture r a document is transported ,llaterally across the vertical bar of light generated by each ¦illumination source 502. Each camera lens assembly 508 ;focuses the reflected light from the document onto line l,scanner 510. Each of the 768 silicon photodiodes contained t~within line scanner S10 produces an electrical signal which ; 15 ~¦is proportional to the intensity of the incident light. The ¦¦photodlodes are then sampled at a'high rate, the line ¦¦scanner u~iliz~d in t,he preferred embodiment may,be sampled l¦at frequencies as high as ten megahertz. The combination of !I the lateral motion of the document and the vertical action l,of se~uential sampling'of the photodiodes in line scanner ,l510 will produce a two dimensional picture of a document ;,with a resolution within .007 of an inch. I
Il .
, The output of line'scanner S10 is amplified and I coupled to additional circuitry as a series of pulses where-, in the area of each pulse is proportional to the intensity ! of the incident light on each photodiode. This series of pulses i utilized in the camera coltrol ~ircuitry to sense , '' " '' .
l . . . .
,1 . . . .
il . ' ' .

11 ~2;21l~
Il . . , .
;¦the presence of a document and to dynamic~lly adjust the threshhold level utilized ~o determine whether a particular value is white or black. The series of pulses is also applied to the data compression system for compression, .
l¦storage and subsequent retrieval. .
. .
C~MERA BUFFER AND INTERFACE CIRCUITRY
! With reference now to Figures 6a-6i, there is l depicted a schematic view of the ma~or components of the ¦camera buffer and interface circuitry of the.document !~processor of the present invention. While the dlsclosed ; ~¦embodiment of the present invention utllizes two video cameras, in many cases only one set of buffer and interface l circuitry will be depicted. Those ordinarily skilled.in the ! art will appreciate the simple duplication of circuitry ¦Inecessary to accomodate two video cameras.
ll Referring now to Figure 6a, oscillators 601 and !! 602 are utilized, in conjunction with the basic cloc~ signal !1~30..5 megahertz in a preferred embodiment) to provide the ! scanning pulses to line scanner 606. Oscillators 601 and l602 are implemented, in a preferred embodiment of the pres-i! ent invention, utilizing standard 74S74 type flip-flop - 'lintegrated circuits. The control pulses necessary to oper- ¦
l¦ate line scanner 606 are applied via amplifiers 603, 604 and I 605, which are utilized to provide level adjustme.nts. Line ! scanner 606, in the illustrated embodimentj is an RL-768C
l~int-gratec circuit manuf~otured by the Re~ico~ Corporation .1~ . ''' '' ~I , . .
Il . . .
,1 I! -20-li . I
I of Sunnyvale, California. Additional ~etails concerning the ¦¦construction of line scanner 606 are disclosed above with llrespect to the v.ideo camera description. Line scanner 606 ¦¦is scanned at a parallel rate of three megahertz. That is, jlthe odd numbered cells in line scanner 606 are scanned at a ¦¦three megahertz rate and the even numbered cells are also ¦scanned at a three megahextæ rate! Thus, line scanner 606, ¦with proper multiplexing of the ~ual outputs, is capable of l generating video pulses at: a six megahertz rate.

1 Even cell and odd cell outputs of line scanner 606 are applied to amplifiers 611 and 610 respectively. Ampli-l¦fiers 611 and 610, in conjunction with capacitors 607 and ,¦608, are utilized to capture the output of each individual scan cell. Switching transistor 609 is utilized to alter-',nately remove all charge accumulated on capacitors 607 and 608 between sampling times for adjacent cells of line scan-l ner 606. The RESET signal accomplishes this and is appliedi to switching transistor ,609 through inverter 612.
ll The outputs of amplifiers 610 and 611, r~present-,1 ing the.relative charge present on capacitors 608 and 607 .j during each cell scan, are further amplifiëd by amplif.iers,! 613 and 614, in a manner well known in the art. The outputs of amplifiers 613 and 614 are next applied to two sample and l hold circuits. The samp.}e a.nd hQld circuits are comprised 25. of switching transistors 617 and .61~ and .storage capacitors l 615 and 616. Thus, the charge present on capacitors 615 and ij ' ' ~ ' .

'1 ~LZ2~

jj616 is indicative of the amount of light striking the cox-jrespondiny scanning cells of line scanner 606 at any selec-ted -time. The signals are then coupled, via lines 620 and ll621 to a final stage of ampli~ication, consisting of ampli 1 fiers 622 and 623 (see Figure 6b).
With reference now to Figure 6b, the outputs of amplifiers 622 and 623 are each applied to two points within lithe dynamic threshold circuitry. Dynamic threshold adjust-jlment is an important feature of the document processing ¦!system of the present invention and allows a single system Ito process multicolored documents without requiring indiv~
idual level adjustments.
The output of amplifier 622, representing the i amplified outputs of the odd numbered cells of line scanner l 606 ~See Figure 6a) is applied to one input of comparator ¦633 and to diode 624. Similarly, the output of amplifier-623, representing the amplified outputs of the even numbered ¦cells of line scanner 606, is applied to one input of !Icomparator 634 and to diode 625.
11 Diodes 624 and 625 perform an OR function and ~apply the more positive of their individual inputs to ;'capacitor 626. Capacitor 62G lS, therefore, rapidly charged to the level of the highest signal applied through diodes 1l624 and 625. This level is the "white" threshold and l~represents a reference point for black/light decisions. The Ivoltage level present or capacitor 626 is applied thFough 'I . . ... .

' " ~21461 ~jdiodes 627 and 628 to the second input of comparators 633 arld 634~ The voltage drop across diodes 627 and 628 assure~
l~that the signal creating charge on capacitor 626 will be ¦Igreater than the resultant reference signal applied to ~lcomparator~ 633 and 634.
The charge present on capacitor 626 will eventual-l ly discharge slowly through resistors 629 and 630; however, .~a reference voltage applied through diode 632 will prevent l~total discharge and will apply a minimum level which a cell ,¦output must exceed in order to be considered "white."
'IAdditionally, the time constraints associated with capacitor ll626 and resistors 629 and 630, while chosen to be "slow"
Ijwith respect to individual cell sample times, are suffic-lliently "fast" to allow discharge of capacitor 626 between Il, adjacent documents. Thus, a totally white background lldocument, while in process, will result in a high reference jsignal being generated on capacitor 62~, and result in any .llsignal greatèr than two diode drops below that level being ¦characterized as "black." However, during the gap between 20. idocuments, capacitor 626 will discharge sufficiently so that . ¦
ja colored background document.(blue, for example) will .Igenerate a lower reference level. This system of dynamic ,¦reference adjustments allows a single system to process an 'lentire variety of multlhued documents without system ad-,jjustment, and without the possibility of.losing all data contained on a relatively da/k backgrouAd document.

I ' ' I
., i'1 , ,, . I
ll -23-j I For reasons of circuit design not important to the I concept, an inverted output is selected from comparators 633 ! and 634. Therefore, a particular cell in line scanner 606 ¦ which detects a "black" area will result in a logic 1 or 1 "high" output of the appropriate comparator, and a cell : which detects a "white" area will result in a logic 0 or ''low'' output from the appropriate comparator.
Referring now to Figure 6c, the document detection lcircuitry of the document processor of the present invention 1 is depicted. The odd and even numbered cell outputs from comparators 633 and 634 ~See Figure 6b) are applied to shift ¦register 635. Shift register 635 multiplexes the dual three megahertz signals into a single six megahertz video signal.
IOne output of shift register 635 is applied to shift regis-,¦ter 636. Shift register 636 is loaded each time a "black"
i!cell is detected and shifts each time a "white" cell is i¦detected. After eight consecutive "white" cells have been ¦¦detected, the output of~shift register 636 is shifted out i¦and sets latch 640. Latch 640 is a simple JK type latch and j~is utilized to generate the signal which indicates the scan ¦is active (bCTSCNl).
The output of shift register 635 is also applied to counters 637 and 638. Counters 637 and 638 are the I¦leading edge detectors and are reset at the end of each scan ' through line scanner 606. Counters 637 and 638 are utilized to count "white" cells in a single scan. If sixty-four "white" cell- are detected in a single scan, counters 637 i . ' . " . I

i2~

¦'ancl G3B set l~tch 639. Latch 639 is also a simple JK la~ch and is utilized to set edge de-tection latch 642.
The ouput of edge detection latch 642 is utilized Ijto generate the signal which indicates a document is present Il(ITMP~Sl).-The output of latch 639 is also applied to Icounter 641.
,¦ Counter 641 is the trailing edge detector~
IICounter 641 is utilized to count the number of complete - i~scans in which less than sixty-four "white" cells are de-lltected. If sixteen such scans are counted, the output of counter 641 is utilized to reset ~dge detectibn latch 642.
,Header 644 is merely a connection means to a~low compata-;lbility between systems which utilize a single video camera l~jand systems which utilize two video cameras.
~! Figure 6d depicts a series of counters and regis- , ¦
'jters utilized to provide operating information to a con- ¦
,itrolling microprocessor type device~ Counters 645a-645f are ',iutilized to count the total number of active cells in a l~particular document. ThP number counted is latched into ,, ~
jregisters 646a-646c and is available upon ~uery by the ¦control device. Similarly, in applications utilizing two 'video cameras, counters 647a-647f are utilized to count the - lltotal number of active cells in the second,side of a par-llticular document and registers 648a-648c store the total I!count.
' Figure 6e depicts further counters and reglsters ¦ used to provide oper-ting informatioA. Counter$ 64~a-649-."', ', '' ''.
, . ' , .
,1 . . .

Il -25-,1 z~

llcoullt the total number of lines scanned in a particular ¦¦document and latch that number into registers 650a and 650b.
Similarly, counters 651a-651c are utilized to count the l total number o lines scanned by the ~econd camera and that ¦ number is latched into registers 652a and 652b. Thus, by knowing the total number of cells and the total number of scans, a control device may simply divide to calculate the exact dimensions o'f a particular document.
¦ Also depicted in Figure 6e is bus driver 653. Bus 1 driver 653 is utilized to drive or amplify data being read ! from any of the interface registers to permi't transmittal to a microprocessor type control device.
Referring now to Figure 6f, there is depicted a ~ series of input and output latches utilized to provide l' communications to and from a microprocessor type control I device. Latches 654, 655, 656 and 657 are utilized to latch ¦
!l in information from the control device'to the system.
¦; Information and/or commands that test, clear or arm the' Il system are received and latched ;nto the'appropriate'latch~
¦1 Information received may be util`ized to appropriate'com- ¦
mands, such as depicted with logic gates 658a-658d.
Informa~ion, device identification, returning test I! data and busy indications may be latched into latches 659, ! 660, 661 or logic gate 662 for access by a control device.
¦ With reference now to Figure 6g, there is depicted I additional addr'ess and control'circuitry. Switch 666 is a multiple position DIP switc~h which may be set in a uniq~e ' ' ., 1l -26-ir~
" 1 ~LZ,Z~6~L I

¦Ipattern to specifically identify a particular tran~port and j¦camera, r~calling that a system may include additional lltransports as a matter of design choiceO The position~ of I~the various switches in switch 666 are coupled to comparator 11 664 for comparison with the eight address bits generated by the microprocessor type control device Thus, it is po6-l sible for the control clevice to accuratqly address.a single i one of a plurality of devices. If comparator 664 indicates l an address match, a valid address signal (VALAD) is gener-¦ ated. .
: I Once a valid address has been detected, the first .. ¦ four bits of address, A0, Al, A2 and A3 are utilized to l address up to a maximum of sixteen addressable registers on I the addressed device. Bus driver 633 is utilized to co~ple 1 these address bits to the addressable registers. Bus driver ¦¦665 is utilized to couple control commands and the A4 address ¦¦bit. The A4 address bit i5 utilized, in the illustrated .l~embodiment, in conjunction with the valid address signal, to lldesignate either of two video cameras, utilizing logic gates l,667d and 667e. Logic gates 667a-667c are utilized in con- .
junction with other decoded commands to generate. internal .
! read and write commands.
Referring now to ~igure 6h, there are depicted six . ¦ decoders utillzed to decode command and address information i from the control device. Decoders 66~ and 67~ are.utilized .
during a memory write command to either ~ideo camera.
Decoders 670 and 673 axe utilized when the control device . .' , . ..
. I . , ,' ' ,' '.
I . ' ' .
!
. -27-4~
Il . .
;¦issues a memory read to either camera. Decoders 671 and 674 deco~de the commands which access the total cell number and total scan number registers depicted in Figures 6d and 6e.
¦ Finally now, with reference to Figure 6i, there is depicted the output circuitry associated with the video l camera of the present invention. The depicted embodiment of I the present invention utilizes eight separate video buses to transmit video data between various components of the sys-I tem. This group of buses is collectively referre~d to as the 0 ' I X bus, and any single bus may be selected for any single device to utilize.
,I Control signals'from the control device are de-! coded utilizing decoders 675, 676,'677 and 678. Decoder I 675, 676, 677 and 678 may be implemented, in a preferred ! embodiment, by an integrated circuit of the type 74LS138 i manufactured by the Signetics Co~poration of Sunnyvale, California. The outputs of decoders 677 and S78 are util-ized to enable selected three state buffers. Three'state' I¦ buffers 679a-679d, in the illustrated embod$ment, will l~ couple the data from one camera to one of four video buses, ,~ while three state buffers 680a-68Qd will couple't~e'data 'I from a second camera to one of the four remaining video buses.

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i ~ l DATA COMPRESSION SYSTEM
l With reference now to Fiyures 7 and B, there is i depicted a schematic representation of the circuitry of the ¦ data compression system.
¦ Referring now to Figure 7a, the system clock and I its complements are applied to the inputs of high speed ¦ diEferential comparator 70I, which acts as a high speed line receiver. In the disclosed embodiment, the system clock is ¦ a 30.5 megahertz signal generated utilizing a crystal con-~ trolled oscillator (not shown). The output of comparator 701 , is applied to multivibrators 702 and 733, where the frequency ¦ is halved in a manner well known in the art.
i The output of multivibrator 702 ls applied to four bit binary counter 704, where the halved clock frequency is further divided into lower frequencies which are utilized ¦ throughout the system.
Cross point switches 705a, 705b and 705c are utilized by a microprocessor type control device to select !¦one of eight bus lines to be coupled to the data compression ijsystem. The cross point switches utilized in a preferred I embodiment of the present invention are Signetics type i SD5301 switches. As previously mentioned, the eight line bus referred to as the X bus is comprised, in one embodiment l of the present invention, of eight three wire bus lines.
¦ Each bus line has a ready line, a clock line and a data line. The parti~ul~r bus selected by cross point switches 1~ . . ' ,, '' ,' ' ., ' .

''I ' 'I ., .
Il -29-¦ ~,;2z~6~ 1 Il I
l 705a, 705b and 705c is controlled by bus control register i 706, in response to commands frorn a microprocessor type ¦ control device.
¦ Bus control register 706 is utilized to control cross point switehes 705a, 705b and 705e in conjunction with shift register 707 Shift register 707 is a parallel in-serial out (PISO) register which is utilized to se~ialize the command data from register 706 and eouple that serial-l ized command data to set up the cross point switehes.
I Shift registers 708a and 708b are utilized in conjunction with logic gates 709a, 709b, 709c and 709d to enable cross point switches 705a, 705b and 705c and to control register 706 when data is being written into regis-l ter 706. By controlling data into register 706 and the 1 clocking of that data out of shift register 707, the oper-ation of the cro~s point switches is earefully sequenc~d.
In the even-t that the seleeted X bus line is ! occupied, or when a pause signal indicates that incoming lldata must temporarily stop, eireuitry is present whieh will 1l cease data input to the data compression system. A not llready condition out of eross point switeh 705a or an intern- -Ijally generated pause signal at the input of NOR gate 710 ¦¦will generate a signal (RBUSY~ whieh will stop the operation ¦ of multivibrator 703, and thenee the operation of the output section.

I ., ', , ' .
,~' , ' , ' , .. .
!
. , . ' . I ~Z21gl61 ~lso depicted ln~Pigure 7a is end of data clock 711. Clock 711 is a simple multivibrator which is utilized l to generate the end of the ou,tput data signal.
¦ Referring now to Figure 7b, there is depicted the circuitry by which the microprocessor type control device may accurately address the data compression system and various registers within the data compression system.
Jumper wire switches 712a and 712b are utilized with various jumper wires to provide a uni~ue-address or the data compression,system. Buffers 713a and 713b are utilized to receiv~ a board address and register address from the control device. Each board may contain up to sixteen separate addressable registers (or thirty-two including read only and write only registers) and therefore I; four bits of address A0-A3 are utilized to select a regis-ter.
¦ The remaining address bits are coupled to com-parators 714a and 714b where they are compared to the ad-l dress of the data compression system board, as determined by j the placement of jumper wires in jumper wire switches 712a lland 712b.
¦¦ ' Control signals from the control device are coupled to buffer 715 and one of eight decoders 716a-716d are util-~ ized to decode the selected register address to determine 1 which register will be read or written to by the current ¦ command.

I . : . !. , ., ,",', ,. .

. ! . .

`, Logic yate 717 i5 utilized to receive the INITI~L
signal and is utilized to generate the signals which ini-tial-ize various other portlons of the data compression system.
Figures 7c and 7d, when placed side by side in the ¦ manner indicated in those two figures, depict a schematic ¦~representation of the "spot remover" circuitry of the data compression system of the present invention. The spot !¦remover circuitry is utilized to remove any single black i "spot" from the data which corresponds to a particular ¦ image. A spot is defined for these purposes as a single I black cell detected by line scanner 606 (see Figure 6), that Ilis surrounded by white cells.
il Referring now to Flgures 7c and 7d, the data stream representative of a scan through a document is 1 coupled to an input of register 718a and then out of reg-ister 718a and into delay register 719a. Delay register 719a is, in a preferred embodiment, a 1024 bit random access memory that is utilized in the manner of a long shift reg-ister 1 20 IThe data out of register 718a is written into l delay register 719a at an address determined by address ¦ generators 720a-720c. Address generators 720a-720c are initially loaded to a number which correlates with the l number of cells in each scan for a particular document or j group of documents. Address generators 720a-720c are four bit counters which are utilized to control the addresses in delay registers 719a and ~lYb. Thus, the da-a from regiStGr Il ~

'I -32-,1 :L2Z~46~ 1 718a is wri~ten into an address oE delay register 719a which I will result in the leadiny edge oE data exi~ing d~lay regis- I
ter 719a at the end o~ each scan.
! The data exiting delay register 719a is coupled to ¦ register 718b and to the input of delay register 719bo As above, the data in delay register 719b is delayed for the length of a scan and is then coupled.to register 718c.
Those skilled in the art will appreciate that this con~ig-l uration will result in a sample of the current scan being I present in register 718a, a sample of the previous scan , being present in register 718b, and a sample of the next I previous scan being present in register 718c.
I It is therefore a simple matter to examine the I surrounding cells, utilizing logic gates 721a and 721b, and 1 to determine whether or not a particular black cell is a "spot" that should be removed. Logic gate 723 compares the i single cell with the surrounding cells and generates the ¦ signal which removes the spot. Wire jumper 724 is provided I to allow the spot remover circuitry to be disabled, if that is desired in a particular embodiment.
'! Register 725 is a four bit, parallel access shift llregister which is utilized, in conjunction with ~lip-flop 726, to generate write enable signals and various system i clock signals.
1 With reference now to Figures 7e and 7f, which when placed side by side in the manner indicated in the i drawings, depict the scan memory address circuitry. The . .,'''',",',,"'',',..

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'' Il -33-`. . ~2Z~L4e~ ~

data associated with a plurality of adjacent scans through a ¦ document must be stored and examined to permit data compres-I sion, and such storage must be accomplished in a precise ¦ manner to permit later synthesis of a document image. In 1 order to accomplish this storage in an orderly fashion, the number of scans and the number of cells in each scan must be j carefully tracked.
¦ Comparator 725 in Figure 7f is utilized to compare I the number of cells in each scan with an incremented address.
l¦ The number of cells in each scan is loaded into the data compression system, by a control device, through registers l which are not shown. The incremented address which controls ¦ the storage location of incoming data is generated by scan l memory address generators 726a, 726b and 726c. Address ~enerators 726a, 726b and 726c are four bit binary counters which are initialized and then utilized to count to an ¦ address which corresponds to the number of cells in each ¦scan as determined in comparator 725. When the address thus li generated is equal to the number of cells in a scan, the il process is repeated.
i¦ Each time comparator 725 detects the end of a j scan, the output signal is coupled to scan counter 727.
¦ Scan counter 727 is utilized to keep track of the number of l scans stored, because, as will be explained below, the data ! compression system of the present invention operates with ~ twelve =cans in temporary storage in scan nenory.

1~ '- -. '.
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Il -34-~LZ;Z~6~1 Read address generators 728a and 728b are utilized to generate the addxesses which will be utilized to read the ¦ scan data from temporary storage ln the scan memory. A
separate read address generator is necessary because as will be explained herein, the scan data in temporary storage is read out of the scan memory in a different order than the order in which it was stored.
Multivibra-tor 729 is utillzed to initiate the i address generators and read address generators at the 1 beginning of operation. Parallel access shift register 730 ¦ and multivibrator 731 are utilized to develop various clocks and reset commands utilized to operate the data compression system of the present invention. Buffers 732 and 733 are jutilized to buffer and isolate the ciocks and reset signals so generated.
Figures 7g and 7h, when positioned side by side in the manner indicated in the figures, form a schematic diagram of the scan memory previQusly discussed. Each of ~ the memory blocks depicted, 734a-734d, 735a-735d and 736a-¦ 736d are implemented utilizing a 1024 bit random access i memory. Thus, each memory block may temporarily store one complete scan through a document, recalling that a scan may consist of up to seven hundred and sixty-eight separate I cells of line scanner 606 of Figure 6. Further, the scan 1 memory formed by the combination of memory blocks 734a-734d, 735a-735d and 736a-736d may temporarily store twelve indiv-idual ~cans l ., ll ~

i ~
Figures 7i and 7j, when positioned as indicated in the figures, form a schematic diayram oE the address multi~
plex circuitry of the scan rncmory of the present lnvention.
I Address multiplex circuitry is necessary because, , althouyh the data obtained from line scanner 606 (Figure 6) is obtained and written into temporary storage in the scan memory in a vertical format (with respect to the document image), experimentation has shown that maximum data com-l pression will occur with analysis of that data in a horizon-¦ tal format.
As previously discussed, the scan memory formed by Il memory blocks 734a-734d, 735a-735d and 736a-736d (~igures 7g i and 7h) fonn temporary s`torage for twelve complete vertical ! scans. The data within the scan memory is analyzed horizon-i tally in groups of four scans. Therefore, the twelve memory Il blocks are further broken down into three groups, two of ¦¦which are being read while the third group is being written ~¦ into.
jl The two gxoups being read are xeferred to as the 1! current data and previous data. The previous data re~re-¦ sents the previous four scans prior to the current four l scans read into the system and is maintained in temporary ¦ storage to determine what, if any, relationship exists ! between that data and the current data. This examination is ¦¦ necessary to detect possible redundancies which may be I removed and replaced wi h codod equivalents.

.

~1 -36-.. . I ,, . I
~;~2~6 The described system of ver~ical writing and l horizontal reading requires address multiplexing to insure I proper operation. Consider the subgroup of four memory I blocks into which data is being written. A memory block is 1 enabled, an address is supplied from scan memory address l generator 726a-726c (Figure 7e), and the address is incre-! mented until comparator 725 (Figure 7f) indicates the ad-dress has reached the end of the number of cells in a sca~.
l Next the memory block enable signal is incremented, the address generators are initialized and the process is re-¦ peated until four scans are written into the scan memory.
i When a subgroup of the memory blocks is being read, an address is generated by read address generators l 728a and 728b (Figure 7e) and the memory block enable signal 1 is incremented through a four count. Next, the address is incremented and the memory block enable signal is incre-¦ mented through the four memory blocks in the subgroup.
Decoder 737 acts as a one of three decoder which , enables one of the three subgroups of the scan memory at a ¦ time. A subgroup of memory is enabled utilizing address Il multiplexers. The first subgroup utilizes address multi-plexers 738a-738d. Each address multiplexer is a quad two line to one line multiplexer. Address multiplexer 738a is ¦ utilized to provide the chip enable signal (CE) which 1l determines which of the four memory blocks within the ¦¦ subgroup is enabled. Address multiplexers 738b-d are ¦ utilized to provide the address within the enabled memory ., .1 . , - , . , 1: .
l .

~ ~ I -37-I l;~:Z1~6~

j blocc, snd the signal which determines whether data is being read from or wri-tten to the select~d address. Address multiplexers 739a-d and 740a-d operate identically with ¦ respect to the second and third scan memory subgroups.
! Decoder 741 is a dual one of ~our decoder which is utilized to provide the read and write enable signals which serve as the inputs to address multipIexers 738a, 739a and 740a. Multiplexer 742 is a dual four line to one line l multiplexer which is utilized to select the output of a ¦ particular subgroup of the scan memory to be output as the l current data, and the output of a second subgroup to be il output as the previous scan data.

i With reference now to Figure 7k, there is depicted the shift registers which allow examination of the scan data 1 temporarily stored in the scan memory~ Current scan data is shifted into the sixteen bit shift register formed by eight ¦¦ bit shift registers 743a and 743b. Data from the previous Il scan is simultaneously shifted into the sixteen bit shift Il register formed by eight bit shi~t registers 744a and 744b.
il In this manner, current data may be compared tG previous data and redundancies in current data may be examined in a I blt by bit manner, as the data shifts through the shift ¦¦ registers.
ll Multivibrator 745 is utilized to enable scan ¦ memory address multiplexer 738a, 739a and 740a (Figure 7i) Il after th completion of the lirst scan.

I . . "' ,-" '' .

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~ -38- _ r i Referring now to Figure 71, multivibrators 746 and 747 are,utllized to develop the shift enable signals (SFTEN
and SFTEN-) which are utilized throughout the system to lenable various shift clocks and reset signals. Multivi-1 brator 748 is utilized to develop the duplicate enable signal tDUPENF) which is utilized during those periods when the scan data is duplicating previous values and the re-¦ dundancy may be removed. Multivibrator 749 is utilized to ! generate the BUSY signal in response to the signal indi-l~cating the system is armed and that dat~ is being clocked ! into the syste~. , Four bit binary counter 750 is utilized as a time ¦out counter. After a signal is received indicating the end ` !If scan data, counter 750 is utilized to provide the slgnal 1~1 which shuts down the system. Flip-flop 751 and multivi-brator 752 are utilized to provide additional clock signals after the end of data has been detected, to ensure that data ¦within the system is completely processed prior to system llshutdown.
,j Figures 7m and 7n, when joined,in the manner indicated in the figures, form a schematic diagram of a section of the redundancy removal circuitry of the data compression system of the,present invention.
ll Experimentation in the field of video image data ~! compression has proven that while examining horizontal llsections of four sc~n cells, there exist c~rtain predo-inant 1~ ' ' ' '' ' ,., , ' ''' , '' .

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I ~221461 repetitive patterns. These patterns are referred to herein as "Q" codes, and the most common three codes are: a black c~ll followed by three white cells ~1000 in binary repxe-¦ sentation); two black cells followed by two white cells (1100 in binary representation); and, three black cells followed by a single white cell (1110 in binary represen~
tation).
In view of thq above, it will prove beneficial to l examine the scan data to determine if a series of these Q
1 codes are present. To that end, current data present in l shift registers 743a and 743b ~figuxe 7k) is coupled to Q
!¦ code logic array 753. Logic array 753 is a field program-¦ mable logic array such as the 82S100, manufactured by ¦ Signetics of Sunnyvale, California. Logic array 753 is 1 utili7ed to determine first, whether or not one of the i aforementioned three Q codes is present in the first four positions of the sixteen bit logic array, and second, how many repetitions of that code are present. It will be ¦ apparent to those skilled in the art that up to ~our con-¦I secutive four bit Q codes may be present at a single time in jl logic array 753.
The current data present in shift registers 743a and 743b is also simultaneously coupled to black/white logic l array 754. In a manner similar to the operation of logic ¦ array 753, logic array 754 examines the first bit present to determine whether- it is black or white, and secondly how many consecutive blacks or whites follow the first bit.

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I l In the preferred embocliment r logic arrays 753 and 754 are utilized to detect the state of the data coupled thereto and to ensure that the redundancy present is at least eight bits in length. This requirement is a design choice; however, since the redundancy to be removed m~st be replaced with an identifyiny code and an indication of the length of the redundancy (count), eight bits seems to be a ¦~practical minimum length.
ll The state of the data in logic array 753 and 754 ¦lis coupled to transparent latches 755 and 756 respectively.
t¦ The output of latches 755 and 756 are coupled to latches jl757a and 757b, each of said latches formed by one half of a llsingle twenty pin latch circuit, and to the address pins of ¦¦count memories 758 and 759. Count memories 758 and 759 are ~1 utilized, in conjunction with four bit binary counters 760 and 761, to disable transparent latches 755 and 756 for a selected period of time. Disabling circuitry is necessary to avoid various proble~s present during data shifting.
IjThose skilled in the art will appreciate that a Q code, as 1l previously defined, loses its identity if shifted one bit.
,ITherefore, if four Q codes are detected in logic array 753, it will be necessary to disable latch 755 until sixteen bits ',jhave been clocked through, to determine if additional Q
¦¦codes are present. To this end, the output of latch 755 l¦will address a value in count memory 758. Counter 760 will ¦disable latch 755 and continue to do so until the selected ~ccunt n count memory 758 i= acnieved.

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Similarly the output of latch 756 will be utilized ! to addres.s a value in count memory 759 and counter 761 wi.ll disable latch 756 to allow the identi~ied data ko be shiEted out of logic array 754. A slight difference in operation is 1 utilized if logic array 754 contains data which indicates a ! series o black cells in tbe scan. In this case, the latch ¦ will be disabled until the last three black cells in the previous group have been shifted to the first three posi-¦ tions in logic array 754. At this point, the data wiIl be 1 examined to determine whether or not the last three black , cells comprise the beginning of a Q code. This operation i repeats until the last black cell is shifted out.
Multivibrators 762 and 763 are utilized to enable 1 latches 757a and 757b. Each time a particular redundancy l, has been finally coded and output by the data compression ~system, latches 757a and 757b are enabled to latch in the ¦outputs of latches 755 and 756.
! Referring now to Figure 7O, two other possible 'states of scan data may be determined. First, in the event ~! that the stream of data examined by the data compression system is not wholly black or white, or comprised of a group of consecutive Q codes, it is still possible that redundancy exists in that data-. The most easily detected redundancy l will exist when the data from the current scan, while 1 varying in no discernible pattern, may entirely duplicate ¦ the data from a previous scan. One s,ch exAmple ~ay be an . '' ' ' ' "
!
. j , , -~2-intricate but repetitive border or edge design on a check or other document.
Such cases are identified using logic array 764.
. . I Loglc array 764 can simultaneously examine eight bits of 1 curren-t data and eight bits of previous data to determine whether or not the data is duplicative. In a manner similar to that explained above with respect to black or white data, .
the output of logic array 764 is coupled to transparent . latch 765. The output of.transparent latch 765 is coupled ¦ to count memory 766 and is utilized to address a value which is coupled to four bit binary counter 767.
. i Binary counter 767 is utilized.to disable latch , 765 while data is being shifted through logic array 764. In l the disclosed embodiment, as a matter of design choice, if l¦ the data changes from one code to another and the duplicate code was available at the beginning of the current code, the ¦ code will be changed to a duplicate code if the data being 1! duplicated also changes and duplicates for at least five ji additional bits.
~! If the.duplication of previous data does not duplicate for at least five additional bits of scan data, then the data compression system will code out the old code , and change to the new code and begin to encode the new . . values of scan data.
, After a previous redundancy has been identified, ¦ coded and output from tne data compression system of the ~. ' .

' -' . .
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, present invention, ]atch 768 is enabled, latching in the next type of redundancy to be coded.
Multivibrators 770 and 771 are utilized to latch in the duplicate data mode throughout the data compression system o~ the present invention and to continue the dupli-cate data mode beyond a chanye in state of data i~;the duplication continues for at least five additional bits of scan data.
l As a last resort, if a series of Q codes, black-1 cells, white cells or duplications are not present, the data compression system of the present invention will store actual data, without compression. To overcome such a deter-mination (referred to herein as "mapping" or a "map" func-~ tion) a minimal amount of redundancy is required before the ¦ data ~ompression system will begin encoding data. As a matter of design choice, the discl-osed embodiments will cease mapping and begin to encode data if at least eleven black or white cells are detected, at least three consecu-~ tive Q codes are detected, or any combination of codes which i exceeds eleven bits. Logic array 769 is the mapping termin-ation logic array and is utilized to examine the scan data for the previously enumerated situations which will overcome I the mapping function~
¦ Referring now to Figures 8a and 8b, which when ¦ joined in the manner indicated in the fiyu~es, form a schematic diagram of the count and code out circuitry of the data ~ompr ssion system of the pr~sent inven~ion.

. ' .
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l . 4'1-iZ~1461 I,ogic gates 801a, 801b and 801a are utili~ed in conjunc~ion wit:h the logic gates associated therewith, to I encode the output of latches 757a and 757b of Figure 7m, and couple that data to quad two input multiplex 803. It should be recalled that the data in registers 757a and 757b repre-l sent the code currently being utilized in the data com-I pression system. .
Similarly, logic gates 802a, 802b and 802c are utilized, in conjunction with the logic gates associated o !¦ therewith, to encode the outputs of latches 755 and 756 of Figure 7m. Latches 755 and 756 are the transparent latches utilized to h~ld the data which represents the next data to , be utilized in the data compression system. Thus, when a section of data is output by the system, the next data to be ~ coded out is switched through multiplex 803.
Those skilled in the art will appreciate that in addition to the type of redundancy being removed from the ¦data stream, it will be'necessary to include the length of lIthe redundancy in order to allow eventual reconstruction of the reaundancy. To this end, counters 804, 805 and 806 form ~¦a twelve bit binary counter. The counter thus formed pro-, vides inputs to the field programmable logic array 807 which ilcontrols the coded count counters. Again, as a matter of i~design choice, the data compression system of the present !¦invention includes certain maximum data counts in each type of redundancy (see Table I). The selection of a particular max1mum count is based upon requirements of h- code selected . -' . , .

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and the physical liklihood that certain redundancies occur with greater length than other redundancies. The longest count acceptable in the disclosed embodiment of the present invention is 4096 bits in either the white cell rnode or the ~ duplicate mode. Each of the other modes has a lower maximum ¦count, as indicated in Table I.
'! When the counter formed by four bit counters 804, ,¦805 and 806 reaches the màximum count of 4095, rollover ¦Imultivibrator 808 is set on the next clock, and the output -¦lof multivibrator 808 is utilized to ensure various actions.
il The lower maximum counts available for black cell mode or Q code mode make it advisable from a data compres-sion viewpoint, to operate in duplicate mode or white cell mode if possible. Multivibrator B09 is utilized, to force j the data compression system into the duplicate mode, if a ,jcode length overflow condition lS reached by counters 804, !j 805 and 806 in other than the white cell mode (white cell ¦mode maximum count being e~ual to duplicate mode maximum count), and the duplicate mode is set. The forced duplicate Imode will also occur if ~ code change occurs ~black to !' white, for example) and the duplicate mode could have been jutilized. Multivibrator 810 is utilized, for similar pur-poses, to keep track of the ccll count in a mapping mode of I operation. If a map count occurs which is greater than five ¦ cells and less than eight, and the duplicate mode could have I been utilized at the- beginning of the count, the duplicate mode will be forced, rather than allow a map çod~.

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1 ~2~461 I

Re~erring now to the Ligure ormed by joining Figures 8c ~nd 8d in the manner indicate~, there is depicted a schematic diagram of additional circuitry including the duplicate mode circuitry of the data compression system of the present invention, Multivibrator 811 is the circuit element utilized to keep the data compression system in,the mapping mode of operation, until one of the aforementioned special map l termination conditions occurs. Multivibrator 812 is the ¦ circuit element utilized to enable a change to duplicate I code when the maximum data count occurs for a redundancy ¦I type other than white cell (white cell maximum count being ¦¦equal to duplicate cell maximum count).
il The group of logic gates labeled 813, and the llinputs associated therewith, are utilized to enable logic ~¦ array 814 after a sufficient time period has elapsed to ¦¦allow the previously identified data to be clocked through.
¦ The output of logic gates 813 is then utilized to enable ll logic array 814, the decision logic array. Logic array 814 1¦ is utilized to determine whether or not the code present should ~e coded out.
Logic array 81$ is utilized to control four bit counters 816, 817 and 818, which are utilized to generate ~¦the coded count of the section of data. Counter 819 is the I duplicate mode load counter and is utilized to count the ~ n~mber of tlmes the ~upl cate counter has be~n lo-ded.

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Quad multiplexers 820, 821 and 822 are utilized to output the duplica-e mode cell coded count or -the coded count of the number oE cells in a black or white cell count, a Q code coun-t or a mapping count, as selected by logic gate 823. `
With reference now to the figure formed by joining Figure 8e and 8f in the manner indicated, there is depicted buffers 824 and 825. Buffers 824 and 825 are first in-first out (FIFO~ buffers that are u-tilized to control the cell ilcount during a mapping function, to determine how many cells ¦are utilized during a particular mapping function.
Multivibrator 826 is utilized to provide additional ¦bits to fil1 up a four bit word in the FIFO data buffers in ¦!order to permit transfer of the cells stored therein. Output Icontrol counters 828 and 829 are four bit counters which are jutilized to count the number of cells output from the bufférs during the mapping mode of operation. Comparator 827 checks l! the output of buffers 824 and 825 against a reference signal !I to determine if the maximum map count was coded. Comparator 1'827 is then utilized to prevent multivibrators 831 and 832 from flushing out the remaining data stored in the map data l!buffer, if the mapping function has been coded out due to a l! maximum count. If the mapping function has been terminated ¦ due to other than a maximum count (a forced duplicate mode, l or a code change) multivibrators 831 and 832 are utilized to j flush out a single four bit byte in the data buffer to ~indlcate th end O r a malping function data stream.
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i ~ 48-Z~

Logic gates 833 and multiple multivibrator 834 are utllized to generate and latch out a terminal coun~ at the end of transmitted data. This artificial count is referred to as a terminal count and is utilized to allow completion of the compxession of the final bits of data.
I Referring now to Figures 8g and 8h, when joined in the manner indicated in the figures,. there is detected multivibrator 835, which is utilized to delay the data entering buffer 836. Buffer 836 is a four by sixteen bit ¦ FIFO buffer that is utilized to temporarily store data i during a mapping function. Recalling that a mapping celL
count of greater than five cells and less than eight cells ~¦ may result in a forced duplicate mode, if duplication is I¦ possible, it should be apparent to those skilled in the art 1 that at least eight cells in a mapping function mode must be examined before a map code is possible. Thus, buffer 836 is utilized to provide temporary storage until such a decision is made. Logic gate 838 is utilized to reset buffer 836 if I a forced duplicate mode occurs.
~1 In the event that eight mapping function mode I ~ells are encountered, and the forced duplicate mode is not ;j utilized, multivibrator 839 is utilized to dump the data ¦ from buffer 836 into four by sixty-four buffer 837. Buffer I 837 is utilized as a first ln-first out buffer which stores ¦ the data u-tilized durîng a map mode of operation. Multi-,ibrator 83 wlll al-o cause the d~ta in buffer 836 to dump l ~' '' ' '," . .

lL

~ 2%~6 . . . j llinto buffer 837 if the data ter,minates prior to eiyht bits ¦¦and is coded out as a map code.
'!I Quad multivibrator 840 is utilized in conjunction ~with multivibrator 834 (see Figure 8f) to provide addit,ional I delayed terminal count signals in the manner explaine~
above. Multivibrator 841 is the serial out clock enable circuit and is utilized to enable the output of buffer 837 when it is desired to 'output the map data. ', Multivibrator 842 is the master serial output enable latch which enables the ~arious code, count and map ~buffer outputs. Multivibrator 843 is the load output counter , latch which is utilized to detect the fact that data is j present at the various counter control buffers, such as buffers 824 and 825 (see Figure 8e) and to load the counters.
1! Multivibrator 844 is the transfer out parallel latch which is utilized to detect the terminal count signals which !!lndicate that each counter has reached the end of the count '~idesired, After' all términal counts are detected, the data ,in storage is transferred out in parallel, and latch 843 is Ithen utilized to latch in new counter control data. Multi-~`lvibrator 895 is utilized to disable thé output of multivi-¦brator 844, at logic gate 846, after the data has beèn lltransferred out, to ensure that only one set of data is ¦!transferred out. ,~ , 1l Multivibrator 847'is utilized to generate the serial output clock to the code buffer and multivibrator 898 ~is utili ed to generaee tho ser_al outpue clock t~ the count !
. . . .
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~ 50-`1 ~LZZ~.9'6 1,~ ' ' .
buffer. These two multivibrators axe then responsible ~or serially outputting both the speciEic code and the count of ¦ cells within that code.
I With reference n,ow to Figure 8i~ there is depicted a schematic representation of the count bit shifter circuit-ry of the present invention. Referring again'to Table I, it can be seen that the number of bits in a particular count ! may vary from a maximum of eleven bits to a minimum of two I bits. In order to accurately keep track of the count in a ¦ particular code, it is necessary to keep track of the most significant bit of the count. The-least significant bit of , the count is fixed and relatively easy to obtain, however, the most significant bit must be ascertained.
ll Logic array 852 is utilized to determine how many i bits are present in a particular code. The inputs to logic I array 852 include the particular code encountered and the I number of times the count,has been loaded. Utilizing this - i input data, logic array~852 is coupled to bit shifters 853-858, to control the position of,the most significant bit of 1 the count. ~
sit shifters 853-858 are four bit shifters with ll three state outputs that-shift each four bit word from zero ¦ to three places. Thus, under the control of logic' array l, 852, it is possible,to shift the most significant bit of the count to a desired position. ~n the preferred embodiment, the most,signific~nt bit of the output count is shifted into the first bit to be serially output.
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I ' ' ' -51-Referring now to ~igures 8j and Bk, when joined in the manner indicated in the figures form a schematic diagram of a section of the output circuitry of the data compressio system of the present invention. Loglc array 859 generates the control informa-tion for ,the code and count logic arrays.
The outputs of logic array 859 are coupled to four by six-teen bit buffers 860 and 861. The data thus stored in buffers 860 and 861 is utilized to control four bit counters 862 and 863 respectively. Counters 862 and 863 are utilized 1 to generate selected terminal count signals.
Lo~ic arrays 864 and 865 are also coupled to the code and load count signals and are utilized to generate the actual code to be serially output (see Table I). The actual l~cade is loaded into buffers 866-869'for serial outputting.
i¦ Buffers 866-869 are all four ,by sixteen bit first in-first ,¦out buffer memories. Buffers 866-869 give the system the ! capability of'utilizing up to sixteen bits of code; however, in the disclosed embodiment not all bits are utilized.
l~ Buffers 870-872 are the count bu~fers. The count iI data output from bit shifters 853-85S (Figure 8i) is coupled ~¦to buffers 870-872 to be serially output from the system.
IlAs above, buffers 870-872 are four by sixteen bit first in-- ¦Ifirst out buffer memories. Logic gates 873 are utilized, in l conjunction with certain outputs of counter 863 to ,genPrate an a~ditio al terminal court sigAal.

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1' . -52-.... , ~2~6~ 1 ~eferring now to Figure 81, there is depicted a schematic representation of the section of the data com yression systern that is utilized to determina the size of ¦ the document image. Four bit counters 874 and 875 are ¦ utilized to divide the coded output of the data compression I system by thirty-two. Each time counters 874 and 875 reach thirty-two, the total in four bit counters 876-879 is incremented. Thus, the data in counters 876~879 represents ~how many thirty-two bit words are present in each image.
¦ The outputs of counters 876-879 are coupled to ¦Iregisters 880 and 881 where the control device may access the data. Multivibrator 882 is utilized to store the count ¦ at the end of an image. Multivibrator 882 is reset when its contents are read. Multivibrator 883 is utilized to initialize the counters by forcing the counters to a load ~¦condition until Feceipt of a first data clock.
il Referring now to Figure 8m, there is depicted a ¦¦schematic representation of the logic circuitry which allows ¦ a coded representation to be output from the data compres-

2~ sion system. Logic gate 884 will allow a code out whenever a code change is allowed (CNGAL) or the end o~ data has been reached. Logic gate 885 will allow a code out during a map Ilfunction if the code is changed to a duplicate mode.
¦¦ Logic gate 886 will allow a code out if one of 1 these special map mode termination se~uences is encountered, as previously discussed. Logic gate 887 is the logic gate which allows black cell codes to be t~rminatec early to l . . , , .', ~ . ' ,. ''',' I ., .

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. .
begin Q code mode of operation, as discussed herein. In conjunction with logic gate B87, multlvibrator 888 is ' utilized to ensure that greater than ~ven black c~119 have been detected prior to allowing an early,termination of black cell mode of operation to code Q codes.
Multivibrator,889 is utilized to detect the over-flow condition which will'result when the bit counters exceed the maximum count for a particular mode of operation~
In s'uch event, the code in question is output and the system begins counting anew.
Each of the previously discussed code out signals are applied to multivibrator 890, which is utilized to generate the parallel load signal which is utilized to load out the current code and count. Multivibrator 891 is trig-lS' gered along with multivibrator 890 and is utilized to select certain multiplexers which allow a look ahead function for the various logic arrays. Multivibrator 892 is utilized to generate a buffer overflow error signal if the data compres-sion system of the present invention attempts to load additional data into the output buffers whiie'these buffers are full.
Referring now to Figure 8n, there is depicted the coded counters for the data compression system of the pres-ent invention. Counter 893 is the load counter which is utilized to determine how many times counters 894a-894c have been loaded. Counters 894a-894c are utilized to generate the coded count of the number of cells in a current black, . . . ,, ~ ..
. . .. ....

`` I lZZ~L416~ 1 white, Q code or mapp;ng mode of operation. Referring finally to Figure 80, logic gate 895 and the logic gates associated therewith are utilized to generate an internal ¦ register full signal in the event that any one of the first ¦ in-first out buffers is full. The internal register full signal is utilized to generate an error slgnal if additional data is loaded into a full register.
Multivibrators 896 and 897a-897d are utilized to ¦ generate a four phase clock signal for utilization in the ¦ operation of the data compression system. Multivibrator 896 is utilized to double the GX/2 clock from multivibrators 702 l and 733 (Figure 7a) from 15.25 megahertz back up to 30.5 ¦¦megahertz. In turn, multivibrators 897a-897d are then I~utilized to divide the 30.5 megahertz clock down into a four phase clock in a manner ,ell known in the art.

MICROFILM SYSTEM
The document processor of the present invention llincorporates a microfilm recorder 238 (See Figure 2~ which ilallows selective microfilming of documents during the same ¦pass in which several other processing ~unctions occur.
' Thus, a particular document may be read, encoded, endorsed, ¦ image captured, sorted and filmed during a single pass I through the document processor.
1 The microfilm system utilized within the present invention is based upon the SMR-200B Scannermate microfilm -recorder, m~nufact~red by th- Terminal Data Corporation of ' 1~ ' ' ' ' - I . ' , : , !

l~ -55-. 1 ~;~2~4~

Woodland Hllls, Cali~ornia. It will be appreciated by those ordinarily skilled in the art that other microfilm recorders will find use in the present system, as a matter of design cholce .
Microfilm recorder 238 films both sides of a document, at a speed of up to one hundred inches per second.
The film motion is synchronized with the document transport and a document detector, stopping between documents so that 1 interimage spacing is independent of other processing, thereby ensuring maximum film usage and format continuity.
~icrofilm recorder 238, in a preferred embodiment, i also records a program controlled sequence number and an image count mark (commonly known as a "blip") above each I recorded image. Approximately 14,000 documents may be ¦ microfilmed on one hundred feet of 16mm. film, assuming an average document length of seven inches. The sequence 1 numbers and image count marks allow rapid addressing and ! accessing of individual documents. The microfilmed copies of the documents being processed may provide either a backup ~o I system for the digital image system, or may be utilized as ¦ hard copy archival storage for the documents in question.
l . ' , ' ' .
¦ DATA EXPANSION SYSTEM
l Referring now to Figures 9a and 9b, and the joint 1 figure formed thereby, there is depicted a block diagram of ¦ the major components of the data expansion system of the plesent inventlon. , , .

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X bus rece.iver 901 is uti.lized to receive data from the specific X bus channel selected by X bus select 902. The data thus received is coupled to serial in-par-allel out register 903, and then latched into latch 904 and 1 parallel in-serial out register 905. The additional latch and register circuitry is required to allow the receipk of ! up to eight more bits of data after the input register of ¦the data expansion system is full. Logic gates 906 and 907 l¦are coupled to latch 904 and register 905 and are utilized i in conjunction with X bus select 908 and X bus transmitter 909 to stop data flow during periods when the aforementioned . latch and register are full. . .
~¦ The data in register 905 is coupled to a sixteen ,Ibit, serial in-parallel out working register 910. The -15 Ijnumber of bits shifted into register 910 is controlled by shift counter 911. Shift counter 911 operates based upon the content of sixteen bit adder 912. The initial count in sixteen bit adder 912 is applied to ROM address generator , 914 which is utilized to address data within code ROM 915.
I Code ROM 915 outputs additional data which is applied to sixteen bit adder 912. The new content of . sixteen bit adder 912 is utilized to control shift counter - ! 911 and thus control the number of bits shifted into . I wor~ing register 910.
¦ Examining the contents of Table I, it can be seen that in the discl~sed embodiment, the minimum number of bits ~in a code s three. ~Therefore, it should be apparent to .1 . ' , , , ' .
! 57 f~
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those skilled in the art, that if adder 912 is ernpty, that condi-tion should cause ROM generator 91~ to select a code within code ROM 915 that will cause three bits to be shifted into register 910.
As the contents of adder 912 are recognized as an identifiable code, code ROM 915 will generate data which will allow the correct number of bits to be clocked into register 910, and provide the bias necessary for the correct count. By way of example, when the system recognizes the lo !1 lllolll code, code ROM 915 will provide data to adder 912 to allow eleven additional bits of data to enter register 910.
I¦(see Table I, White Cell Mode3 As eleven bits of count are i¦coupled to adder 912, a bias of 1024 is coupled into adder .
1¦912 to be swmmed with the eleven bit number. The bias value 1¦ may be coupled directly to adder 912, or, should the value i! be higher than eight bits, by means of high bias latch 916.
Code ROM 915 also generates a function code based upon the translation of~the code initially antered into . adder 912. The function code is applied to function latch 1 917, where it is applied to data multiple~ 918. Data multi-;¦plex 918 is utilized to select a voltage potential (black cells in this embodiment), a ground potential (white cells) a duplicate function pin, a mapping function pin, or Q code .
! register 919. Q code register 919 is a recirculating ¦ register which contains each of the three Q codes previously . discussed, and may be accessed repeatedly to provlde a s_ream of reE e~itive Q Fodes.
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Durlng a mapping function, no data compression wa6 possible and the actual data has been stored. Whell data multiplex 918 selects the mapping function pin, data multi-I plex 91B is coupled to the input o register 910, and re-ceives actual data received from the X bus. During a dup-licate function data multiplex 918 is coupled to the output of duplicate buffer 920, the operatioh of which will be ex-plained below.
Il The output of data multiplex 918, representing ¦¦expanded image data, is coupled through serial in-parallel ,lout latch 925 and 926 onto a four bit wide data ~us. The image data is then coupled simultaneously to four scan buffers 923 and 924, and four scan dupe buffer 920. Up to l eight complete scans of data are selectively stored in ¦ buffers 923 and 924, as sequenced by the operation of multi-! plexes 927 and 928. Four scan dupe buffer 920 stores the ¦most current four previous scans of data and thus permits ¦duplication. The output of buffer 920 is coupled back to data multiplex 918 by means of register 922.
, The data contained in buffers 923 and 924 may now be selectively accessed by multiplex 930 to provide at least two formats of data. The data stored in buffers 923 and 924 ¦may be output in the "scan" mode, that is, in the manner in ¦ which the data was captured by the digital scanning circuitry.
¦ This method of data output is obtained by accessing buffer 923 and reading out an entire scan, then incrementing the scan numbe~.

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¦¦ In other applications, it is more advantageous to output ima~e data in the "ladder" mode. In the ladder mode, data is obtained from the first address in each scan and the I scan number is then incremented. After the first ell or j address has been read out of each of the four scans in buffer 923, buffer 924 is accessed in, a similar manner.
Thus, the ladder mode provides eight bits o~ data, each bit ¦ from a different scan of the digital scanning circuitry.
IlThe next eight bits provided are from the next address in -!¦each scan. The process of restoring eight scans of data, at I one cell per scan resembles the structure of a ladder, and therefore is described as the "ladder" mode.
Il As a final variation and possible image data ,Imanipulation, latches 932 and ~33 may be uti~ized to re~erse 'Ithe order of each byte of eight bits. This technique may be 'lutilized to provide mirror imaging. In systems which utllized two digital cameras to capture the image of each jside of a document, onç~side will invariably be mirrored Ifrom the other. Latches 932 and 933 are utilized to correct Ithe situation when restoring the mirrored image.
j The data out of latches 932 and 933 i5 coupled through buffer 936 to output control circuitry 937. Output ¦control circuitry 937 is utilized to select an appropriate ! x bus channel and transmit the data. Output control circuitry 1l 937 is also utilized to control the receipt of signals from the X bus to indicate the-availability of a particular channel.

it `~ ,, I

VIDEO TERMINAL SUE~SYSTEM
Referring now to Figure 10, there i~ depicted a I more detailed block diagram of video terrninal subsystem 136 j ~see Figure lb). Video terminal subsystem 136 is utilized, in the document processing system of the present invention, to provide video ima~es of selected documents along with alphanumeric inormatioIl. Video terminal subsystem 136 ll provides the selected video images by means of digital image ., data captured by-the digital camera, in one embodiment, and I is utilized to allow processing oE data present on documents ¦which is not in machine readable format. For example, video ¦~images may be utilized to examine signatures, to compare two I~signatures or.to examine handwritten amount fields on docu-Ilments such as checks. Video terminal subsystem 136 will 1l also find broad application in other areas wherein it is .¦desired to present a .video image generated by digital data, IIwith or without the additional of alphanumeric characters.
: Digital facsimile trans~ission, digital document storage and l word processing are.a few of the many uses such a system may ¦ find.
¦ . Video image data is transferred to.video terminal subsystem 136 by means of X bus distributor 142. Control or program information is transferred to video terminal sub-!Isystem 136 via synchronous data link control slave 138 and Ij is mapped by way of direct memory access 1002 into micro-processor I004 and memo~y 1006. In a preferred embodiment of ,1 ' .
!j ! - -61-~ZZ~61 ,... .' the present invention, microprocessor 1004 iB a high level device capable o addressing external memory 1006 for pro-gram instructions.
The video image data transferred via X bus dis-tributor 142 is coupled to an appropriate video formatter.
In the embodiment disclosed, up to fou~ video formatters are utilized with each video terminal subsystem; however, additional subsystems may be utilized and/ox the number of terminal controllers may be modifiëd as a matter of design choice. Each video formatter contains a substantial amount of memory and is capable of storing sufficient digital data to support an entire image or the appropriate video terminal.
The detailed description of the circuitry and capability of the video formatters will be explained in greater depth with reference to Figures lla-llo and 12a-12O. Video formatters 1008, 1010, 1012 and 1014 each correspond to a single video terminal, namely, video terminals 1018, 1020, 1022 and 1024.
Each video terminal is coupled to an appropriate video formatter and keyboard by means of dual terminal controller ItO devices 1016 and 1017 and terminal I/O de-vices 1019, 1021, 1023 a~d 1025. Dual terminal controller I/O devices 1016 and 1017 each different-ially drive video to two terminals and provide differential receivers and serial to parallel conversion for inputs from two keyboards.
Terminal I/O devices 1019, 1021, 1023 and 1025 each receive ¦ difieLenti ly driven video for one eerminal and provid-.' . ,'.,.' ,', .,1,, , . ~ ' .

' ~1 ', , parallel to ~erial conversion ancl differential drive ~or l data from one terminal keyboard to the appropriate dual ¦ terminal controller I/0 port.
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! With reference now to E~igures lla-llo and 12a-12q, ,1 there is depicted a schematic diagram of the circu1t compon-ents of the video formatter o,f the present invention. The . I video formatter of the present inven,tion is utilized to 1 provide image data and control to the video terminals of video terminal subsystem 136 and image data to the laser '¦printer of laser printer subsystem 124. In alternate em-¦bodiments, the video formatter of the present in~ention will ¦Ifind wide application in various areas wherein images are !!required to be stored or manipulated in digital format.
¦Applications such as digi,tal facsimile transmission/reception ' and word processing equipment are but a few of the many -' ' applications such a device wlll find.
Referring now particularly to Figures'lla and llb, ,Iwhich, when joined in the manner indicated in the figures, depict a schematic diagram of the device control registers and memory address generation circuitry of the video for- ¦
matter of the presen~ invention. Multivibrator 1101 is utilized to provide a power up master clear signal to ¦1 initialize the video formatter. Control register 1102 is ' i~ utilized t~ receive control signals'from an appropriately !¦ programmed external control,devlce. The outputs of controi 'I -63-` 12Z1461 register 1102 are coupled to the logic gates associated ! therewith and are utilized to generate various internal control signals. The control signals thus generated are l utiliæed throughout the system to ready the bus, select a 1 bank o internal memory for access by the control device, determine in what sequence data will be transferred and to generate an interlace synchronized signal for image display.
Buffer 1103 is the device identification buffer ¦and is utilized by the external control device to determine ¦what type of device is coupled to the bus. Similarly, l¦buffer 1109 is utilized by the control device to test the Istatus of the video formatter during and before operation.
In the discussion of the video subsystem it was I stated that the video formatter could subdivide the display into up to nine separate display zones. Multivibrators 1105 through 1108 are utilized to address these zones. Multi-!I vibrators 1105 and 1106 form the band counter, which is !¦ utilized to determine a horizontal band across the display.
- 1I Multivibrators 1107 and 1108 form the zone counters which il are utilized to determine the address of the section within a particular band. Those skilled in the art will recognize that by utilizing two bit binary numbers to characterize both the band and zone address the system wiil have the capability of defining up to sixteen separate zones.- In-1 deed, although only nine zones are visible in the disclosed 1~ embodiment the remaining seven zones are utilized for ., ' ''' ' ' '.

!
I
,, . . , Il -64-~2,%~.416 horizontal'and vertical retrace, In alternate embodiments, utilizing laser printers or other non-display devices, all sixteen zones may be utilized to provide visible image.
l Quad multivibrator ilO9 is utilized simply to 1 provide a shift delay in order to coordinate wi~h a video ¦ attribute circuit which will be discussed below.

! Octal transceiver 1110 is utilized to couple data , to and from t~e internal memory bus and inverter buffer 1111 I acts as a bus receiver to the internal control memory of the 1 video formatter.
One of eight decoder lll2 is utilized to select a ,Iparticular integrated circuit memory chip in the internal ,I control memory and buffer 1113 is utilized to couple the 'I appropriate memory address to the selected integrated cir-ll cuit control memory chip.
! Referring now to the joint figure formed by Fig-¦¦ ures llc and lld there is depicted a schematic representa-~¦ tion of the main timing'circuitry and display memory timing Il circuitry of the video formatter of the present invention.
,¦ The main timing signal is generated by crystal !1 oscillator 1114 which provides an extremely stable 30 5 I~, megallert2 clock signal. The main clock signal is then di-' ! vided by'two utilizing multivibrator 1115. Serial in-¦ parallel out register 1116 is utilized to provide the' 25 ' ~¦ individual bit timing signal. Register 1116 is operated in the manner of a counter, propagating a pulse through'the ' register.

, , -65-46~ I I
l . .
l The video Eormatter of the pre~ent invenkion may ¦ be utilized to supply ~ormatted video ko a display terminal ! or other device such as a laser printer. In those appli-¦ cations in which it is desired to supply video to a remote ¦ device, it will be necessary to provide the image data over a bus, such as the aforementioned X bus. In such applica-tions, it is imperative that the data transmission begin at , a known point, such as the upper leEt corner of the image in ¦ the disclosed embodiment. To that end, multivibrators 1117 ¦~and 1118 are utilized to ensure data trànsmission beglns at i the appropriate point. Multivibrator 1117 is utilized to enable the transmit pause as the appropriate portion of the data approaches. Multivibrator 1118 is then utilized to l establish the synchronization of data transmission at that '1 point.
, Similarly, multivibrators 1119 and 1120 are util-,¦ized to temporarily pause during transmission of image data !¦ if the image memory must be re~reshed or~the device receiv-l ing the image data is not ready to receive additional data.
¦ Multivibrator 1119 is utilized to enable the clock pause I which will eventually stop transmission of the image data.
Multivibrator 1120 then synchronizes the paused data trans-mission with fetches of data from image memory~
l¦ Multivibrator 1121 is the memory timing multi-~Ivibrator and generates the timing signals utilized to re ¦¦trieve data from the image memory to be displayed or trans-¦ mitted to a remote devlce. Multibrator 1122 is a slightly . ' ' ' ', . 1, , ,, , , , , .
,, , jl -66-~Z~4~3l faster reacting multivibrator which is utilizecl to signal Il the end of a byte o image data to the video display con-¦¦ troller circuit, thus triggering the reading and displaying ¦ of that byte of data. Multivibrator 1123 is the address ' 1 advance vibrator, which is'utilized to load or increment the address counters which are utilized to access image data.
Referring~now to Figures lle, l~f and llg, which, when joined in the manner indicated in the figures, form a l schematic diagram of the,video screen format timing circuitry ¦ of the video formatter of the present invention. The circuitry thus depicted is that circuitry which allows the definition of the discrete display areas previously dis- !
l . . , i cussed. Each of the display areas or zones is defined by an l operator in terms of'certain parameters. These parameters ¦ include the zone width and height. The zone height is ,¦ defined by an arbitrary dimension called "rows" and each ''row'' is further defined as a particular number of scans by ¦ the control device.
!¦ ' 'Recalling that.although nine discrete display 1l areas are possible in the disclosed embodlment, an addi-tional seven areas are also defined and are utilized for horizon,tal and vertical retrace in the video terminal appli-¦ cation. The data defining these 16 zones is stored in ¦~ counter control memories,which serve to control associated ¦ counters. Each of the counter control memories is comprised li of a sixty-four bit random access memory, organized into sixteen four bit,words.
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Thus, counter control memories 1124 and 1125 are loaded with data specifying the number of scans of the ¦ display system per row of height. In actual practice, the ¦ data loaded into counter control memories 1124 and 1125 ¦ represents the two's complement of the desired number. The two's complement is utilized to permit simplified operation ! of four bit counters 1126 and 1127, which are loaded with ¦the two's complement number and allowed to count to a carry condition.
In similar fashion, counter control memories 1128 ¦and 1129 are loaded with data specifying the zone height in rows, and serve to control four blt counters 1130 and 1131.
Additionally, counter control memories 1132 and 1133 are l loaded with data specifying the width of-the zone and serve to control four bit counters 1134 and 1135. Those skilled in the art will appreciate that the sixteen four bit words I stored in each counter control memory will serve to define i sixteen separate zones. `
l Multivibrator 1136 is utilized to keep track of ' whether the current rame is odd or even in number, to Ipermit control of the interlace circuitr~ utilized to in-! crease image resolution. Four bit counter 1137 is utilized lin conjunction with the video display controller circuitry when alphanumeric characters are being generated. A par-ticular code specifying a selected alphanumeric character is utilized to enable the video display controller circuitry to ge er-te the selected character, howevor, it is still . ' ' - , ' ,' l .
~ -68-~ ... .......

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necessary to keep track of what scan through the display device tlle system is currently'displaying. Indivldual characters, ln the dis'elosed embodiment of the present , invention, are typieally twelve scans in height and the image generated to perform a particular character will vary with eaeh scan. Four bit counter 1137 is thus utilized to count the number oE scans during character generation.
Those skilled in the art will appreciate this as being standard dot-matrix character generation.
'10 Multivibrators 1138 and 1139 are utilized to cause the initial loading of counters 1126, 1127, 1130, 1 1131, 1134~ 1135 and 1137 from their respective control ¦ memories, during startup. Once operating, the aforemen-¦ tioned counters are reloaded during'each carry condition, ¦ however, initially this load must be forced as no earry exists'. Multivibratox 1140 is utilized during alphanumerie character generation to ensure that an address bump by delta (explained below) does not occur until after twelve scans ' are complete, thus ensuring continuity of alphanumeric characters. Multivibrator 1141 is utilized to ehable the address control memories during the first scan in each band of the display. Multivibrators 1142 and 1143 are coupled to the carry outputs of eounters'll34 and 1135,and arè utilized to generate various zone ~idth carry,signals (ZWCRY) for utiliz~ti througbou~ tho video 'ormatter.

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Logic gates llq4a-1199d are coupled to the outputs of zone width counters 1134 and 113S and the mode select signal and are utilized to generate wait signals to a con-trol device.
Referring now to Figures llh and lli, and the joint figure formed thereby, there is depicted the display address circuitry of the video formatter of the present invention.
¦ Having previously defined the-parameters of each ;
l of the sixteen zones (nine of which are display zones and llseven of which are utilized for retrace signals) in terms of !I zone width and zone height in the arbitrary dimension of ¦I''rows'' and the number of scans through the display per I¦ "row," it is now necessary to provide two additional pa-- l¦rameters to operate the video formatter in the manner described.
! First, it is necessary to define a starting I address within the image memory to determine what section of l¦the image will be contained within a selected zone. Sec-11 ondly, it is likely that the zone width may not be suf-¦ficently wide to encompass the entire image, and therefore simple unitary address incrementing will not sufflce. As ¦ the end of the zone width is reached, the address of the ¦ next byte of image data displayed must be determined by 1 incrementing with a selected number, which is dependent upon the width of the entire image. T~is selected numbex is referred to variously herein as the "delta" or "bump"
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~incremen . The bump incremen~ is calculated by examining the width of the image and determining what number must be I I added to the starting address to arrive at the start of the next scan through that zone.
The s,tarting address of each of the zones within the display may be stored within control memories 1145-1149 Control memories 1145-1149 are also sixty-four bit random , access memories, organized into sixteen four bit words. As I a matter of design choice, the address of image data stored 1 within image memories in the video formatter of the present l invention typically contains seventeen bits. Thus, control i memories 1145-1149 are capable of storing the seventeen bit ,Istarting address of each of the sixteen display zones as I¦written into the control memories by a control device.
1I Control memories 1150-115~ are utilized in a similar manner to receive and store the "delta" or "bump"
number by which the address of the next byte of image to be lldisplayed is determined.~ The starting address of each scan ,ithrough the zone is incremented ~y the bump increment to !addres,s the first bit of image necessary for the next scan through a selected zone. Quad two input multiplexers 1153-j1155 are utilized to shift the "delta" number and thereby llmultiply lt ~y two. This shiftin~ is necessary du~ing ¦interlace in the non alphanumeric (image) mode. Interlace llis utilized to increase resolution of the image, and is accomplished by skipping a line of the image,and then ~utilising the skipped imago data during the next complete I
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ll -71-` 1 . 122~6~ 1 frame of the image. In order to skip a line of image data, the increment number must be twice the normal number to arrive at the address of the beginning of the scan following the next scan.
Having defined each ~one by size and starting address within the image memory, and by knowing the incre-ment or address necessary to address the first bit in the next scan through the zone, it is possible to display a l variable window within the display which may be easily l scrolled in either axis (by incrementing the starting ad-dress) or enlarged (by changing zone dimensions) and may be utilized to visually display a selected portion of an image.
Further, as will be explaine~ below, certain zones may be l dedicated to alphanumeric characters indicative of operating 1 parameters, prompting cues or other pertlnent data.
Referring now to the joint figure formed by Figures llj and llk and to Figure lll, there is depicted a j schematic diagram of the~display address generation cir-l cuitry of the present invention.
20 - I As discussed above, during operation o~ display devices, as the beginning of a zone occurs, the previous starting address must be incremented by a value equal to l that of the width of the image to ensure that appropriate ; ! data is available during the next scan through a zone (or by I twice the width of the image if image interlace is desired).
Since this increment must take place at the beginning of each scan throuyb a ~one, it i~ convenie~t to co~duct such .' ,,'', . ' .

IZ~14~

!l an incrementation at each scan, including the first scan.
¦ISince the increment would then be added to the starting address for each zone, a compensation offsek to each start-ing address is necessary.
The aforementioned compensated starting address is stored as previous]y discussed, in control memories 1145-114~ and is coupled to the inputs of four bit full adders 1156-1160. Also coupled to adders 1156-1160 are the outputs , I of multiplexers 1153-1155, representing the "delta" incre-¦¦ment. Thus, adders 1156-1160 add the delta increment to the ¦¦compensated s,tarting address and couple the sum to four bit i by four bit registers 1161-1165. The data thus stored ¦ represents the actual starting address o~ lmagP data to be ! displayed in each zone.
lS I The outputs of registers 11~1-1165 are coupled to ¦¦four bit up counters 1166-1170. Counters 1166-1170 are four I bit counters with three state outputs which are utilized to increment the address da~a. The,initial data clocked into I counters 1166-1170 is immediatel~ clocked out onto the bus . I¦ and around to adders 1156-1160 to be incremented b~ the ,¦delta increment again. As the new starting address (for the , next scan) is coupled into registers 1161-1165, counters 1166-1170 ~egin unitary incrementation of the previous starting address. It is therefore possible, with ~he de-picted circuitry, to generate a starting address,,increment that address until the zone boundary is reached,,add a delta increment to n~e previous sLarting address to obtsin tle , , I . ' , '' .. l .. ..
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.
, -73-LZZ146 1l next starting addres's, and begin incrementing again when the zone is next entered. Also depicted in Figure llk are buffers 1171 and 1172 which are utilized to couple the control device into the internal bus.
. 5 Referring now to the joint figure formed by Figures llm, lln and llo, there is depicted a schematic diagram of the video generatlon and video display controller il circuitry of the video formatter.of the present invention.
¦ Centxal to the video generation'and video attri-¦ bute circuitry is video generator 1173. Video generator 1173 is comprised of, in the illustrated embodiment, an SMC
il 8002 video display controller manufacture'd by the SMC Micro~
il systems Corporation o~ Hauppauge, New York, and contains a Il mask programmable, on chip, one hundred twenty-eight bhar-1¦ acter generator which utilizes a seven by eleven dot matrix ¦ block. Video generator 1173 also includes attribute logic I including reverse video, character blank, characte;r blink, - ¦ underline and strike-through.' Additionally, video generator l 1173 has four cursor modes including.underline, blinking l underline, reverse video and. blinking reverse yideo.
ll Attribute control signals are coupled to video .
Il generator 1173 by means.of multiplexers 1174 and 1175.
l¦ Multiplexers. 1174 and 1175 receive their inputs from either ¦ attribute latch 1176 or from the data bus. If a global i attribute is selected, the coxrect attribute code is written into attribute control memories 1177 and 1178 by the control device. Attribute contlol memorie 1177 and 1178 are . .' ,'' .'' . . , '.' ''.

l -74~

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¦¦sixty-four bit random access memorie~ and are utilized to store the attribute codes for each of the display zones.
During field attribute operation (available only in the alphanumeric mode), selected data from the data bus is utilized to generate specific attributes for selected portions (fields) o~ the display ~one, rather than,the entire zone as in global attribute vperations. The selected field attribute data is applied to video generator 1173 by I means of multiplexers 1174 and 1175. Additional data from ¦ the data bus is applied to pins AO-A6 of video generator 1173 and is utilized to select a specific character from the character generator.
Logic gates 1179 and 1180, and the logic gates !¦associated therewith, are utilized as a gating ~unction for l¦ the attribute capability. Logic gate 1180 is utilized to ~enable multiplexers 1174 and 1175,and the output of logic ! gate 1179 is applied to the attribute enable pin (ATTBE) of i video generator 1173, thus controlling the generation of ¦ video attributes.
~: 20 ¦1 Retriggerable single shot multivibratoxs 1181, j1182 and 1183 are utilized in conjunction ~ith four bit ~! counter 1184 to time and generate horizontal and vertical sync pulses. Multivibrator 1181 tri~gers for approximately l¦2.5 microseconds after the beglnning of horizontal retrace 'Ito provide what is commonly referred to as the "fxont porch"
of the horizontal retrace pulse. One output of multivibra-tor 1181 is utilized to ~rigger multivibratox 1182 Which , il l -75-2;2~ 6~ ;

provides a five microsecond horizon~al sync, the remaining peri~d of hortzontal retrace is the "back porch".
Multivibrator llB3 is u~ilized to provide inter-lace holdoff of the vertical sync pulse~ Vertical sync is delayed for approximately one-half of the horizontal sweep time to cause interlace and thereby increase image resol-ution. Four bit counter 1184 is the~ utilizea to generate ¦ the vertical sync pulse and the "front porch" and "back porch" periods.
Multivibrators 1185 and 1186 are ~tilized to provide a delay before the application of horizontal retrace blanking to compensate for delay encountered due to pipe-lined internal operation during character generation by video ~enerator 1173. Interface 1187 is provided to inter-connect the video formatter of the present invention to a video terminal interface for use in a video subsystem.
Referring now to Figure 12a, there is depicted a schematic diagram o~ the cursor control circuitry of the l video formatter of the present invention. Memory locations ¦ within the image memory of the video formatter of the present ! invention are, as a matter of design choice, characterized ¦ by seventeen bit addresses. Since a typical microprocessor type control device utilizes an eight bit bus, three sepa-rate write commands must be generated to load in seventeen bits. The cursor address is loaded into multivibrator 1201 and eight bit registers 1204 and 1205. The additional circuitry depicted is coupled to the video address bus and -! `~ .

¦ is utilized to compare the curscr address with each video address and generate the cursor signal when the correct I address is reached.
¦ Logic gate 1207 is utilized to compare one bit of cursor address ~ith one bit of video address, and to enable eigllt bit comparators 1202 and 1203. If the comparator circuitry indicates a match, and the video display terminal I is not in the image mode (no cursor being utilized during image mode) then logic gate 1206 is utilized to generate the ¦ cursor signal.
With reference now to Figures 12b and 12c, and the joint figure formed thereby, there is depicted a schematic ! diagram of the intra device addressing circuitry and run , length counters of the video formatter of the present inven-1 tion. As discussed with respect to the data compression system, it is possible to have up to sixteen separate ad-dressable registers per system which may be directly ad-dressed by a control device.
Il The address of a selected register is coupled from ! a microprocessor type control device through buffers 1208 il and 1209 r while various control signals are coupled through ,¦ buffer 1210. Wire strap option 1211 is utilized to speci-¦¦ fically identify a particular video formatter, and the ~ register address is applied to field programmable logic l arrays 1212 and 1213, where the actual addr~ss data is ~ decoded ar.d utilized to aore,s dcsired regi5ters.

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Also depic~ed in Fi.gure 12c are the run leng~h counters and controllers. ~ecalling that the video ima~e data being generated by the data expan.sion circuitry may be . generated in either a ladder or scan mode, it is necessary to keep track of the length of each "run" of data through . the image in order to accurately reconstruct an original image as the data is loaded into display memory.
As in previous similar circuits, the run leng-th is loaded into counter control registers 1214 and 1215, in two's complement form. The contents of xegisters 1214 and 1215 are then loaded into four bit counters 1216-1219, and counters 1215-1219 are incremented until they reach a carry condition, tllus indicating the end of a run of data.
Referring now to the joint figures formed by joining Figures 12d and 12e and by joining Figures 12f and 12g, there `is depicted the address generation circuitry whereby image data coupled to the video formatter is stored in image memory within the video formatter. Recalling the discussion of ladder format versus scan format for image data, those skilled in the art will .appreciate that coherent l storage of image data within the image memory will require I that each successive byte of image data, while in the ladder ¦ format, will be stored at an address in memory which is l either greater than or less than the previous address by a value equal to the width of the image. As counters 1216-1219 enter the carry condition, indicating the end of a run, the next b~ e of imago data -ll be stored a~ an address . ,,. ,.
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l ~78-ll ~LZ2~L4~61 which is either greater than or less thasl the previous starting address by one. Conversely, while in the scan ¦ format, image data addresses will increment or decrement by . ~ one, until a carry condition in counters 1216-1219 indicates 5 . I the end of a run, at which tlme the next byte of data will be stored at an address.greater than, or les~ than the pre-vious starting address by a value equal to the width of the . image~ The determination in either case of whether to I increment or decrement the address of the image data is l¦ determined by the point in a document image at which the !I data begins. .
Data bus transceiver 1220 is utilized to couple the value of the width of the image to width registers 1221 ! and 1222. The two most significant bits in register 1222 l (pins 8Q and 7Q) are utili2ed for the sign bits for the j address increments~ The outputs of width registers 1121 and Il 1222 are coupled to multiplexers 1223-1226. Multiplexers !i 1223-1226 are utilized to outp~t either a plus or a minus . ,j one, or a plus or minus width value, as determined by image ¦1 orientation. .
¦¦ . The output of multiplexers 1123-1126 is then .
l coupled to full adders 1227a-1227f tadders 1227e and 1227f are depicted in Figure 12g) where, the address increment or I¦ decrement is added to the previous address, or previous ¦ starting address to determine the storage address for the ~ next byte of imago data. The result of this address !

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incrementing is coupled to address registers 1228a-c ~reg- ¦
ister 1228c i5 depicted in Figure 12g).
Bus transceivers 1229~1231 are utilized ~o couple the image data address to the control device. Registers 1232-1234 are utilized to temporarily store the starting address o~ each run of image data. The starting address is ¦¦ utilized when counters 1216-1219 enter a carry condition, indicating the end of a run. The next data address is determined by incrementing the previous starting address, -1 and registers 1232-1234 are therefore utilized to retain each starting address of a run.
Referring now to Figures 12h and 12i, and the joint figure formed thereby, there is depicted a schematic I representation of certain of the timing circuits of the 1 video formatter of thè present invention. Four bit counter ¦ 1235 serves as the end of data timer for the video formatter, ¦ counting the number of clock signals after data reception on I the X bus ceases.
l As a matter of design choice, if the X bus clock 1 goes low for eight master clocks, the system will interpret I it as an end of data, causing end of data multivibrator 1236 ¦ to set. The output of multivibrator~1236 is utilized to clear multivibrator 1237, but not until the completion of any memory access in progress. Multivibrator 1231 ~lso serves to generate the busy signal when data is being received.

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Dual four bit ripple counters 1238 and 1239 are ! the refresh timers which are utilized to time the periocls between each successive reEresh operation of the image I memory. Refresh takes place every 1.6 milliseconds, and the S ~ signal output from logic gate 1240 ~XCMMIT) is utilized to cause the incoming data on the X bus to temporarily stop.
The refresh signal (RFRSH) is coupled to ripple l¦ counter 1241 which is utilized to cycle through the row !i addresses of the image memories to accomplish refresh. The ~I refresh addresses thus generated are latched out through the ¦Ithree state outputs of buffer 1242.
l Dual serial/parallel latch 1243 is the receive I latch for image data input frQm the X bus. Latch 1243 i accepts eight bits serially off the X bus and then shi~ts ! the eight bits into an eight bit wide parallel output latch where they are gated to the data bus and written into image memory while the next eight bits are being shifted into latch 1243. Four bit counter 1244 is utilized to count the ¦input bits from the X bus to determine when an eight bit l¦byte has been input to th~ system. One ou-tput of counter '¦1244 is utilized to set first byte multivibrator 1~45.
First byte multivibrator 1245 is utilized to disable the writing of data into the image memory. Recalling the opex-ation of latch 1243, those ordinarily skilled in the art 2~ will appre a~e that ~s byle of daea _s a~cumulated, th~

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.',' l . ' ' , .j . ''' i~ ~22146 j, , ., previous byte is being wxitten illtO memory. Since during accumulation o~ the first byte, no previous byte exists, the memory write is disabled.
~ Second byte multivibrator 1246 is cleared at the I second byte of image data and is utilized to provide the load pulse which causes the run length to be loaded into counter control registers 1214 and 1215. (see Figure 12c) Further, since the address incrementing circuitry will not I be required for the starting address of image data, multi-¦ vibrator 1246 also is utilized to disable multiplexers i 1223-1226. (see Figure 12d) ¦I Four ~it counter 1247 is the memory timing gener-- l¦ ator, which is utilized to operate the ima~e memory independ-ll ently of the X bus clock. Each time an eight bit byte is jl accumulated in latch 1243, multivibrator 1248 is utilized to ''I initiate a memory timing cycle, through logic gatè 1250 and il multivibrator 1249.
Re~erring now~to Figures 12j and 12k, and the ~¦ joint figure formed thereby, there i5 depicted a schematic li representation of the display memory timing and control , circuitry of the video formatter of the present invention. I
'j Multiplexers 1251 and 1252 are utilized to multi- ¦
¦ plex the video address into row and column addresses. The l~ outputs of multiplexers 1251 and 1252 are coupled to buffers 1 1253 and 1254, which are utilized to drive the image memory ¦ addres~ lines.
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Data is wxitten into the image memory via write buffer 1255 and may be read out onto tlle data ~us via buffer 1256. One of eight decoder 1257 is utilized to decode the l highest three bits of video address to select one of the 1 elght banks of image memory. A bank of image memory is ¦ selected by selecting the proper column address strobe ¦ signal (CAS). The selected bank column address strobe i signal is driven by buffer 1258, which is disabled during l refresh by the output of logic gatë 1260, acting as an ; 10 l inverter.
Bu~er 1259 is utilized to drive the write and row I address strobe signals. Shift registers 1261 and 1262 are driven by the 30.5 megahert~ clock and are utilized to I generate timing signals for the image memory. Wire strap ll options 1264 and 1265 are utilized to vary the timing signals ¦¦ generated to accomodate various types of integrated circuit ~I memories which may be utilized in the image memory~ Multi-I vibrator 1263 is cleared by the obtput of logic gate 1266 during a read, write or refresh action, and serves to control 1 shi~t registers 1261 and 1262.
! Referring now to the joint figure ~ormed by joining j Figures 121, 12m, 12n and 12O, there is depicted a schematic 11 representation of the image memory of the video fo~matter of !I the present invention. Image memory integrated circuits !¦ 1266a-h, 1267a-h, 1268a-h, 1269a-h, 1270a-h, 1271a-h, 127Za-~ h and 1273a-h are e-ch, in a preferred e~oodiment, a 16K bit ~1 ' ''- ' ,.
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dynamic random access memory, such as the 'I'MS 4116 manu-factured by Texas Instrùments, Incorporated of Dallas, I Texas. The eight banks of memory fo~m a 128K byte image ¦Imemory which contains sufficient image data to accurately portray an entire display image. Further, in addition to image data, alphanumeric character codes may be stored I within the image memory for character generation by means of video generator 1173 (see Figure lln).
il Finally now, referrirlg to the joint figures formed i by joining Figures 12p and 12q in the manner indicated in the figures, there is depicted a schematic diagram of the , interface circuitry which couples the video formatter of the present invention to the other subsystems in the document processor by means of the X bus.
- 15 1 X bus control register 1274 is an internal video I formatter register which is directly addressable by the external control device in the manner described herein. The jdata input to X bus control re~ister 1274 is utilized to 'jselect a particular one of the eight X bus channels, and lalso specifies whether the video formatter will receive data or transmit data :
!I The upper four bits in X bus control register 1274 ,Ispecify a receive condition and are applied to one of ten lldecoder 1275. The output of one of ten decoder 1275 is 1! applied to inverter buffer 1276 and is then utilized to select one of the eight X bus transceivers 1278a-h.

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In the transmit mode, the lower ~our bits of X bus control register 1274 are utilized and specify a transmit condition. The lower four bits are applied to one of ten decoder 1277, the output of which is utilized to select one of eight X bus transceivers 1278a-h.
During transmission of data from the video for-matter, eight bit wide bytes of data are coupled to parallel in-out shift register 1279 for serialization and application to X bus transceivers 1278a~h.
Multivibrator 1280 is utilized to temporarily pause transmission of data during the refresh cycle, and is gated to ensure that the pause takes place at the end of a clock pulse, to prevent possible split clocks. Multivibra-tor 1281 is set and holds the clock low when the end of image data is encountered. After the last bit of data in the sixteen display zone has been transmitted, multivibrator 1281 is set and remains set until cleared by the external control device. This provides the end of data signal to the receiving device.
¦l LASER PRINTER SUBSYSTEM
l An important feature of the document processing ¦ system of the present invention is the ability to produce a facsimile image of the entire image of a processed document, any portion thereof, or multiple portions thereof, for inclusion in a s-tatement, letter, or other document. With referonce again to Flgure 1, the documen~ images for a ' ' ',' . ', ~1 , ,, I
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plurality o~ documents are stored, in one preEerred embodi-ment, in magnetic disk storage. Digital computer 100 accesses a selected plurality o~ digital images via disk ~ controller 102 and channel selector 116.
The selected digital imayes are transEerred through multiplexed direc-t memory access 166l a sixteen channel direct memory access designed to be compatible with digital computer 100. The'selected digital images are then transferred to local X bus through multiplexed direct memory ¦access 164, a fo~r channel direct memory access designed to ¦be compatible with the microprocessor utilized in the'local subsystems. If the image data selected is in compacted form, it is transferred via local X bus to digital image expander 162 for expansion. The resultant expanded data is transferred through X bùs distributor 170 and X bus dis-tributor 132 into a video formatter 134 for formatting and interfacing into the sequence requlred by the specific laser printer system. Video formatter 134 utilizes identical circuitry to that utilized in video forma~ters 100~, 1010, 1012 and 1014 of Figure 10, and that circuitry is explained ¦ in greater depth with reference to Figures lla-llo and 12a-12q. The properly formatted image data is temporarily stored in image memory 128, and selectively applied to laser printer 130 by printer controller 126.
Video formatter 134 may also be utilized to gen-erate alphanumeric characters for use in addition to the digital'image data, ln those applications wherein a single . . , ,, ,~.
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document is required to have an irnage and alphanumeric information. In such applications, the ima~e and data reguired for the alphanumeric characters are both stored ln image memory 128.
Laser printer 130, in the embodiment disclosed, is a Model ND2 high speed printer manufactured by the Siemens Corporation of Cherry Hill, New Jersey. Laser printer 130 employs laser technology and electrophotogra~hic techniques.
The digital image data is utilized to control a laser which exposes selected portions of a rotating, photocond~ctor surfaced drum. Toner will adhere to the exposed portions of the drum and will then be transferred to paper in the manner well known in the art.
It should ~e appreciated by those skilled in the ¦ art that ink jet or other state o~ the art printing systems may be utilized with the document processing system of the present invention.
¦ Although the invention has been described with r~ference to a specific embodiment, this description is not meant to be construed in a limiting sense. Various modifi-cations of the disclosed embodiment às well as alternative embodiments of the invention will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that the appended claims will cover any such modifications or embodiments that fall within the true scope of the invention.

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Claims (7)

WHAT IS CLAIMED IS:

1. A digital document scanning system comprising:
digital scanning means including a fixed array of photo-electric transducers arranged to scan in a selected axis along a fixed focal plane;
transport means for transporting a continuously moving series of variegated documents along said fixed focal plane;
means for generating a first output signal when a selected output of said fixed array of photoelectric transducers is above a reference level and a second output signal when said selected output of said fixed array of photoelectric transducers is below said reference level; and means responsive to the outputs of said fixed array of photo-electric transducers for adjusting said reference level.

2. A digital document scanning system comprising:
digital scanning means including a fixed array of photo-electric transducers arranged to scan in a selected axis along a fixed focal plane;
transport means for transporting a continuously moving ir-regularly spaced series of documents along said fixed focal plane;
means for selectively coupling the outputs of said fixed array of photoelectric transducers to an output bus in response to a control signal ; and means responsive to particular outputs of said fixed array of photoelectric transducers for producing said control signal.

3. The digital document scanning system according to claim 2, further including an illumination source focused upon said fixed focal plane.

4. The digital document scanning system according to claim 2, further including a second digital scanning means whereby said system scans both sides of each document.

5. Digital document scanning system for capturing and digitizing the image from the face of documents having backgrounds of different hues, said scanning system comprising:
transport means for continuously transporting said documents past a viewing station, illumination means for directing light at said viewing station, scanning means comprising a fixed array of photoelectric transducers so disposed with respect to said viewing station to receive light reflected from said documents, each of said photoelectric transducers generating signals having levels proportional to the intensity of the reflected light impinging thereon, whereby the intensity of said reflected light, and the signal levels from said transducers, vary as a function of said different hues, and means coupled to said scanning means for discriminating between the document background and data appearing on the face of each such document, for documents having backgrounds of different hues, said discriminating means comprising:
dynamic threshold adjustment means responsive to the levels of signals from said scanning means for establishing a reference signal, the level of the reference signal varying as a function of said different hues, and indicative means for generating a signal which is indicative of said document background when a level of a signal from said scanning means has a first relationship to the so-established level of said reference signal, and for generating a signal which is indicative of said data when a level of a signal from said scanning means has a second relationship to the so established level of said reference signal.

6. The digital document scanning system as defined by claim 5 wherein said first relationship is when the level of said signal from said scanning means exceeds the level of the said established reference signal, and wherein said second relationship is when the level of said signal from said scanning means is below the level of said established reference signal.

7. The digital document scanning system as defined by claim 5 wherein:
said array has odd and even numbered photoelectric transducers;
said scanning system further comprises:
(a) first means for amplifying the electrical signals from the even numbered photoelectric transducers of said fixed array, and (b) second means for amplifying the electrical signals from the odd numbered photoelectric transducers of said fixed array, said indicative means comprises first and second comparator means, the output of said first amplifying means being coupled to an input of said first comparator means, the output of said second amplifying means being coupled to an input of said second comparator means; and said dynamic threshold adjustment means comprises OR gate means and a capacitor, the outputs of said first and second amplifying means being respectively coupled to said respective inputs to said OR gate means, the output of said OR gate means being connected so as to charge said capacitor, said OR gate output also being connected to another input of said first comparator and to another input of said second comparator.