CA1216639A - Voltage controlled pulse width modulation circuit - Google Patents
Voltage controlled pulse width modulation circuitInfo
- Publication number
- CA1216639A CA1216639A CA000473844A CA473844A CA1216639A CA 1216639 A CA1216639 A CA 1216639A CA 000473844 A CA000473844 A CA 000473844A CA 473844 A CA473844 A CA 473844A CA 1216639 A CA1216639 A CA 1216639A
- Authority
- CA
- Canada
- Prior art keywords
- output
- input
- terminal
- operational amplifier
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000000977 initiatory effect Effects 0.000 claims abstract description 4
- 230000005281 excited state Effects 0.000 claims description 7
- 230000001419 dependent effect Effects 0.000 claims description 3
- 238000012935 Averaging Methods 0.000 claims 1
- 230000001960 triggered effect Effects 0.000 claims 1
- 239000003990 capacitor Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0232—Monostable circuits
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- Pulse Circuits (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A pulse width modulation arrangement for providing an output pulse having a duration which varies linearly with an input control signal having a comparator for comparing signals on first and second inputs, a synchronization network including an RC timing network for initiating the output pulse and for supplying a time varying signal to the first input of the comparator, and a feedback arrangement having one input connected to the output of the comparator, a second input for receiving the input control signal and an output connected to the second input of the comparator for controlling the comparator so that the output pulse on the output of the comparator bears a substantially linear relationship to the input control signal.
A pulse width modulation arrangement for providing an output pulse having a duration which varies linearly with an input control signal having a comparator for comparing signals on first and second inputs, a synchronization network including an RC timing network for initiating the output pulse and for supplying a time varying signal to the first input of the comparator, and a feedback arrangement having one input connected to the output of the comparator, a second input for receiving the input control signal and an output connected to the second input of the comparator for controlling the comparator so that the output pulse on the output of the comparator bears a substantially linear relationship to the input control signal.
Description
~Z16~39 VOLT ~ONTROLLED_~ULSE WIDTH ~ODUL~ION CIRCUIT
BACKGROUND OF THE INVENTION
The present invention relates to a pulse width modulation circuit in which the duration of the output pulse varies according to an input signal such as an input voltage and, more particularly, to such an arrangement wherein the output pulse varies in a linear manner with the input signal.
Pulse width modulation circuits have found many applications such as, for example, in condition controlling systems. In such systems, a sensing apparatus senses a condition being controlled and provides a signal which has a level dependent upon the condition being sensed. The level of this signal then controls the width of the output pulse from a pulse width modulator. This output pulse controls a load which in turn controls the condition, the load being controlled as a function of the width of the output pulse.
Prior art pulse width modulated circuits have traditionally provided output pulses which vary in a nonlinear relationship with the input voltage or signal.
If this nonlinearity remains uncompensated, the control action in a condition controlling system will be inaccurate. The present invention provides a simple means for insuring that the output pulse width it linear in relation to the controlling input signal or voltage.
SWAMPIER OF THE INVE~CIQN
Accordingly, a pulse width modulation arrangement for supplying an output pulse hazing a duration which varies linearly with an input control signal is provided having a comparator with first and second inputs and an output, the comparator comparing a first signal on the first input with a second signal on the second input, a synchronization input circuit connected to the comparator for initiating the output pulse, the synchronization arrangement including a timing network connected to the first input of the comparator, the timing network providing an input timing signal varying with time, and a feedback network having an output connected to the second input of the comparator for supplying the second signal, a input connected Jo the output of the comparator, and a second input for receiving the input control signal, the feedback network being arranged to control the comparator so that the output pulse bears a substantially linear relationship with the input control signal.
63~
BRIEF DESCRIPTION OF THE DRAWINGS
These and other features and advantages will become more apparent from a detailed consideration of the invention when taken in conjunction with the drawings in which:
Figure 1 shows a prior art pulse width modulation arrangement;
Figure 2 shows a pulse width modulation arrangement accord-in to the present invention;
Figure 3 shows the functional contents of the 555 timer shown in Figures 1 and 2;
Figure 4 shows a timing diagram for the signals associated with Figure 2; and, Figure 5 shows a refinement of the pulse width modulation arrangement shown in Figure 2.
DETAILED DESCRIPTION
The prior art arrangement as shown in Figure 1 typically uses a standard 555 timer connected in a monostable multi vibrator configuration as shown with the input trigger signal connected to sync terminal 11. Timing capacitor 12 is connected between ground and the threshold input terminal of the timer 13 and is also connected through diode 14 to sync terminal 11. The voltage source Vcc is connected to one side of timing resistor 15 to the other side of which is connected to capacitor 12~
I 63~
The output pulse from timer 13 is initiated when the sync pulse drives terminal 11 low discharging capacitor 12 through diode 14. At the same time, the sync pulse drives the output of the 555 timer high or to its excited state. This excited state is defined as the output pulse. The period T of the output signal is determined by the period of the sync pulse. As capacitor 12 charges, timer 13 compares the voltage across the capacitor with the input control voltage Viny Once the voltage across capacitor 12 reaches a predetermined relationship with respect to the control voltage Viny the output signal switches to its unexcited state which, in the example shown, is low.
The relationship between the control voltage Viny and the duration of the output pulse is defined by the following equation:
to = RtCtIn loin (1 ) where to is the length of the output pulse, Rut is the resistance of the timing resistor, Cut in the capacitance of the timing capacitor, Viny is the input control voltage, and Vcc is the supply voltage to the timer 13.
As can be seen from this equation, the duration of the output pulse, Leo the excited state on the output line 16, is a nonlinear function of Viny Also, the length to of the output pulse is dependent on timing components Rut and Ct.
I ~21~39 Figure 2 shows an approach by which the length of the output pulse is made linear with respect to the input control voltage and independent of the timing resistor and capacitor The common portions between Figures 1 and 2 have the same reference numerals.
However, Figure 1 has been modified according to the inventive concept so that the length of the output pulse is linear with respect to the input control voltage and independent of the timing ARC network.
Output terminal 16 is connected to one input of operational amplifier 17 through feedback resistor 18.
The other input, the positive input, of operational amplifier 17 receives the input control voltage Viny The output of the operational amplifier is then connected to the voltage control terminal Icon of timer 13 and is also connected back to its negative input through feedback capacitor 19.
Figure 3 shows a block diagram of the standard timer 555. Also, Figure 4 shows the timing diagram for the arrangement shown in Figure 2. The output pulse is initiated by the leaving edge of the negative going sync pulse. The sync pulse sets flip-flop 21 through comparator 22 for setting output line 25 to its excited state through output stage 23. At the same time, discharge transistor 24 is turned off which will permit the capacitor to begin charging. However, the charge on capacitor 12 is held to one diode drop my diode 14 until ~i216639 the negative going sync pulse terminates. When this sync pulse terminates, the capacitor 12 is allowed to charge through timing resistor 15 from source Vcc.
Comparator 2Z will compare the voltage across capacitor 12 at its input line Vth to the control voltage Icon When the charge across capacitor 12 reaches the control voltage Icon comparator 26 will reset flip-flop 21 for resetting the output on line 25 to terminate the output pulse.
When the inputs to amplifier 17 are balanced, Viny is given by the following equation:
Viny TV OH + TDVOH + T-- SOL (2) where Viny is the input voltage, to is the length of the sync pulse, T is the period of the sync pulse which also matches the period of signal on the output line, VOW is the voltage of the output pulse, to is the length of the output pulse less the length of the sync pulse, and VOW
is the voltage on the output line during its unexcited state. This equation can be rewritten to yield the following equation:
VOW OX OH OX
If the period of the signal on the output line is very much greater than the length of the sync pulse to, then equation (3) reduces to the following equation:
to V -v T (4) I I
As can be seen from equations 2, 3 and 4, if the load on output line 16 is constant, then there is a linear relationship between the duration of the output pulse and the input voltage Viny The operational amplifier 17 configured as shown in Figure 2 is an integrating amplifier which tends to average the signal on output line 16 arid supply an output voltage to the control voltage terminal Icon of timer 13 that is the difference between the controlling input signal Viny and the average of the voltage on line 16. Thus, operational amplifier 17 will operate to balance the voltage on output line 16 with Viny In this manner, the duration of the output pulse is made linear with respect to the input control signal Viny and independent of the timing network comprising capacitor 12 and resistor 15.
As mentioned above, it is assumed that the load on output line 16 is and remains substantially constant.
Figure 5 shows an arrangement which includes a buffer 30 in the case where the load on the output of timer 33 varies. Compensation such as buffering is required since a change in load will change VOW and Volt Thus, a Zoner clamp 32 is provided having one side connected to ground and the other side connected to the output voltage terminal Volt of timer 13 through resistor 31.
The junction of resistor 31 and Zoner diode 32 is connected through resistor 33 to the base of ~2~3~
transistor 34 having its collector connected to source Vcc and its emitter connected to the output terminal 36. Resistor 35 connects the emitter of transistor 34 to ground. Buffer 30 then acts to isolate the load on line 36 from output 16 of timer 13.
The Zoner changes equations 3 and 4 to:
to = Viva a T V~tz (5 and to in Volt (6) where Vz - zoner voltage thereby restricting Viny to VoL<vin~vz -Also, RUB may not be necessary since voltage across resistor 35 would not exceed Vz-VBE and current is limited through transistor 34 by resistor 35.
BACKGROUND OF THE INVENTION
The present invention relates to a pulse width modulation circuit in which the duration of the output pulse varies according to an input signal such as an input voltage and, more particularly, to such an arrangement wherein the output pulse varies in a linear manner with the input signal.
Pulse width modulation circuits have found many applications such as, for example, in condition controlling systems. In such systems, a sensing apparatus senses a condition being controlled and provides a signal which has a level dependent upon the condition being sensed. The level of this signal then controls the width of the output pulse from a pulse width modulator. This output pulse controls a load which in turn controls the condition, the load being controlled as a function of the width of the output pulse.
Prior art pulse width modulated circuits have traditionally provided output pulses which vary in a nonlinear relationship with the input voltage or signal.
If this nonlinearity remains uncompensated, the control action in a condition controlling system will be inaccurate. The present invention provides a simple means for insuring that the output pulse width it linear in relation to the controlling input signal or voltage.
SWAMPIER OF THE INVE~CIQN
Accordingly, a pulse width modulation arrangement for supplying an output pulse hazing a duration which varies linearly with an input control signal is provided having a comparator with first and second inputs and an output, the comparator comparing a first signal on the first input with a second signal on the second input, a synchronization input circuit connected to the comparator for initiating the output pulse, the synchronization arrangement including a timing network connected to the first input of the comparator, the timing network providing an input timing signal varying with time, and a feedback network having an output connected to the second input of the comparator for supplying the second signal, a input connected Jo the output of the comparator, and a second input for receiving the input control signal, the feedback network being arranged to control the comparator so that the output pulse bears a substantially linear relationship with the input control signal.
63~
BRIEF DESCRIPTION OF THE DRAWINGS
These and other features and advantages will become more apparent from a detailed consideration of the invention when taken in conjunction with the drawings in which:
Figure 1 shows a prior art pulse width modulation arrangement;
Figure 2 shows a pulse width modulation arrangement accord-in to the present invention;
Figure 3 shows the functional contents of the 555 timer shown in Figures 1 and 2;
Figure 4 shows a timing diagram for the signals associated with Figure 2; and, Figure 5 shows a refinement of the pulse width modulation arrangement shown in Figure 2.
DETAILED DESCRIPTION
The prior art arrangement as shown in Figure 1 typically uses a standard 555 timer connected in a monostable multi vibrator configuration as shown with the input trigger signal connected to sync terminal 11. Timing capacitor 12 is connected between ground and the threshold input terminal of the timer 13 and is also connected through diode 14 to sync terminal 11. The voltage source Vcc is connected to one side of timing resistor 15 to the other side of which is connected to capacitor 12~
I 63~
The output pulse from timer 13 is initiated when the sync pulse drives terminal 11 low discharging capacitor 12 through diode 14. At the same time, the sync pulse drives the output of the 555 timer high or to its excited state. This excited state is defined as the output pulse. The period T of the output signal is determined by the period of the sync pulse. As capacitor 12 charges, timer 13 compares the voltage across the capacitor with the input control voltage Viny Once the voltage across capacitor 12 reaches a predetermined relationship with respect to the control voltage Viny the output signal switches to its unexcited state which, in the example shown, is low.
The relationship between the control voltage Viny and the duration of the output pulse is defined by the following equation:
to = RtCtIn loin (1 ) where to is the length of the output pulse, Rut is the resistance of the timing resistor, Cut in the capacitance of the timing capacitor, Viny is the input control voltage, and Vcc is the supply voltage to the timer 13.
As can be seen from this equation, the duration of the output pulse, Leo the excited state on the output line 16, is a nonlinear function of Viny Also, the length to of the output pulse is dependent on timing components Rut and Ct.
I ~21~39 Figure 2 shows an approach by which the length of the output pulse is made linear with respect to the input control voltage and independent of the timing resistor and capacitor The common portions between Figures 1 and 2 have the same reference numerals.
However, Figure 1 has been modified according to the inventive concept so that the length of the output pulse is linear with respect to the input control voltage and independent of the timing ARC network.
Output terminal 16 is connected to one input of operational amplifier 17 through feedback resistor 18.
The other input, the positive input, of operational amplifier 17 receives the input control voltage Viny The output of the operational amplifier is then connected to the voltage control terminal Icon of timer 13 and is also connected back to its negative input through feedback capacitor 19.
Figure 3 shows a block diagram of the standard timer 555. Also, Figure 4 shows the timing diagram for the arrangement shown in Figure 2. The output pulse is initiated by the leaving edge of the negative going sync pulse. The sync pulse sets flip-flop 21 through comparator 22 for setting output line 25 to its excited state through output stage 23. At the same time, discharge transistor 24 is turned off which will permit the capacitor to begin charging. However, the charge on capacitor 12 is held to one diode drop my diode 14 until ~i216639 the negative going sync pulse terminates. When this sync pulse terminates, the capacitor 12 is allowed to charge through timing resistor 15 from source Vcc.
Comparator 2Z will compare the voltage across capacitor 12 at its input line Vth to the control voltage Icon When the charge across capacitor 12 reaches the control voltage Icon comparator 26 will reset flip-flop 21 for resetting the output on line 25 to terminate the output pulse.
When the inputs to amplifier 17 are balanced, Viny is given by the following equation:
Viny TV OH + TDVOH + T-- SOL (2) where Viny is the input voltage, to is the length of the sync pulse, T is the period of the sync pulse which also matches the period of signal on the output line, VOW is the voltage of the output pulse, to is the length of the output pulse less the length of the sync pulse, and VOW
is the voltage on the output line during its unexcited state. This equation can be rewritten to yield the following equation:
VOW OX OH OX
If the period of the signal on the output line is very much greater than the length of the sync pulse to, then equation (3) reduces to the following equation:
to V -v T (4) I I
As can be seen from equations 2, 3 and 4, if the load on output line 16 is constant, then there is a linear relationship between the duration of the output pulse and the input voltage Viny The operational amplifier 17 configured as shown in Figure 2 is an integrating amplifier which tends to average the signal on output line 16 arid supply an output voltage to the control voltage terminal Icon of timer 13 that is the difference between the controlling input signal Viny and the average of the voltage on line 16. Thus, operational amplifier 17 will operate to balance the voltage on output line 16 with Viny In this manner, the duration of the output pulse is made linear with respect to the input control signal Viny and independent of the timing network comprising capacitor 12 and resistor 15.
As mentioned above, it is assumed that the load on output line 16 is and remains substantially constant.
Figure 5 shows an arrangement which includes a buffer 30 in the case where the load on the output of timer 33 varies. Compensation such as buffering is required since a change in load will change VOW and Volt Thus, a Zoner clamp 32 is provided having one side connected to ground and the other side connected to the output voltage terminal Volt of timer 13 through resistor 31.
The junction of resistor 31 and Zoner diode 32 is connected through resistor 33 to the base of ~2~3~
transistor 34 having its collector connected to source Vcc and its emitter connected to the output terminal 36. Resistor 35 connects the emitter of transistor 34 to ground. Buffer 30 then acts to isolate the load on line 36 from output 16 of timer 13.
The Zoner changes equations 3 and 4 to:
to = Viva a T V~tz (5 and to in Volt (6) where Vz - zoner voltage thereby restricting Viny to VoL<vin~vz -Also, RUB may not be necessary since voltage across resistor 35 would not exceed Vz-VBE and current is limited through transistor 34 by resistor 35.
Claims (19)
1. A pulse width modulation arrangement for providing an output pulse having a duration which varies linearly with an input control signal, said arrangement comprising:
comparator means having first and second inputs and an output, said comparator means comparing a first signal on said first input with a second signal on said second input;
synchronization means connected to said compar-ator means for initiating said output pulse, said synchronization means including a timing network connected to said first input of said comparator means, said timing network providing an input timing signal varying with time; and, feedback means having an output connected to said second input of said comparator means for supplying said second signal, an input connected to said output of said comparator means, and a second input for receiving said input control signal, said feedback means being arranged to control said comparator means so that said output pulse bears a substantially linear relationship to said input control signal.
comparator means having first and second inputs and an output, said comparator means comparing a first signal on said first input with a second signal on said second input;
synchronization means connected to said compar-ator means for initiating said output pulse, said synchronization means including a timing network connected to said first input of said comparator means, said timing network providing an input timing signal varying with time; and, feedback means having an output connected to said second input of said comparator means for supplying said second signal, an input connected to said output of said comparator means, and a second input for receiving said input control signal, said feedback means being arranged to control said comparator means so that said output pulse bears a substantially linear relationship to said input control signal.
2. The arrangement of claim 1 wherein said feedback means comprises an amplifier having first and second input terminals and an output terminal, means connecting said first input terminal to said output of said comparator means, said second input terminal receiving said input control signal, and means connecting the output of said amplifier to said second input of said comparator means.
3. The arrangement of claim 1 wherein said feedback means comprises an operational amplifier having a negative input terminal, a positive input terminal and an output terminal, feedback resistance means connecting the output of said comparator means to said negative input terminal of said operational amplifier, means connecting said input control signal to said positive input terminal of said operational amplifier, means connecting said output terminal of said operational amplifier to said second input of said comparator means, and capacitive feedback means connecting said output terminal of said operational amplifier to its negative input terminal.
4. The arrangement of claim 3 wherein said timing network comprises an RC network connected between a source and a reference.
5. The arrangement of claim 4 wherein said comparator means comprises a standard 555 timer.
6. The arrangement of claim 1 wherein said feedback means comprises a buffer means connected between said output of said comparator means and a load output terminal connectable to a load for supplying said output pulse to said load, said feedback means further comprises an operational amplifier having a negative input terminal, a positive input terminal and an output terminal, feedback resistance means connecting the output of said comparator means to said negative input terminal of said operational amplifier, means connecting said input control signal to said positive input terminal of said operational amplifier, means connecting said output terminal of said operational amplifier to said second input of said comparator means, and capacitive feedback means connecting said output terminal of said operational amplifier to its negative input terminal.
7. The arrangement of claim 6 wherein said timing network comprises an RC network connected between a source and a reference.
8. The arrangement of claim 7 wherein said comparator means comprises a standard 555 timer.
9. A pulse width modulation arrangement for providing an output pulse having a duration which varies linearly with an input control signal, said arrangement comprising:
monostable multivibrator means having a control terminal, a sync terminal and an output terminal, said monostable multivibrator having an excited state and an unexcited state, said monostable multivibrator means being triggered to said excited state by a sync signal applied to said sync terminal and returning to said unexcited state depending upon a timing network and a signal on its control terminal; and, feedback means having an output connected to said control terminal of said monostable multivibrator means, an input connected to said output terminal of said monostable multivibrator means, and a second input for receiving said input control signal, said feedback means being arranged to control said monostable multivibrator means so that said output pulse occurring during said excited state of said mono-stable multivibrator means bears a substantially linear relationship to said input control signal.
monostable multivibrator means having a control terminal, a sync terminal and an output terminal, said monostable multivibrator having an excited state and an unexcited state, said monostable multivibrator means being triggered to said excited state by a sync signal applied to said sync terminal and returning to said unexcited state depending upon a timing network and a signal on its control terminal; and, feedback means having an output connected to said control terminal of said monostable multivibrator means, an input connected to said output terminal of said monostable multivibrator means, and a second input for receiving said input control signal, said feedback means being arranged to control said monostable multivibrator means so that said output pulse occurring during said excited state of said mono-stable multivibrator means bears a substantially linear relationship to said input control signal.
10. The arrangement of claim 9 wherein said feedback means comprises an amplifier having first and second input terminals and an output terminal, means connecting said first input terminal to said output of said monostable multivibrator means, said second input terminal receiving said input control signal, and means connecting the output of said amplifier to said control terminal of said monostable multivibrator means.
11. The arrangement of claim 9 wherein said feedback means comprises an operational amplifier having a negative input terminal, a positive input terminal and an output terminal, feedback resistance means connecting the output terminal of said monostable multivibrator means to said negative input terminal of said operational amplifier, means connecting said input control signal to said positive input terminal of said operational amplifier, means connecting said output terminal of said operational amplifier to said control terminal of said monostable multivibrator means, and capacitive feedback means connecting said output terminal of said operational amplifier to its negative input terminal.
12. The arrangement of claim 11 wherein said timing network comprises an RC network connected between a source and a reference.
13. The arrangement of claim 12 wherein said monostable multivibrator means comprises a standard 555 timer.
14. The arrangement of claim 9 wherein said feedback means comprises a buffer means connected between said output terminal of said multivibrator means and a load output terminal connectable to a load for supplying said output pulse to said load, said feedback means further comprises an operational amplifier having a negative input terminal, a positive input terminal and an output terminal, feedback resistance means connecting the output terminal of said monostable multivibrator means to said negative input terminal of said operational amplifier, means connecting said input control signal to said positive input terminal of said operational amplifier, means connecting said output terminal of said operational amplifier to said control terminal of said monostable multivibrator means, and capacitive feedback means connecting said output terminal of said operational amplifier to its negative input terminal.
15. The arrangement of claim 14 wherein said timing network comprises an RC network connected between a source and a reference.
16. The arrangement of claim 15 wherein said monostable multivibrator means comprises a standard 555 timer.
17. A pulse width modulation arrangement for providing an output pulse having a duration dependent upon an input control signal, said arrangement comprising:
comparator means having first and second inputs and an output, said comparator means comparing a first signal on said first input with a second signal on said second input;
synchronization means connected to said compar-ator means for initiating said output pulse, said synchronization means including a timing network connected to said first input of said comparator means, said timing network providing an input timing signal varying with time; and, integrator feedback means having an output con-nected to said second input of said comparator means for supplying said second signal, an input connected to said output of said comparator means, and a second input for receiving said input control signal, said integrator feedback means being arranged for averaging the signal on the output of said comparator means and for supplying a signal on its output to said second input of said comparator means which is a function of the difference between said input control signal and the average of the output signal on the output of said comparator means.
comparator means having first and second inputs and an output, said comparator means comparing a first signal on said first input with a second signal on said second input;
synchronization means connected to said compar-ator means for initiating said output pulse, said synchronization means including a timing network connected to said first input of said comparator means, said timing network providing an input timing signal varying with time; and, integrator feedback means having an output con-nected to said second input of said comparator means for supplying said second signal, an input connected to said output of said comparator means, and a second input for receiving said input control signal, said integrator feedback means being arranged for averaging the signal on the output of said comparator means and for supplying a signal on its output to said second input of said comparator means which is a function of the difference between said input control signal and the average of the output signal on the output of said comparator means.
18. The arrangement of claim 17 wherein said integrator feedback means comprises an operational amplifier having a negative input terminal, a positive input terminal and an output terminal, feedback resistance means connecting the output of said comparator means to said negative input terminal of said operational amplifier, means connecting said input control signal to said positive input terminal of said operational amplifier, means connecting said output terminal of said operational amplifier to said second input of said comparator means, and capacitive feedback means connecting said output terminal of said operation amplifier to its negative input terminal.
19. The arrangement of claim 17 wherein said feedback means comprises a buffer means connected between said output of said comparator means and a load output terminal connectable to a load for supplying said output pulse to said load, said feedback means further comprises an operational amplifier having a negative input terminal, a positive input terminal and an output terminal, feedback resistance means connecting the output of said comparator means to said negative input terminal of said operational amplifier, means connecting said input control signal to said positive input terminal of said operational amplifier, means connecting said output terminal of said operational amplifier to said second input of said comparator means, and capacitive feedback means connecting said output terminal of said operational amplifier to its negative input terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000473844A CA1216639A (en) | 1985-02-08 | 1985-02-08 | Voltage controlled pulse width modulation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000473844A CA1216639A (en) | 1985-02-08 | 1985-02-08 | Voltage controlled pulse width modulation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1216639A true CA1216639A (en) | 1987-01-13 |
Family
ID=4129788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000473844A Expired CA1216639A (en) | 1985-02-08 | 1985-02-08 | Voltage controlled pulse width modulation circuit |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1216639A (en) |
-
1985
- 1985-02-08 CA CA000473844A patent/CA1216639A/en not_active Expired
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