CA1202728A - Digital computer having analog signal circuitry - Google Patents
Digital computer having analog signal circuitryInfo
- Publication number
- CA1202728A CA1202728A CA000483376A CA483376A CA1202728A CA 1202728 A CA1202728 A CA 1202728A CA 000483376 A CA000483376 A CA 000483376A CA 483376 A CA483376 A CA 483376A CA 1202728 A CA1202728 A CA 1202728A
- Authority
- CA
- Canada
- Prior art keywords
- analog
- digital
- output
- card
- computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Abstract
Abstract of the Disclosure A combination of a programmable logic controller with analog circuitry. The analog circuitry includes a summation point to which several items are coupled.
Analog inputs are selectively coupled to the summation point through analog switches. Also, the output of a digital to analog converter couples to the summation point. Still further, the analog output for the controller is obtained from a sample and hold circuit which has its input connected to the summation point and which includes means for outputting the analog value at its output back to the summing point. Even still further, a comparator input couples to the summation point. The arrangement provides for direct processing of analog information either by direct output of analog processed analog data or by obtaining one bit data from the comparator which represents whether a threshold has been reached by the analog data. Digital processing of the analog data may be accomplished, if necessary by using the circuit to convert from analog to digital and back again.
The equipment is designed so that digital or analog, input or output cards may be inserted into any of the I/O
positions without rewiring.
Analog inputs are selectively coupled to the summation point through analog switches. Also, the output of a digital to analog converter couples to the summation point. Still further, the analog output for the controller is obtained from a sample and hold circuit which has its input connected to the summation point and which includes means for outputting the analog value at its output back to the summing point. Even still further, a comparator input couples to the summation point. The arrangement provides for direct processing of analog information either by direct output of analog processed analog data or by obtaining one bit data from the comparator which represents whether a threshold has been reached by the analog data. Digital processing of the analog data may be accomplished, if necessary by using the circuit to convert from analog to digital and back again.
The equipment is designed so that digital or analog, input or output cards may be inserted into any of the I/O
positions without rewiring.
Description
lZ~ 7Z~
4-~022j DIGI~AL (,()~ U~E~ ;V~
ANALOG SlG~AL CII~Ulll~
The inv~ntion relates to a hy~rid co~rlputer having both digital clnd analog signal circuitry.
Severctl methods to deai ~itll the use o~ digital processors in connection with ancllog data have been tried. United States Patent No. 4,14U,~ to Fcrn~orth discloses a digital processor combined witn circuitry to interlace with analog inputs and analog ou~puts. Such a system se~uentially samples inputs and s~que~tially converts them into digital signals which are then available for conventional digital processing or storage.
The aigital output information is sequ~ntl~lly strobed into a plurality oE sampl~ and nold circuits to provide the analog ou~put signals. Convencional data processir)g is ~on~ digitally. This type o~ processing of analog signals is common.
United States Patenc ~lo. 4,21~,174 to ~lorley et al.
discloses a combincttion of a progrctmtnable one bit logic controller having circuitry to inter~ace with analog input signals. With this circuit, individual analog input voltages are automatically scaled by the controller into appropriate units so that the user can set limit points in terms oi degrees, pounds per square inch, minutes, and other ~amiliar units. Tbls simpliEies Lhe control progrclm, and thus makes it easy to understand and maintain the con~rol logic. ~los~ o~ the tim~ this con~roller does not detertnine the actual voltclge of the a[-alog input but ~,~/,"~N' merely whecller or n~ e vol~aOe oL l~ inl)uL e,:ceecls the desired prese~ value esCablished L)y Lhe soitwclre wi~h regarcl to CLle preset value selected ~y the user. In such cases, the digital signal represellting Lile prese~ v~lue is converted by a (ligital to analoO collver~ec l:o al- anal~g signal, This signal i~ then compclre~ to ~he analog input signal in question. The output of the c~n~parator is a one bit signal indic~ting whet~ec the analog input signal is higher or lower than the generaced analog re~erence signal. (~y increlnenting che reference signal and detecting the change of state of the colllparator, ~he circuit can function to conver~ an analoO siOnal to a digital signal.) ~ United States Patent lNo. 3,493,73l to Lemonde discloses a combination of a multibit digital ana an analog system in which addressable analog~inl)ut signals may firs~ be combined and therl converted to a digital signal. In operation o~ the hybrid sysCelll under the control o~ the digital program, the digit~l ~ystem communlcaCes across the hy~rid interface to s~lecc the particular operational modes of the analog system, to select and~provide appropriate resistive values o~ the potentiometers representing the coefficients of the ~particular equations involved as well as to supply tne nitlal conditior)s values With which the computation is to start.
~ United States ~atent No. 3,761,6~9 to ~atanabe discloses an analog and digital colnputer using an
4-~022j DIGI~AL (,()~ U~E~ ;V~
ANALOG SlG~AL CII~Ulll~
The inv~ntion relates to a hy~rid co~rlputer having both digital clnd analog signal circuitry.
Severctl methods to deai ~itll the use o~ digital processors in connection with ancllog data have been tried. United States Patent No. 4,14U,~ to Fcrn~orth discloses a digital processor combined witn circuitry to interlace with analog inputs and analog ou~puts. Such a system se~uentially samples inputs and s~que~tially converts them into digital signals which are then available for conventional digital processing or storage.
The aigital output information is sequ~ntl~lly strobed into a plurality oE sampl~ and nold circuits to provide the analog ou~put signals. Convencional data processir)g is ~on~ digitally. This type o~ processing of analog signals is common.
United States Patenc ~lo. 4,21~,174 to ~lorley et al.
discloses a combincttion of a progrctmtnable one bit logic controller having circuitry to inter~ace with analog input signals. With this circuit, individual analog input voltages are automatically scaled by the controller into appropriate units so that the user can set limit points in terms oi degrees, pounds per square inch, minutes, and other ~amiliar units. Tbls simpliEies Lhe control progrclm, and thus makes it easy to understand and maintain the con~rol logic. ~los~ o~ the tim~ this con~roller does not detertnine the actual voltclge of the a[-alog input but ~,~/,"~N' merely whecller or n~ e vol~aOe oL l~ inl)uL e,:ceecls the desired prese~ value esCablished L)y Lhe soitwclre wi~h regarcl to CLle preset value selected ~y the user. In such cases, the digital signal represellting Lile prese~ v~lue is converted by a (ligital to analoO collver~ec l:o al- anal~g signal, This signal i~ then compclre~ to ~he analog input signal in question. The output of the c~n~parator is a one bit signal indic~ting whet~ec the analog input signal is higher or lower than the generaced analog re~erence signal. (~y increlnenting che reference signal and detecting the change of state of the colllparator, ~he circuit can function to conver~ an analoO siOnal to a digital signal.) ~ United States Patent lNo. 3,493,73l to Lemonde discloses a combination of a multibit digital ana an analog system in which addressable analog~inl)ut signals may firs~ be combined and therl converted to a digital signal. In operation o~ the hybrid sysCelll under the control o~ the digital program, the digit~l ~ystem communlcaCes across the hy~rid interface to s~lecc the particular operational modes of the analog system, to select and~provide appropriate resistive values o~ the potentiometers representing the coefficients of the ~particular equations involved as well as to supply tne nitlal conditior)s values With which the computation is to start.
~ United States ~atent No. 3,761,6~9 to ~atanabe discloses an analog and digital colnputer using an
2~
aucomatic connection ~ype s~ c~llnuLri:. ~o es~:u~lisll connections alllong anulog operutionul ~evices. ~lmilarly, UniCea SCates l~atenC No. ~,2~3,5~2 to l-lols~ discloses a ~igically contro:Lled analog compuLer.
In muny of th~se systems~, su~stan~.ial COlmpUCitl~ delay occurs because of the need for conversion o~` analog duta into diOital Lorin. 'l~l~e delay may n~ake some real-Lil]le calculatlons diflicult or iulpossi~le. A~ldition~lly some of these systems can l~andle only one analo~ inl)u~ at a Cilne or require several analog to digital converters to handle several analog inpuCs. In some cases the cost of the converters muy approach or ev~n exceed t~le cost of the computer.
lZ~ 7Z8 ~u~ llary oi. Ll~ v~l)Lioll The invention relates to a hybrid co~ )uLer having bo~h digital and analog si~nal circuicry. Various asl)~cts of the hybri~ compuLer are novel and provicle lor in~E)cove~
operation. While the actuai nature oL t~e invention covered herein can ~e determined only WiLII ref~rence co the claims appended hereto certain teatures which are characceristic of the preferre~ en~bodilnenL of the novel concroller disclosect herein can be descril)ed brieLly.
One aspect ot the inVenLion relaLes to Lhe desi~,n oL a hybrid colllputer so that various com~inations oE iifferent interface modules can be inserted withou~ rei~iring.
Typical interface modules would includ~ an analog input card an analog output card a digital inpu. card and a digital output card. In t~e pre~erred en1~odiment of the invention any one of thest- cards can be inserted into any one of the I/O interface positions. I`t~is allows for a great improvement of Lhe l:lexibility o~ use of Lhe cornputer by the customer wich cllallgirlg circumsLanc~s.
Tte preferred embodiment of che inventiotl is an improverllent upon the progralnmable logic collcroller shown in United Scates Patent No. 4 178 634 an~ che corresponding divisional United States Patent No.
4 275 455 to Bartlett. The improvelnent allows the programmable controller to do analog calculations in addition to the digital calculations done in the earlier patenced circuitry. In cllese pi~tenLs Ll~ inl)uc and out~uc interfacing circuitry was directe~ cowards one bit f~lrD~q~o digital signals (see also Bartlett Unitetl States Patent Nos. 4,055,793 and 4,063,121). However, many uses for programmable controllers require the interfacing with analog data. The conventional approach to the problem of analog data has been simply to first convert each channel, sequéntially or in parallel to digital signals, and to thereafter digitally process the signals. The processed output would then be converted, either sequentially or in parallel to analog signals. The analog -to digital converters for the inputs would be separate Erom the circuitry for converting the processed OlltpUt back into analog circuitry. The programmable controller shown in the Bartlett patents had no means for processing analog data without separate conversion to a digital signal. The controller is provided with analog computing functions merely by the addition of two wires tanalog ground and analog signal bus) common to the input/output card positions and by insertion of analog processing cards into those positions.
A programrnable logic controller, as used herein, is meant to refer to a digital computer having one bit Boolean logic instructions which instructions include an "AND" or "OR" instruction Eor use with a one bit accumulator. An ins-truction set used in a prior art controller is set forth in United States Patent No.4,178,634 to Bartlett. Such a controller has input and output address lines and a digital data bus.
,.
. ~ ~
~:OZ~2~
Whi]e the description of the invention will be in the context of a programmable controller, the scope of the invention as set forth in certain of the claims is by no means limited thereto. The invention has broad application to analog computers, generally, as well as to a hybrid computer which contains analog computing functions and digital computing functions which are not performed by a programmable logic controller.
With the preferred embodiment of the invention, analog data can be rapidly handled with a miniml1m of hardware components. The arrangement provides for direct processing of analog information either by direct output of analog processed analog data or by obtaining one bit data from a comparator which represents whether a threshold has been reached by the analog data. Digital processing of the analog data may be accomplished, if necessary by using the circuit to convert from analog to digital and back again.
In accordance with a broad aspect of the invention there is provided a hybrid digital and analog computer comprising:
a. a hybrid computer having several interface locations each suitable for insertion of an interface module and each of said interface locations having connections for (1) common multibit data bus (2) common analog signal bus (3) common read and/or write signal bus (4) common supply voltage (5) common ground (6) card enable address line (7) multiple external lines for connection to external devices;
b. means for permitting either of the following to be operationally inserted into any one of said several interface locations without re-wiring being necessary: (1) a digital da~a interface module for controlling connections between the computer and external devices, or (2) an analog data interface module for controlling connections between the computer and external devices.
,~ r :~LZ~27Z8 ~ L D~cri!)ti~ rJ~.~it~ s FIG. 1 illustrates the preLerred em~odil)lent ol che invention in block forlll, and s~ows the wiring to the incerface cards.
FIG. 2 is a diagrain o~ a princecl circuit card edge connector into which printed circuit cards, such ~S in FIGS. 3-5, are inserted in pOsitiOIls 1 chrou~ oE FIG.
1.
FlG. 3 illustr~tes the details oL an analog signal input card of che invention of FIG. l as are loun~ in I/0 positions 4 through 7.
FIG. 4 illustrates the details of ~r- analog signal output card of the invention of FIG. 1 ~s are found in I/0 positions ~ through 10.
FIG~. 5a and 5b are a diagr~m of an aLialo~ function card to be inserte~ into the edge connector of FIG. 3 in position 16 of FIG. 1. FlGS. 5a and 5b align along the edges when FIG. 5a is pIaced to ctle leE~ oi FIG. 5b.
FIGS. 6a-~ illustrates in abbreviated form che resultant connection (external inpuc on and external lnput off) achieved with the inpuc card of FlG. 3 and two of ~he resultant connections (hold and incernal inpuc on) achieved with the output card of FIG. 4.
FIG. 6e-g illustrates in abbreviated ~orm thrée more of the resultanc connections (integrate, amplify-first mode, and amplify-second mode) achieved with the outl)uc card of FlG. 4.
-~ZOZ7~
FIG. ~t-~-; illustrate~ in ~bbr~viareci f~rln ~llr~e of ~ne resultant connections (colllpara~or, posi~ive reference, an~
negative reEerence) achieved with ~he analog Lunction card of FIG. 5.
FIG. 7 Illustrates an analog invertin~ and summing operation using Lwo external inputs on ~rom FIG. ~b and one amplify-first mode fr~m FIG. 6f.
FIG. ~ illustrates an aoalog in~egrating circuit operation using one external input on from FIG. ~b and one inregrate fro~l FIG. 6e.
FIG. ~ illustrates an analog comparator oper~L.ion using one excernal input on ~rom FIG. 6b, one positive reference from FlG. bi, and one comparator from FlG. 6h.
FIG. 10 il:lustrates a more complex analog operation oi differentiation, which mus~ be done in sequential steps.
FIGS. lla through lle represent the sequence of steps which are p~riodically folIowed to accomplish the operation of FIG. 1~. .
~2~%721~ -Descril~tio[l Ol the l~reLerrecl ~;;3ll~0diillenc For the pl~rl)oses of- pro;noting an understan~ing o~ the principles o~ the invention, reference will now be rnacle Co the e~nbo~iment illustrated In the drawings and specific language will be used to describe the s~me. It will nevertheless be underscood that no lilnitacion oE the scope o~ the invention is thereby intended, such alter~cions and further m~difications in Che illustrated device, anl SUCtl ~urther a~plicacions oE the principles oL- Che invention as illustrate~ tllerein being contemplated as tiould norrnally occur to one skilled in the art to t~hich the invention relates.
Referring in particular to FIG. 1, there is illustrated a ~r~nsfer line or machine tool ~00 having associated with it digital outpuc devices-202, digital sensors 201, analog outpuC devices 13 and analog sensors 12. An exainple of an analog sensor is a thermistor and an example o~ an analog output device would ~e a chart recorder or a meter. As reflected in United States Paten, No. 4,178,634, digital output interfacing circuir ~18 controls the digital devices and digit~1 input interfacing circuit 211 receives the signals from the digital sensors 201.
Analog signal circuits present in I/O positions 4 10 -and 15 and 16 receive analog signals irom the analog , i ~ .. .
- sensors and provide analog signals to the an~log output devices 13, respectively. 1/0 positions 4 - 7 include analog inpuc cards 411. I/0 positions 8 -1~ include ~`
~2~Z~3 ~nalog ouLpu~ car~ls 41~. ~osition 15 inclu(les aLl al~.ilo output card 4~ identical to caLds 41~ ~ut i~ does noL
connect to any external devices. It is merely used as supplelnentary analog nlemory. 'l'he ~unction o~ melnory card 490 could alternatively be accomplished by a card especial1y made for that purpose si~ply b~ havin~ one output circuit as in the conventional output cards and by having analog switches to subs~itute various capacitors in that circuit L-or additional memory positions. Position 16 includes an analo function circuit ~00 WtliCh does noc connect to any exLernal devices but ~hich provides for certain analog functions not provided for in the other cards. ~hile the connection t~ external devices is not shown in the a'rawing for positions 15 and 1~ it lS
contemplated that these may be connected to e~ternal terminals in ~he saLne fashion as the othei- vositions so that a full complement of d'igital cards could be uséd if no ana10a functions ~ere desired.
Controller logic 300 provides the data address and control for the digital intertacing circuits 211 and 21~
and for the analog signal circuits 411 41& 450 and 50~.
All of the I/O positions are wired in the same fasnion so that digital or analog inpuc or output cards can be placed in any slot.
Referring to FlG. 2 there is illustrated the printed circuit card edge connector into ~hich input or outpuc interfacing circuit cards such as in FIG 1 are inserted.
1~) ~Z~27Z1~3 This printed circuit card edge connector has connections identical to those disclosed in United States Patent No. 4,178,634 except that the previously unused contact positions 11 and M now have connected to them, an analog bus and an analog ground, respectively.
These connections are common to all of the edge connectors for I/0 positions l through 16.
Referring more particularly to FIG. 3, there is illustrated an analog input card 411 such as is inserted into I/0 position 4 of FIG. 1. The printed circuit edge card connections are designated around the edge of the dotted line portion representing the card.
These include letter designated connection terminals A, C, E, J, L, M, P
and additionally include numbered connections l, 3-ll, and 13, which are designated. In addition, the I/0 pairs are illustrated. All of these printed circuit edge card connections are placed on the card in a fashion to mate with the edge card connector of FIG. 2. Since the card is provided only with positive voltage and a ground reference through tPrm;n~l~ l and A, filtered by capacitor 30, a -5.6 volt supply 31 is used. (The -5.6 volt supply is optional on this card, depending upon the need in connection with the analog switches 46-49.
As illustra~ed in FIG. 3, an analog sensor such as potentiometer 32 provldes, in connection with a battery 455. a varying analog signal for processing by the computer. External connections to the computer are made at a terminal block 453 containing terminals such as 470 ~ 11 ~
,,~, ., ~Z~i~721~
to which the potentiometer 32 is connected and terminal 471 to which the grounded terminal of -the battery is connected. The positive -t~rmin~l of the battery then connects to the other side of potentiometer 32. An externally mountable resistor 33 has been placed in series with the path to -the computer for purposes of scaling the value. This is shown for illustrative purposes only, since most scaling would be done by the analog computer itself.
An alternative external resistor placement in certain applications would be between terminals 470 and 471. In the preferred embodiment, all of the analog processing is done in relationship to a single analog summing node and a corresponding analog ground.
The analog summing node connects to edge connector 11 and the analog ground to edge connector M. This node and ground are common to all of the analog input and output cards 411 and 418, as well as the analog Function card 500 and analog memory card 490.
On each input card 411, connection of the analog signals from the external sensors is made by eight separate analog input circuits which are controlled by the eight bits of the data bus when the input card is enabled. Each of the eight analog input circuits are identical to each other. A card is enabled by the presence of a 1 on both the C and the L card enable lines. The state of read/write control line E determines whether an enabled card will have the on/off values written onto, or merely read by the digital controller which proOra~ the anal~ LUnc~ionS. ~ar~l ~n.,bl~
circuitry 3~ includes a ~AI~ gat~ ~5 .Ind .1 secon~ A1~'D
gaLe 36 WlliCh cun~rul ~he genercltion ~L read c~lir,nands on line 40 ancl write coi-llLnands on line ~ n~se ar~-generaced tllrough rather sLraignLforward logic by NA~1D
ga~es 37 and 38 and ~ gate 3~. A sinlpli~ied Lorln of the logic of c~rd ena~le circuitry 34, as shown in card enable circuitry ~4 of FlG. 4, could alternatively be used.
Since the data ~us connecLing ~o terminaLs 3 through 1~ is bi-direccional, an arrangeli~ent o~ latch 4~ and gate 43 allow dsta frolll the data bus to be laLched co ~rovide a permanent record of the state oE the analog input, and gace 43 allows that state to be Lransini~ed ~ack to the data bus when an appropriate read comnan~ is received on line 40. Ttie switctlinO o~ the analog sigs~als is accomplished with a ~lotorola triple 2-channel analog mu~tiplexer/demultiplexer number ~IC14053. lt is represence~ functionally by inverter 45 c~ntrolling four analog st~itches 46, 47, 48 and 49. When ~he data on line
aucomatic connection ~ype s~ c~llnuLri:. ~o es~:u~lisll connections alllong anulog operutionul ~evices. ~lmilarly, UniCea SCates l~atenC No. ~,2~3,5~2 to l-lols~ discloses a ~igically contro:Lled analog compuLer.
In muny of th~se systems~, su~stan~.ial COlmpUCitl~ delay occurs because of the need for conversion o~` analog duta into diOital Lorin. 'l~l~e delay may n~ake some real-Lil]le calculatlons diflicult or iulpossi~le. A~ldition~lly some of these systems can l~andle only one analo~ inl)u~ at a Cilne or require several analog to digital converters to handle several analog inpuCs. In some cases the cost of the converters muy approach or ev~n exceed t~le cost of the computer.
lZ~ 7Z8 ~u~ llary oi. Ll~ v~l)Lioll The invention relates to a hybrid co~ )uLer having bo~h digital and analog si~nal circuicry. Various asl)~cts of the hybri~ compuLer are novel and provicle lor in~E)cove~
operation. While the actuai nature oL t~e invention covered herein can ~e determined only WiLII ref~rence co the claims appended hereto certain teatures which are characceristic of the preferre~ en~bodilnenL of the novel concroller disclosect herein can be descril)ed brieLly.
One aspect ot the inVenLion relaLes to Lhe desi~,n oL a hybrid colllputer so that various com~inations oE iifferent interface modules can be inserted withou~ rei~iring.
Typical interface modules would includ~ an analog input card an analog output card a digital inpu. card and a digital output card. In t~e pre~erred en1~odiment of the invention any one of thest- cards can be inserted into any one of the I/O interface positions. I`t~is allows for a great improvement of Lhe l:lexibility o~ use of Lhe cornputer by the customer wich cllallgirlg circumsLanc~s.
Tte preferred embodiment of che inventiotl is an improverllent upon the progralnmable logic collcroller shown in United Scates Patent No. 4 178 634 an~ che corresponding divisional United States Patent No.
4 275 455 to Bartlett. The improvelnent allows the programmable controller to do analog calculations in addition to the digital calculations done in the earlier patenced circuitry. In cllese pi~tenLs Ll~ inl)uc and out~uc interfacing circuitry was directe~ cowards one bit f~lrD~q~o digital signals (see also Bartlett Unitetl States Patent Nos. 4,055,793 and 4,063,121). However, many uses for programmable controllers require the interfacing with analog data. The conventional approach to the problem of analog data has been simply to first convert each channel, sequéntially or in parallel to digital signals, and to thereafter digitally process the signals. The processed output would then be converted, either sequentially or in parallel to analog signals. The analog -to digital converters for the inputs would be separate Erom the circuitry for converting the processed OlltpUt back into analog circuitry. The programmable controller shown in the Bartlett patents had no means for processing analog data without separate conversion to a digital signal. The controller is provided with analog computing functions merely by the addition of two wires tanalog ground and analog signal bus) common to the input/output card positions and by insertion of analog processing cards into those positions.
A programrnable logic controller, as used herein, is meant to refer to a digital computer having one bit Boolean logic instructions which instructions include an "AND" or "OR" instruction Eor use with a one bit accumulator. An ins-truction set used in a prior art controller is set forth in United States Patent No.4,178,634 to Bartlett. Such a controller has input and output address lines and a digital data bus.
,.
. ~ ~
~:OZ~2~
Whi]e the description of the invention will be in the context of a programmable controller, the scope of the invention as set forth in certain of the claims is by no means limited thereto. The invention has broad application to analog computers, generally, as well as to a hybrid computer which contains analog computing functions and digital computing functions which are not performed by a programmable logic controller.
With the preferred embodiment of the invention, analog data can be rapidly handled with a miniml1m of hardware components. The arrangement provides for direct processing of analog information either by direct output of analog processed analog data or by obtaining one bit data from a comparator which represents whether a threshold has been reached by the analog data. Digital processing of the analog data may be accomplished, if necessary by using the circuit to convert from analog to digital and back again.
In accordance with a broad aspect of the invention there is provided a hybrid digital and analog computer comprising:
a. a hybrid computer having several interface locations each suitable for insertion of an interface module and each of said interface locations having connections for (1) common multibit data bus (2) common analog signal bus (3) common read and/or write signal bus (4) common supply voltage (5) common ground (6) card enable address line (7) multiple external lines for connection to external devices;
b. means for permitting either of the following to be operationally inserted into any one of said several interface locations without re-wiring being necessary: (1) a digital da~a interface module for controlling connections between the computer and external devices, or (2) an analog data interface module for controlling connections between the computer and external devices.
,~ r :~LZ~27Z8 ~ L D~cri!)ti~ rJ~.~it~ s FIG. 1 illustrates the preLerred em~odil)lent ol che invention in block forlll, and s~ows the wiring to the incerface cards.
FIG. 2 is a diagrain o~ a princecl circuit card edge connector into which printed circuit cards, such ~S in FIGS. 3-5, are inserted in pOsitiOIls 1 chrou~ oE FIG.
1.
FlG. 3 illustr~tes the details oL an analog signal input card of che invention of FIG. l as are loun~ in I/0 positions 4 through 7.
FIG. 4 illustrates the details of ~r- analog signal output card of the invention of FIG. 1 ~s are found in I/0 positions ~ through 10.
FIG~. 5a and 5b are a diagr~m of an aLialo~ function card to be inserte~ into the edge connector of FIG. 3 in position 16 of FIG. 1. FlGS. 5a and 5b align along the edges when FIG. 5a is pIaced to ctle leE~ oi FIG. 5b.
FIGS. 6a-~ illustrates in abbreviated form che resultant connection (external inpuc on and external lnput off) achieved with the inpuc card of FlG. 3 and two of ~he resultant connections (hold and incernal inpuc on) achieved with the output card of FIG. 4.
FIG. 6e-g illustrates in abbreviated ~orm thrée more of the resultanc connections (integrate, amplify-first mode, and amplify-second mode) achieved with the outl)uc card of FlG. 4.
-~ZOZ7~
FIG. ~t-~-; illustrate~ in ~bbr~viareci f~rln ~llr~e of ~ne resultant connections (colllpara~or, posi~ive reference, an~
negative reEerence) achieved with ~he analog Lunction card of FIG. 5.
FIG. 7 Illustrates an analog invertin~ and summing operation using Lwo external inputs on ~rom FIG. ~b and one amplify-first mode fr~m FIG. 6f.
FIG. ~ illustrates an aoalog in~egrating circuit operation using one external input on from FIG. ~b and one inregrate fro~l FIG. 6e.
FIG. ~ illustrates an analog comparator oper~L.ion using one excernal input on ~rom FIG. 6b, one positive reference from FlG. bi, and one comparator from FlG. 6h.
FIG. 10 il:lustrates a more complex analog operation oi differentiation, which mus~ be done in sequential steps.
FIGS. lla through lle represent the sequence of steps which are p~riodically folIowed to accomplish the operation of FIG. 1~. .
~2~%721~ -Descril~tio[l Ol the l~reLerrecl ~;;3ll~0diillenc For the pl~rl)oses of- pro;noting an understan~ing o~ the principles o~ the invention, reference will now be rnacle Co the e~nbo~iment illustrated In the drawings and specific language will be used to describe the s~me. It will nevertheless be underscood that no lilnitacion oE the scope o~ the invention is thereby intended, such alter~cions and further m~difications in Che illustrated device, anl SUCtl ~urther a~plicacions oE the principles oL- Che invention as illustrate~ tllerein being contemplated as tiould norrnally occur to one skilled in the art to t~hich the invention relates.
Referring in particular to FIG. 1, there is illustrated a ~r~nsfer line or machine tool ~00 having associated with it digital outpuc devices-202, digital sensors 201, analog outpuC devices 13 and analog sensors 12. An exainple of an analog sensor is a thermistor and an example o~ an analog output device would ~e a chart recorder or a meter. As reflected in United States Paten, No. 4,178,634, digital output interfacing circuir ~18 controls the digital devices and digit~1 input interfacing circuit 211 receives the signals from the digital sensors 201.
Analog signal circuits present in I/O positions 4 10 -and 15 and 16 receive analog signals irom the analog , i ~ .. .
- sensors and provide analog signals to the an~log output devices 13, respectively. 1/0 positions 4 - 7 include analog inpuc cards 411. I/0 positions 8 -1~ include ~`
~2~Z~3 ~nalog ouLpu~ car~ls 41~. ~osition 15 inclu(les aLl al~.ilo output card 4~ identical to caLds 41~ ~ut i~ does noL
connect to any external devices. It is merely used as supplelnentary analog nlemory. 'l'he ~unction o~ melnory card 490 could alternatively be accomplished by a card especial1y made for that purpose si~ply b~ havin~ one output circuit as in the conventional output cards and by having analog switches to subs~itute various capacitors in that circuit L-or additional memory positions. Position 16 includes an analo function circuit ~00 WtliCh does noc connect to any exLernal devices but ~hich provides for certain analog functions not provided for in the other cards. ~hile the connection t~ external devices is not shown in the a'rawing for positions 15 and 1~ it lS
contemplated that these may be connected to e~ternal terminals in ~he saLne fashion as the othei- vositions so that a full complement of d'igital cards could be uséd if no ana10a functions ~ere desired.
Controller logic 300 provides the data address and control for the digital intertacing circuits 211 and 21~
and for the analog signal circuits 411 41& 450 and 50~.
All of the I/O positions are wired in the same fasnion so that digital or analog inpuc or output cards can be placed in any slot.
Referring to FlG. 2 there is illustrated the printed circuit card edge connector into ~hich input or outpuc interfacing circuit cards such as in FIG 1 are inserted.
1~) ~Z~27Z1~3 This printed circuit card edge connector has connections identical to those disclosed in United States Patent No. 4,178,634 except that the previously unused contact positions 11 and M now have connected to them, an analog bus and an analog ground, respectively.
These connections are common to all of the edge connectors for I/0 positions l through 16.
Referring more particularly to FIG. 3, there is illustrated an analog input card 411 such as is inserted into I/0 position 4 of FIG. 1. The printed circuit edge card connections are designated around the edge of the dotted line portion representing the card.
These include letter designated connection terminals A, C, E, J, L, M, P
and additionally include numbered connections l, 3-ll, and 13, which are designated. In addition, the I/0 pairs are illustrated. All of these printed circuit edge card connections are placed on the card in a fashion to mate with the edge card connector of FIG. 2. Since the card is provided only with positive voltage and a ground reference through tPrm;n~l~ l and A, filtered by capacitor 30, a -5.6 volt supply 31 is used. (The -5.6 volt supply is optional on this card, depending upon the need in connection with the analog switches 46-49.
As illustra~ed in FIG. 3, an analog sensor such as potentiometer 32 provldes, in connection with a battery 455. a varying analog signal for processing by the computer. External connections to the computer are made at a terminal block 453 containing terminals such as 470 ~ 11 ~
,,~, ., ~Z~i~721~
to which the potentiometer 32 is connected and terminal 471 to which the grounded terminal of -the battery is connected. The positive -t~rmin~l of the battery then connects to the other side of potentiometer 32. An externally mountable resistor 33 has been placed in series with the path to -the computer for purposes of scaling the value. This is shown for illustrative purposes only, since most scaling would be done by the analog computer itself.
An alternative external resistor placement in certain applications would be between terminals 470 and 471. In the preferred embodiment, all of the analog processing is done in relationship to a single analog summing node and a corresponding analog ground.
The analog summing node connects to edge connector 11 and the analog ground to edge connector M. This node and ground are common to all of the analog input and output cards 411 and 418, as well as the analog Function card 500 and analog memory card 490.
On each input card 411, connection of the analog signals from the external sensors is made by eight separate analog input circuits which are controlled by the eight bits of the data bus when the input card is enabled. Each of the eight analog input circuits are identical to each other. A card is enabled by the presence of a 1 on both the C and the L card enable lines. The state of read/write control line E determines whether an enabled card will have the on/off values written onto, or merely read by the digital controller which proOra~ the anal~ LUnc~ionS. ~ar~l ~n.,bl~
circuitry 3~ includes a ~AI~ gat~ ~5 .Ind .1 secon~ A1~'D
gaLe 36 WlliCh cun~rul ~he genercltion ~L read c~lir,nands on line 40 ancl write coi-llLnands on line ~ n~se ar~-generaced tllrough rather sLraignLforward logic by NA~1D
ga~es 37 and 38 and ~ gate 3~. A sinlpli~ied Lorln of the logic of c~rd ena~le circuitry 34, as shown in card enable circuitry ~4 of FlG. 4, could alternatively be used.
Since the data ~us connecLing ~o terminaLs 3 through 1~ is bi-direccional, an arrangeli~ent o~ latch 4~ and gate 43 allow dsta frolll the data bus to be laLched co ~rovide a permanent record of the state oE the analog input, and gace 43 allows that state to be Lransini~ed ~ack to the data bus when an appropriate read comnan~ is received on line 40. Ttie switctlinO o~ the analog sigs~als is accomplished with a ~lotorola triple 2-channel analog mu~tiplexer/demultiplexer number ~IC14053. lt is represence~ functionally by inverter 45 c~ntrolling four analog st~itches 46, 47, 48 and 49. When ~he data on line
3 is hign, and the card is enabled through high signals on lines C and L and there is a high signal on the read/write line E, then tl~é oucput of latch 4~ will go high, turning on analog switches 46 and 48. When analog switch 46 is turned on, the external analog signal ~rom resistor 33 couples througll resistor 50 to the analoO bus 11. At the sa~e time, the corresponding ground connection E~r the external input c~uples to the analog ground M through analog switch 48. Depending upon the stace of ttle various ~2~27213 lines o~ the co~ on ~i bit ~u~ ny coli~bin;~ion oL inputs may be connected to the analog bus al: the san~e Lilne. Due to the action o~` inverting ampliLier 45 t~hich connects from the oucput o~: latch 42 to the analo~ s~itches 47 and
4~, a zero output ot latch ~2 will cause the analog input signal and its corresponding ground co be connected directly to ground. Consistent ~ith the desi~n of the I/O
circuits in United States Patent No. 4 17~ 634, the analog version also has an input disable circuit 51. Ilhen an input/output disable signal J is received the action o~
NAND gates 52 and 53 and their corresponcling resistors 54 and 55 produce a reset signal 1~ apacit:or 56 functions to place a high on one input of NAI~I) gate 53 only when the power supply is first turned on. The R output of this NAND gate 53 is connected co latch 42 and the corresponding latches in the other 7 analog input circuits to insure that all of the analog inputs are turned off when the power supply is firs~ turned on. .
~ e~`erring now rnore particularly to FIG. 4 there is illustrated an analog output card 418. A -5.6 volt supply 61 is identical to the -5.6 volt supply 31 o~ FIG. 3. The card also has an output disable circuit 62 corresponding to the lnput dlsable circuit 51 of FIG. 3. A -~5.6 volt supply 63, necessary for operational ampliÇiers used in the output circuit, i5 of conventional design. Since the ~unctions of an analog output card of the inventiorl are more colnplex than a correspondin~ digital output card two bits oÇ intormation are r.eede~l Çor each output circuic.
~` ~
)2728 The sin~plest ~ay oL desigrlin~r an ou~l)ut car-l wit~ ~his constrain~ is simply t~ have c~nnections to orll~ half 01 the ou~put positions and ~his i~ ~hat ha~ ~een c~one in this instanc~. Anol:her alt~rnativ~, not si~own, would be to provid~ ~otll voltage anci current OUtl>~LS for ~ach outpur circuit, tllereby using all of the t~rminal connections. I~ t~ould, of course, be anotller alternative to provide a double byte oE data to the carci (iE sl)ace is available to get a suEEicient nuln~er ol colllpotlellts on ~he ~j car~) to perforu~ .he analog output Eunctions for all eigh~
output pairs of wir~s. ~ard enable circuit ~4 including two 3-1nput NAN'D gates 65 and 66 are connected in a conventional East)ion from the C, L ancl ~ lines to provide a read signal on line 70 and a wri-te signal on line 71 for the card.
Analog output circuit ~1 will be desc~ibed in d~tail.
Analog output circui~ts #2-4 are iclentical in configurdtion~ A terrninal block 454 having ter~inals such as termirlals 480 and 481, are useci for making conn4ctions to exterodl analog out~ut devices such as rnetel~7~. The data from line 3 can be latched in latch 72 and read back through gate 7~. Si~:ilarly, the data Erom line 4 can be latched in latch 82 and read back through gate ~3.
When the output of latch 7~ is high, the action of la~ch 72 an~cl lnvert~iog alnplifler 75 on analog switches 7 through 7~ is to turo on analog-switches 7~, 78, and-79.
This connects the minus inl3ut oE operational ainpliEier 90 to the analog signal bus 11 and the positive input to the 15' ~ q~
-- ~L2C~2~Z8 analog grourld ~l and Co circuiL gcounli. L~le cunnec~1ons to circuit grouncl are indicacecL L~y an "~ar~:h" cl~sigr)acion to dif~erentiate frolll the n~ore conven~ional gro-lndin~ ~Jnich is fou[]d in many cli~ital systems. Grounds having che "earth" clesignation are intended to be s~ar grou[l(ls with all grounds connecting to the same point to minimi-~e difficulcies with ground loops. ihe outpuc of la~ch 7~ is high during the integrate ancl amplify mod~s of operation.
The output oL lacch 7~ is 1C)W during the hola and internal signal input mocles of oper~tion. ~Ihen ~he oucput of latch 7~ is low then the positive input of operational smplifier 9~ connects to analog grourlcL ~I or to circuit ground depencling upon the state of latch ~2. The negacive input o~f operationa~l amplifier 9L) connects througll analog s~itch 77 to cap.lcitor 91 which connects at its otLler end to Lhe~outpuc of operational amplifier 9~' In this configuration the operaticinal amplilier will holcl the value oL the vo1tage across capaciCor 91 and proviae it at its output.
A r~sistor 92 couples the value of the output of opèrational amplifier 9~ either to ground through analog s~icch~87 (liold or integrate mode) or back to the analog slgnal bus through dnalog s~itch ~ (int~rnal signa1 input ~or amplify mode) d~pending upon the scate ol che output of lat~ch 82 and inverter ~5 controlling the analog s~itches ~6 an~ ~7.
As a Lurther consideration of the pro~lem of grounding ~hen the output ol latch 72 is l~w ~uring the 1~
hold and internal signal input modes of operation, the positive input of operational ampli~ier 90 needs to be connected to circuit ground for the hold mode and to ~he analog ground M for the internal signal input mode of operation. The output of latch 82 controls analog switch 95 to connect the positive input to the analog ground bus in the internal signal input mode. An inverting amplifi~r 93 which has its input connected to the output of latch 82 controls analog switch 94 to connect the positive input to the circuit ground in the hold mode. Operation of the computer of this invention is premised upon the fact that only one amplifier with feedback will be connected to the analog signal bus at a time. Since it is desired that there be only one internal ground at a time (to m;n;m; Y.e the problem of ground loops), the grounding point has been chosen to be at the input of the one amplifier which is connected in a mode with feedback. For the preferred circuit operation, the operational amplifiers used in this invention are MOSFET input 3160 amplifiers adjusted with external potentiometers connected to pins 1, 4 and 5 in conventional fashion (not shown) to eliminate offset voltage error.
AND gate 97 has inputs which connect to the outputs of latches 72 and 82. The output of AND gate 97 couples through capacitor 98 and inverter 101 to control analog switches 106 and 107. A resistor 103 serves -to bring the voltage at the input of inverter lOl to ground after a period of time. A problem occurs when operational amplifier 90 ~" ~
:~Z~2~28 is connec~d in ~n ~np1iLyin~ con~i ur~ti~n to ctl~ ~nalog signal cbus. Initially upoo connection su~stanLia1 alnounts o~ current ~1Ow into CapaClCOr ~1. So chat this does not inter~ere tJich the op~racion o~ Lhe operacional alnplifier analog switch 10~ is curned on and tl)e current through capacitor ~1 goes to ground. A~Cer a tilne determined by t~e time constant ol cZ~acitor 9~ and resistor 1~3 analog switch 106 upens and analog swiccll 107 c1Oses connecLin~ cap.lcitor ~1 to che negativ~ input o~ the operational alnp1ifier. 1t~is de1ayed conneccion of capacitor 91 prevents the large currents flowing through ~he capacltor Erom interfering with the outpuc values when tne operationa1 amplifier is first connected t~ the analog bus and allot~s for an exact value ~o ~e achieved lor storage by che capacitor once the value is very nearly achieved.
ReEerring now to FIG~. 5a and 5b analog function circuit 50~ is iilustraced in two separate sheecs which can be laid side-by-side. In FIG. 5a there are a -5.6 volt supply 112 and a +5.~ volt supply 113 ~hich are identical to the corresponding supplies 61 and 63 of FIG.
4. Card enable circuit 1~4 is very si~lilar to tl~e card enable circuic ~4 oE FIG. 4 except that clata bus line 10 is used with lin~s ~ and E so that a double by~e o~ data can be o~tained if ciesired. Operational amplifier 11~ is identical to operational amplifier ~ Ol FIG. 4.
1~3 ~zo;z~z~ -~iulilarly, olally oi the itelnS associ~ed WiCtl operational amplifier 110 are the ~alne in operation an(l function as the correspoLl~in~ items associated with operational amplifier 90. Therefore, the same item numbers are used to designate those correspo~ding items except that they are follos~ed with a prime indication. When operational amplifier 110 is conrlected as a comE)arator, its one bit digital output is available for coupling through gate lll to the data ~us of the digital controller. 1t-is is the sole digital output ~rom the analog processing portion of the invention which can be utilized by the digital processing of the digital controller.
The analog function circuit of F1~. 5a and b differs from the analog output card of FIG. 4 in several respects. First, it contains a selectable reference voltage. Second, it provides a selectable inverte~ or non-inverte~ signal. Third, instead of the single feedback resistor 92, there is a ladder network l~l of resistors 18~-19~ s~hich are binary weighte~ in value. The resistor ladder values range from ~ to -r~- This compares with the standard feedback resistor such as 92 and the standard input resistor such as 49 which are a va1ue of R/10. With this range o~ values, operational a~lplifier 110 can be made to multiply or divide s~ith ease. By applying the referenc~ voItage through this ladder net~rh to the analog bus, an amplifier in an analog output circuit can also be affected.
While Eor purposes of clarity chere is illustrated herein a resis~or l~dder network of 9 discrete resistors, ~LZ~Z7Z~3 i t l S cunc~ml~lu ce~:l Lha c a ~ ! L) 1 L ~ 1); lonol Ithlc C;l()S
rligitally collcr~ pocentiometer suc~ a'; A[lal(J~, ~evic~s AD 752, ~ould be approprlace. As an alternaclve- co ch~
d~ubl~ L)yL~ ~l,c~l)r~ h (~ s~ r~:in, Lll~ L blL l~
coulcl be divldeu inco cwo groups of four ~)iLs an~l use(~
wich a 1~ bit, 4~4 r~gist~r. ~ihe firsc gr~up of four Clts ~oul~ c~,nsisc ~f one blt ~or colliparator oucpuc, one ~ic to reset tne re~,isLer, and 2 bits lor a one-of-1our r~giscer select. ~he sec~nd group o~ Lour Di~S, ln Che home position o~ the regiscer, wou1~ have one bic Lor tne mosc significant value resixt~r, one bit for ~/- cuncrol~ and 2 bits for mo~e select (nol~, incernal slgnal input, rel~rence volc~ge, an~ alr,pllfy). ~he LOUr ~its lrorn each vf Lhe oth~r three positi~ns of che regiscer c~uld b~ used ~or the remaining 12 r~siscors.
Dacu input thruugh lln~ 7 is handled ~y a latch and gace comDindtlon 1~0 icl~ntlcal to thac o~ latch 72 and gate 73'. The oucput of the l~ccn portlon of laccl and g~te combination 1~ c~nLrols the polari~y of slgnals co th~ resiscur ladder necwork 1~1 lnclu~ing resistor~
1~2-1~0 and resiscor switching ciruul L S 1 7 ~ 0 . Egual v~lue reslsturs 1~6 ~ncl 127 couple cu and around the negatlve input of operatiunal ampliLier 1~ to provicie a ~ega~lv~ voltage egual and OppOSlte cu the input volt~ge from the output of ~u~ferlng operatlonal alllyll~ier 150. A
high signal frolT~ latch and gate combinacion 120 will cause an~lug switch 137-co turn un und analog s~icch 136 to curn o~f. Ihis inverts the signul cu reslscor lacicier necwor~
1~1 .
~(~
~Z~27Z~
A precision voltage reLerence l~2 (leLe~ e Semiconductor C~ 5) ouLpucs a five vol~ r~ference signal.
Data input tllrou~h line ~ is hanclled b~ a latcll and gace colrlbination 142 iden~ical to thaL of laLch 7~ ancl ~aL~
73'. The output Erom the lLitch portion ol latch ancl gate combination 142 througn inverter 145 determines whether Lhe output of operLItionLll ampliEier 11~ co~ ects ~I~rough analog s~itch 146 to operate in a fashic)n similar to the analog out~)ut circuits or if ch~ rererence volcag~ couples through analog gate 147 to the resistor network and the operational arnplifier 110 converts to a high gain coMparator mc?de of operation. Operational a[np1ifier 15 is providecl to assure that there is suEficient current available to drive the resistor laclcler network as well as to charge capacitor 91' in the apL~ropriate circuit configurations.
A resistor swit~ching circulc 172 includes latch and gate colnbinaLion 162 idénCical LO that oL lLlLch 72' and gate 73 to retain data EroLn line ~ oE the daca bus. The outpuc ~rom the latch portion oE latch and gate coLIlbinatioo 1~2 thruugtl inverter 165 de~erlllines whettler the resistor 1~2 with a value of R connects through analog switch 166 ~o the common side of the ladder network 181, or to ground through analog switch 167. r~esistor 1~2 is connected between the outpu~ oE the operational amplifier 110 (as bufferecl by operational amplifier 15~
and possibIy invertecl by operational ainpliEier 12~) to the analo~ signal bus ll when the output oL Lhe latch portion ~1 Z7Z~3 ~
o~ lacch a[l(l gate 162 is ~lig~) uncl th~ ouL~)u~ oL 1atcn ~' is high. IJhen cll~ ouLpuc of ~he 1~tctl porciorl ol 1at~h and gate 16~ is low, resistor 1~ si~nply connecLx to ground so t~lat che loa~ing on ~he operaLionaL alllp1ifiers l5~ or 1~ is noL affected by-the change.
l~eferring more particu1ar1y to FIG. 5b, there are a series of resistor connecting circuits 173 through l~
whlc~l op~race in idencical ~ashion co the resistor connecting circuic 172 and r~sistor l~. In order to all~w a double byte of data, a secon~ car~ enable circuit 1~2 is provided with an inverter 193 to 1nvert the logic level of the data on line 10. Card enable circui~ry 192 is otherwise identical to that of card enable circuit 164. While FIG. Sb shows duplicat~ external connections for purposes of cl~rity, aceu~lly, each car~ has only one ext~rnal conneccion. The interconnects wiChin the card have been avoided for purposes of clarity.
Ref~rring more particularly to FIGS. 6a-b, there are illustratea in ab~reviaced forrn, the resulcanc connections ~or the ~wo cvn~itiorls of an input with the input carc of FIG. 3 . It can ~e observed that an input is either grounded or connect~d to ~he single analog s1gnal ~us ll used In the analog porcion of the compucer. For purposes of clarity, the corresponding ground connections in the follo~ing descriptions are not considered. Also, for pùrposes of clarity, in connection wich further discussioos of operation, designations have been assigned to the various simplified conn~ction diat,rams. When the 2~
O~Z8 exterl-al input is o[E, as in ~ a, tl~e desigtlacion oi Il is used. Ihis configura~ion is obtained b~ writing onco an ana1Og input card 411 (as sllowrl in I~IG. 3) ~ h data line 3 low, l~i)en the e~ternal inpu~ is on, as in FIG. 6b, tt~e designation I~ i-, u~ hi~ c~nfi~,uration is obtained by writing onco an analo~ input car~ 411 (as shown in FIG. 3) with data line 3 high.
FIGS. 6c-g illustrate possible con~igurations for an ana1Os7, output circuit o~ FIG. 4 (and by an(J1Ogy Lor tne corresponding circuits of FIG. 5). FIG. 6c i1lustrates 00, a hold configuration which simp1y provides an output signal wich the storage capacitor 91 being positioned between the negative input of operationa1 anlpli~ier 90 and its output. Resistor 92 maintains a standard load on the operational a~pli~ier. Tnis c~nflguration is ol~tained by writing onto an analog output card 4l8 (as shown in FIG.
4) with data lines 3 and 4 low.
As illustrated in FIG. 6d, configuration 01 is a condition witLl the internal input on. In the circuic of the preferred embodiment, there are situations where an analog value at an oucput is desired to be read int~ the single analog bus. 1his configuration is obtaine~ ~y wricing onto an analog output card 418 ~as shown in FIG.
4) with data line 3 low and data line 4 higt~.
Referring more particularly to FIG. 6e, the integrate configuration 02 is obtained by writing onto an analog output card 41~ (as shown in FIG. 4) wi~h data line 3 high and data line 4 low.
~Z~Z7Z~ `
ReLerrin~ more l~articulclrly l:o l~'I(J. f~, conl:lguration 03A is the configuration WhiCtl occurs in Lhe firsL rnoae oE
the amplify conEiguration. Ini~ially operational amp1ifier YU ac~s m~rely aS an a~ liLier whose va1u~ is stored on capacitor 91 as well as being pr~sented at the output. ~or~fi~ur~ti~n 03B is the secon~ Inod~ o~ ~mpliiy in which the capacitor position af~r r~achlng approxim~tely the correcL value is ~rans1erred in its conneccions ~roln ground to the neg~tive inpu~. This second mocle is accomplished ac this tirne so ~hat later disconnection of the negative input of operational ampli~ier ~0 ~rom the analog sl~nal bus ll does not change the v~lue oi the stored an~log signal. ConfiguraCions o3A
and 03~ ~re obtained auton~atically and se4uentially by writing onto an analog output card 418 (as shown in FIG.
4) with data lines 3 and 4 high.
ReEerring more particularly to FIG. 6h the comparator configuracion Dl is obtained by writing onto the analog function card 500 (as shv~n in FIG. 5) wich data lines 3 and lO higb and data line 6 10w. This configur~t10n provides a l bit digital output to the d1gital compucer on line 5 of the 8 bit data bus. This comparator circuit will determine wt3ett~er or noc one analog value is greacer than another. ~lost often in industrial proc~sses Lhere is no need to convert to digital form to make a co~lparison.
Referring more parcicularly to FIG. 6i the positive reEerence confi~uratiotl Kl is obtained by wricing onto the . ~4 ~ wl Z7~
analog fUIlCLi~n car~ 5~ (as xhown in 1"~7. 5) wich data lines 4 and 10 hi,h and ~a~a lines 6 and 7 low.
Configuration 1~1 provicles 3 posicive reLerel-ce value which may be used in connecCion with the colllpar~cor or as an analog value of~set. ~eferring more parcicularly to FIG.
6j c~e ne~aLive referenc~ conEiguration l~2 is ~tained by writing onto the analog function card 50U (as sL~oi/n in FIG. 5) with data lines 4 7 and 1~ hioh and dac~ line 6 low. ~nli~urati~n ~2 is a negative rei~rence configuratl~n which can be used in a similar lashion to Rl. The value o~ the pvsitive and negative reference are adjustable digitally by selection ol appropriate resistors 1~2 through 19~.
In connection ~ith ~IGS. 6c-g resistor 92 of FIG. 4 was illustrated to show the conventional ~utput circuit.
All of the func~ions 00 01 02 03A and ~3~ can also be performe~ e4ually well with the circuitry of tne analog funccion circuit o~ FIG. 5 but withou~ e~ternal ou~put.
Additionally the value o~ resistor 92 carl be replaced by the digitally selected yalues of resistor network 181 providing variab1e amp1ifier gain.
In FIGS. 7 through lle combinations of the basic configurations of FIGS. 6a-j are set for~h. In FIG. 7 two external inputs are turned on and an output circuit has just been connected in che ampli~y con~iguration.
This comt~ination results in an inverting and sumuling operation ~rom tl~o inputs Vl and V2 to produce an inverted al)d sulnllled oucput V~. ~IG. ~ se~ts fortil a ~5 ~2C~27;2~
confiOurcation wtler~ an exc~r~lal inpu~ hcns b~en curned on and an outl?uc circui~ has been connecced in an inte~ra~e configuratioll. 'r~lese two combined cotlEigurci~lons will result in an oucput at V~ which is an inverted value of ~he integral of Vl. In int~gracion and in differentiation, the time that the circui~ remains connect~d to the analog bus affects the value produced at the output. Since the preferred embodilnent of ~his inv~ntion envisions only a single ana:Lo~, bus to handle all analog processing, the digital computer is programmed to allow integrativn and differentiation for brief periods of time over regularly spaced intervals. Ihe duty cycle of these rate related functions is rather small, but the values of the capacitor and scalinv resistors are chosen so that clle end result incegrated value is not measurably different than what could be obtained ii che inte~ration were allowed to proceed co~itinuously. 1he timing and duration of the rate sensitive calculations can be accomplished either automatically as an inherent function of the position in the sequence of statemen~s ~shictl are being executed by the controlling com~ut~r, or Lnay be regularly con~rolled by timing circuits ~hich insure a periodic sampling for a consisten~ amount of time.
Referring to FIG. 9, there is illustrated a comparator circuit which compares the value of an externally connected input Vl to see if it is above or belo~s a threshold va91ue wtlich is obtained frum configura9tion Rl.
The value of this tllreshold is, oE course9 easily set by 2~
~7f'q~, ~r, Z~7Z~
tl~e appropri~Le s~l~ction ol tlle resisLors io the resistor la~der ne~ork 1~1. The oucput o~ the col~lpar(ltor ~ will be aigitaL in forln an~ connects to tne ~igital computer.
A more colnple~ circuit is se~ forth in lIG. 10. As shown in Fl~. 10 this circuic for differen~iation c~nnot be sil~ultaneously vperated usin~ the sil~ol~ analo~ bus which the preferred embodiment uses. Ihe output V2 of the differentiator is a value ~hich corresl)ollds to the-differentia~ion of the input Vl. FIG. lU represents the end result ~hich occurs froln repeating a sequence of five steps shown in FI~. lla-lle a series of tilnes. As can be observed ~y the use of the sa~e item nulllber on difEerent resiscors the s~lne r~sistor functions differently at different times in the sequence. ~o illustrate the difference a prime has been used beside the second use of resistor even though in actual operatio~ the resistor ~ould be the s~me resistor. Capacitors 91a and gLb are put in the circuic in dotted configuration since their only function is to store values which allow the til~e sequential operation to occur. They t~ould not be necessary~for the differentiation to occur in this circuit if the circuit were configured to operate in a simultaneous fashion.
The Vl signal fr~m the external input couples through resistor 49 to the negative input oE operational amplifier 90a. Also connecting co this negative input is r~sistor 92c which provides ~ signal from the output of operational amplifier 9~c. ~ fee~ack r~sisc~r 9~ connects froln Lhe 7Z~
ou~l)uc oL ~p~ra~ional a~ if i~r ~j~a to Ll~ rleg(l~ive input. I'~-e outl~uc o~' oper~tion~ plirier 4~ I,rovides the dif~'~r~ntiated output at V2. 'ro ac~lieve the differentiation, the value oi' this output coul)les to the negative input o~ operational alllplilier 9Ub chrou~h resistor 92a'. A fe~back resistor 9~b connects fro(n the output oE operational ampliEier 90b to the negative input. This amplifier provides a signal inv~rsion at unity gain. I~le output ti~en couples tllrou~ resiscor 42b' to the negative input of ol)eratiollal alnpliCier 9~c.
Capacitor ~lc couples Erom the output oL amplifier ~Uc to the negative input to achieve integration o~' the signal.
This integrated signal is then subtracted from the incoming signal by its coul)ling Chrough resistor ~2c to the negative input of operational ampLifier 50a. That's ho~ the circuit appears to work in composite forlll. To view how tbe circuit works in the time sequential form which actually takes place with the preferred ernbodiment, re~erence should first be made to FI&. lla. Just as above, the output of th~ integrator is SUlllllled ~ith the external input Vl. This value is then ampliEied and produc~ed ac the oucput V2. I'he value of the amplified signal is inltially stored on capacitor 91a in its connection to ground.
ReEerring m~re parcicularly to F'IG. llb, the only change in the con~iguration is for capacitor 91a to change its connection froln being connected to ground to being connected to the negati've input o~ alllplifier ~j~a'. ~ihis ~` ~2027ZE~
~rovi~es a In~r~ accur;lce value co be store~J on Ch~
capacicor and mini;nizes the error causei1 in the disconnection of the negacive input Erom ~he da~a bus whicll will occur in the n~c step. As ca1l be observe~ in FIG. llc the negative input oE operational ampliEier 90a has been re[nove~ fro11l the data bus as h1s the external input resistor. Resistor 92a cemained c~nnecte~ and is designated as ~2a to correspond with the IIG. l0 designacion. Operational amplifier 90c was ~isconnected from the bus and placed in a hold configuration to preserve whatever interim value it had achieved in its integrated signal. ~perational ampiiEier 4~1~ is in the f1rst step oE tLle a11lplify mode and is tunctioning mGrely to achieve an inverced level signal.
Referring now to FIG. lld the same sicuation appears except that capacitor 9lb has changed its position in its second portion of the amplify mode of amplifier 90b.
ReEerring to FlG. lle ampliEier 90~ has cllanged its conEigurdtion Erom the ampliEy arrange1nent to the internal input "on" conf1guration so that the inverted value which it generated can be applied back to the single analog bus through its resistor 9~b . This signal is then used to continue the integration process of operational amplifier 90c. While this is occurring amplifier 90a is in a hold configuration to maintain the previous value of the output available for any external devices wnich are sampling the differentiated value.
After tt-e configuration in lle all the involved operational amplifiers are placed in hold mode and the 2~
~p Z~2~
analog c~lnputer ~es other proces~in,,. ~ er a l'i:ed tilne period, the circuit reverts back again co the configuration in lla ancl continues the sequence again.
After several cycles Ctlrou~Ll these configurations, a very accurate value of a differentiaced outpuc is achieve~.
Because the programl~able controlle~ ~hich concrols the connections of th~ analo~ circuit c~mponet-cs w~rks very rapidly in real time, the analog computer can function to the excernal world as thoul,h all of its colnponencs were permanéntly connected in various configurations, notwithstanding the fact that all of these configurations are constantly changing a~ a very rapicl rate. ~l~he net result is a general purpose analo~ colllpucer which can be infinitely versatile in its applications, exceedingly fast in its operation, exceedingly simple in ics design, and highly reliable in view of the very few nulDber of co~ponents which are present. The fact tt-at each of the operational ampllfiers has the ability no~ only to receive data from the single analog bus, but also to outpuc its value retained in its melllory back to tha~ very s~ e bus with extremely efficient digital colllulands provides for very rapid operation.
~ hile the invention has been illustr~t~d and described in detail in the drawings and foreg~ing description, the same is co be considered as illustrative and n~t rescrictive in character, it being understood thac only the preferred elnbodiment has been shown and described and that all cl-an~es and Ino~iLicatl~ns chat COllle wictlin Lhe spirit of the invention are desired c~ be procected.
. 3~
circuits in United States Patent No. 4 17~ 634, the analog version also has an input disable circuit 51. Ilhen an input/output disable signal J is received the action o~
NAND gates 52 and 53 and their corresponcling resistors 54 and 55 produce a reset signal 1~ apacit:or 56 functions to place a high on one input of NAI~I) gate 53 only when the power supply is first turned on. The R output of this NAND gate 53 is connected co latch 42 and the corresponding latches in the other 7 analog input circuits to insure that all of the analog inputs are turned off when the power supply is firs~ turned on. .
~ e~`erring now rnore particularly to FIG. 4 there is illustrated an analog output card 418. A -5.6 volt supply 61 is identical to the -5.6 volt supply 31 o~ FIG. 3. The card also has an output disable circuit 62 corresponding to the lnput dlsable circuit 51 of FIG. 3. A -~5.6 volt supply 63, necessary for operational ampliÇiers used in the output circuit, i5 of conventional design. Since the ~unctions of an analog output card of the inventiorl are more colnplex than a correspondin~ digital output card two bits oÇ intormation are r.eede~l Çor each output circuic.
~` ~
)2728 The sin~plest ~ay oL desigrlin~r an ou~l)ut car-l wit~ ~his constrain~ is simply t~ have c~nnections to orll~ half 01 the ou~put positions and ~his i~ ~hat ha~ ~een c~one in this instanc~. Anol:her alt~rnativ~, not si~own, would be to provid~ ~otll voltage anci current OUtl>~LS for ~ach outpur circuit, tllereby using all of the t~rminal connections. I~ t~ould, of course, be anotller alternative to provide a double byte oE data to the carci (iE sl)ace is available to get a suEEicient nuln~er ol colllpotlellts on ~he ~j car~) to perforu~ .he analog output Eunctions for all eigh~
output pairs of wir~s. ~ard enable circuit ~4 including two 3-1nput NAN'D gates 65 and 66 are connected in a conventional East)ion from the C, L ancl ~ lines to provide a read signal on line 70 and a wri-te signal on line 71 for the card.
Analog output circuit ~1 will be desc~ibed in d~tail.
Analog output circui~ts #2-4 are iclentical in configurdtion~ A terrninal block 454 having ter~inals such as termirlals 480 and 481, are useci for making conn4ctions to exterodl analog out~ut devices such as rnetel~7~. The data from line 3 can be latched in latch 72 and read back through gate 7~. Si~:ilarly, the data Erom line 4 can be latched in latch 82 and read back through gate ~3.
When the output of latch 7~ is high, the action of la~ch 72 an~cl lnvert~iog alnplifler 75 on analog switches 7 through 7~ is to turo on analog-switches 7~, 78, and-79.
This connects the minus inl3ut oE operational ainpliEier 90 to the analog signal bus 11 and the positive input to the 15' ~ q~
-- ~L2C~2~Z8 analog grourld ~l and Co circuiL gcounli. L~le cunnec~1ons to circuit grouncl are indicacecL L~y an "~ar~:h" cl~sigr)acion to dif~erentiate frolll the n~ore conven~ional gro-lndin~ ~Jnich is fou[]d in many cli~ital systems. Grounds having che "earth" clesignation are intended to be s~ar grou[l(ls with all grounds connecting to the same point to minimi-~e difficulcies with ground loops. ihe outpuc of la~ch 7~ is high during the integrate ancl amplify mod~s of operation.
The output oL lacch 7~ is 1C)W during the hola and internal signal input mocles of oper~tion. ~Ihen ~he oucput of latch 7~ is low then the positive input of operational smplifier 9~ connects to analog grourlcL ~I or to circuit ground depencling upon the state of latch ~2. The negacive input o~f operationa~l amplifier 9L) connects througll analog s~itch 77 to cap.lcitor 91 which connects at its otLler end to Lhe~outpuc of operational amplifier 9~' In this configuration the operaticinal amplilier will holcl the value oL the vo1tage across capaciCor 91 and proviae it at its output.
A r~sistor 92 couples the value of the output of opèrational amplifier 9~ either to ground through analog s~icch~87 (liold or integrate mode) or back to the analog slgnal bus through dnalog s~itch ~ (int~rnal signa1 input ~or amplify mode) d~pending upon the scate ol che output of lat~ch 82 and inverter ~5 controlling the analog s~itches ~6 an~ ~7.
As a Lurther consideration of the pro~lem of grounding ~hen the output ol latch 72 is l~w ~uring the 1~
hold and internal signal input modes of operation, the positive input of operational ampli~ier 90 needs to be connected to circuit ground for the hold mode and to ~he analog ground M for the internal signal input mode of operation. The output of latch 82 controls analog switch 95 to connect the positive input to the analog ground bus in the internal signal input mode. An inverting amplifi~r 93 which has its input connected to the output of latch 82 controls analog switch 94 to connect the positive input to the circuit ground in the hold mode. Operation of the computer of this invention is premised upon the fact that only one amplifier with feedback will be connected to the analog signal bus at a time. Since it is desired that there be only one internal ground at a time (to m;n;m; Y.e the problem of ground loops), the grounding point has been chosen to be at the input of the one amplifier which is connected in a mode with feedback. For the preferred circuit operation, the operational amplifiers used in this invention are MOSFET input 3160 amplifiers adjusted with external potentiometers connected to pins 1, 4 and 5 in conventional fashion (not shown) to eliminate offset voltage error.
AND gate 97 has inputs which connect to the outputs of latches 72 and 82. The output of AND gate 97 couples through capacitor 98 and inverter 101 to control analog switches 106 and 107. A resistor 103 serves -to bring the voltage at the input of inverter lOl to ground after a period of time. A problem occurs when operational amplifier 90 ~" ~
:~Z~2~28 is connec~d in ~n ~np1iLyin~ con~i ur~ti~n to ctl~ ~nalog signal cbus. Initially upoo connection su~stanLia1 alnounts o~ current ~1Ow into CapaClCOr ~1. So chat this does not inter~ere tJich the op~racion o~ Lhe operacional alnplifier analog switch 10~ is curned on and tl)e current through capacitor ~1 goes to ground. A~Cer a tilne determined by t~e time constant ol cZ~acitor 9~ and resistor 1~3 analog switch 106 upens and analog swiccll 107 c1Oses connecLin~ cap.lcitor ~1 to che negativ~ input o~ the operational alnp1ifier. 1t~is de1ayed conneccion of capacitor 91 prevents the large currents flowing through ~he capacltor Erom interfering with the outpuc values when tne operationa1 amplifier is first connected t~ the analog bus and allot~s for an exact value ~o ~e achieved lor storage by che capacitor once the value is very nearly achieved.
ReEerring now to FIG~. 5a and 5b analog function circuit 50~ is iilustraced in two separate sheecs which can be laid side-by-side. In FIG. 5a there are a -5.6 volt supply 112 and a +5.~ volt supply 113 ~hich are identical to the corresponding supplies 61 and 63 of FIG.
4. Card enable circuit 1~4 is very si~lilar to tl~e card enable circuic ~4 oE FIG. 4 except that clata bus line 10 is used with lin~s ~ and E so that a double by~e o~ data can be o~tained if ciesired. Operational amplifier 11~ is identical to operational amplifier ~ Ol FIG. 4.
1~3 ~zo;z~z~ -~iulilarly, olally oi the itelnS associ~ed WiCtl operational amplifier 110 are the ~alne in operation an(l function as the correspoLl~in~ items associated with operational amplifier 90. Therefore, the same item numbers are used to designate those correspo~ding items except that they are follos~ed with a prime indication. When operational amplifier 110 is conrlected as a comE)arator, its one bit digital output is available for coupling through gate lll to the data ~us of the digital controller. 1t-is is the sole digital output ~rom the analog processing portion of the invention which can be utilized by the digital processing of the digital controller.
The analog function circuit of F1~. 5a and b differs from the analog output card of FIG. 4 in several respects. First, it contains a selectable reference voltage. Second, it provides a selectable inverte~ or non-inverte~ signal. Third, instead of the single feedback resistor 92, there is a ladder network l~l of resistors 18~-19~ s~hich are binary weighte~ in value. The resistor ladder values range from ~ to -r~- This compares with the standard feedback resistor such as 92 and the standard input resistor such as 49 which are a va1ue of R/10. With this range o~ values, operational a~lplifier 110 can be made to multiply or divide s~ith ease. By applying the referenc~ voItage through this ladder net~rh to the analog bus, an amplifier in an analog output circuit can also be affected.
While Eor purposes of clarity chere is illustrated herein a resis~or l~dder network of 9 discrete resistors, ~LZ~Z7Z~3 i t l S cunc~ml~lu ce~:l Lha c a ~ ! L) 1 L ~ 1); lonol Ithlc C;l()S
rligitally collcr~ pocentiometer suc~ a'; A[lal(J~, ~evic~s AD 752, ~ould be approprlace. As an alternaclve- co ch~
d~ubl~ L)yL~ ~l,c~l)r~ h (~ s~ r~:in, Lll~ L blL l~
coulcl be divldeu inco cwo groups of four ~)iLs an~l use(~
wich a 1~ bit, 4~4 r~gist~r. ~ihe firsc gr~up of four Clts ~oul~ c~,nsisc ~f one blt ~or colliparator oucpuc, one ~ic to reset tne re~,isLer, and 2 bits lor a one-of-1our r~giscer select. ~he sec~nd group o~ Lour Di~S, ln Che home position o~ the regiscer, wou1~ have one bic Lor tne mosc significant value resixt~r, one bit for ~/- cuncrol~ and 2 bits for mo~e select (nol~, incernal slgnal input, rel~rence volc~ge, an~ alr,pllfy). ~he LOUr ~its lrorn each vf Lhe oth~r three positi~ns of che regiscer c~uld b~ used ~or the remaining 12 r~siscors.
Dacu input thruugh lln~ 7 is handled ~y a latch and gace comDindtlon 1~0 icl~ntlcal to thac o~ latch 72 and gate 73'. The oucput of the l~ccn portlon of laccl and g~te combination 1~ c~nLrols the polari~y of slgnals co th~ resiscur ladder necwork 1~1 lnclu~ing resistor~
1~2-1~0 and resiscor switching ciruul L S 1 7 ~ 0 . Egual v~lue reslsturs 1~6 ~ncl 127 couple cu and around the negatlve input of operatiunal ampliLier 1~ to provicie a ~ega~lv~ voltage egual and OppOSlte cu the input volt~ge from the output of ~u~ferlng operatlonal alllyll~ier 150. A
high signal frolT~ latch and gate combinacion 120 will cause an~lug switch 137-co turn un und analog s~icch 136 to curn o~f. Ihis inverts the signul cu reslscor lacicier necwor~
1~1 .
~(~
~Z~27Z~
A precision voltage reLerence l~2 (leLe~ e Semiconductor C~ 5) ouLpucs a five vol~ r~ference signal.
Data input tllrou~h line ~ is hanclled b~ a latcll and gace colrlbination 142 iden~ical to thaL of laLch 7~ ancl ~aL~
73'. The output Erom the lLitch portion ol latch ancl gate combination 142 througn inverter 145 determines whether Lhe output of operLItionLll ampliEier 11~ co~ ects ~I~rough analog s~itch 146 to operate in a fashic)n similar to the analog out~)ut circuits or if ch~ rererence volcag~ couples through analog gate 147 to the resistor network and the operational arnplifier 110 converts to a high gain coMparator mc?de of operation. Operational a[np1ifier 15 is providecl to assure that there is suEficient current available to drive the resistor laclcler network as well as to charge capacitor 91' in the apL~ropriate circuit configurations.
A resistor swit~ching circulc 172 includes latch and gate colnbinaLion 162 idénCical LO that oL lLlLch 72' and gate 73 to retain data EroLn line ~ oE the daca bus. The outpuc ~rom the latch portion oE latch and gate coLIlbinatioo 1~2 thruugtl inverter 165 de~erlllines whettler the resistor 1~2 with a value of R connects through analog switch 166 ~o the common side of the ladder network 181, or to ground through analog switch 167. r~esistor 1~2 is connected between the outpu~ oE the operational amplifier 110 (as bufferecl by operational amplifier 15~
and possibIy invertecl by operational ainpliEier 12~) to the analo~ signal bus ll when the output oL Lhe latch portion ~1 Z7Z~3 ~
o~ lacch a[l(l gate 162 is ~lig~) uncl th~ ouL~)u~ oL 1atcn ~' is high. IJhen cll~ ouLpuc of ~he 1~tctl porciorl ol 1at~h and gate 16~ is low, resistor 1~ si~nply connecLx to ground so t~lat che loa~ing on ~he operaLionaL alllp1ifiers l5~ or 1~ is noL affected by-the change.
l~eferring more particu1ar1y to FIG. 5b, there are a series of resistor connecting circuits 173 through l~
whlc~l op~race in idencical ~ashion co the resistor connecting circuic 172 and r~sistor l~. In order to all~w a double byte of data, a secon~ car~ enable circuit 1~2 is provided with an inverter 193 to 1nvert the logic level of the data on line 10. Card enable circui~ry 192 is otherwise identical to that of card enable circuit 164. While FIG. Sb shows duplicat~ external connections for purposes of cl~rity, aceu~lly, each car~ has only one ext~rnal conneccion. The interconnects wiChin the card have been avoided for purposes of clarity.
Ref~rring more particularly to FIGS. 6a-b, there are illustratea in ab~reviaced forrn, the resulcanc connections ~or the ~wo cvn~itiorls of an input with the input carc of FIG. 3 . It can ~e observed that an input is either grounded or connect~d to ~he single analog s1gnal ~us ll used In the analog porcion of the compucer. For purposes of clarity, the corresponding ground connections in the follo~ing descriptions are not considered. Also, for pùrposes of clarity, in connection wich further discussioos of operation, designations have been assigned to the various simplified conn~ction diat,rams. When the 2~
O~Z8 exterl-al input is o[E, as in ~ a, tl~e desigtlacion oi Il is used. Ihis configura~ion is obtained b~ writing onco an ana1Og input card 411 (as sllowrl in I~IG. 3) ~ h data line 3 low, l~i)en the e~ternal inpu~ is on, as in FIG. 6b, tt~e designation I~ i-, u~ hi~ c~nfi~,uration is obtained by writing onco an analo~ input car~ 411 (as shown in FIG. 3) with data line 3 high.
FIGS. 6c-g illustrate possible con~igurations for an ana1Os7, output circuit o~ FIG. 4 (and by an(J1Ogy Lor tne corresponding circuits of FIG. 5). FIG. 6c i1lustrates 00, a hold configuration which simp1y provides an output signal wich the storage capacitor 91 being positioned between the negative input of operationa1 anlpli~ier 90 and its output. Resistor 92 maintains a standard load on the operational a~pli~ier. Tnis c~nflguration is ol~tained by writing onto an analog output card 4l8 (as shown in FIG.
4) with data lines 3 and 4 low.
As illustrated in FIG. 6d, configuration 01 is a condition witLl the internal input on. In the circuic of the preferred embodiment, there are situations where an analog value at an oucput is desired to be read int~ the single analog bus. 1his configuration is obtaine~ ~y wricing onto an analog output card 418 ~as shown in FIG.
4) with data line 3 low and data line 4 higt~.
Referring more particularly to FIG. 6e, the integrate configuration 02 is obtained by writing onto an analog output card 41~ (as shown in FIG. 4) wi~h data line 3 high and data line 4 low.
~Z~Z7Z~ `
ReLerrin~ more l~articulclrly l:o l~'I(J. f~, conl:lguration 03A is the configuration WhiCtl occurs in Lhe firsL rnoae oE
the amplify conEiguration. Ini~ially operational amp1ifier YU ac~s m~rely aS an a~ liLier whose va1u~ is stored on capacitor 91 as well as being pr~sented at the output. ~or~fi~ur~ti~n 03B is the secon~ Inod~ o~ ~mpliiy in which the capacitor position af~r r~achlng approxim~tely the correcL value is ~rans1erred in its conneccions ~roln ground to the neg~tive inpu~. This second mocle is accomplished ac this tirne so ~hat later disconnection of the negative input of operational ampli~ier ~0 ~rom the analog sl~nal bus ll does not change the v~lue oi the stored an~log signal. ConfiguraCions o3A
and 03~ ~re obtained auton~atically and se4uentially by writing onto an analog output card 418 (as shown in FIG.
4) with data lines 3 and 4 high.
ReEerring more particularly to FIG. 6h the comparator configuracion Dl is obtained by writing onto the analog function card 500 (as shv~n in FIG. 5) wich data lines 3 and lO higb and data line 6 10w. This configur~t10n provides a l bit digital output to the d1gital compucer on line 5 of the 8 bit data bus. This comparator circuit will determine wt3ett~er or noc one analog value is greacer than another. ~lost often in industrial proc~sses Lhere is no need to convert to digital form to make a co~lparison.
Referring more parcicularly to FIG. 6i the positive reEerence confi~uratiotl Kl is obtained by wricing onto the . ~4 ~ wl Z7~
analog fUIlCLi~n car~ 5~ (as xhown in 1"~7. 5) wich data lines 4 and 10 hi,h and ~a~a lines 6 and 7 low.
Configuration 1~1 provicles 3 posicive reLerel-ce value which may be used in connecCion with the colllpar~cor or as an analog value of~set. ~eferring more parcicularly to FIG.
6j c~e ne~aLive referenc~ conEiguration l~2 is ~tained by writing onto the analog function card 50U (as sL~oi/n in FIG. 5) with data lines 4 7 and 1~ hioh and dac~ line 6 low. ~nli~urati~n ~2 is a negative rei~rence configuratl~n which can be used in a similar lashion to Rl. The value o~ the pvsitive and negative reference are adjustable digitally by selection ol appropriate resistors 1~2 through 19~.
In connection ~ith ~IGS. 6c-g resistor 92 of FIG. 4 was illustrated to show the conventional ~utput circuit.
All of the func~ions 00 01 02 03A and ~3~ can also be performe~ e4ually well with the circuitry of tne analog funccion circuit o~ FIG. 5 but withou~ e~ternal ou~put.
Additionally the value o~ resistor 92 carl be replaced by the digitally selected yalues of resistor network 181 providing variab1e amp1ifier gain.
In FIGS. 7 through lle combinations of the basic configurations of FIGS. 6a-j are set for~h. In FIG. 7 two external inputs are turned on and an output circuit has just been connected in che ampli~y con~iguration.
This comt~ination results in an inverting and sumuling operation ~rom tl~o inputs Vl and V2 to produce an inverted al)d sulnllled oucput V~. ~IG. ~ se~ts fortil a ~5 ~2C~27;2~
confiOurcation wtler~ an exc~r~lal inpu~ hcns b~en curned on and an outl?uc circui~ has been connecced in an inte~ra~e configuratioll. 'r~lese two combined cotlEigurci~lons will result in an oucput at V~ which is an inverted value of ~he integral of Vl. In int~gracion and in differentiation, the time that the circui~ remains connect~d to the analog bus affects the value produced at the output. Since the preferred embodilnent of ~his inv~ntion envisions only a single ana:Lo~, bus to handle all analog processing, the digital computer is programmed to allow integrativn and differentiation for brief periods of time over regularly spaced intervals. Ihe duty cycle of these rate related functions is rather small, but the values of the capacitor and scalinv resistors are chosen so that clle end result incegrated value is not measurably different than what could be obtained ii che inte~ration were allowed to proceed co~itinuously. 1he timing and duration of the rate sensitive calculations can be accomplished either automatically as an inherent function of the position in the sequence of statemen~s ~shictl are being executed by the controlling com~ut~r, or Lnay be regularly con~rolled by timing circuits ~hich insure a periodic sampling for a consisten~ amount of time.
Referring to FIG. 9, there is illustrated a comparator circuit which compares the value of an externally connected input Vl to see if it is above or belo~s a threshold va91ue wtlich is obtained frum configura9tion Rl.
The value of this tllreshold is, oE course9 easily set by 2~
~7f'q~, ~r, Z~7Z~
tl~e appropri~Le s~l~ction ol tlle resisLors io the resistor la~der ne~ork 1~1. The oucput o~ the col~lpar(ltor ~ will be aigitaL in forln an~ connects to tne ~igital computer.
A more colnple~ circuit is se~ forth in lIG. 10. As shown in Fl~. 10 this circuic for differen~iation c~nnot be sil~ultaneously vperated usin~ the sil~ol~ analo~ bus which the preferred embodiment uses. Ihe output V2 of the differentiator is a value ~hich corresl)ollds to the-differentia~ion of the input Vl. FIG. lU represents the end result ~hich occurs froln repeating a sequence of five steps shown in FI~. lla-lle a series of tilnes. As can be observed ~y the use of the sa~e item nulllber on difEerent resiscors the s~lne r~sistor functions differently at different times in the sequence. ~o illustrate the difference a prime has been used beside the second use of resistor even though in actual operatio~ the resistor ~ould be the s~me resistor. Capacitors 91a and gLb are put in the circuic in dotted configuration since their only function is to store values which allow the til~e sequential operation to occur. They t~ould not be necessary~for the differentiation to occur in this circuit if the circuit were configured to operate in a simultaneous fashion.
The Vl signal fr~m the external input couples through resistor 49 to the negative input oE operational amplifier 90a. Also connecting co this negative input is r~sistor 92c which provides ~ signal from the output of operational amplifier 9~c. ~ fee~ack r~sisc~r 9~ connects froln Lhe 7Z~
ou~l)uc oL ~p~ra~ional a~ if i~r ~j~a to Ll~ rleg(l~ive input. I'~-e outl~uc o~' oper~tion~ plirier 4~ I,rovides the dif~'~r~ntiated output at V2. 'ro ac~lieve the differentiation, the value oi' this output coul)les to the negative input o~ operational alllplilier 9Ub chrou~h resistor 92a'. A fe~back resistor 9~b connects fro(n the output oE operational ampliEier 90b to the negative input. This amplifier provides a signal inv~rsion at unity gain. I~le output ti~en couples tllrou~ resiscor 42b' to the negative input of ol)eratiollal alnpliCier 9~c.
Capacitor ~lc couples Erom the output oL amplifier ~Uc to the negative input to achieve integration o~' the signal.
This integrated signal is then subtracted from the incoming signal by its coul)ling Chrough resistor ~2c to the negative input of operational ampLifier 50a. That's ho~ the circuit appears to work in composite forlll. To view how tbe circuit works in the time sequential form which actually takes place with the preferred ernbodiment, re~erence should first be made to FI&. lla. Just as above, the output of th~ integrator is SUlllllled ~ith the external input Vl. This value is then ampliEied and produc~ed ac the oucput V2. I'he value of the amplified signal is inltially stored on capacitor 91a in its connection to ground.
ReEerring m~re parcicularly to F'IG. llb, the only change in the con~iguration is for capacitor 91a to change its connection froln being connected to ground to being connected to the negati've input o~ alllplifier ~j~a'. ~ihis ~` ~2027ZE~
~rovi~es a In~r~ accur;lce value co be store~J on Ch~
capacicor and mini;nizes the error causei1 in the disconnection of the negacive input Erom ~he da~a bus whicll will occur in the n~c step. As ca1l be observe~ in FIG. llc the negative input oE operational ampliEier 90a has been re[nove~ fro11l the data bus as h1s the external input resistor. Resistor 92a cemained c~nnecte~ and is designated as ~2a to correspond with the IIG. l0 designacion. Operational amplifier 90c was ~isconnected from the bus and placed in a hold configuration to preserve whatever interim value it had achieved in its integrated signal. ~perational ampiiEier 4~1~ is in the f1rst step oE tLle a11lplify mode and is tunctioning mGrely to achieve an inverced level signal.
Referring now to FIG. lld the same sicuation appears except that capacitor 9lb has changed its position in its second portion of the amplify mode of amplifier 90b.
ReEerring to FlG. lle ampliEier 90~ has cllanged its conEigurdtion Erom the ampliEy arrange1nent to the internal input "on" conf1guration so that the inverted value which it generated can be applied back to the single analog bus through its resistor 9~b . This signal is then used to continue the integration process of operational amplifier 90c. While this is occurring amplifier 90a is in a hold configuration to maintain the previous value of the output available for any external devices wnich are sampling the differentiated value.
After tt-e configuration in lle all the involved operational amplifiers are placed in hold mode and the 2~
~p Z~2~
analog c~lnputer ~es other proces~in,,. ~ er a l'i:ed tilne period, the circuit reverts back again co the configuration in lla ancl continues the sequence again.
After several cycles Ctlrou~Ll these configurations, a very accurate value of a differentiaced outpuc is achieve~.
Because the programl~able controlle~ ~hich concrols the connections of th~ analo~ circuit c~mponet-cs w~rks very rapidly in real time, the analog computer can function to the excernal world as thoul,h all of its colnponencs were permanéntly connected in various configurations, notwithstanding the fact that all of these configurations are constantly changing a~ a very rapicl rate. ~l~he net result is a general purpose analo~ colllpucer which can be infinitely versatile in its applications, exceedingly fast in its operation, exceedingly simple in ics design, and highly reliable in view of the very few nulDber of co~ponents which are present. The fact tt-at each of the operational ampllfiers has the ability no~ only to receive data from the single analog bus, but also to outpuc its value retained in its melllory back to tha~ very s~ e bus with extremely efficient digital colllulands provides for very rapid operation.
~ hile the invention has been illustr~t~d and described in detail in the drawings and foreg~ing description, the same is co be considered as illustrative and n~t rescrictive in character, it being understood thac only the preferred elnbodiment has been shown and described and that all cl-an~es and Ino~iLicatl~ns chat COllle wictlin Lhe spirit of the invention are desired c~ be procected.
. 3~
Claims (9)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A hybrid digital and analog computer comprising:
a. a hybrid computer having several interface loca-tions each suitable for insertion of an interface module and each of said interface locations having connections for (1) common multibit data bus (2) common analog signal bus (3) common read and/or write signal bus (4) common supply voltage (5) common ground (6) card enable address line (7) multiple external lines for connection to external devices;
b. means for permitting either of the following to be operationally inserted into any one of said several inter-face locations without re-wiring being necessary:
(1) a digital data interface module for con-trolling connections between the computer and external devices, or (2) an analog data interface module for con-trolling connections between the computer and external devices.
a. a hybrid computer having several interface loca-tions each suitable for insertion of an interface module and each of said interface locations having connections for (1) common multibit data bus (2) common analog signal bus (3) common read and/or write signal bus (4) common supply voltage (5) common ground (6) card enable address line (7) multiple external lines for connection to external devices;
b. means for permitting either of the following to be operationally inserted into any one of said several inter-face locations without re-wiring being necessary:
(1) a digital data interface module for con-trolling connections between the computer and external devices, or (2) an analog data interface module for con-trolling connections between the computer and external devices.
2. The hybrid computer of claim 1 which additionally includes a common analog ground connection in each of said several interface locations.
3. The hybrid computer of claim 1 in which there are at least eight interface locations.
4. The hybrid digital and analog computer of claim 1 which additionally includes an analog data input card as said analog data interface module and a digital data input card as said digital data interface module.
5. The hybrid digital and analog computer of claim 1 which additionally includes an analog data output card as said analog data interface module and a digital data output card as said digital data interface module.
6. The hybrid digital and analog computer of claim 1 which additionally includes:
(a) digital data input card, (b) analog data input card, (c) digital data output card, and (d) analog data output card as said analog and digital data interface modules.
(a) digital data input card, (b) analog data input card, (c) digital data output card, and (d) analog data output card as said analog and digital data interface modules.
7. The hybrid digital and analog computer of claim 6 which additionally includes said analog and digital data input and output cards in said locations, all having common pin connections for the common multibit digital data bus.
8. The hybrid digital and analog computer of claim 7 in which there are at least eight interface locations.
9. The hybrid digital and analog computer of claim 6 which additionally includes a common analog ground connection in each of said several interface locations.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000483376A CA1202728A (en) | 1982-06-25 | 1985-06-06 | Digital computer having analog signal circuitry |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US392,374 | 1982-06-25 | ||
| US06/392,374 US4499549A (en) | 1982-06-25 | 1982-06-25 | Digital computer having analog signal circuitry |
| CA000431135A CA1195006A (en) | 1982-06-25 | 1983-06-24 | Digital computer having analog signal circuitry |
| CA000483376A CA1202728A (en) | 1982-06-25 | 1985-06-06 | Digital computer having analog signal circuitry |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000431135A Division CA1195006A (en) | 1982-06-25 | 1983-06-24 | Digital computer having analog signal circuitry |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1202728A true CA1202728A (en) | 1986-04-01 |
Family
ID=25670072
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000483377A Expired CA1203319A (en) | 1982-06-25 | 1985-06-06 | Digital computer having analog signal circuitry |
| CA000483376A Expired CA1202728A (en) | 1982-06-25 | 1985-06-06 | Digital computer having analog signal circuitry |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000483377A Expired CA1203319A (en) | 1982-06-25 | 1985-06-06 | Digital computer having analog signal circuitry |
Country Status (1)
| Country | Link |
|---|---|
| CA (2) | CA1203319A (en) |
-
1985
- 1985-06-06 CA CA000483377A patent/CA1203319A/en not_active Expired
- 1985-06-06 CA CA000483376A patent/CA1202728A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| CA1203319A (en) | 1986-04-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4499549A (en) | Digital computer having analog signal circuitry | |
| Braatz et al. | Computational complexity of/spl mu/calculation | |
| Yih et al. | A neural network design for circuit partitioning | |
| CA1202728A (en) | Digital computer having analog signal circuitry | |
| Richard | Scaling behaviour of two-dimensional polygon models | |
| Feldberg et al. | Hopscotch-finite-difference simulation of the rotating ring-disc electrode | |
| Šebek et al. | On H∞ Problems for 2-D Systems | |
| US6453309B1 (en) | Method for correcting errors in parallel A/D conversion, corrector and parallel A/D converter | |
| US8369452B2 (en) | Majority detector apparatus, systems, and methods | |
| JPH10247205A (en) | Device and method for gate delay calculation | |
| Douglas et al. | Fast hybrid solution of algebraic systems | |
| US6415429B1 (en) | Field programmable analogue processor | |
| Rossmann et al. | Implementation of a biologically inspired neuron-model in FPGA | |
| US5633640A (en) | Method and apparatus for a data converter with a single operational amplifier | |
| Suh et al. | Stability condition of state-delayed systems based on stability-guaranteed discretization | |
| Chen et al. | An interactive net connectivity check strategy | |
| KANUNNIKOV et al. | Design of hybrid functional converters(K raschetu gibridnykh funktsional'nykh preobrazovatelei) | |
| JPH0327425A (en) | Input discrimination system by micro computer | |
| BRUNSON | Decommutator patchboard verifier[Patent] | |
| Acha et al. | Explicit expressions for the parameter sigma in two-pair cascaded realization of digital transfer functions | |
| Teng et al. | A VHDL library for current-mode CMOS multiple-valued logic | |
| Bai et al. | On digital control of continuous time systems using generalized hold functions | |
| Oddone et al. | Mixed analog-digital circuit for linear-time programmable sorting | |
| CN112085389A (en) | Three-phase load unbalance commutation strategy evaluation method, terminal equipment and storage medium | |
| SHEA | On the fitting and forecasting of vector time series models |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |