CA1178346A - Phase modulator with phase-unlocked state detecting function - Google Patents
Phase modulator with phase-unlocked state detecting functionInfo
- Publication number
- CA1178346A CA1178346A CA000409992A CA409992A CA1178346A CA 1178346 A CA1178346 A CA 1178346A CA 000409992 A CA000409992 A CA 000409992A CA 409992 A CA409992 A CA 409992A CA 1178346 A CA1178346 A CA 1178346A
- Authority
- CA
- Canada
- Prior art keywords
- phase
- output
- frequency
- pll circuit
- phase comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
Abstract
ABSTRACT OF THE DISCLOSURE
A phase modulator is of a type using a phase-locked loop (PLL) circuit in which a function for detecting a phase-unlocked state of the PLL
circuit is provided. It comprises a reference oscillator, a PLL circuit having a first phase comparator, a low-pass filter and a voltage controlled oscillator, modulating means for applying a modulation signal to the control loop of the PLL
circuit, first and second frequency modulators for respectively dividing in frequency the output of the reference oscillator and the output of the voltage ocntrolled oscillator, a second phase comparator for comparing the phases of the outputs of the first and second frequency dividers, and a discriminator for comparing the output level of the second phase comparator with a preset level. By providing the above frequency dividers, a stable phase modulating operation can be performed in which detection on whether or not the PLL circuit is in the phase-locked state can be performed accurately.
A phase modulator is of a type using a phase-locked loop (PLL) circuit in which a function for detecting a phase-unlocked state of the PLL
circuit is provided. It comprises a reference oscillator, a PLL circuit having a first phase comparator, a low-pass filter and a voltage controlled oscillator, modulating means for applying a modulation signal to the control loop of the PLL
circuit, first and second frequency modulators for respectively dividing in frequency the output of the reference oscillator and the output of the voltage ocntrolled oscillator, a second phase comparator for comparing the phases of the outputs of the first and second frequency dividers, and a discriminator for comparing the output level of the second phase comparator with a preset level. By providing the above frequency dividers, a stable phase modulating operation can be performed in which detection on whether or not the PLL circuit is in the phase-locked state can be performed accurately.
Description
~7~33~
This invention relates to a phase modulator utilizing a phase-locked loop (PLL) circuit and, more paxticu-larly, to a phase modulator which has a function for detecting phase-unlocked state of the PLL circuit.
The invention will be described in more detail with reference to the accompanying drawings, in which:-FIG. 1 is a block diagram showing the circuit arrange-ment of a conventiOnal phase modulator;
FIGS. 2 and 3 are timecharts showing an example of the operation of the second phase comparator of the phase modulator shown in Fig. l;
FIG. 4 is a block diagram showing an example of the first phase comparator of the phase modulator in Fig. l;
FIG. 5 is a timechart illustrating an example of the operation of the first phase comparator in Fig. 4;
FIGS. 6A and 6B are diagrams illustrating the integrated output characteristics of the firs-t phase comparator shown in Fig. 4 and of the second phase comparator shown in Fig. l;
FIG. 7 is a block diagram showing an embodiment of a phase modulator according to the present invention;
FIG. 8 is a timechart illustrating an example of the operation of the phase modulator shown in Fig. 7;
FIG. 9 is a diagram illustrating the integrated output characteristics of the first and second phase compara-tors in the phase modulator shown in Fig. 7; and 3~i FIGS. 10 and ll are block diagrams illustrating the other examples of the phase modulator according to the present invention.
The conventional phase modulator is heretofore constructed as shown in Fig. l, in which the phase modulator includes a reference oscillator 10 for generating a signal of a predetermined reference frequency, a PLL circuit 20 which typically has a phase comparator 21, (referred to as "first phase comparator") a loop filter 22 and a voltage controlled oscillator (VCO) 23, a phase comparator 30 (referred to as "second phase comparator") which includes an exclusive OR
circuit(EX-OR circuit) 31 and an integrator 32, a level dis-criminator 40 which compares the output signal level of the second phase comparator 30 with a present reference voltage Vref and discriminates whether or not the output signal of the second phase comparator 30 falls within a predetermined level range, and an unlock detection - la -~ 3 ~ ~
terminal 50 which leads out a discrimination signal from the level discriminator 40. An adequate modulation signal M such as a voice signal ls applied to an adder 60 which is connected to the output of the first phase comparator 21 of the PLL circuit 20, thereby causing the PLL circuit 20 to operate as a phase modulator, and a phase-unlocked state of the PLL circuit 20 is monitored by the second phase comparator 30 and the level discriminator 40 during the operation as the phase modulator.
When the PLL circuit 20 operates in phase-locked state, the output a of the VCO 23 is synchronized with the output b of the reference oscillator 10 as shown in Fig. 2, and the output c of the EX-OR
circuit 31 and therefore the output of the integrator 32 become always the low level. On the other hand, when the PLL circuit operates in phase-unlocked state as shown in Fig. 3, the output a' of the ~CO 23 is not synchronized with the output b' of the reference oscillator 10. Accordingly, the output c' of the EX-OR circuit 31 repeats, as shown in Fig. 3, the high ~.nd the low levels. Thus, the output of the integrator 32 becomes approximately a central value between the high level and the low level.
If a certain component in the PLL circuit 20 becomes defective so that either one of the two input signals a and b of the EX-OR circuit 31 is not ~7i33~i inputted there-to (This is a case of phase-unlocked state), the output of the integrator 32 also becomes around a central value between the high level and the low level.
Hence, if the reference voltage Vref of the level discriminator 40 is set, for example, to 1/4 from the low level side between the high level and the low level, the level discriminator 40 can discriminate whether the PLL circuit 20 is in phase-locked or phase-unlocked state.
When the PLL circuit 20 is used as a phase modulator as shown in Fig. 1, there occurs an instantaneous phase error proportional to the magnitude of the modulation index of the modulation signal M, between the output b of the reference oscillator 10 to be inputted to the first and second phase comparators 21 and 30 and the output a of the VCO 23. This will be described in more detail with reference to Figs. 4 to 6.
Referring to Fig. 4 in which the first phase comparator 21 consists of an RS flip flop 211 and an inverter 212, the output b from the reference oscillator 10 is inputted to the terminal S of ~he RS
flip-flop 211, the output a from the VC0 23 is inputted to a terminal R of the RS flip-flop 211 through the inverter 212 and the output of a terminal Q of the RS flip-flop 211 is outputted as the output ~ 3 ~ ~
of the first phase comparator 21 itself.
Fig, 5 shows a timing chart indicating the operation of the first phase comparator 21. As evident from Fig. 5, the signal a is inverted via the inverter 212 to become a signal d, with the result that the output e is produced from the terminal Q of the RS flip-flop 211 in accordance with the relationship between the signal _ and the signal d.
More particularly, it is understood that the duty cycle of the output e becomes 50% and the average of the output voltage of the first phase comparator 21 coincides with the central level between the high level and the low level when the phase difference of the two inputs a and b of the first phase comparator 21 is zero. When the phase of the signal a is shifted so as to vary the phase difference between the signals a and b from 0 to - ~ or from 0 to ~, as shown in Fig. 6, the duty cycle of the signal e produced from the RS flip-flop 211 respectively vary from 50% to 0% or from 50% to 100%. If the output of the RS flip-flop 211 is integrated to be smoothened, it becomes as shown in Fig. 6A.
On the other hand, in the second phase comparator 30 which consists of the EX-OR circuit 31 and the integrator 32, the output c of the EX-OR
circuit 31 always becomes the low level as shown in Fig. 2, that is, the duty cycle is 0% during the ` ~7~33~
synchronized state, i.e., the phase difference between the signals a and _ is zero. When the phase of the signal a is shifted so as to vary the phase difference between the signals a and b from 0 -to - ~
or from 0 to ~, the duty cycle of the output c of the EX-OR circuit 31 respectively vary from 0% -to 100% or from 0% to 100%. When the output c of the EX-OR
circuit 31 is integrated by the integrator 32, the output of the second phase comparator 30 becomes as shown in Fig. 6B.
When the PLL circuit 20 shown in Fig. 1 operates in phase-locked state, the phase difference between the signals a and _ falls within a predetermined small range of a stationary phase error which extends over the small range on the line of the integrated output characteristics with the zero-phase difference point being as its center in Figs. 6A and 6B. If the signals a and _ are completely synchronized with each other with the stationary phase error being zero, the PLL circuit 20 is phase-locked at the position in which the phase difference is zero.
On the other hand, when the modulation signal M
is applied to the adder 60 so that the PLL circuit 20 operates as a phase modulator, the phase difference between the two inputs a and b of the firs-t and second phase comparators 21 and 30 move, for example, in the range designated by a thick line in Figs. 6A
3~6 and 6B taking the point of the phase difference zero as a center in accordance with the modulation signal M. The phase difference in this case is the above described instantaneous phase error.
The magni-tude of this instantaneous phase error and hence the range designated by the thick line in Figs. 6A and 6B is proportional to the magnitude of the maximum modulation index o~ the PLL circuit 20 operating as a modulator. When the voltage of the modulation signal M is raised, the range of the thick line will increase. In other words, when the modulation signal M is applied to the adder 60 in the PLL circuit 20, the phase difference increases by the amount of the applied modulation signal M and hence it seems as if the phase-unlocked state took place.
Assume that the maximum modulation index of the PLL circuit 20 operating as a modulator is considerably large, the modulator operates in the range of the thick line in Fig. 6A (e.g., within lock-in range limit) and the reference voltage Vref of the level discriminator 40 is set to the value designated by a broken line in Fig. 6B by considering a certain safety factor, then the phase difference of the two inputs a and b to the first and second phase comparators 21 and 30 reaches to the ends (both ends) of the range designated by the thick line at the timing when the instantaneous level of the modulation ~:~7~
signal M becomes maximum. As a result, it is so judged that the PLL circuit 20 temporarily becomes in phase-unlocked state even though it operates normally as a phase modula-tor. In order to avoid such misjudge, it might be thought of to further raise the reference voltage Vref of the level discriminator 40. However, if the reference voltage Vref is excessively raised, there occurs a danger of a misjudge in which actual phase-unlocked state, that is, true fre-quency offset exceeding lock-in a phase-unlocked s~ate not caused by modulation, fails to be detected. Another met'nod is also thought of as another remedy in which the -time con-stant of the integrator 32 is set to sufficiently large compared with the period of the modulation signal M. How-ever, in such a method, it has such a disadvantage that it takes a long time to detect the phase-unlocked state.
Accordingly, the present invention provides a phase modulator which can elimina-te the aforementioned draw-backs and disadvantages of the conventional phase modulators and which performs a stable phase modulating operation by effectively detecting whether or not the PLL circuit opera-tes in phase-locked state under any condition of a modula-tion signal and the PLL circuit.
When two signals to be applied to a phase ~7~3~;
comparator are frequency-divided by N, the gradient of the integrated output of the phase comparator becomes l/N. In other words, when these frequency-divided signals are phase-modulated in -the same degree as in a case in which signals are not frequency-divided, the variation in the output voltage of the phase comparator (the integrated output) becomes remarkably lower in the case of frequency-divided signals than that in case of no frequency division. This invention has taken notice of this point and according to this invention two signals to be applied to the second phase comparator for monitoring the phase-unlocked state of the PLL
circuit are frequency-divided. In this manner, the degree of the variation in the output voltage of the phase comparator due to the phase modulation viewed from the level discriminator becomes substantially low, thereby effectively and accurately discriminating in large margin whether or not it is the variation based on the phase-unlocked state even if this is monitored with the reference voltage Vref as in the conventional phase modulator. The delay of the discriminating operation due to the frequency division becomes N times, but it is small enough to be ignored as compared with the above described method of increasing the time constant of the integrator compared with the period of the ~71~346 modulation signal.
According to the phase modulator of this invention, it can effectively and rapidly discriminate in large margin whether or not the PLL circuit is in phase-locked state and hence whether or not the PLL circuit normally performs a phase modulating operation, and can, therefore, perform stable and highly reliable phase modulation. Further, the output of the level discriminator can be used as a signal for driving a suitable indicator or a signal for interrupting the output of the phase modulator. When this phase modulator is applied for a modulation circuit of an angular modulation transmitter, it can provide great effects and advantages.
Thus the present invention provides a phase modula-tor with phase-unlocked state detecting function comprising:
a reference oscillator for oscillating a signal of a predeter-mined frequency; a PLL circuit having a first phase compara-tor, a low-pass filter and a voltage controlled oscillator;
modulating means for applying a modulation signal to the con-trol loop of said PLL circuit; first and second frequencydividers for respectively frequency-dividing the outputs.of said reference oscillator and said voltage controlled oscilla-tor applied to said first comparator; a second phase compara-tor receiving the outputs of said first and second frequency ~5 dividers for comparing the phases of the outputs of said first and second frequency dividers to produce a signal corresponding to the phase difference therebetween; and a discriminator for comparing the output level of said second phase comparator with a present level to discriminate whether or not said PLI. circuit is in phase-locked state.
~ ~ 7 ~ 3 Referring once more to the drawings, Fig. 7 shows one preferred embodiment of a phase modulator according to the present invention, wherein elements which are the same as those in Fig. 1 are referred -to as the same reference numerals and symbols, and reference numerals 71 and 72 designate frequency dividers which hase the same frequency dividing ratio. The frequency divider 71 is for frequency-dividing -the output b of a reference oscillator 10 to supply the frequency-divided output into an EX-OR circuit 31. The frequency divider 72 is for frequency-dividing the output a of a ~7CO 23 to supply the frequency-divided output into an EX-OR
circuit 31. In this embodiment1 the RS flip-flop 211 and the inverter 212 shown in Fig. 4 are used in a first phase comparator 21.
10The operation of the circuit thus constructed will now be described with reference to ~igs. 8 and 9. Fig. 8 is a timechart illustrating the operations of various points of the phase modulator in Fig. 7 in which T flip-flops whose frequency dividing ratio is 15"2" are used for the frequency dividers 71 and 72.
This timechart shows the case that the phase difference between the output b of the reference oscillator 10 and the output a of the VCO 23 is zero.
Reference symbols f, f' and g, g' in Fig. 8 indicate the outputs of the frequency dividers 71 and 72, but it is undefinite whether the outputs of the frequency dividers 71 and 72 become either ones, that is, f or f', g or g'. This depends on an initial state of the T flip-flops. Therefore, when the outputs of the frequency dividers 71 and 72 become f and g, the output of the integrator 32 becomes the low level as designated by h, and when the outputs of the 3~
frequency dividers 71 and 72 become f and g', the output of the integrator 32 becomes a high level as designated by h'.
According to this embodiment, the output characteristic of ~he first phase comparator 21 becomes similar to the conventional one (Refer to Fig. 6A.) as shown in Fig. 9A , while the output characteristic of the second phase comparator 30 becomes a line as shown in Fig. 9B having a gradient of 1/2 of the conventional characteristic (Refer to Fîg. 6X), even though the characteristic of the integrator 32 itself is not varied at all (The output characteristic of the second phase comparator 30 may become as shown in broken lines in Fig. 9b according to the initial value of the T flip-flops).
In other words, this is the characteristic which is obtained by inserting the frequency dividers 71 and 72 whose frequency dividing ratio is "2", and since the period of time of the signals inputted to the second phase comparator 30 become twice, the phase difference of twice of the conventional one is required to vary the duty cycle of the output of the EX-OR circuit 31 from 0% to 100% or from 100% to 0%.
When the range in which the phase difference between the two inputs a and b of the first phase comparator 21 of the PLL circuit 20 operated as a phase modulator varies is the same as the range shown ~ 8 3~ ~
by the thick line in Fig. 6A, the output voltage of the integrator 32 varies in small amount since the gradient in Fig. 9B is smaller. In other words, by frequency-dividing with during ratio being N the variation range of the output of the integrator 32 (the voltage range of the thick line) becomes l/N of that in the conventional PLL circuit. TherPfore, the reference voltage Vref of the level discriminator 40 can be set out of the frequency difference varying range varying due to the modulation. Since the initial states of the frequency dividers 71 and 72 are unfixed, the reference voltage V'ref is necessary as shown in Fig. 9B to perform discrimination in the case where the characteristic is designated by broken lines in Fig. 9B. When both the frequency dividers 71 and 72 are simultaneously reset, the reference voltage V'ref becomes unnecessary.
In Fig. 7, reference numeral 80 designates a gate circuit, 90 a transmitter, and 100 an indicator, which are employed in connection with the phase-unlocked detection signal outputted from the level discriminator 40. More particularly, the gate circuit 80 is operated to interrupt the output of a phase modulator when the phase-unlocked detection signal is applied thereto, thereby inhibiting the transmission of an abnormal signal from the ~ ~ 7 ~ 3 ~ ~
transmitter 90 due to the phase-unlocked state, and the indicator 100 indicates the state of the PLL
circuit 20 based on the phase-unlocked detection signal. The detection signal may be utilized in either one, or may also be used in ano-ther use such as the direct control of the VCO 23.
In the embodiment shown in Fig. 7, the adder 60 used as means for applying the modulation signal M is connected to the output side of the first phase comparator 21, but the equivalent function can also be obtained by connecting the adder 60 to the output side of the loop filter 22.
The frequency dividing ratio of the frequency dividers 71 and 72 may not always be equal to each other so long as equivalent logic can be obtained by the circuits provided before and after these dividers.
In the embodiment shown in Fig. 7, the second phase comparator 30 consists of the E~-OR circuit 31 and the integrator 32, but however an equivalent effect may be obtained if it consists of a so-called analog type phase comparator (e.g., a switching type phase detector, a double balanced type phase comparator, etc.) and an integrator.
In an actual PLL circuit, it is frequently constructed that the output of the VCO 23 is further, as shown in Fig 10 or 11, frequency-divided by a '~ ~ 7 ~ 3 ~ ~
frequency divider 25 through a buffer amplifier 24 or is mixed by a mixer 26 with an OFFSET signal having a predetermined frequency different from thP frequency of the output of the VCO 23, is thereafter frequency-divided by a freqllency divider 27 and is then applied to the first phase comparator 21. In such a case, the frequency divider 72 is, as shown in the same Figure, constructed to receive the outpu~ of the frequency divider 25 or 27. In Fig. 11, the above-described OFFSET signal is outputted from a suitable reference oscillator (not shown).
This invention relates to a phase modulator utilizing a phase-locked loop (PLL) circuit and, more paxticu-larly, to a phase modulator which has a function for detecting phase-unlocked state of the PLL circuit.
The invention will be described in more detail with reference to the accompanying drawings, in which:-FIG. 1 is a block diagram showing the circuit arrange-ment of a conventiOnal phase modulator;
FIGS. 2 and 3 are timecharts showing an example of the operation of the second phase comparator of the phase modulator shown in Fig. l;
FIG. 4 is a block diagram showing an example of the first phase comparator of the phase modulator in Fig. l;
FIG. 5 is a timechart illustrating an example of the operation of the first phase comparator in Fig. 4;
FIGS. 6A and 6B are diagrams illustrating the integrated output characteristics of the firs-t phase comparator shown in Fig. 4 and of the second phase comparator shown in Fig. l;
FIG. 7 is a block diagram showing an embodiment of a phase modulator according to the present invention;
FIG. 8 is a timechart illustrating an example of the operation of the phase modulator shown in Fig. 7;
FIG. 9 is a diagram illustrating the integrated output characteristics of the first and second phase compara-tors in the phase modulator shown in Fig. 7; and 3~i FIGS. 10 and ll are block diagrams illustrating the other examples of the phase modulator according to the present invention.
The conventional phase modulator is heretofore constructed as shown in Fig. l, in which the phase modulator includes a reference oscillator 10 for generating a signal of a predetermined reference frequency, a PLL circuit 20 which typically has a phase comparator 21, (referred to as "first phase comparator") a loop filter 22 and a voltage controlled oscillator (VCO) 23, a phase comparator 30 (referred to as "second phase comparator") which includes an exclusive OR
circuit(EX-OR circuit) 31 and an integrator 32, a level dis-criminator 40 which compares the output signal level of the second phase comparator 30 with a present reference voltage Vref and discriminates whether or not the output signal of the second phase comparator 30 falls within a predetermined level range, and an unlock detection - la -~ 3 ~ ~
terminal 50 which leads out a discrimination signal from the level discriminator 40. An adequate modulation signal M such as a voice signal ls applied to an adder 60 which is connected to the output of the first phase comparator 21 of the PLL circuit 20, thereby causing the PLL circuit 20 to operate as a phase modulator, and a phase-unlocked state of the PLL circuit 20 is monitored by the second phase comparator 30 and the level discriminator 40 during the operation as the phase modulator.
When the PLL circuit 20 operates in phase-locked state, the output a of the VCO 23 is synchronized with the output b of the reference oscillator 10 as shown in Fig. 2, and the output c of the EX-OR
circuit 31 and therefore the output of the integrator 32 become always the low level. On the other hand, when the PLL circuit operates in phase-unlocked state as shown in Fig. 3, the output a' of the ~CO 23 is not synchronized with the output b' of the reference oscillator 10. Accordingly, the output c' of the EX-OR circuit 31 repeats, as shown in Fig. 3, the high ~.nd the low levels. Thus, the output of the integrator 32 becomes approximately a central value between the high level and the low level.
If a certain component in the PLL circuit 20 becomes defective so that either one of the two input signals a and b of the EX-OR circuit 31 is not ~7i33~i inputted there-to (This is a case of phase-unlocked state), the output of the integrator 32 also becomes around a central value between the high level and the low level.
Hence, if the reference voltage Vref of the level discriminator 40 is set, for example, to 1/4 from the low level side between the high level and the low level, the level discriminator 40 can discriminate whether the PLL circuit 20 is in phase-locked or phase-unlocked state.
When the PLL circuit 20 is used as a phase modulator as shown in Fig. 1, there occurs an instantaneous phase error proportional to the magnitude of the modulation index of the modulation signal M, between the output b of the reference oscillator 10 to be inputted to the first and second phase comparators 21 and 30 and the output a of the VCO 23. This will be described in more detail with reference to Figs. 4 to 6.
Referring to Fig. 4 in which the first phase comparator 21 consists of an RS flip flop 211 and an inverter 212, the output b from the reference oscillator 10 is inputted to the terminal S of ~he RS
flip-flop 211, the output a from the VC0 23 is inputted to a terminal R of the RS flip-flop 211 through the inverter 212 and the output of a terminal Q of the RS flip-flop 211 is outputted as the output ~ 3 ~ ~
of the first phase comparator 21 itself.
Fig, 5 shows a timing chart indicating the operation of the first phase comparator 21. As evident from Fig. 5, the signal a is inverted via the inverter 212 to become a signal d, with the result that the output e is produced from the terminal Q of the RS flip-flop 211 in accordance with the relationship between the signal _ and the signal d.
More particularly, it is understood that the duty cycle of the output e becomes 50% and the average of the output voltage of the first phase comparator 21 coincides with the central level between the high level and the low level when the phase difference of the two inputs a and b of the first phase comparator 21 is zero. When the phase of the signal a is shifted so as to vary the phase difference between the signals a and b from 0 to - ~ or from 0 to ~, as shown in Fig. 6, the duty cycle of the signal e produced from the RS flip-flop 211 respectively vary from 50% to 0% or from 50% to 100%. If the output of the RS flip-flop 211 is integrated to be smoothened, it becomes as shown in Fig. 6A.
On the other hand, in the second phase comparator 30 which consists of the EX-OR circuit 31 and the integrator 32, the output c of the EX-OR
circuit 31 always becomes the low level as shown in Fig. 2, that is, the duty cycle is 0% during the ` ~7~33~
synchronized state, i.e., the phase difference between the signals a and _ is zero. When the phase of the signal a is shifted so as to vary the phase difference between the signals a and b from 0 -to - ~
or from 0 to ~, the duty cycle of the output c of the EX-OR circuit 31 respectively vary from 0% -to 100% or from 0% to 100%. When the output c of the EX-OR
circuit 31 is integrated by the integrator 32, the output of the second phase comparator 30 becomes as shown in Fig. 6B.
When the PLL circuit 20 shown in Fig. 1 operates in phase-locked state, the phase difference between the signals a and _ falls within a predetermined small range of a stationary phase error which extends over the small range on the line of the integrated output characteristics with the zero-phase difference point being as its center in Figs. 6A and 6B. If the signals a and _ are completely synchronized with each other with the stationary phase error being zero, the PLL circuit 20 is phase-locked at the position in which the phase difference is zero.
On the other hand, when the modulation signal M
is applied to the adder 60 so that the PLL circuit 20 operates as a phase modulator, the phase difference between the two inputs a and b of the firs-t and second phase comparators 21 and 30 move, for example, in the range designated by a thick line in Figs. 6A
3~6 and 6B taking the point of the phase difference zero as a center in accordance with the modulation signal M. The phase difference in this case is the above described instantaneous phase error.
The magni-tude of this instantaneous phase error and hence the range designated by the thick line in Figs. 6A and 6B is proportional to the magnitude of the maximum modulation index o~ the PLL circuit 20 operating as a modulator. When the voltage of the modulation signal M is raised, the range of the thick line will increase. In other words, when the modulation signal M is applied to the adder 60 in the PLL circuit 20, the phase difference increases by the amount of the applied modulation signal M and hence it seems as if the phase-unlocked state took place.
Assume that the maximum modulation index of the PLL circuit 20 operating as a modulator is considerably large, the modulator operates in the range of the thick line in Fig. 6A (e.g., within lock-in range limit) and the reference voltage Vref of the level discriminator 40 is set to the value designated by a broken line in Fig. 6B by considering a certain safety factor, then the phase difference of the two inputs a and b to the first and second phase comparators 21 and 30 reaches to the ends (both ends) of the range designated by the thick line at the timing when the instantaneous level of the modulation ~:~7~
signal M becomes maximum. As a result, it is so judged that the PLL circuit 20 temporarily becomes in phase-unlocked state even though it operates normally as a phase modula-tor. In order to avoid such misjudge, it might be thought of to further raise the reference voltage Vref of the level discriminator 40. However, if the reference voltage Vref is excessively raised, there occurs a danger of a misjudge in which actual phase-unlocked state, that is, true fre-quency offset exceeding lock-in a phase-unlocked s~ate not caused by modulation, fails to be detected. Another met'nod is also thought of as another remedy in which the -time con-stant of the integrator 32 is set to sufficiently large compared with the period of the modulation signal M. How-ever, in such a method, it has such a disadvantage that it takes a long time to detect the phase-unlocked state.
Accordingly, the present invention provides a phase modulator which can elimina-te the aforementioned draw-backs and disadvantages of the conventional phase modulators and which performs a stable phase modulating operation by effectively detecting whether or not the PLL circuit opera-tes in phase-locked state under any condition of a modula-tion signal and the PLL circuit.
When two signals to be applied to a phase ~7~3~;
comparator are frequency-divided by N, the gradient of the integrated output of the phase comparator becomes l/N. In other words, when these frequency-divided signals are phase-modulated in -the same degree as in a case in which signals are not frequency-divided, the variation in the output voltage of the phase comparator (the integrated output) becomes remarkably lower in the case of frequency-divided signals than that in case of no frequency division. This invention has taken notice of this point and according to this invention two signals to be applied to the second phase comparator for monitoring the phase-unlocked state of the PLL
circuit are frequency-divided. In this manner, the degree of the variation in the output voltage of the phase comparator due to the phase modulation viewed from the level discriminator becomes substantially low, thereby effectively and accurately discriminating in large margin whether or not it is the variation based on the phase-unlocked state even if this is monitored with the reference voltage Vref as in the conventional phase modulator. The delay of the discriminating operation due to the frequency division becomes N times, but it is small enough to be ignored as compared with the above described method of increasing the time constant of the integrator compared with the period of the ~71~346 modulation signal.
According to the phase modulator of this invention, it can effectively and rapidly discriminate in large margin whether or not the PLL circuit is in phase-locked state and hence whether or not the PLL circuit normally performs a phase modulating operation, and can, therefore, perform stable and highly reliable phase modulation. Further, the output of the level discriminator can be used as a signal for driving a suitable indicator or a signal for interrupting the output of the phase modulator. When this phase modulator is applied for a modulation circuit of an angular modulation transmitter, it can provide great effects and advantages.
Thus the present invention provides a phase modula-tor with phase-unlocked state detecting function comprising:
a reference oscillator for oscillating a signal of a predeter-mined frequency; a PLL circuit having a first phase compara-tor, a low-pass filter and a voltage controlled oscillator;
modulating means for applying a modulation signal to the con-trol loop of said PLL circuit; first and second frequencydividers for respectively frequency-dividing the outputs.of said reference oscillator and said voltage controlled oscilla-tor applied to said first comparator; a second phase compara-tor receiving the outputs of said first and second frequency ~5 dividers for comparing the phases of the outputs of said first and second frequency dividers to produce a signal corresponding to the phase difference therebetween; and a discriminator for comparing the output level of said second phase comparator with a present level to discriminate whether or not said PLI. circuit is in phase-locked state.
~ ~ 7 ~ 3 Referring once more to the drawings, Fig. 7 shows one preferred embodiment of a phase modulator according to the present invention, wherein elements which are the same as those in Fig. 1 are referred -to as the same reference numerals and symbols, and reference numerals 71 and 72 designate frequency dividers which hase the same frequency dividing ratio. The frequency divider 71 is for frequency-dividing -the output b of a reference oscillator 10 to supply the frequency-divided output into an EX-OR circuit 31. The frequency divider 72 is for frequency-dividing the output a of a ~7CO 23 to supply the frequency-divided output into an EX-OR
circuit 31. In this embodiment1 the RS flip-flop 211 and the inverter 212 shown in Fig. 4 are used in a first phase comparator 21.
10The operation of the circuit thus constructed will now be described with reference to ~igs. 8 and 9. Fig. 8 is a timechart illustrating the operations of various points of the phase modulator in Fig. 7 in which T flip-flops whose frequency dividing ratio is 15"2" are used for the frequency dividers 71 and 72.
This timechart shows the case that the phase difference between the output b of the reference oscillator 10 and the output a of the VCO 23 is zero.
Reference symbols f, f' and g, g' in Fig. 8 indicate the outputs of the frequency dividers 71 and 72, but it is undefinite whether the outputs of the frequency dividers 71 and 72 become either ones, that is, f or f', g or g'. This depends on an initial state of the T flip-flops. Therefore, when the outputs of the frequency dividers 71 and 72 become f and g, the output of the integrator 32 becomes the low level as designated by h, and when the outputs of the 3~
frequency dividers 71 and 72 become f and g', the output of the integrator 32 becomes a high level as designated by h'.
According to this embodiment, the output characteristic of ~he first phase comparator 21 becomes similar to the conventional one (Refer to Fig. 6A.) as shown in Fig. 9A , while the output characteristic of the second phase comparator 30 becomes a line as shown in Fig. 9B having a gradient of 1/2 of the conventional characteristic (Refer to Fîg. 6X), even though the characteristic of the integrator 32 itself is not varied at all (The output characteristic of the second phase comparator 30 may become as shown in broken lines in Fig. 9b according to the initial value of the T flip-flops).
In other words, this is the characteristic which is obtained by inserting the frequency dividers 71 and 72 whose frequency dividing ratio is "2", and since the period of time of the signals inputted to the second phase comparator 30 become twice, the phase difference of twice of the conventional one is required to vary the duty cycle of the output of the EX-OR circuit 31 from 0% to 100% or from 100% to 0%.
When the range in which the phase difference between the two inputs a and b of the first phase comparator 21 of the PLL circuit 20 operated as a phase modulator varies is the same as the range shown ~ 8 3~ ~
by the thick line in Fig. 6A, the output voltage of the integrator 32 varies in small amount since the gradient in Fig. 9B is smaller. In other words, by frequency-dividing with during ratio being N the variation range of the output of the integrator 32 (the voltage range of the thick line) becomes l/N of that in the conventional PLL circuit. TherPfore, the reference voltage Vref of the level discriminator 40 can be set out of the frequency difference varying range varying due to the modulation. Since the initial states of the frequency dividers 71 and 72 are unfixed, the reference voltage V'ref is necessary as shown in Fig. 9B to perform discrimination in the case where the characteristic is designated by broken lines in Fig. 9B. When both the frequency dividers 71 and 72 are simultaneously reset, the reference voltage V'ref becomes unnecessary.
In Fig. 7, reference numeral 80 designates a gate circuit, 90 a transmitter, and 100 an indicator, which are employed in connection with the phase-unlocked detection signal outputted from the level discriminator 40. More particularly, the gate circuit 80 is operated to interrupt the output of a phase modulator when the phase-unlocked detection signal is applied thereto, thereby inhibiting the transmission of an abnormal signal from the ~ ~ 7 ~ 3 ~ ~
transmitter 90 due to the phase-unlocked state, and the indicator 100 indicates the state of the PLL
circuit 20 based on the phase-unlocked detection signal. The detection signal may be utilized in either one, or may also be used in ano-ther use such as the direct control of the VCO 23.
In the embodiment shown in Fig. 7, the adder 60 used as means for applying the modulation signal M is connected to the output side of the first phase comparator 21, but the equivalent function can also be obtained by connecting the adder 60 to the output side of the loop filter 22.
The frequency dividing ratio of the frequency dividers 71 and 72 may not always be equal to each other so long as equivalent logic can be obtained by the circuits provided before and after these dividers.
In the embodiment shown in Fig. 7, the second phase comparator 30 consists of the E~-OR circuit 31 and the integrator 32, but however an equivalent effect may be obtained if it consists of a so-called analog type phase comparator (e.g., a switching type phase detector, a double balanced type phase comparator, etc.) and an integrator.
In an actual PLL circuit, it is frequently constructed that the output of the VCO 23 is further, as shown in Fig 10 or 11, frequency-divided by a '~ ~ 7 ~ 3 ~ ~
frequency divider 25 through a buffer amplifier 24 or is mixed by a mixer 26 with an OFFSET signal having a predetermined frequency different from thP frequency of the output of the VCO 23, is thereafter frequency-divided by a freqllency divider 27 and is then applied to the first phase comparator 21. In such a case, the frequency divider 72 is, as shown in the same Figure, constructed to receive the outpu~ of the frequency divider 25 or 27. In Fig. 11, the above-described OFFSET signal is outputted from a suitable reference oscillator (not shown).
Claims (9)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A phase modulator with phase-unlocked state detecting function comprising:
a reference oscillator for oscillating a signal of a predetermined frequency;
a PLL circuit having a first phase comparator, a low-pass filter and a voltage controlled oscillator;
modulating means for applying a modulation signal to the control loop of said PLL circuit;
first and second frequency dividers for respectively frequency-dividing the outputs of said reference oscillator and said voltage controlled oscillator applied to said first comparator;
a second phase comparator receiving the outputs of said first and second frequency dividers for comparing the phases of the outputs of said first and second frequency dividers to produce a signal corresponding to the phase difference therebetween;
and a discriminator for comparing the output level of said second phase comparator with a preset level to discriminate whether or not said PLL circuit is in phase-locked state.
a reference oscillator for oscillating a signal of a predetermined frequency;
a PLL circuit having a first phase comparator, a low-pass filter and a voltage controlled oscillator;
modulating means for applying a modulation signal to the control loop of said PLL circuit;
first and second frequency dividers for respectively frequency-dividing the outputs of said reference oscillator and said voltage controlled oscillator applied to said first comparator;
a second phase comparator receiving the outputs of said first and second frequency dividers for comparing the phases of the outputs of said first and second frequency dividers to produce a signal corresponding to the phase difference therebetween;
and a discriminator for comparing the output level of said second phase comparator with a preset level to discriminate whether or not said PLL circuit is in phase-locked state.
2. A phase modulator as claimed in claim 1, in which said modulating means is connected to the output side of said first phase comparator.
3. A phase modulator as claimed in claim 1, in which said modulating means is connected to the output side of said low-pass filter.
4. A phase modulator as claimed in claim 1, in which said first and second frequency dividers respectively have the same frequency dividing ratio.
5. A phase modulator as claimed in claim 1, in which said second phase comparator comprises an exclusive OR circuit and an integrator for integrating the output of said exclusive OR circuit.
6. A phase modulator as claimed in claim 1, in which the output of said voltage controlled oscillator is applied to said first phase comparator and said second frequency dividers, and is applied to a transmitter by way of a gate circuit opening or closing based on the output of said discriminator.
7. A phase modulator as claimed in claim 1, in which an indicator is driven based on the output of said discriminator.
8. A phase modulator as claimed in claim 1, wherein said PLL circuit further comprises a buffer amplifier and a third frequency divider, the output of said voltage controlled oscillator in said PLL
circuit is applied to said first phase comparator through said buffer amplifier and said third frequency divider, and the output of said third frequency divider is applied to said second frequency divider.
circuit is applied to said first phase comparator through said buffer amplifier and said third frequency divider, and the output of said third frequency divider is applied to said second frequency divider.
9. A phase modulator as claimed in claim 1, wherein said PLL circuit further comprises a mixer and a fourth frequency divider, the output of said voltage controlled oscillator in said PLL circuit is mixed by said mixer with an OFFSET signal having a predetermined frequency different from the oscillation frequency of said voltage controlled oscillator, is then applied to said first phase comparator through said fourth frequency divider, and the output of said fourth frequency divider is appled to said second frequency divider.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56134250A JPS5838035A (en) | 1981-08-28 | 1981-08-28 | Detection circuit for out-of-lock |
| JP134250/1981 | 1981-08-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1178346A true CA1178346A (en) | 1984-11-20 |
Family
ID=15123899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000409992A Expired CA1178346A (en) | 1981-08-28 | 1982-08-24 | Phase modulator with phase-unlocked state detecting function |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS5838035A (en) |
| CA (1) | CA1178346A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4787097A (en) * | 1987-02-11 | 1988-11-22 | International Business Machines Corporation | NRZ phase-locked loop circuit with associated monitor and recovery circuitry |
| EP0735680A1 (en) * | 1995-03-31 | 1996-10-02 | Texas Instruments Deutschland Gmbh | 2-Wire bus digital signal transmission receiver circuit |
| KR100382328B1 (en) | 1997-01-23 | 2003-12-18 | 산요 덴키 가부시키가이샤 | Pll circuit and phase lock detecting circuit |
-
1981
- 1981-08-28 JP JP56134250A patent/JPS5838035A/en active Pending
-
1982
- 1982-08-24 CA CA000409992A patent/CA1178346A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5838035A (en) | 1983-03-05 |
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