CA1154835A - High k plzt ceramic capacitor and method for making - Google Patents

High k plzt ceramic capacitor and method for making

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Publication number
CA1154835A
CA1154835A CA000380989A CA380989A CA1154835A CA 1154835 A CA1154835 A CA 1154835A CA 000380989 A CA000380989 A CA 000380989A CA 380989 A CA380989 A CA 380989A CA 1154835 A CA1154835 A CA 1154835A
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CA
Canada
Prior art keywords
lead
bismuth
compound
lanthanum
silver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000380989A
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French (fr)
Inventor
Galeb H. Maher
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Sprague Electric Co
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Sprague Electric Co
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Filing date
Publication date
Priority to US06/178,669 priority Critical patent/US4324750A/en
Application filed by Sprague Electric Co filed Critical Sprague Electric Co
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Publication of CA1154835A publication Critical patent/CA1154835A/en
Priority to US178,669 priority
Expired legal-status Critical Current

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Abstract

HI&H K PLZT CERAMIC CAPACITOR AND METHOD FOR MAKING

Abstract of the Disclosure A powder blend of precursors of a single anti-ferroelectric compound of lead-barium-lanthanum-zirconate titanate doped with silver, includes at least 0.7 mole percent bismuth permitting a near-full reaction to be achieved at calcining at 1000°C to 1130°C. A body formed of the pulverized calcined material is then sintered in a closed container at 1100°C. The body is then annealed in open atmosphere at 950°C so as to drive out the free PbO remaining in the body, thereby providing an excellent dielectric having an unusual combination of high K and low TCC.

Description

HIGH K PLZT CERAMIC CAPACITOR AND METHOD FOR MAKING
The present invention relates to a method for making a lead-lanthanum-zirconate-titanate (PLZT) ceramic capacitor, and more particularly to a method for making such a capacitor which removes any free lead oxide, and to the capacitor made thereby.
A silver doped PLZT capacitor dielectric is described in my patent CA 1,028,399 issued March 21, 1978. The method disclosed therein includes calcining -the PLZT start materials at a peak temperature of 1232C, adding silver and glass, forming a capacitor body and sintering at from 1038 to 1121G.
In my subsequent patent US 4,135,224 is.s.ued January 16, 1979, bismuth trioxide is added to the cal-cined PLZT material to reduce the required sintering temperature and to accelerate the incorporation of sil-ver in the PLZT grains at sintering. Full densification was achieved at a peak sintering temperature as low as llSO~G with no glass having been added.
In my later patent CA 1,096,604 issued March 3, 1981 barium was added to the start materials. so as to achieve a higher dielectric constant. A ferroelectric dielectric w.as defined therein as being composed of a lead zirconate and a barium titanate wherein 0.07 to 0.16 molar parts of the lead are replaced by lanthanum, wherein from 0.10 to 0.40 molar par~s of the zirconate are replaced by titanate, and wherein the atomic ratio of bariumi to lead is from 0.015 to 0.39.

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- 2 -In the present invention, the term "anti-ferroelectric compound of lead-barium~lanthanum-zirco-nate-tîtanate" is to be interpreted as including only those compounds as defined and limited above. As in my CA 1,096,604 patent, the dielectric compounds oE this invention are preferably doped with silver and bismuth.
A feature o~ the present invention is a pro-cess for making an antiferroelectric dielectric having a higher dielectric constant (K) without sacrifice in the stability of K over a broad operating temperature range. Another feature is the provisiorL of a PLZT
ceramic capacitor having no free lead oxide.
In accordance with this invention a PLZT
ceramic capacitor is produced by including bismuth in the start materials, calcining at a low temperature, sintering a capacitor body in a closed container, and then annealing the body to remove free lead oxide.
In a drawing which illustrates embodiments of the invention, Figure l shows in side sectional view a mono-lithic ceramic capacitor, Figure 2 shows in side sectional view a cera-mic chip capacitor, and Figure 3 is a graph showing the change in capacitance as a function of operating temperature for two capacitors.
In general, the ceramic capacitor of this inven-tion is made by forming a powder blend of precursors of a single antiferroelectric compound of lead-barium~lantha-num-zirconate-titanate doped with silver and bismuth, calcining this blend at less than 1130C, pulverizing the calcined compound, forming a body of the pulverized compound, and sintering the body in a clc1sed container.
The sintered body is subsequently annealed at less than 1000C to drive out the free lead oxide from the body.
At least two spaced electrodes are either applied to opposite faces of the sintered body or may be buried within the body prior to sintering.

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It has been found that the addition of small amounts- of bismuth, e.g. 1/2 weight percent Bi203, to the PLZT start materials permits the use of lower cal-cine temperatures that will result in full reaction and a solid solution of those start materials. Using bis-muth in this way also advantageously expedites the incor-poration of a silver dopant into the calcined PLZT com-pound. In the present invention the start PLZT materials need not be lead rich. In fact, they may be, and are preferably, added in stoichiometric amounts that conform to an overall large/small ca~ion balance in the start materials. Bismuth and silver atoms enter this system as large cations.
At least one mechanism by which charge balance is attained in the grains at calcining involves the creation of lead vacancies in the crystal lattice. Accor-dingly, each two of the large cation donors La~3 occupy the sites of two pb+2 cations and a third pb~2 is removed leaving one lead vacancy. Thus one lead vacancy exists in the crystal for each two lanthanum atoms incorporated, and this lead shows up as a free lead oxide in the cal-cined material. This kind of mechanism is described in the paper by K.H.Hardtl and D.Hennings entitled "Distri-bution of A-Site and B-Site Vacancies in (Pb,La)(Ti,Zr)03"
Ceramics, Vol. 55, No. 5, pp 230 to 231.
The incorporation of bismuth has the same lead displacement and lead vacancy result. Each silver ~Ag~l) cation charge balances a lanthanum (La+3) or (Bi+3) cation on a one to one basis and thus tends to reduce the expul-sion of lead from the grains. The net free lead oxide is molten at the calcining temperatures and in effect reduces the temperature of calcining at which a full reaction of the start materials occurs to form stoichiometric PLZT
grains. From weight loss measurements it was ascertained that the free lead oxide in the calcined materials o~
this invention amounts to as much as 1.5 ~eight percent but is typically from 0.2 to 0.5 weight percent. Mate-rials that were calcined at the conventionally higher , , ~,; -. .. : : , : . : : .. : :~

temperatures with no bismuth include essentially nofree lead oxide.
The presence of free lead oxide aids comple-tion of the reaction at calcining so that lower cal-cining temperatures may be used. Lower calcining tempe-ratures are preferred, because of conventional calcine temperatures the free lead oxide solidifies and bonds the calcined cake so as to make it refractory and diffi-cult to crush and pulv~rize. At calcining temperatures lU of about 1130C and lower, this problem is greatly ame-liorated. At calcine temperatures lower than about 1000C
it becomes impossible to achieve the desired full reaction of the start materials so that calcining is restricted to the temperature range of from 1~00~C to 1130C.
In my previously noted patent C~ 1,096,604 the addition of minor amounts of barium titanate to an anti-ferroelectric PLZT dielectric provided higher dielectric constants with only small changes in the temperature coefficient o~ capacitance (TCC) and the voltage coeffi-cient of capacitance. In comparison with capacitors of that patent, capacitors made by the present method, wherein bismuth is included in the start materials prior to calcining, are capable of providing substantially greater dielectric constants (K) for a given flatness in the K versus operating temperature characteristics. For example a capacitor body of this invention has a K of 2000 that varies with respect to room temperature no more than 15% from -55C to 125~C (a so-called X7R charac-teristic, as designated by the Electronic Industries Association). Heretofore, PLZT bodies exhibiting an X7R
characteristic have had a K of no more than 1700.
However, a special difficulty presented itself as a result of the low temperature calcining step. Minute amounts of free lead oxide that do not react at the low temperature calcining step remain as a small second phase between the grains of the capacitor dielec~ric to cause a greatly reduced life characteristic. This is attribu-ted to the fact that PbO tends to be semiconducting.

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It has been ~ound that the free lead oxide may be removed by annealing the sintered body in an open atmosphere. This additional step provides capacitors having long life times that are commensurate with or better than those obtained by the old method wherein calcining was accomplished at a higher temperature. The old higher temperature calcining drove out free lead oxide at the calcining step. In the method of this inven~
tion, the dielectric constant increases about 5% as a result of annealing, due to elimination to the atmosphere of the lead oxide from the grain boundaries. Based upon weight loss measurements at annealing, there has been observed a loss of from 0.125 to 1.5 weight percent lead oxide. Thu5 the combination in the method of this inven-tion o adding bismuth to the PLZT start materials, calci-ning at a low temperature, and a post anneal step provides capacitors having an exceptionally useful combination of properties.
The monolithic ceramic capacitor of Figure 1 has a ceramic body 10. Film electrodes 11 are interleaved with film electrodes 12; all electrodes being buried in the body 10. Conductive termination coatings 13 and 14 contact electrodes 11 and 12, respectively. Lead wires 15 and 16 are attached by solder bonds 17 and 18 to ter-minations 13 and 14, respectively. Al-though the capacitor of Figure 1 has three active ceramic dielectric layers between adjacent and oppositely polarized electrodes, experimental monolithic capacitors to be described herein have more active dielectric layers.
T~e chip capacitor of Figure 2 has a ceramic body 20 and two film electrodes 21 and 22 on the opposite major surfaces of the body 20, respectively. Chip capac-i~ors may have a rectangular or circular shape, and for high voltage uses may have a thickness equaling or exceed-~5 ing the largest dimension of a major surface.
A brief description of the steps employed for making experimental capacitors is as follows:

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,.., A powder blend was prepared consisting by weight of 55.0 PbO, 5.70 La2~3, 3.40 BaO, 0.68 Ag(metal~, 1.47 Bi203, 2~.7 ZrO and 9.0 TiO2. The blend was ball milled and precalcined at 790C for 5 hours. The resulting cake was then granulated mechanically and calcined in a closed high purity aluminum sagger at 1090C for 3 hours. The calcined ca~e was crushed and jet pulverized to form a fine ceramic powder.
X-ray diffraction analysis of this material showed lattice parameters corresponding to a single PLZ,T
compound and also corresponding to ~-ray Lattice para-meters exhibited by a dense sintered body subsequently formed of this material. In a series of experiments wherein the calcinin~ temperature was varied from 1010C
to 1120C, the same result was obtained indicating that for this low range of calcining temperatures the start materials are substantially fully reacted at calcining and the crystalline structure of the sintered bod~ (sin-tering at 1100C) was essentially unchanged from that of the calcined cake.
The above-noted start materials correspond to a compound (Pbo 78LaO llBaO 07AgO.02Bio.o2)(zro.64Tio 36)o3 which compound is formed with lead vacancies at calcining and is structurally that of the grains in the subsequently sintered dielectric. Because of the existence of lead vacancies, there is slightly less lead ir~ the grains than indicated by this formula.
At this point, the calcined ancL pulverized pow-der may or may not be mixed with a sintexing aid such as - 30 a glass or other low melting sintering flux. Also small amounts of materials such as TiO2 or Nb2C~5 may be added to the calcined powder to react with and tie up the free lead oxide. However, even with such addi.~ives, some free lead remains and annealing is found necessary to insure good life test performance. Such additives also produce an integranular phase and reduce the dielectric constant.

The calcined powder or powder mixture was stir-red with an organic binder medium of essentially turpen-tine, 6% pine oil and 5% lecithin to produce a dispersion or slurry containing about 70% by weight of solids. This slurry was ball milled for about 10 hours.
Eight groups of experimental monolithic capaci-tors were produced by applying successive coatings of the above-noted milled slurry to a substrate, drying each la-yer in turn, and screen printing an electroding paste of 70% silver and 30% palladium particles onto each except the last of the dried layers of the dielectric material.
Each layer is about 1 mil (0.025 mm) thick.
This assembly of dried layers with seven inter-leaved films of electroding paste was then diced into a multiplicity of square bodies and baked at 870C to re-move the organic material. ~le electrodes were so arran-ged that, after dicing, each body had alternate electrodes extending to one cut end of body 10, and the other elec-trodes extending to the opposite cut end of body 10 as illustrated in Figure 1. The body was subsequently buried in lead zirconate powder and sintered in a closed alumina crucible at a peak temperature of 1100C for 2.5 hours.
Closed container sintering is preferred with the container substantially filled with the bodies to be sintered, be-cause this results in maintaining a positive atmosphere of lead oxide leading to the retention during sintering of the lead oxide that acts by itself as a sintering aid so that densification is achieved at this low sintering temperature.
Removal of free lead oxide was then accomplished by annealing the experimetnal sintered bodies of examples 1, 3, 5, 7 and 8, in an open atmosphere at 950C for 1 hour. The bodies in examples 2, 4 and 6 were not annealed.
~ silver paste was applied to the opposite ends of the sintered body and the body was heated to about 760C for5 minutes to form cured terminals, e.g. 13 and 14 in Fig-ure 1. Lead wires 15 and 16 were then soldered to each of the two silvered terminals 13 and 14.

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Chip capacitors as illustrated in Figure 2 are made by casting the above-noted slurry on a glass plate to a thickness of about 0.020 inch (0.051 cm~, drying the ca~t layer, rPmoving the dried layer and cutting it into square pieces (e.g. 20) each having an area of 0.25 in2 (1.61 cm2). The binder is then removed by baking, and the chips are then sintered in a closed crucible. A
silver paste is applied over the two opposite major sur-faces of the mature chips and the chips heated to 790C
for 1/2 hour to cure the electrodes 21 and 22 illustrated in Figure 2.
The experimental variables for the eight lots of monolithic capacitors are indicated in Tables I and II.
Table I
15 Expt. Additive Annealed Weight K D.F.
Number to Calcined Loss at 25C (%) Powder (wt%) (wt/o) 1 0 Yes n.d. 2100 0.05 2 0.5TiO2 No - 2100 0.20
3 0.5TiO2 Yes n.d. 2200 0.10
4 l.OTiO2 No - 1750 0.45 l.OTiO2 Yes 0.2 1900 0.40 6 1.0 Glass No - 1750 0.30 7 1.0 Glass Yes 0.3 1830 0.25 8 0.5 Glass Yes 0.5 2000 0.20 Table II
Expt. TCC Life Test Results Number (%~ rel. 25C) (No. failures/No. tested/
-55C ~125C Time tested) 1 -7.5 -14.0 0/12/100 hr.
2 -7.5 -12.0 12/12/1 hr.
3 -7.5 -12.0 0/12/100 hr.
4 -5.0 -10.0 6/10/48 hr.
-5.0 -10.0 2/14/48 hr.
6 -7.0 - 5.0 8/8f24 hr.
7 -7.0 - 5.0 0/12/500 hr.
8 -7.0 -11.0 0/12/200 hr.

.. ~ , ~15~5 The results of accelerated life tests to which a number of the experimental capacitors of each group were subjected are also presented in Tables I and II. I,ife test conditions consisted in applylng 200 volts to each capacitor held at a temperature of 125C. Failure of a capacitor was defined as the event wherein the normal-lized insulation resistance of a capacitor fell below 30 ohm-farads. By modern standards, high quality ceramic capacitors will survive at least 100 hours under these conditions before failure.
The actual time under test is indicated in Table II. The unannealed capacitors of groups 2, 4 and 6 exhibited a high rate of failure, because small amounts of free lead oxide remain in the sintered body. The ca-pacitors of groups 4 and 5, did not completely densify andwere slightly porous because of the relatively large addi-tive amount of titania, which was responsible for the low insulation resîstance and poor lïfe test performance.
There were no failures of annealed capacitors of experi-mental groups l, 3, 7 and 8, the open atmosphere anneal-ing step having driven out the lead oxide.
All capacitors exhibited a temperature coeffi-cient of capacitance (TCC) that conforms to the above-noted standard X7R characteristic, namely, with respect to room temperature capaci-tance, the capacitance variation remained within ~ 15% over the operating temperature range of -55C to 125C. Representative of capacitors of this invention, the TCC curves 31 and 36 corresponding to capacitor groups 1 and 6, respectively, are shown in Figure 3.

:

Claims (10)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
1. A method for making a PLZT ceramic capacitor comprising:
(a) forming a powder blend consisting essentially of precursors of a single antiferroelectric compound of lead-barium-lanthanum-zirconate-titanate doped with silver and bismuth;
(b) calcining said blend in a closed container at a peak temperature of less than 1130°C to form said anti-ferroelectric compound;
(c) pulverizing said calcined compound;
(d) forming a body of said pulverized compound;
(e) sintering said body in a closed container;
(f) annealing said sintered body in an open atmos-phere at less than 1000°C to drive out the free lead oxide residing in said body; and (g) forming two spaced electrodes in contact with said body.
2. The method of claim 1 wherein said forming a powder blend includes proportioning said precursors to provide about equal molar quantities of large cations of lead, barium, lanthanum, silver and bismuth, and small cations of titanium and zirconium.
3. The method of claim 1 wherein said annealing is accomplished at about 950°C.
4. The method of claim 1 wherein said powder blend consists of PbO, BaO, La2O3, ZrO2, TiO2, Ag and Bi2O3.
5. The method of claim 4 wherein the positive ions of said oxides are in the approximate relative atomic amounts of 0.78 Pb, 0.11 La, 0.07 Ba, 0.02 Ag, 0.02 Bi, 0.64 Zr and 0.36 Ti.
6. The method of claim 1 wherein said peak calci-ning temperature is greater than 1000°C.
7. The method of claim 1 wherein said bismuth in said start materials is at least 0.7 mole percent of the large cations consisting of said lead, barium, bismuth, lanthanum and silver.
8. The method of claim 1 wherein said sintering is accomplished at a peak temperature of from 1050°C to 1120°C.
9. The method of claim 1 wherein said lanthanum is about 11 mole percent of the large cations in said powder blend.
10. A ceramic capacitor comprising a ceramic dielec-tric body and two spaced electrodes in contact with said body, said body consisting of antiferroelectric crystal-line grains composed of the single compound structurally represented by the formula (Pb0.78La0.11Ba0.07Ag0.02Bi0.02)(Zr0.64Ti0.36)O3 said body exhibiting a dielectric constant greater than 1800 that varies no more than ? 15 percent from the value at 25°C over the operating temperature range of from -55°C
to 125°C.
CA000380989A 1979-01-12 1981-07-02 High k plzt ceramic capacitor and method for making Expired CA1154835A (en)

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US06/178,669 US4324750A (en) 1979-01-12 1980-08-18 Method for making high K PLZT ceramic capacitor
US178,669 1988-04-07

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0465652U (en) * 1990-10-12 1992-06-08
DE102012111023A1 (en) * 2012-11-15 2014-05-15 Epcos Ag Multilayer capacitor and method for producing a multilayer capacitor

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4219866A (en) * 1979-01-12 1980-08-26 Sprague Electric Company Ceramic capacitor having a dielectric of (Pb,La) (Zr,Ti)O3 and BaTiO3

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JPH027166B2 (en) 1990-02-15
JPS5762521A (en) 1982-04-15
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