CA1151743A - Serial data bus communication system - Google Patents

Abstract

Abstract of the Disclosure A node device for use in a digital data processing and communications system of the type utilizing a bus organization for facilitating the interconnection of a large plurality of digital data processing devices (user devices) in which redundant cables are employed.
The node devices are interposed between the user devices and the redundant cables to permit automatic reconfiguration of the interconnection of the user devices in the event of malfunctioning or severing of one or more of the cable sets within a minimum period of time. The node devices provide the user devices with the structure needed to detect and diagnose system problems and to effect recovery procedures. In accordance with the invention, one of the plurality of nodes functions as the Bus Controller and by sampling the remaining nodes in the system, it determines the priority with which user devices may transmit or receive data over the bus. Each of the nodes employed is substantially identical and any one may be selected to function as the Bus Controller. Each includes a Microprogrammed Controller and necessary firmware to permit the controller to function in conjunction with special purpose hardware including a Programmable Logic Array (PLA) configured to perform a pre-processing function on control line inputs so that poll/response traffic on the active cables can continue with a minimum of delay.

Description

~ ~ 5 ~ ~t~ 3 BACKGROUND OF THE INVLiNTION

This invention relates generally to a serial data bus for interconnecting large numbers of computers or other digiLal clata processing equipment in a local area and more specifically to the design ,.~

1 ~5~743 of the nodes used in such a system for coupling the user devices to the serial data bus whereby the throughput of the system is enhanced.
DISCUSSION OF THE PRIOR ART
The interconnection of large numbers of computers in a loca~
area is a need which is quite different from computer interconnection 5 requirements perceived in the past. Prior art approaches at local processing networks involved the so-called star configurations wherein peripheral equipments and computers were connected directly to a computer having centralized control over the resources comprising the network. It has been found that the rapid increase in the use of digital 10 processing in all areas of a network in the form of microcomputers embedded in a process, mini computers for specialized front-end processing and large computers for large-scale operations has created a need for a flexible and extensible method of interconnecting processing elements. Interconnecting large numbers of processing elements for 1 complete intercommunication can be accomplished, of course, by direct transmissions to all elements connécted to a data bus or by indirect transmissions relayed by point-to-point interconnections. It is found, however, that thé use of only point-to-point connections to establish a local processing network composed of a large number of computers is 20 quite complex and cumbersome and does not easily satisfy the need for flexibility and extensibility.
The serial data bus in which the present invention finds application provides the medium for the complete interconnection of processing elements in a local processing network. The term "local" is 25 intended to mean that the user devices are physically located within a well defined area such as a building, a ship or an aircraft as distinguished from remote communication systems which may be spread over many miles.

~l1517~3 To be effective, a serial data bus network interconnection scheme should take into account the throughput requirements and bottlenecks clue to a saturated transmission system or non-uniform flow of data are to be avoided. In accordance with the present invention, the control of information flow on the serial data bus is programmable and 5 thereby allows the fitting of the bus to a specific application.
A drawbaek of prior art local processing networks and especially the interconnection scheme used therewith relates to the fact that they tended not to be particularly fault tolerant. Fault tolerance is the attribute of the local processing network to continue its operation after 10 the occurrence of faults. The system of the present invention overcomes that drawback through the judicious use of redundancy and a built-in self-monitoring capability for detecting and isolating faults. The nodal structure comprising the present invention enhances the overall fault tolerance of the serial data bus system with which they are used by 15 allowing redundant cables, isolated connections to the cables and programmable time-out interrupts for calling into play fault recovery sof tware.
Closely associated with the need for fault tolerance is the requirement that the interconnection system be able to accommoclate 2 0 incremental change without deleteriously impacting other parts of the network. Stated otherwise, the occurrence of faults represents a change in the system configuration and corrective action by way of removal of system parts from the network must be tolerated while still maintaining a continuous information flow to suit particular modes of operation or 25 system applications.

1l15~L743 The node structure of the present invention permits user programs to change the organization of information flow which is controlled through a polling operation. ~Iso, user software can be employed to inhibit specific messages from flowing to a particular user device. - 5 Another attribute of a local da-ta processing network and its interconnect scheme, especially where military and other highly critical real-time operations must continue even upon the occurrence of catastrophic events is that it exhibits survivability. For example, it is essential that the user devices be able to communicate even when one or 10 more interconnect cables is severed or when one of the system modules is destroyed. The local communication system in which the present invention finds use exhibits this property, primarily due to~the fact that redundant cables are employed which cables are physically distributed throughout the local area along different paths and because the nodes of lS
the present invention are modularly arranged and function such that any one may assurne the role of Bus Controller in the event of a catastrophi failur~ of the type indicated.
The r~ode device of the present invention which is used to interface a user device to the serial data bus ernploys a systern moni-tor to 20 control the initialization and reconfiguration and the system rnonitor function is assigned to one of the user processors with backup as required.
During initialization, the Bus Controller node and the active primary bus cables are selected, message screens are loaded into each node, and each node is checked through a built-in -test routine. During operation, the 2 5 node hardware monitors the systern for invalid formats, parity, rnissing responses/polls, and other fault indicators. On detection of a faul-t, a reconfiguration rnode is initiated through the user processor which contains the systern monitor function. For redundancy, other user processors can assume the system monitor function and perform the 30 ~S~743 reconfiguration process. Usin~ this technique, the level of reconfiguration becomes a function of the type or types of fault(s) detected which may include the following:

Switching a node to an alternate B~ls Access Module stub in the event of a failure in this transmission path;
Switching all nodes to a backup primary bus cable in the event of breakage of this cable; and Assigning the Bus Controller functions of a user/node to an alternate user/node in the event of failure including the user/node that contains the System Monitor/Bus Controller function.

To facilitate the configuration process, each node continuously monitors data on the alternate stub cables and if data is detected on a previously inactive cable, it will, under certain conditions, interpret such data as commands for initiating reconfiguration.

The preferred embodirnent being described herein permits a local data processing network to involve up to 256 separate users (computers) each being associated with a node device having a plurality of ports for connection to the primary bus cables, thereby accommodating the desired redundancy requiremerlts. That is, a plurality of primary bus cables are 20 provided for redundancy purposes and at all times, two of the plurality are designated the control cable which carries control type data words and a message cable for carrying message data. The systern is configured such that if one or the other of the active control or rnessage cables is interrupted, the user devices are automatically reconfigured to cooperate 25 with a different (previously inactive) one of the plural prirnary bus cables.
Cornmunications within t'ne data bus system are implementecl by assignirlg control of the active bus to one of the node devices, which then controls transmission of messages on the data cable. Contention between bus users is resolved by selectively polling the users and then granting bus 30 access to the highest priority user. Addressing ~vithin the data bus system uses both physical and logical addresses with each node having a manually selectable address register.
One of the nodes in the data bus system has the responsibility for bus control. Users with time-critical communication requirements are 5 polled more frequently than other non-priority users. The priority structure is controlled by user defined parameters so that it can be modified to adapt to the particular application in process.
When a particular node is polled, a response is transmitted to the Bus Controller, indicating the needs of the node as well as the current 10 status. As such, a bus malfunction can be detected within the time required for a full system polling cycle. Poll commands, responses, and other types of system commands are arranged to be transmitted on a control cable of the bus. The data cable is reserved for information messages only. The traffic on both cables is asynchronous, enabling 15 polling and queuing of user devices concurrently with information messages being t~ansmitted on the data cable.
OBJECTS
It is accordingly the principal object of the present inveotion to provide means for interconnecting a large plurality of digital data 2 0 processing devices to one another via a serial transmission data bus.
Another object of the invention is to provide an irnproved node device for coupling a digital data processor to one of a plurality of data channels.
Still another object of the invention is tc> provide a node for 25 coupling a digital data processor such as a user cornputer to a two cable system wherein one cable is arranged to carry polling/command signals and the second cable carries data messages.
A further and related object of the invention is to provide a node device for coupling a user computer to transmission cables such that 3 o concurrent polling and data transrnission can be performed so as to minimize access time.
A yet further object of the invention is to provide a node system in which message traffic on a serial bus to which the node is coupled is controlled by one of a plurality of nodes which has been designated as the 5 Bus Controller.
A still further object of the invention is to provide in a serial data bus transmission systern a plurality of node devices, any one of which can function as the Bus Controller at any given timeO
A still further object o the invention is to provide in a serial 10 data bus communication system a plurality of distributed cables, each capable of carrying serial binary data between nodes and which al!ows for switching of all nodes to a backup primary bus cable in the event of breakage of the bus cable over which data and control signals had previously been conveyed. 15 Still another object of the invention is to provide in a node device hardware and firmware whereby each node in the system can continuously monitor data on alternate stub cables such that iE data is detected on a previously inactive cable, the node may interpret such data as calling for bus reconfiguration. 2 0 Another object of the invention is to provide a node structure for a serial data bus system which includes special purpose hardware and firmware in a general purpose microprogram controller for maximizing the polling rate.
A yet still further object of the invention is to provide a node for 25 a serial data bus transrnission system ernploying a dynamic reconfiguration method whereby one of the nodes in the systern, namely, the ~us Controller node, sends commands to the remaining n~des in the system so that those rernaining nodes reconfigure automatically to a new cable. 3 0 .

Yet another object o-E the invention is to provide a node for use in a serial data bus transrnission system whereby real-time reassignment of the so-called Bus Contro~ func~ion can be attained.
A still further and related object is to provide a node design for use in a serial data bus communication system whereby real-time channel 5 change can be accomplished to facilitate recovery from faults in the transmission system.
Yet another object of the invention is to provide a hi~h speed resource allocation mechanism which achieves a maximum bus access time of less than 1/2 millisecond for up to 16 different nodes on a serial 10 data bus communication system.
These and other objects and advantages of the invention will become apparent to those skilled in the art from the following detailed description of the preferred embodiment, especially when considered in conjunction with the accompanying drawings. 15 DESCRIPTION OF THE DRAWINGS
Figure 1 is a system block diagram of a serial data bus in which the node structure of the present invention finds use;
Figures 2a through 2d, when arrangecl as shown in Figure 2, depict a block diagram of the node portion of the system shown in Figure 20 ;
Figures 3a and 3b depict by means of a block diagram the organization of the Microprogrammable Controller employed in the node;
Figure 4 illustrates by means of a logic diagram the Mapping PL~ used in the node; 25 Figures 5a and 5b, when arranged as shown in Figure 5, illustrate the logic for implementing the Tirne for Select Flag Circuitry;
Figures 6a and 6b, when arranged as shown in Figure 6, depict the control line output circuitry portion of the node;

l~LS~ 3 Figures 7a and 7b, when arranged as shown in Figure 7, depict further portion5 of the control line output circuitry;
Figure 8 illustrates by means of a logic diagram the command registers forming a portion of the Control Line Output Circuitry;
Figure 9 illustrates the circuitry for implementing the Select 5 Multiplexer/Register and Comparator portions o:E the Control Line Outpu-t Circuitry;
Figures 10a and 10b, when arranged as shown in Figure 10, depict by means of a logic diagram the Priority Poll Lists portion of the node;
Figure 11 depicts by a logic diagram the Non-priority Poll Lists; 10 Figure 12 illustrates the logic for implementing the Non-Priority Sub-cycle Control;
Figures 13a and 13b, when arranged as shown in Figure 13, illustrate the logic for implementing the Priority Poll List Control Circuitry of the node; 15 Figure 14 shows the logic for implementing the Last Poll Address ~egister and the Own Node Poll Comparator;
Figures 15a and 15b, when arranged as shown in Figure 15, depict the logic comprising a portion of the Control Line Input Circuitry;
Figure 16 depicts the logic for implementing the comparator 2 0 portion of the Control Line lnput Circuitry;
Figure 17 depicts by means of a logic diagram the Con-trol Line Input FIFO buffer employed in the Control Line Input Circuitry;
Figures 18a and 18b, when arranged as shown in Figure 18, depict the Processor Con-trol Line Input Register portion o:E the Control Line 2 5 Input Circuitry;
Figures 19a and 19b, when arranged as shown in Figure 19, depic-t the logic for implementing the Control Line Sequencer PLA;
Figure 20 illustrates further logic circui try ùsed in the implementation of the Control Line Sequencer PLA; 30 1~S~43 Figure 21 shows the implementation of the Dispatch Queue Input Multiplexer portion of the Control Line Input Queue;
Figures 22a and 22b, when arranged as shown in Figure 22, depict the Priority and Non-Priority Dispatch FIFO buffers comprising a portion of the Control Line Input Queue; 5 Figure 23 depicts the logic for implementing the Destination Bus Holding Register and the Ac~ivity Mask Register portions of the node;
Figure 24 depicts by means of a block diagram the Control Line Decoder portion of the node;
Figure 25 illustrates by means of a block diagram the Control ~ o Line Encoder portion of the node;
Figures 26, 27 and 28 together illustrate the control circuitry for the Control Line Encoder/Decoder apparatus of Figures 24 and 25;
Figures 29 and 30, together illustrate by a logic diagram the stub vectoring logic portion of the node; 15 Figure 31 illustrates the Control Line Activity Detector Circuitry of the node;
Figure 32 is a flow diagram illustrating the bus arbitration methodology;
Figures 33a and 33b, when arranged as shown in Figure 33, 2 0 comprises a firmware flow diagram depicting the bus arbitration methodology; and Figure 34 is a further flow diagram helpful in understanding the bus reconfiguration process.
DESCRIPTION OF THE PREFERRED EMBODIM~NT 25 Before explaining the overall construction and mode of operation of the node devices c:-mprising the present invention, it is deemed expedient to explain in summary fashion the overall system configuration in which the node devices find application. In this regard, reference is made to the general block diagram of Figure I which depicts graphically 30 1~7~3 the serial data bus architecture. User devices such as the user computers 40, 42 and 44 are but three of a large plurality of user devices which are adapted to communicate, one with the other, on the bus system. In a system actually constructed, up to 256 user devices were allowed for.
Associated with each user device is a so-called node, node 34 bein8 5 associated with user computer 40, node 36 with user compu~er 42 and node 38 with user computer 44. The serial data bus system functions to permit two-way, point-to-point communication between any pair of user computers or, alternatively, to permit any one user computer to broadcast simultaneously to all other users in the system. Interuser communication 10 is accomplished via the main bus channels, here shown as including six sùch channels labeled 46-56, respectively. By utiiizing plural channels, the desired redundancy is provided in that any two of the six are sufficient ta support communication between all user devices.
Each of the channels 46-56 may comprise a triaxial cable 15 capable of supporting Manchester encoded serial data at a 10 megabit per second rate. The six cables 46-56 will hereinafter be referred to as the primary bus system.
As is illustrated in the drawing of Figure 1, each node 34, 36, etc., communicates with the primary bus system via stub cables 58, 60 20 and 62. The stub cables associated with each node correspond in number to the number of main bus channels employed in the data bus system. The interconnection between a node stub cable and one of the main bus channels is via a so-called Bus Access Module or BAM. Those desiring an explanation of the construction and operation of the BAM devices used 25 herein are referred to a paper entitled "A Triaxial ~us Transmission System" by R.O. Starkson which was published on October ?3,1979 in the IEEE Proceedin~s, 4th Conference on ~ocal Computer Networks, pp. 82-~S3~ 43 As is explained in the aforereferenced article, the BAM provides a zero length stub connection to the prirnary bus system and provides local signal regeneration to drive the stub cables. In a practical system that has been put into use, up to 64 BAM's can be accommodated on each of the primary bus cables 46, 48 . . . 56 without degrading the electrical 5 performance of the system. Further, each BAM is capable of driving up to four stub cables such that it can serve a maximum of four separate nodes. The BAM may be positioned anywhere along the length of the primary bus cables which may, for example, each be approximately 300 meters in length. The stub cables 58, 60, etc., may typically be up to 30 10 meters in length, but no limitation to this particular dimension is intended. However, it is readily understandable, then, that these typical dimensions allow a system designer considerable flexibility in choosing the physical location of the channels of the primary bus system and the associated ~us Access Modules. Maximum fault tolerance is achieyed by 15 providing a significant number of redundant communications paths which may be physically disbursed. It is to be noted, for example, that nodes 34 and 36 gain access to the primary bus cable 46 by way of the common BAM l0 while they gain access to the primary bus cable 54 via BAM's 26 and 28, respectively. 20 It is generally intended that each node 34, 36, etc., will communicate with all six of the main bus channels 46-56, although it is to be understood that some of these redundant cables can be eliminated in the interests of economy and only two cables are essential for operation.
That is to say, the serial data bus depicted schematically in Figure l 25 requires two channels to be available in the bus transmission system at any given time. One of the two channels, called the "Control Channel", is used solely for the purpose of system control a~d reconfiguration. ~us arbitration is carried out on this channel with the net result being a controlled allocation of the other channel for the purpose of sending data 30 7~3 messages. The second of the two active channels is called the "Da-ta Channel" and is reserved entirely for message traffic. This feature makes it possible for the serial data bus to sample the requirements of the nodes in the system asynchronously and in parallel with the data transfers taking place. 5 High bus performance (low access time and high message throughput) is achieved through the use of a lO megabit/second transmission rate. The two cable system, with one cable for bus polling/command signals and the second cable for data transmission also enhances the performance. It allows concurrent polling and data 10 transmission on the bus system and minimizes access time. While data is being transmitted on one cable, the queue for the next user may be established. The two cable system also facilitates recovery from casualty or system failures in that at least one active alternate cable is available for reconfiguring the system in the event of cable breakage. 15 Message traffic is controlled through a single node which performs the polling cycle. Messages are transmitted sequentially on the data cable based on a priority algorithm of the poll cycle. In this manner, positive control and status of the bus system is maintained. This attribute is essential to those operations, such as military systems, where positive 20 and timely transmission of critical messages must be guaranteed.
As was pointed out in the introductory portion of this specification~ to guarantee reliable operation, both commercial and military bus systems must strive to eliminate or at least minimize single points of failure. The use of passive rather than active taps on the 2 5 primary bus is the key to achieving this desired requirernent. In addition, alternate cables are provided as backup in case oi cable breakage or casualty. As is shown in Figure 1, it is also important, especially in military systems, that the cable system, i.e., cables 46-56, be disbursed and that stubs 58 - 62 which physically separate the primary bus from the 30 node/user be employed. In the system depicted in the block diagram of Figure l, each node 34, 36, etc. may be connected up to six primary bus cables, any two of which provide a full systém capability.
In that the bus control function is duplicated in several nodes, failure of the particular node which happens to be in command at any 5 given time, i.e., the Bus Controller, does not disable the bus. Rather, the bus control function is handed off to one of the other nodes based on a predetermined sequence In this manner, single points of failure are virtually eliminated in the overall system. The manner in which this is accompllshed will be set forth in considerably more detail hereinbelow 10 when the overall design and operation of the node, per se, is set out.
NODE CONSTRUCTION
Figures 2a through 2d, when arranged as shown in Figure 2, illustrates by means of a block diagram the basic organization and implementation of any one of the nodes 34, 36, etc., illustrated in the 15 block diagram of Figure 1. A node contains the circuitry to:
(I) support the serial data communications protocol;

(2) to communicate with the user computer; and

(3) to detect and report errors and hardware f~ilures.
The failures mentioned may be within the node itself, they may be 2 0 detected and reported from other nodes, or they may be failures or errors detected in one of the cables. Overall control of the node is accomplished by a Microprogrammable Controller which in the preferred embodiment is based upon the so-called 2900 family of integrated circuits manufactured and sold by Advanced Micro Devices, Inc. However, limi-tation to this 25 particular Microprogrammable Controller is not to be implied. As will be explained in still greater detail hereinbelow, these devices are employed in the Microsequencer 160 (Fibure 2b) and the Arithmetic Logic Unit or ALU 180 (Figure 2d). During each so-called microcycle, the Microsequencer 160 generates an address for the Microprogram Memory 30 ~51743 162, the contents of which are then loadecl into a Microinstruction Register 164 in a conventional and well known fashion. Certain bits of the Microinstruction are translated by Decoder 166 and the outputs of this decoder, along with the remaining bits of the Microinstruction itselI
comprise the control signals appearing on the Control Bus 168 internal to 5 the node itself. These control signals are distributed to every control point throu~hout the node, both within and external to the Microprogrammable Controller.
The condition of the node is sensed by the Node Status circuitry 154. This information is presented to the Condition Test Multiplexer 1~6 10 and to the Mappin~ PLA (Pro~rammable Logic Array) 158. The Mappin~s PLA 158 causes the microprogram to be vectored to a specific task as required by a given node condition, while the Condition Test Multiplexer 156 permits the program to branch on any selected status condition.
The features thus far described with respect to Figure 2 permit 15 the so-called ~irmware running in the Microprogrammable Controller including the Microsequencer 160, the Microprogram Memory 162 and the Microinstruction Register 164 to exercise supervisory control over the remainder of the node hardware. Communication from the Microprogrammable Controller to various registers throughout the node is 20 via the 8-bit Destination Bus 172, while communication from any of the various node registers to the Microprogrammable Controller is via the 8-bit Source Bus 170.
Located at the top of the composite node block dlagram of Figures 2a and 2b are a plurality of Stub Transceivers 100-110 which are 25 coupled to communicate with the primary bus system (see Figure 1~ via their respective BAM's. These transceivers are clesigned to convert the received low level Manchester encoded serial data signal to a logic level Manchester signal. During transmission, they convert the logic level Manchester encoded serial data to the low level signal required to 3 ~iS~43 conform to existing electrical communications standards such as NATO
STANAG 4153.
Lines 112-122 are presented to the Channel Selection Network 124 via serial data and contro! lines. Channel selection is primarily determined by the contents of the Active Bus Number Register 150. This 5 register is arranged to be loaded by the Microprogrammable Controller previously described. If, for example, line 114 is selected to be the control line, two-way communication will be established from the Control Line Encoder 130 by way of .he Serial Control line 126, through line 114 and Stub Transceiver 102 to its respective primary bus. Similarly, any of the 10 remaining five lines could be selected to be the Data l ine and thus provide a two-way communication path through the Serial Data line 128 to the Data Line Encoder/Decoder 186. The details of how this selection is made will be discussed later under the heading "Reconfiguration". For now, however, it is sufficient to understand that a selection is required 15 such that all nodes have one common control line and another common data line.
The Control Line Encoder/Decoder 130 permits two-way conversion between the serial Manchester encoded data on line 126 and the 16-bit parallel interface on the Control Input/Output (CIO) bus 132. 20 All control line transmissions are 16-bit words in which the first bit is always a "1", and is referred to as the "sync bit", and the last bit is a parity bit for error detection purposes. When a Control Word is received on line 126, the bi-phase Manchester code is decoded to recover the clock and data signals. The recovered Manchester clock is used to shift the 16- 25 bit data word into a 16-bit register within the Control Line Encoder/Decoder 130 which is then presented to the CIO bus 132. The control word i5 then captured in a Control Line Input Register 146.
In the case of a transmitted word, the 16 bit parallel word is first developed in a Control Line Output Multiplexer 134 and presented to the 30 ~153l743 CIO bus 132. This data is captured in a 16-bit shift register within the Control Line Encoder/Decoder 130. It is shifted out serially into the Manchester Encoder section (not shown) of device 130 which converts it to Manchester bi-phase data at the Serial Control Line 126. The timed ~ating signals used to load and unload data from the CIO bus 132 and to 5 initiate the serial transmission are derived from the programmable lo~ic array based Control Line Sequencer 144. In all other respects, the Control Line Encoder/Decoder 130 operates asynchronously with the rest of the nodes. In a related manner, the Data Line Encoder/Decoder 186 (Figure 2b) performs the serial-to-parallel and parallel-to-serial data conversion 10 between the Serial Data line 128 and a so-called Message Input/Output bus (MIO bus) 187, the only difference being that in this case, the message length can be a multiple of 32-bit words.
Both Control l~ine and Data Line transmissions are checked for parity and format errors. In the event an error is detected, the 15 Microprogrammable Controller is notified via the Node Status circuitry 154.
Each node has the capability to 8enerate four types of control transmissions, namely:
(I) Poll; 2 0 (2) Response;
(3) Select; and ~4) Command.
These control words are generated by the Poll List 140, the Response Register 138, the Select Queues 142 and a Command Output Register 136, 25 respectively. The poll, select and command transmissions are employed only by the particular node which has been selected to function as the system's Bus Controller. All other nodes employ only the response form of transmission.

L7~3 In the Bus Controller rnode, the Control Line Sequencer 144 controls the Control Line Output Multiplexer 134 to select the appropriate type of transmission. A poll is an interrogation addressed to another node asking it to respond as to its status. In this regard, each node maintains a status word in its respective Response Register 138 which is indicative of 5 the node status or an indication whether that node requires access to transmit on the data line. The poll is broadcast by the Bus Controller to all nodes.
However, only the particular node addressed will generate a "Response". All Responses are loaded into the Control Line Input Queue 10 148 and the Microprogrammable Controller is notified of this via the Mapping PLA. The Control Line Sequencer is now in a condition to continue polling while the Microprogrammable Controller concurrently processes the Response. Polling proceeds sequentially on the basis of two ordered poll lists contained in Poll List 140, one ~or up to 16 so-called 15 priority nodes and the other list for the remaining (up to 256) non-prio~ity nodes. If the Microprogratnmable Controller determines that a node requires service, the address of that node is transferred from the Control Line Input Queue 148 to the Select Queue 142. This "Select" is the rneans by which the E~us Controller grants a node the use of the data Bus. The 20 Microprogrammable Controller may also determine that a Command should be sent. In this event, the Command Register 136 is loaded via the Destination bus.
Once the Microprogrammable Controller has loaded either Register 136 or Select Queue 142, the Control Line Sequencer proceeds 25 automatically to generate the correct sequence of Polls, Selects and Commands.
In the Non-Bus Controller mode, the operation of the Control Line Sequencer 144 is sirnilar, except that now the Microprogramrnable Controller tests the Control Channel inputs to determine i~ the node has 30 received a Poll or a Command~ Also, instead of transmitting Commands, Polls or Selects a node which is n~t functionin~ as a Bus Controller will only transmit a Response via Response Re~ister 138.
A novel aspect of the present invention lies in the ability of the Control Line Sequencer to automatically process all Control Line 5 transmissions in either mode without incurring any nominal delay due to processing by the Microprogrammable Controller. These features will be discussed in greater detail hereinbelow when the flow charts of Figures 33 and 34 are considered.

Because the remaining node functions do not relate directly to the inventian, only a brief description thereof will be presented at this point so as to provide the reader with a more complete understanding of the overall system construction and operation.
The User Interface may consist of 32 input lines designed to 15 carry digital signals which are arranged to be latched into Input Register 196 and 32 output lines which are driven by Output Register 197.
Communication is via the 32-bit User Bus 195. Communication from the Microprogrammable Controller to the User is by way of a Bus Output Register 176. A 32-bit output word is assembled from four 8-bit bytes 20 coming from the Destination Bus 172. Communication from the User to the Microprogrammable Controller is via the Bus Input Register 174. A
32-bit User word is latched into this register 174 and then disassembled into four 8-bit bytes which are sent sequentially to the Source Bus 170.
The Microprogrammable Controller supports all of the User protocol, but 25 does not become directly involved in the transmission of data. In a first instance where the User is the originator of a message, the User computer in guestion places a 32-bit header word on the User Bus 195. The Header Format circuit 194 converts this word into the header required for serial data transmission. This involves the insertion of a sync bit and a node 30 address. This word also is used to load a Buffer Control circuit 190 with a message word count. The reformatted header is loaded into the first word of a 128-word by 32-bit Data Output Buffer 192.
Next, 32-bit message words are sequentially loaded into the Buffer 192 until the word count specified by the contents of the Buffer 5 Control 190 has been reached. The complete message is now resident in the Output Buffer, ready for serial transmission. If the message to be sent exceeds the 128-word limit, it must be divided into packets by the user and then treated as a single message. With the Output Buffer 192 now loaded, the node requests service irom the Bus Controller which is 10 the node then acting as the "master" at the particular time. When a "select" is received, the output data is loaded in 16-bit bytes onto the Message Input/Output bus (the MIO bus) 187 and is transmitted via the Serial Data Line 128 out to the associated main bus channel in an uninterrupted serial data stream. All data transfers proceed 15 automatically to support a 10 MHz serial data rate.
Next to be considered is the case where a User Computer is to be the recipient of a message. All serial data is converted by the Data Line Encoder/Decoder 186 and presented to the MIO bus 187. A Message Screening circuit 188 coupled to this bus functions to examine the header 20 of each message and ignores all messages which are no t addressed physically or logically to this particular node. If the message is intended for the node's User, the Buffer Contral circuit 190 is initiated to cause the message to be captured in a Data Input 3uffer 191 which, too, mav comprise a 256-word by 32-bit storage de~ice. When the complete 2 5 message has been loaded into buffer 191, the node hardware inforrns the User that it has a message waiting and this message is then read out fro,n the Input Data Buffer 191 and sent to the associated User via the User E3us 195 and the output register 197. The Header Format circuit 193 conYerts the first 32-bit word of a message from the serial data format to the User 30 ~~" ~ lS~l~7~3 Bus format. Because it is possible that a second message can arrive before the first message has been emptied from the Data Input Buffer 191, this buffer is organized as an exchange rnemory ~vhich permits simultaneous loadin~ and unloadin~ of messages. In designing the node of the present invention, the buffer 191 is sized suc~h that two complete 5 messages of the maximum length, e.g., 128 words, can be held without over-running it. Any abnormal message conditions are reported by the Buffer Control circuit 190 to the Node Status circuit 154.
SYSTEM TIMING
All timing for the node is derive~ from a stable crystal oscillator 10 which may, for example, produce 20 MHz square waves. -The output of this oscillator is used to form iive critically lapped clock pulses designated Phase I through Phase V. Each clock pulse may typically be 50 nanoseconds wide and may occur every 250 nanoseconds. The resulting pulse-to-pulse interval defines the cycle during which an instruction is 15 executed by the Microprogrammable Controller and also determines the execute cycJe for the Control Line Sequencer 144. The 20 MHz oscillator is also used in the encoding of the 10 MHz bi-phase Manchester serial data stream. The Phase 111 clock pulse is used to clock a 16-bit binary divider which generates 16 square wave outputs ranging from a 0.5 microsecond 20 period to a 16,3~4 millisecond period. Certain of these output signals are employed in the various time-out checking performed by various modules within the node.
Now that the overall organization of a typical node has been explained with the aid of the system block diagram of l~igure 2, 2 5 consideration will now be given to various modules set Eorth in tha t general block diagram.

~iS~ 3 MICROPE~OGRA,~MABLE CONTROLLER
Figures 3a and 3b together illustrate by means of a more detailed block diagram the organization of the Microprogrammable Controller employed. The Microsequencer 160 of Figure 2 is represented in Figure 3 by a block identified by numeral 814 and provides an ll-bit 5 address to a programmable read-only memory (PROM) ~16 which may, typically, comprise 2048 words, each 56 bits in length. At the beginning of each cycle, a new word is fetched from the PROM 816 and loaded into a 56-bit Microinstruction Register 818. The 56 separate outputs from this register are used to control both the internal operation of the 1 Q
Microprogrammable Controller and to provide the hardware control signals for the remainder of the node. Selected bits of the register ~18 are thus connected to each function of the Microprogrammable Controller.
Two instruction formats are utilized. When one format is 15 involved, branching and program control can be effected. A second forrnat dictates that data transfers and data manipulations are to occur.
Referring to Figure 3a, the particular format in use is defined by the state of bit 34 which causes the bits 0 through 33 to be interpreted differently. As is illustrated in Figure 3a, bit 34 is received by the 2 0 Format Control circuit 820 which selects the appropriate functions for a given format. The interpretation of the upper portion of the ins-truction bits, i.e., bits 35 through 55 is identical for both formats.
Consider first the interpretation of the lower order bits when bit 34 is a binary "0". As rnentioned above, this defines the branch or 25 program control format. Bits 0 through 3 of the Microinstruction word provide the command instruction for the Microprogram Sequencer 814.
These bits are decoded to select one of 16 possible operations as defined for the Advanced Micro Devices series 2910 type integrated circuit. This instruction determines the source of the next address which will be used 30 ~lS~3 to fetch the next Microinstruction. If the program does not branch, the address count is sirnply incremented by 1. If a branch is required, the output o~ Branch d,ddress Multiplexer 810 provides the source for the new address. As might be expected, branching can be either conditional or unconditional. For the conditional case, the decision to branch is decided 5 by the output of Test Condition Multiplexer 812. Bits 4 throlJgh 17 of the Microinstruction are provided to the Test Condition Multiplexer 812 to select one of 83 possible test si~nals which will be used for conditional branching. These signals are comprised of 32 firmware flags which become available at the output of the Firmware Flag Decoder 824 and the 10 various Test Condition Flags identified in Table I below.

TEST CONDlllON FLAGS

Active State Function H INTER MESSAGE TIMEOUT
H DATA LINE DATA STREAMING TIMEOUT
H DATA LINE PARITY ERROR
H IMMEDIATE REQUEST
H MESSAGE TO SEND FLAG
H CONTROL LINE SYNC ERROR
H CONTROL LINE PARITY ERROK
H SEQUENCER WAIT FLAG
H FORCED COMMAND ENABLE
H POLL/RESPONSE
H SELECT ENABLE
H COMMAND ENABLE
H PREVIOUS POLL PRIORITY/NON-PRIORITY INDICATE
L NON-PRIORITY LIST ENABLE
H SElECT TIME FLAG
L OWN NODE SELECT FLAG
L OWN NODE POLL FLAÇ
L NON-PRIORITY QUEUE EMPTY
L PRIORITY QUEUE EMPTY
H NON-PRIORITY QUEUE FULL
H PRIORITY QUEUE FULL
H CONTROL LINE ACTIVITY TIMEOUT
H POLI;/RESPONSE TIMEOUT
H AUTO LOOP ERROR FLAG
H PROCESSOR CONTROL LINE~ INPUT
QUEUE FULL
H CONTROL LINE INPUT WORD INDICATOR

~15~l743 H PROCESSOR CONTROL LINE INPUT

H PROCESSOR CONTROL LINE INPUT

H PROCESSOR CONTROL LINE INPUT

H PROCESSOR CONTROL LINE INPUT

H PROCESSOR CONTROL LINE INPUT

H LATCHED MCU INTERRUPT FLAG
H FORCED EXTERNAL FUNCTION
FLAG
H LATCHED INPUT DATA ACKNOWLEDGE
FLAG
H LATCHED USER DATA INPUT FLAG
H LATCHED EXTERNAL FUNCTION
INPUT FLAG
H LATCHED DATA & HEADER LOST.
H LATCHED ERROR ACTIVITY INDICATOR
L ALU SIGN FLAG
H EXTERNAL INTERRUPT/DATA SWITCH
H ALU SIGN FLAG
H ALU CARRY FLAG
H ALU = ZERO FLAG
H ALU OVERFLOW FLAG
H NODE POWER FAULT
H BREAKPOINT FLAG
H LATCHED DISPLAY MODE

(AUTO LOOP) ERROR IND) H LATCHED INCOMPLETE MESSAGE
H LATCHED DATA LINE DATA LOST
(HEADR
COMPLETE) H LATCHED CONTROL LINE ACTIVITY
INDICATOR FLAG
TABLE I

l743 It can be seen, then, that the state of any flag can be ascertained by the microprogram by executing the appropriate conditional branch instruction. Bit 19 of the microinstruction contained in register 818 determines the source of the branch address via the Branch Address Multiplexer 810. If this bit is a 0, the branch address is determined by bits 5 2û throu~h 31 of the microinstruction. If, however, bit 19 is a binary "1"
signal, the branch address is determined by the output of the Mapping PLA 158 of Figure 2b. By executing a branch instruction with bit 19 set to a 1, the program can be vectored to the starting address of one of a number of processing tasks as defined by the Mapping PLA. Bits 32 and 10 33 are not used in this format.
Next to be considered is the case where bit 34 of the Microinstruction is a binary "1", thus definin~ the data transfer and manipulation format. Bits 0 through 4 are present~d to the Destination Field Decoder 828 to generate the 29 destination field decode signals 15 Jdentified in Table 11 below. Each of these signals has a unique code which, if programmed, causes the data on the 8-bit destination bus 846 to be latchecl into the corresponding register.

DESTINAllON FIELD DECODE 2 0 SCREEN RAM ADDRESS REGISTER LOAD ENABLE

CONTROL LINE INPUT REGISTER BYTE I LOAD ENABLE
ACTIVITY MASK REGISTER LOAD ENABLE
DEST BUS HOLD REGISTER LOAD ENABLE

COMMAND REGISTER BYTE I LOAD ENABLE
SELECT REGISTER LOAD ENABLE
NUMBER NON-PRIORITY USERS/SUBCYCLE REGISTER LOAD ENABLE
END NON-PRIOE~ITY LIST REGISTER LOAD ENABLE
END PRIORITY LIST REGISTER LOAD ENABLE
RESPONSE REGISTER LOAD ENABLE
CONTROL LINE ACTIVITY TIMEOUT REGISTER LOAn ENABL
CABLE SELECTION REGISTER LOAD ENABLE
INPUT RAM ACCUMULATOR LOAD ENABLE
SCREEN RAM CONTENTS LOAD ENABLE
OUTPUT DATA RAM ADDRESS LOAD ENABLE
INPUT DATA RAM UNLOAD ADDRESS LOAD ENABLE
DATA RAM CONTROL REGISTER LOAD ENABLE

INPUT DATA RAM LOAD ADDRESS LOAD ENABLE
MICROPROCESSOR CONTROLLER EXTERNAL INTERRUPT FORMING REGISTER BYTE I LOAD ENABLEMICl~OPROCESSOR CONTROLLER EXTERNAL INTERRUPT FORMING REGISTER BYTE 2 LOAD ENABLE

Data thus flows from the 8-bit Arithmetic Logic Uni~ 838, through the Destination E~us Driver 836 to the selected register. When in this format, bit 5 of the microinstruction controls the write enable (WR
EN) input of a Word Register File 844. Typically, the file 844 may cornprise 16-word registers each 8 bits in length. If bit 5 of the 10 microinstruction is a binary "1", the destination for the data becomes the word of the Register File 844 specified by bits 0 through 3 of the Microinstruction, which is selected by the Multiplexer 842. Bits 6 through 14 of the microinstruction determine the source of the data to be put on the 8~bit Source Bus 848. When bit 14 is a "0", the Vlicroinstruction 15 Constant Driver 834 is enabled via inverter 835, causing bits 6 through 13 of the Microinstruction to be used directly as the source data applied to the bus 848. When bit 14 is a binary "1", the output of Multiplexer 832 is enabled such that it becomes the data source. Bits 6 through 13 of the instruction word are decoded by the Source Field Decoder 830, the output 20 of which is used to select one of 19 possible source inputs for a source Multiplexer 832.
The various source Registers from which data can be accessed are identified in the following Table IIT.

SOU}~CE ~IELD DECODE
SELECT REGISTER
NUMBER NON-PRIORITY USERS/SUBCYCLE
END NON-PRIORITY LIST REGISTER
END PRIORITY LIST REGISTER
LAST POLL ADDRESS
POLL LIST OUTPVT
CABLE SELECTION REGISTER
NODE ADDRESS

~5~7~3 CONTROL LINE ACTIVITY INDICATORS
CONTROL LINE INPUT LOWER BYTE
CONTROL LINE INPUT UPPER BYTE
INPUT DATA RAM ACCUMULATOR
INI~UT DATA RAM CONTROL REGISTER
OUTPUT DATA RAM WORD COUNT
OUTPUT DATA RAM ADDRESS
INPUT DATA RAM UNLOAI) ADDRESS
INPUT DATA RAM WORD COUNT
INPUT DATA RAM LOAV AI~DRESS
MICROINSTRUCTION CONSTANT
SCREEN RAM CONTENTS REGISTI~R
NODE STATUS REGISTER BYTE I

NODE STATUS REGISTER BYT~ 3 EXTERNAL FUNCTION HOLDING REGISTER BYTE I

EXTERNAL FUNCTION HOLDING R~GISTER BYTE 3 EXTERNA~ FUNCTION ~IOLDING REGISTER BYTE 4 TABLE III
One of the outputs of the Source Field Decoder 830 comprises the file source enable signal which, when activated, enables the output of the 16-Word Register File 844. In this case, the data source is the register 15 file word specified by bits 6 through 9 of the microinstruction, these being selected by the Multiplexer 842.
Bits 15 and 16 of the microinstruction control the operation of the Arithrnetic Logic Unit Shift Control and Status Latch 840. During shift operations, these bits select one of four shift types; narnely, 0 Fill, l 20 Fill, Single Length Rotate, or Double Length Rotate. The Advanced Micro Devices 2901A Arithmetic Logic Unit integrated circuit employs two 4-bit address fields used in the manipulation of the 16 internal registers of the ALU itself. Microinstruction bits 17-20 provide the B-address field, while bits 21-24 provide the A-address field. The ALU 838 25 also employs two 3-bit fields to define the internal destination and source for arithmetic operations. These fields are provided by microinstruction bits 25-27 and 28-30, respectively. Bits 31-33 determine the type of arithmetic function to be executed by the ALU. Microinstruction bit 52 is used for carry control. 30 `` ~15~l'743 A Fi~m~al-e Flag Decoder 824 which may colnprise a 32-bit addressable latch is adapted to receive bits 35 thro~lgh 39 af the microinstruction and ~unctions to select one of these 32 flags while microinstruction bit 40 defines whether the flag is to be set or cleared.
As will be explained in greater detail, these ~irmware ~la~s are available 5 to both of the control points of the node as well as for inle~nal test by the Microprogram sequencer 814 by way of the Test Condition Multiplexer 812.
A Hardware Control Field Decoder 826 functions to translate microinstruction bits 41 throu~h 50 to thereby develop 52 possible Hardware Control signals, these signals being set out in Table IV below. 10 CONTROL SIGNALS
Active State Function H LOAD SCREEN RAM
H CLEAR BREAKPOINT FLAG
H CLEAR CONTROL LINE INPUT INDICATOR
H FORCE PRIORITY POLL
H ENABLE SEQUENCER
H LOAD SELECT REGISTER
H CLEAR POWER FAULT FLAG
H CLEAR ACTIVITY MONITOR l~LAGS
L CLEAR DATA LINE INTERMESSAGE
TIMEOUT
L CLEAR PROCESSOR PLAGS
L CLEAR MESSAGE TO SEND FLAG
L CLEAR CONTROL LINE PARITY
ERROR
L CLEAR POLL/RESPONSE TIMEOUT
H CLEAR SEQUENCER WAIT
FLAG
H SET SEQUENCER WAIT FLAG
H SET FORCED COMMAND ENABLE
H SET COMMAND ENABLE
H SET SELECT ENABLE
H SET POLL/RESPONSE ENABLE
H CLEAR AUTO LOOP ERROR FLAG
H POLL LIST WRITE ENABLE
H ADVANCE POLL LIST
H UNLOAD REQlJEST QUEUE
tl LOAD REQUEST QUEUE WITH CONTROL
LINE REG
H LOAD REQUEST QUEUE WITH DESTINATION
BUS
H LOAD REQUEST QUEUE WITH NODE
ADDRESS
H RESET POLL LIST
H TRANSMIT ENABLES

~-~S~743 -L CLEAR USER INTERFACE
L DELETE OUTPUT MESSAGE
H CLEAR CONTROL LINE SYNC ERROR
L CLEAR SELECT TIME FLAG
L ~ET NODE POLLED INDICATOR
L CLEAR SELECT QU EU ES
L CLEAE~ CONTROL LINE IN QUEUE
L CLEAR ENCODER INTERFACE
H DISABLE SEs~UENCER
L CLEAR CONTROL LINE ACTIYITY
TIMEOUT
L CLEAR INPUT DATA ACKNOWLEDGE
L SET USER OU1PUT DATA RES;~UEST
L CLEAR USER EXTERNAL FUNCTION
LOGKOUT
1~ CLEAR USER OUTPUT DATA ACKNOWLEDGE
FLAG
L CLEAR USER EXTERNAL FUNCTION
ACKNOWLEDGE FLAG
L SET MICROPROCESSOR CONTROLLER
MESSAGE COMPLETE
L SET USER INPUT DATA ENABLE~
L SET USER EXTERNAL INTERRUPT
ENABLE
L ENABLE DATA LINE MESSAGE TRANSMISSION
L CLEAR DATA LINE PARITY ERROR
L CLEAR INCOMPLETE MESSAGE
LOCKOUT
L CLEAR INCOMPLETE MESSAGE
ERROR
FlAG
L CLEAR DATA LOST HEADER OK
ERROR
L CLEAR DATA LOST ALL ERROR

TAe~LE lV

These signals are active only for the instruction cycle during which they are selected. Microinstruction bit 51 is used directly to form the Priority Queue Enable signal on line 827 which specifies the particular select queue to be referenced or operated upon during a current machine cycle. Continuing, microinstruction bit 55 is set to a state which 25 establishes odd parity for the Microinstruction word. Parity is checked by the Parity Check Circuit 822 which functions to disable the node clock in the event a parity error is detected.
Reviewing momentarily, it can be seen from an analysis of the Microinstruction and the manner in which its individual bits are assigned 30 ~5~7~3 ~APPING PLA TRUTH TABLE
TABLE V A

A- Inputs Term 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XlXOOXXXXXXXXXXX

4 X 0 ~ 0 0 X X 1 0 0 1 0 X X X X

7 X 0 1 0 0 X X 0 0 1 n o x x o: x 8 X O 1 0 0 X X t) O 1 0 0 X X 1 X

17 X 0 1 0 0 X X X 1 0 o 1 X X X X
18 X 0 1 0 0 X X X 1 0 o X X X X X

~ ~ 5~ 43 MAPPING PLA TRUTH TABLE
TABLE V A

. -A- Inputs .
Term 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 _. .

X O O O O 1 X X X X X X X X x 1

5~ 3 TERM DESCRIPTION

3 CO~TROL LINE INPUT - ASSIGN BUS CONTROL

FUNCTION CODE = 2 ADDRESSING MODE BIT = 1 CONTROL LINE INPUT - CHANNEL CONTROL

6 CONTROL LINE INPUT - ILLEGAL COMMAND
FUNCTION CODE = 3 ADDRESSING MODE BIT = 1

7 CONTROL LINE INPUT - STATUS REPLY - NOT WAITING

8 CONTROL LINE INPUT - STATUS REPLY - WAITING =>IGNORE

9 CONTROL LINT INPUT - STATUS RE,O,UEST - NOT WAITING
CONTROL LIN~ INPUT - STATUS REQUEST - WAITING

FUNCTION CODE = 5 FUNCTION CODE = 6 FUNCTION CODE = 7 ADD~ESSING MODE BIT -- 0 14 CONTROL LINE INPUT - BIT #l CONTROL LINE INPUT - ILLEGAL COMMAND
FUNCTION CODE = 8 ADDRESSING MODE BIT = 0 16 CONTROL LINE INPUT - BIT ~2 FUNCTION CODE = 9 18 CONTROL LINE INPUT - ILLEGAL COM~AND
FUNCTION CODE - 10, 11 19 CONTROL LINE INPUT - RESPONS~ - DISABI,ED -->IGNOR~
CONTROL LINE INPUT - RESPONSE - hUS CONTROLLER -->
INTERNAL HARDWARE EXROR

11 ~S1l~7~3 (continued3 TERM ~ESCRIPTION

NOT WAITING ~ UNEXPECTED POLL RESPONSE

CONTROLLER - WAITING

CONTROLLER - WAITING
24 CONTROL LINE INPUT - NO~MAL BUS REQUEST - BUS
CONTROLLER - WAITING
CONTROL LINE INPUT - IMMEDIATE BUS REQUEST - BUS
CONTROLLER - WAITING
26 CONTROL LINE INPUT - POLL OR SELECT - DISABLED -->
IGNORE

. DISABLED =~ ILLEGAL POLL OR SELECT

DISABLED - NOT WAITING --~ERROR

CONTROLLER - WAITING => LEGAL POLL
CONTROL LINE INPUT - SELECT - DISABLED - BUS
CONTROLLER - WAITING --~ LEGAL SEI.ECT
3]. CONTROL LINT IMPUT - ILLEGAL COMMANDS FUNCTION CODE =
14, 15 ADDRESSING MODE BIT = 1 34 NOR~AL MESSAGE TO SEND
IMMEDIATE MESSA~E TO SEND

MAPPING PLA
STATE DESCRIPTIOMS
TABLE V B

L7~3 INPUTS

Al5 NOT USED
Al4 ERROR FLAG
Al3 CONTROL LINE INPUT FLAG
Al2 USER ACTIVITY FLAG
All MIC.ROPROCESSOR CONTROLLER INTERRUPT
FLAG

A9 DEFERRED TASK FLAG (FIRMWARE FLAG 3) BIT 2 (ADDRESSING MODE BIT) BIT 6 (FUNCTION CODE 3) A6 PROCESSOR CONI'ROL LINE INPUT QUEUE
BUT 6 (FUNCTION CODE 2) BIT 4 (FUNCTION CODE l) BIT 3 (FUNCTION CODE 0) A.3 BUS CONTROLLER (FI.RMWARE FLAG 2) A2 DISABLE (FIRMWARE FLAG 1) Al WAITING FOR POLL/RESPONSE FLAG
A0 NORMAL (0)/IMMEDIATE (1) MESSAGE

MAPPING PLA

TABLE V C

S~7~

to different functions that the Microprogrammable Controller possesses the following capabilities:
(l) It executes a general purpose stored program;
(2) It can be directed to specific processing tasks via the Mapping PLA; 5 (3) It can interchange data with various node registers via the source and destination buses;
(4) It can issue control signals to the node; and (5) It can sense the status of various node parameters.

All firmware tasks executed by the Microprogrammable Controller are initiated via the Mapping Programmable Logic Array (PLA) 158 in Figure 2b. When the performance of a specific task is required, the PLA generates an output which corresponds to the starting address of that task. As is shown in Figure 4, the Mapping PLA 224 is driven by the 15 output of octal latches 220 and 222. Each clock phase 5 timing signal latches the data on their respective input lines to generate a specific PLA
output. If, on the next cycle, the Microprograrnmable Controller execu-tes a branch instruction with bit 19 of the Microinstruction Register set, it will branch to any one of 38 possible addresses determined by the various 20 combinations of the inputs to latches 220 and 222. The so-called truth table for the Mapping PLA 224 is shown in Table VA below. Any combination of inputs A0 through Al5 results in one of 38 PLA terms, each one corresponding to a unique output address labelecl Z0 through Z7.
Table VB is indicative of the task to be performed for each term while 25 Table VC indicates the interpretation of inputs A0 through Al5.

Inputs A9 through A14 can be considered to be the activity group.
When all of these inputs are binary 0's and the Microprogrammable l~ontroller has completed its previous task, it will go into an idle loop corresponding to Term 37 in Table VB. The PLA is programmed such that when any one of these lines goes high the appropriate task is initiated and, 5 in the event that more than one line in this group goes high in a ~iven cycle, a priority scheme is invoked to resolve the order in which the tasks will be executed. The highest priority activity is an interrupt from the Maintenance Control Unit ~MCU) on input A-ll. It will unconditionally generate output Term 33. The next highest priority is "user activity" on 10 input A-12. It will generate output Term 32 conditional only on a 0 on input A-ll. The next priority activity is the so-called "Error Flag"
associated with input A-14 which will generate as its output Term 0 whenever inputs A-ll and A-12 are 0. This error flag will be generated by a I at any input of NOR gates 200, 202, 204, 206 or 208. 15 The next highest priority is associated with the "control line input flag" - input A-13. This will cause one of the output Terms from 1 to 31 in Table VB to be generated where the specific ternn is determined by the states of the inputs A-l through A-8 in Table VA. Inputs A-4 through A-8 are from the Control Word received from another transrnitting node 20 in the systern. Inputs A-4 through A-7 represent the 4-bit control line function code while input A-8 is the so-called "addressing rnode bit".
When input A7 is a "0", the function code is a command resulting in output states defined by Terms I through 14 in Table VB. If inputs A-7 and A-6 are l's, however, the function code is either a poll, a select or a response 25 corresponding to the output states defined by Terms 19 through 31. Notc that output terms are generated for both valid and invalid input eodes.
Inputs A-0 through A-3 are driven by firmware flags and define the state that the node is in. For example, if input A-3 is a "0", -the node is not functioning as the Bus Controller and therefore tasks will be 30 - ~lS~l743 initiated upon receipt of a poll or other bus commands. However, if input A-3 is a "I", the particular node is functioning as the Bus Controller and a task will be initiated upon receipt of a response during normal operation.
Next in order of priority activity is the Message-to-Send ~lag input A-lO
which results in either the output state defined by Term 3~ or Term 35, 5 dependin~ on the binary value of input A-0. Finally, the lowest priority activity is associated with the Deferred Task Flag input A9 which results in output Term 36. The use of a PLA to analyze these inputs greatly improves the response of the Microprogrammable Controller to either polls or responses, since no firmware overhead is required to test for 10 abnormal conditions. This feature is essential to achieving the high polling rate inherent in the preferred embodiment described herein.
TIME FC:~R SELECT FLAG
Referring next to Figures 5a and 5b, there is shown by means of a logic diagram the circuitry employed to generate the so-called Time- 15 for-Select flag. It is this flag which is interpreted by the Microprogrammable Controller to indicate that, acting as the Bus Controller, it can now authorize another node to use the data channel.
Toward this end, the Data Channel State Register shown enclosed by dashed line box 267 is cornprised of two D-type flip-flops 268 and 270 20 which, together, may exist in four separate states, to wit:
(I) State 0 - No activity currently exists on the data channel and no node has been authorized to use the channel.
(2) State I - A select has been issued to a node and that node is currently using the data channel. 25 (3) State 2 - A select has been issued to a node but that node has not begun to use the data channel.
(4) State 3 - A select has been issued to a second node during the transmission sequence of the previously selected node. 30 1l~5~3 The foregoing states are controlled by the signals on the Select lssued line 261 which connects to a "select" inpu t of a dual 4 to I
multiplexer 264 and by the "data line activity indicators" which control the setting of flip-flops 260 and 262 (Figure 5a). When a message is transmitted by another node, it is detected at the bus input causin~ the 5 Data Line Envelope Detect (Message Receive Envelope) line 255 to go high, such that the output from inverter 258 also goes high. If the node under consideration itself initiates a message transmission, the Data Line Output Trans$er line 257 goes high and when the TB (Register ~) line 253 also goes high, AND ~ate 250 is enabled. Thus, on clock phase 5, Elip-flop 10 254 is set, causing the output from inverter 258 to go high. This condition prevails until the Data ~ine Output Transfer line 257 again goes low, indicating the end of the message transmission, after which the flip-flop 254 is clocked to its reset state. It can be seen, then, that the output from inverter 258 is high whenever the data line is active. The output 15 from inverter 258 is passed through a 2-bit shift register comprised of the flip-flops 260 and 262 which are clocked by the phase I clock pulse. On the leading edge of the message, the flip-flop 260 will be set while flip-flop 262 remains reset, thereby causing the output of the Exclusive OR
circuit 263 to be a binary "1" for a single clock pulse interval in that on 20 the next clock pulse, both flip-flops 260 and 262 will be set. Similarly, on the trailing edge of the message, flip-flop 260 resets while flip-flop 262 remains set, such that the output frorn the Exclusive OR gate will again go positive for a single cycle. The output from the Exclusive OR circuit 263 can thus be considered as a form of edge detection for the message. 25 It forms the lower order bit selection for the dual four-to-one multiplexer 264. The higher order bit selection of this multiplexer is governed by the Select Issued line 261 which goes positive for one clock period e~ch tirne a select-type control transmission is issued.

11 ~1S~l~743 The inputs to multiplexer 264 are hard wired to generate a unique 2-bit output for all four possible combinations of the selection inputs. This output is presented to the ~-inputs of a 4-bit adder network 266. The A-inputs of this adder come from the outputs of the Data Channel State Register 267 and the outputs of the adder 266 are, in turn, 5 applied as inputs to that same register. Thus, on the leading edge of each phase l clock pulse, the output of the multiplexer 264 is added to the contents of the Data Channel State Register and the resulting sum is stored back in that register. If there has been no "Select Issued" signal on line 261 and no message edge (leading or trailing) detected, the output 10 from multiplexer 264 will be 0,0 and the Data Channel State Register 267 will have its contents remaining unchanged. If there is a "Select Issued"
generated, but no edge detected, the output from multiplexer 264 will be 1,0 and the Data Channel State E~egister will thus be incremented by 2.
When a message edge is detected, but a "select" has not been issued, the 15 output of multiplexer 264 will be l,l which will have the effect of decrementing the Data Channel State Register by l. If a "select" is issued simultaneously with a message edge detection, the output of multiplexer 264 will be 0,1, thus incrementing the Data Channel State Register 267.
If Firmware Flag #5 is set, or if either the Priority or Non- 20 priority queues are not empty, the NOR gate 272 will output a low signal indicating that a select is required as soon as the message line becomes available. The output of NOR gate 272 is used to partially enable the negative NAND gate 27~ so that whenever the flip-flop 268 is reset indicating a data channel state of l or 0, it will be fully enabled. Thus, on 25 the next phase l clock pulse, flip-flop 276 will output a high signal at its Q
output, thus indicating thé Latched Time for Select signal. This method of data line selection minimizes the firmware response time required to generate the next "select" transmission when the data line activity of the current select has been sensed. As such, in most cases, the next node to 30 L7~3 be selected will have received the Select command and will be ready to transmit its message at the end of the current message. Hence, inter-message dead time, which reduces channel capacity, is effectively avoided.

Referring again to the overall system block diagram of ~igure 2 and particularly to Figures 2a, there are four sources of Control Line output words, namely, the Command Register 136, the Response Re~ister 138, the Poll List 140 and the Select Queue Register 142. Selection of the Control Word source is determined by Control Line Output Multiplexer 10 400 in Figure 6a. These selections correspond to the states of 0,0; 0,1;1,0;
and 1,1 of Control Line Mux select lines 401 and 403. The Control Line Output Multiplexer outputs ~2 through Z14 to the corresponding inputs of the Control Word Latch 442 (Figure 7b). Inputs A0 and Al of latch 442 (Figure 7b) are forced to the 1 state by virtue of being connected to a +5V 15 source. A0 provides the "sync" bit while Al identifies the transmission as a control word. Input A15 of latch 442 is the parity bit generated by a Parity Generator 402 and 404.
Control word transmission is initiated by the "Send Word" signal which is initiated on clock phase I by the Control Line Sequencer PLA 144. 20 On clock phase 3, NAND gate 440 is enabled causing the output of NAND
424 to go low and to latch in that condition via cross-coupled NAND gate 426. This enables the tri-state outputs of the Control Word Latch 442.
On the trailing edge of clock phase 3, the output of NAND gate 440 goes positive, clocking latch 442 and putting the output of the Control Line 25 Multiplexer on the CIO bus 132. Subsequently, clock phase 5 enables NAND gate 438 which causes the output of NAND gate 432 to go low and latch via cross-coupled NAND gate 434. This generates the "Control RC"
signal at the output of inverter 436 which initiates the Control Line Encoder 130. At the end of the control word transmission, the "Control 30 ~tS~43 TC" signal resets the "Control I~C" signal via inverter 406 and NAND gate 432. When the Control word has been latched in the Control ~ine Encoder, the "CONTROL CT" signal causes the output of NAND gate 432 to go high and latch via NAND gate 434, thereby clearing the "Control RC" signal. During initialization or after a fault condition, this function 5 is accomplished by the "CLEAR ENCODER INTERFAC~" signal. (See Table IV.) Flip-flops 472 and 474 (Figure 8) comprise the 2-bit Response Register 13~ of Figure 2a. The Response Register provides the code from the responding node to inform the Bus Controller or polling node of its 10 status. The four possible responses, i.e., a "Node Fault" response, a "No Request" response, a "Normal Bus Request" and an "Immediate ~us Request", are encoded 0,0; 0,1; l,0 and l,l, respectively. These codes will be interpreted by inputs A4 and A5 of the Mapping PLA of the controlling node. The Response Register is not used by the Bus Controller node. The 15 Response Register is loaded from the Microprogrammable Controller via the two least significant bits carried by the Destination Bus. When the Response Register Load ~nable line 463 is selected, a phase 5 clock pulse will load the data off bits 0 and I of the Destination Bus into the Response Register (See Figure 8). Immediately after the r_sponse word has been 20 loaded into the Control Word Latch 442, a phase 4 clock pulse will complete the enable of NAND gate 462, thus clearing the Response Register comprised of flip-flops 472 and 474. This action ~eaves the value 0,1 stored in the Response Register, corresponding to the "No Request"
response. Thus, if no action is taken by the Microprograrnmable 25 Controller to reload the register before ihe next poll, the "No Reques-t"
response will be issued.
The forrnat for the response word requires that bi-t 2 thereof be a 0, that bits 5 and 6 be l's and, further, that bits 7 througll 14 contain the address of the responding node.As can be seen from Figure 6b, B2 is 30 .

-` 'l.lS~7~3 forced to 0 (ground) while the inputs B5 and B6 are forced to l's (+5V).
Inputs B3 and B4 to the Control Line Output .~lultiplexer 400 are the 2-bit response code from flip-flops ~72 and 474. Inputs B7 through B14 are node address bits 0 through 7, respectively.
Registers 468 and 470 constitute the upper and lower bytes of 5 the 16-bit Command Register 136 in Figure 2a. The register is loaded, one byte at a time, from the Microprogrammable Controller via the Destination Bus When Command Register Byte 2 Load Enable line 457 is selected, a subsequent clock phase 5 pulse enables NAND gate 456 to-load the upper byte. Similarly, a Command Reeister Byte 1 Load Enable on 10 line 459 will cause the lower byte to be loaded. The format for a command word requires that bit 6 be a 1. Bits 3, 4 and 5 are the command code, while bit 2 indicates the addressin~ mode. If bit 2 is a 0, the command will be broadcast to all nodes. If it is a 1, the command will be broadcast to the addressed node where this address is contained in bits 7 15 through 14 of the command word. The Command Register outputs correspond to the A inputs of Control Line Output Multiplexer 400 of Figures 6a and 6b. The Select Multiplexer/Register 480 of Figure 9 is a digital storage device which can be loaded frorn two sources via its A and B inputs. If the Select Register Destination Decode line 475 carries a 0 20 and the Load Select Register line 477 is selected, the next phase 5 clock pulse will enable negative AND gate 478 to thereby clock register 480. In this case, the outputs of the Select Register Queue corresponding to the A
inputs of the multiplexer 480 will be loaded into the register. This is the condition for a "Normal" bus request. If the Microprogrammable 25 Controller is processing an "Immediate" bus request, the Select Register Destination Decode line 475 will be set high, thus causing the contents of the Destination Bus (corresponding to the B inputs of the multiplexer) to be loaded into register 480, thus allowing the immediate bus request to gain precedence over previously queued selects. 30 .51~13 The contents of register 480 can be sensed by the Microprogrammable Controller via the Source Multiplexer 832 of Figure 3b. The control word format for a "select" requires that bits 2, 3, 5 and 6 each be a l and that bits 7 through 14 contain the address o~ the node to be selected. Referring to multiplexer 400 in Figures 6a and 6b, it is to be 5 noted that the D-inputs thereto correspond to the select mode. Inputs D2, D5 and D6 are ~orced to l's while inputs D7 through Dl4 are connected to the output of the Select Register 480. The format for the poll control word also requires that bits 2, 5 and 6 be set. It is distinguished from the select word only by the different response code as previously mentioned.
The poll word corresponds to the C inputs of multiplexer 400. Inputs C2, C5 and C6 are all forced to l's. Inputs C7 through Cl4 are connected to the outputs of the Poll List, which provides the address of the node to be polled. This method of generating control word outputs is significant in maintaining a high degree of control line bus utilization. ~Vhenever a 15 control word is transmitted, the next control word of that type is computed and loaded into the corresponding register. Thus, it can be automatically sent, as required, under control of the Control Line Sequencer PLA 144 in Figure 2a. This eliminates any dead time that would otherwise be required for processing overhead. One of the features 20 of the present sys~em is that the Bus Controller's responsibility is assignable to various nodes. This requires that each node, when in the Bus Controller role, be able to sense when it is itself being selected~ This is the function of comparator 482 which compares the output of the Select Queue FlFO's 811 and 819 in Figures 22a and 22b to the node address, thus 25 generating the "Own Node Select Flag". When this condition is detected, the Micropro~rarnmable Controller suppresses the transmission of the select word and handles the select internally in its own firmware.

~15~7~3 POLL LISTS
It is the Poll Lists which determine the order in which the Bus Controller polls all nodes, including itself. The polling order is contained in the user computer and is loaded-into various registers and mernories of the Poll Lists via the Microprogràmmable Controller. Once this 5 inf ormation has been entered into the poll lists, polling proceeds as previously described. The Priority Poll List contairis the node addresses of up to 16 priority nodes, while the Non-priority Poll List contains the node addresses of all other nodes utilized in the system. The polling process proceeds as follows: lQ
(I) Priority nodes are sequentially polled until the end of the Priority Poll l,ist is reached;
(2) Starting at the top of the Non-priority Poll List, a specified number of non-priority nodes are polled where this number is referred to as the sub-cycle count; 15 (3) All priority nodes are again polled;
(4) Polling of non-priority nodes resumes at the point after the last non-priority poll and continues until the sub-cycle count is reached;
(5) Polling alternates between priority and non-priority 2 0 polls until the end of the Non-priority List is reached; and (6) Non-priority polling starts at the top of the Non-priority List.
It can be seen then that the information required to initialize the poll lists consists of: 25 ~a) The poll addresses;
(b) The number of priority polls;
(c) The number of non-priority polls; and (d) The sub-cycle count.

llS~ 3 Referring to Fi~ure 10b, there is identified by numeral 518 the 16-word Priority Poll List Memory which is arranged to store the node addresses of the priority node~. The memory 518 is arran~ed to be addressed by the output of a ~-bit Priority Counter 506 which has its Q0 through Q3 outputs coupled to the select inputs of the Priority Poll List 5 Memory 518. When a low signal is applied to line 505 labeled CLR
PRIORITY CTR, the 4-bit Priority Counter 506 will be reset, thus pointing to the top of the Priority Poll List stored in the RAM device 518.
The outputs from the Priority Poll List Memory 518 are normally in a high state. If the Priority List Memory Enable line 517 goes low, it causes the 10 contents of memory address 0 to be put on the Poll List Output Bus which bus is shared by the Non-priority Poll List Memory 530 (Figure 11). This data is also available to the Microprogrammable Controller via the Source Multiplexer 832 (Figure 3), thereby allowing polling order verification.
When the Advance Priority List line 507 goes high, it causes the Priority 15 Counter 506 to be incremented to thereby point to the next poll stored in the Priority Poll List Mernory 518. To enter a poll address into the Priority Poll List, the Non-Priority List Mernory Enable line 529 must be high and the Poll List Write E~nable line 509 must also be high. Hence, when on the leading edge of clock phase ~, the output from NAND gate 20 508 goes low, generating a Priority List Write Enable, the data from the Destination Bus Holding Register 856 (Figure 23) is loaded into the memory 518 at the particular address which is specified by the then-contents of the Priority Counter 506.
A further register termed the End Priority List Register 502 is 25 provided and is utilized to hold the address of the last entry contained in the Priority List. The register 502 is adapted to be loaded frorn the Microprogrammable Controller by way of the Destination Bus when the End Priority List Register Load Enable line 501 is activated on the leading edge of a phase 5 clock pulse. The output from the End Priority List 30 ~ ~IS~743 Register 502 is applied to a first set of inputs of a 4-bit comparator 510, while the second set of inputs to the comparator arrive from the Priority Counter 506. When the first and second set of inputs become equal, the comparator 510 outputs a "1". It is to be noted at this point that the flip-flop 504 is cleared at the same time that the Priority Counter 506 is 5 cleared. If the count in register 502 is less than sixteen, its output Q4 will be low, and, hence, the output of Exclusive OR gate 512 will also be low such that inverter 514 outputs a high signal to a first input of AND
gate 516. When the count in thc counter 506 becomes equal to the count in the End Priority List Re~ister 502, AND gate 516 will be ~ully enabled 10 to thereby generate the command Priority List End Compare which is used to shift operation from priority polling to non-priority polling. If the count contained within the register 502 is sixteen, its Q4 output will be a binary "I" signal and the outputs Q3 through Q0 will be 0's. Now, when the counter 506 is cleared, there will be a match detected by the cornparator 15 510 causing its output to go high. However, AND gate 516 is disabled at this tirne because the output frorn the Exclusive OR gate 512 will be a "1"
under the assurned circurnstances. When polling has progressed through all sixteen addresses, the Priority Counter S06 overElows, causing flip-flop 504 to be clocked to its set state. Now, the output of Exclusive OR 512 20 goes low, enabling the generation o~ the Priority List End Compare command.
The addresses of the non-priority nodes are contained in a 256-word Non-priority Poll List Mernory 530. Its operation is quite similar to the above-described operation of the Priority Poll list Memory 518. That 25 is, the memory address is derived from an 8-bit Non-priority Counter 520.
As before, when this counter is cleared by a low signal on line 519, it addresses or points to the top entry in the Non-priority Poll List Memory 530.

aS~743 When the Advance N~n-Priority List line 521 goes high, it increments the counter 520 to access the next succeeding non-priority poll entry. The address of the node to be polled is put out on the Poll List Output Bus whenever the Non-priority List Memory Enable line 529 ~Fi~ure 11) goes low. 5 Writing into the Non-priority Poll List Memory 530 is under control of a flip-flop comprised of cross-coupled NAND gates 526 and 528. Whenever the Poll List Write Enable line 525 and the Priority List Memory Enable line 527 are simultaneously high, the leading edge of a clock phase 4 pulse will enable NAND gate 524, causing the output of 10 NAND gate 528 to go low, thus transferring the contents of the Destination Bus Holding Register 856 (Figure 23) into the address location in memory 530 specified by the then-contents of the Non-priority Counter 520. The leading edge of clock phase I terminates the Memory Write Enable command. 15 Shown in Figure 12 is an 8-bit counter 536, referred to as the Sub-cycle Counter, which controls the non-priority sub-cycle interval.
The counter 536 is cleared when the Clear Non-priority Sub-cycle Counter line 535 goes low and is incremented each time the Advance Non-priority List line 537 goes high. The Sub-cycle Count Register 534 is adapted to 20 be loaded by the Microprogrammable Controller via the Destination Bus on the leading edge of a clock phase 5 pulse whenever the line 531 labeled "Number of Non-priority Users Per Sub-cycle Load Enable" is selected and goes high. The output from the Sub-cycle Count Register 534 is available to the Microprogrammable Controller for verification via the Source 25 Multiplexer 832 of Figure 3.
As was earlier true with the priority list accessing circuitry, in the case of the non-priority accessing circuitry the con~ents of register 534 and the counter 536 are compared in an 8-bit comparator 538 such that when equality is detected, the output from the comparator 538 goes 30 ` -`` 11. ~151743 low, thus generating the End of Non-priority Sub-cycle Compare signal on line 539.
~Vith reference to Figure 13a, the End Non priority List Register 540 is loaded from the Microprogrammable Controller via the Destination Bus on the leading edge of a clock phase 5 signal whenever the End Non- 5 priority List Re~ister Load Enable line 577 is selected. The output from the register 540 is compared with the output of counter 520 in an 8-bit comparator 542. Hence, when these two counts become equal, the output of inverter 576 goes high. Again, the output from the register 540 becomes available to the Microprogrammable Controller for verification 10 by way of the Source hlultiplexer on Figure 3.
The polling mode is determined by the state of the flip-flop comprised of the cross-coupled NAND ga~es 548 and 550. When the output of NAND gate 548 is low, the priority polling mode is enabled and when the output of NAND gate 550 is low, the non-priority polling mode is 15 enabled. When the polling operation is first initiated, the Force Priorlty Poll line 543 is selected. Thus, on clock phase 4, NAND gate 544 is enabled and NAND gate 550 is disabled. This establishes the priority polling mode. Next, the Reset Poll List line 553 is selected. Hence, on clock phase 4, the AND gate 554 is fully enabled, causing the Non-priority 2 0 Counter 520 to clear via the output from NOR gate 570, the Non-priority Sub-cycle Counter 536 to clear due to the control signal applied thereto from the output of NOR gate 572 and the Priority Counter 506 to clear due to the control signal emanating from NOR gate 574. The foregoing events cause the first poll to be accessed from address 0 of the Priority 25 Poll List Memory 518. When that poll is complete, the Advance Poll List line 563 is selected. Because the output of NAND gate 550 is high at this time, a clock phase 4 signal will enable AND gate 566, thus generating an Advance Priority List pulse which, when applied to the Priority List Counter 506, causes it to be incremented. The flip-flop 580 is clocked at 30 ~ ~t51743 the beginnin~ of each cycle of the phase I clock pulse. Thus, its output reflects the polling mode of the previous cycle. For the priority mode, the output of flip-flop 580 is low and thus the output of inverter 560 is high. Polling proceeds sequentially to the end of the priority polling list stored in the random access memory device 518 at which time the output 5 from AND gate 516 (Figure 10a) generates the Priority List End Compare signal which is applied as a first input to AND gate 562. Hence, on clock phase 2 ANn gate 562 will be fully enabled, causing NOR gate 574 to output the command "Clr Priority Counter" which, in turn, is applied by way of line 505 to the appropriate terminal of the Priority Counter 506 10 causing it to be set to all zero's. Also, NAND gate 548 will be disabled by way of the output from the inverter 546 causing the flip-flop comprised of NAND ~ates S48 and 550 to chan~e to the non-priority polling mode condition.
The next poll will thus be accessed from address 0 of the Non- 15 priority Poll List Memory 530. The output from NAND gate 548 is now high. Thus, when the Advance Poll List line 563 is selected, the phase 4 clock pulse will enable AND gate 564, thus incrementing the Non-priority Counter 520 and the 8-bit Sub-cycle Counter 536. Because the output of flip-flop 580 will now be high, AND gate 558 will be partially enabled. 20 Then, when the Sub-cycle Counter 536 reaches its count limit, the output from comparator 538 will cause inverter 556 to output a high signal. On the next phase 2 clock pulse, AND gate 558 will be fully enabled and will cause the NOR gate 572 to output a signal for clearing the Non-priority Sub-cycle Counter 536 while simultaneously causing NAND gate 550 to be 25 disabled via the output from inverter 552. This latter action causes the mode control flip-flop (548 - 550) to revert to the priority polling mode condition.
It is to be noted that the state of the Non-priority Counter 520 remains unchanged by this action. Polling proceeds alternating between 30 5~743 the priority and non-priority mode until the end of the non-priority list is reached at which time the output from c~mparator 542 causes the output of inverter 576 to go high. When this happens, on the next phase 2 clock pulse, AND gate 568 will be enabled causing the counter 520 to be cleared via the output from NOR gate 570. When the Clear Poll/Response Enable 5 line 585 (Figure 14) goes high, the current output of the poll list is latched into a holdin~3 re~ister 586 and the state of the Non-priority List Memory Enable line coming f~om the output of NAND gate 548 is latched into a D-type flip-flop 582. The output of this flip-flop is, in turn, latched into flip-flop 584 on the next subsequent phase 1 clock pulse to thereby yield a 10 signal at its Q output indicative of whether the previous poll was a priority-type or a non-priority-type transaction.
The output from the holding register 586 is used to compare the address of the response to the address of the poll. The holding register is required since the next polling cycle is being set up while the response to 15 the previous poll is being compared. The output from register 586 is also available to the Microprogrammable Controller by way of the Source Multiplexer 832 of Figure 3.
The outputs from the Poll List Memories 518 and 530 are compared to the node address by a further 8-bit comparator 588. When 20 equality is detected, the output from comparator 588 goes low thereby indicating that the node in question is polling itself. This polling technique maintains a very high polling rate by minimizing the processing overhèad in the Microprogrammable Controller. Only a single microinstruction is reguired to generate the Advance Poll List signal for 25 each poll. The high polling rate, coupled with the ability to distinguish priority frorn non-priority nodes, assures that the priority nodes will gain access to the bus in the minimum time.

~.~S~743 CONTROL LII~E INPUT
The Control Line Inpu~ Multiplexer/Register consists of the upper byte 628 and the lower byte 630 (Figures 15a and 15b). Data is entered into these registers, either from the Control Line Decoder 130 via the CIO bus 132 or from the Mi~roprogrammable Controller via the 5 Destination Bus 172, the former being the more normal mode of operation.
When the Control Line Encoder has assembled a control word, the Control Line Input Present si~nal goes low, causing the output o~ NAND gate 603 to go high and latch via NAND gate 601. This occurs on clock phase 3.
With the output from NAND gate 601 low, the output of inverter 610 is 10 high, partially enabling NAND gate 618. Then, on the next phase 5 clock pulse, NAND gate 618 is enabled, causing clack pulses to be generated via negative OR gates 620 and 622. Since at this time both the byte I and byte 2 Control Line Input Register Load Enable lines 611 and 612 are low, the output of NOR gate 624 will be high. Thus, the output of inverter 626 15 will be low, selecting the A-inputs to the multiplexer 628 - 630. This causes the control word on the CIO bus to be latched simultaneously into both the upper and lower bytes of the Control Line Inpu t Multiplexer/Register. At this time, NAND gate 608 is also partially enabled via NAND gate 601 and negative OR gate 606 so that on the next 20 phase I clock pulse, flip-flop 612 is clocked to the set condition, indicating that a valid word is now loaded into the Control Line Input Register.
Finally, the Phase 2 clock pulse causes the output of NAND gate 601 to go high and latch via NAND gate 603, thus resetting the systern for the next control word transfer. Ei ther a Clear Valid Word signal or a Clear 2 5 Encoder Interface signal will propagate through negative OR gate 600 and inverter 602 to clear flip-flop 612.
To load the Control Line Input Register 628 - 630 f rom the Microprogrammable Controller, the Control Line Input Register Byte I
Load Enable signal on line 611 is selected, thus partially enabling NAND 30 1l~S~ 3 gate 616 and causing the B-inputs to the multiplexer to be selected via NOR gate 624 and inverter 626. The next phase 5 clock pulse will enable NAND gate 616 and negative OR gate 622 to generate a clock pulse which loads the contents of the Destination Bus into the lower byte register 630.
Similarly, on a subsequent cycle, the Control Line Input Register Byte 2 5 Load Enable signal on line 613 is selected to cause the contents of the Destination Bus to be loaded into the upper byte regist~r 628. This action also sets the flip-flop formed by cross-coupled NAND gates 604 and 605, thus enabling the next phase I clock pulse ~o set flip-flop 61Z to indicate a valid word. This flip-flop is reset on the next Phase 2 clock pulse. 10 With reference to Fi~ure 16, the Node Address Selector Switches 631 are set to define an 8-bit code identifying the node address. The node address is c~mpared to output bits 7 through 14 of the Control Line Input Register by the 8-bit comparator 632. If the node has received a poll, select or a command in which the address field of the control word 15 matches the node address, the output of comparator 632 generates the "Node Address Match" signal. This signal is used by the Sequencer PLA
when the node in question is not that designated as the Bus Controller to allow it to ignore all point-to-point transmissions which are addressed to other nodes. The address field of the Control Line Input Itegister is also 20 compared to the last poll address by an 8-bit comparator 634 to generate the "Response Address Match" signal. This signal is used by the Sequencer PLA when the node in question is the Bus Controller to verify that the responding node was, in fact, the node which had been previously polled.
Since it is possible that control line inputs occur more rapidly 25 than the Microprogrammable Controller can process them on an instantaneous basis, an elastic buffer is required. This is the function of the 16 word control line input FIFO buffer 636 of Figure 17. The FIFO
buffer is initialized by selecting the Clear Control Line Input Queue line 635 which resets both the input and output pointers in the FlFO 636. The 30 Output Ready signal (OR) of FIFO 636 will thus be low inclicating that the queue is empty. The FIFO buffer is loaded by the positive transition of the Clock B input and is unloaded by the positive transition of the Clock In input.
With reference also to Figure 18a, consider first the case where 5 the queue is ernpty and the flip-flop formed by NAND gates 670 and 672 is reset, such that the Control Line Input Word Indicator line 675 is low.
When the Control Line Sequencer PLA detects a control word which is relevant to the node, it generates a Load Processor Queue si~nal which functions to partially enable NAND gate 664. Since inverter 662 and 10 NAND gate 670 are both high at this time, the next phase 3 clock pulse will fully enable NAND gate 664, thus disabling Negative OR gate 668.
On the leading edge of the phase 3 clock pulse, the contents of the Control Line lnput Register 628 - 630 are loaded into Register 676. Since the Processor Control Line Input Queue is empty, the selection of inputs 15 for the Processor Control Line Input Multiplexer/Register 676 will be its A-inputs.
The output of Negative OR gate 668 also causes the output of NAND gate 672 to go high and latch via NAND gate 670. This indicates to the Mapping PLA that there is a new control word present and the 20 ~licroprogrammable Controller is vectored to the appropriate processing task to deal with this control word. When the Microprogrammable Controller has completed branching to the specified processing task, it initiates the Clear Control Line Input Indicator signal on line 659 which is AND'ed with a phase 4 clock signal to reset the CONTROL Line Input 25 Word Indicator flip-flop 674. If the Microprogrammable Controller completes this response before the ne%t Load Processor Queue commancl appears on Jine 663, it effectively keeps up and the queue is completely by-passed with the data flowing directly from -the Control Line Input Register 628 - 630 to the Processor Control Line Input Mux/Register 676. 30 1l~5~43 Note that outputs Q2 through Q6 of register 676 provide the control line inputs to the l\lapping PLA and also that all outputs of register 676 are available to the Microprogrammable Controller via the source multiplexer.
With continued reference to Figure 18a, consider next the case 5 where a Load Processor Queue Command on line 663 occurs before the flip-flop comprised of cross-coupled NAND gates 670 and 672 can be reset. In this case, the output of NAND gate 670 is low, thus disabling NAND ~ates 664 and 666. Since the output of NANI~ gate 672 is high, NAND gate 644 (Figure 17) is partially enabled via inverter 642 and NOR 10 gate 640. Thus, on the phase 2 clock pulse, the NAND gate 644 is fully enabled generating a Load FIFO signal via inverter 646. This causes the Processor Control Line Input Queue Empty line 637 to go high. At this time, the output of FIFO 636 corresponds to the output of the Control Line Input ~egister 628 - 630 of Figures 15a and 15b. Once there is a word 15 in the queue, subsequent control line input words will continue to be directed into the queue since the FIFO output enables NAND gate 644 via inverter 642 and NOR gate 640. It is to be noted that, now, NAND gate 664 is disabled via inverter 662 and that NAND gate 666 is par tially enabled. }lence, when the Control Line Input Word Indica-tor flip-flop 670 20 - 672 is reset, the next phase 3 clock pulse will enable NAND gate 666 which disables Negative OR gate 668 so that on the leading edge of this clock pulse register 676 is loaded. Since the Select line 677 is now high, the data is taken from the B-inputs, which correspond -to -the output of FIFO 636, thus loading the first control word queuecl into the register. At 25 the same time, the Control Line Input Word Indicator flip-flop is again set. The output of NAND gate 666 also sets the flip-~lop formed by NAND gates 6~8 and 650 (Figure 17) thus partially enclbling N~ND gate 652 so that on the next phase 4 clock pulse a FIFO Unload clock pulse is generated, advancing the pointer in the FIFO such that the output now 30 l7~3 corresponds to the next queued control word. This flip-flop is then reset on the next phase I clock pulse. This process of sequentially unloading the queue continues until the Microprogrammable Controller catches up, at which time the circuit reverts to the queue by-pass mode.

The Control Line Sequencer 14~ in Figure 2 is set out in greater detail in Figures 19a, 19b and 20 and serves to control the node's interface with the data bus system control line. It performs a pre-processing function on all control line inputs and sorts out all words that are irrelevant to this node. Only the control line words of importance to this 10 particular node will be passed on to the node's Microprogrammable Controller for further processing. This pre-processing function provides the prompt response necessary to maintain a high polling rate. The Control Line Sequencer can initiate the next appropriate transmission on the control line generally within less than 1.5 microseconds after receipt 15 of the previous transmission. If ~11 of the necessary processing were to be performed solely within the Microprogrammable Controller, it would take significantly longer and would thus reduce the efficiency of the bus control system. The key to the high speed operation of the Control Line Sequencer is the fact that it can do many operations in parallel. For 2 0 example, in a single 250 nanosecond machine cycle, it can recognize that a control line input has occurred, decode the function code, check the address field to see if it is relevant to this node and check -to see if a word should be sent out in response. Another significant feature of the Control Line Sequencer is its ability to handle all types of con trol line 2 5 transmissions, either as a Bus Controller or as a non-bus controller.

~S~7~3 The centra~ element of the Control Line Sequencer is the Programmable Logic Array 748 (Figure 19a). The Truth Table for the PLA
is shown in Table VIA below. A description of the 36 possible ou tput terms generated is shown in Table VIB and a description of the A-inpu-ts and Z outputs is shown in Table VIC. 5 - ~ ~L51'~'43 CONTROL LINE SEQUENCER PLA TRUTH TABLE
TABLE VI A

A-lnputs Z-Outputs .
Term 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 , . ,, ,.

3 0 0 X ~ 0 1 X X X X X 1 0 0 1 X 1 1 0 0 0 1 0 0 24 0 1 0 X 1 0 1 1 1 0 0 0 X X ~ X 0 0 1 0 1 0 1 0 .

CONTROL LINE SEQUENCER PLA TRUTH TABLE
TABLE VI A
. . . .
A-Inputs Z-Outputs .
Term 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 . .

0 1 X 0 1 10 1 1 X X 1 Y~ 0 0 0 0 0 1 1 1 0 0 1 All Other Input Conditions 0 0 0 0 0 0 0 0 ~IS:~r 1~3 TERM DESCRIPTION

RESPONSE QUEUED WAIT CLEAR-TO-S~ND ENABLED

SELECT QUEUED ~ WAIT CLEAR-TO-SEND
4 NO INPUT BUS CONTROLLER CO~MAND QUEUED -SELECT ~UEUED POLL QUEUED WAIT CLEAR-T~-SEND
VALID WORD WAIT STATUS RESPONSE

VALID WORD WAIT BROADCAST STATUS RESPONSE

COMMAND NODE ADDRESS MATCH
14 VALID WORD ~ WAIT BUS CONTROLLER BROADCAST -RESPONSE
VALID WORD WAIT BUS CONTROLLER BROADCAST -RESPONSE

COMMAND POLL ~ NODE ADDRESS MATCH
17 VALID WORD WAIT ~ BUS CONTROLLER POINT-TO-POINT
COMMAND POLL NODE ADDRESS MATCH
18 VALID WORD WAIT BUS CONTROLI,ER POINT-TO-POINT
COMMAND POLI, NODE ADDRESS MATCH

COMMAND POLL ' NODE ADDRESS MATCH ENABLED
VALID WORD WAIT BUS CONTROLLER POINT-TO-POINT
COMMAND POLL NODE ADDRESS MATCfl DISABLED

~ IS1l743 (continued) TE.RM DESCRIPTION
21 VALID WORD WAIT BUS CONTROLLER POINT-TO-POI~T
COMMAND SELECT NODE ADDRESS MATCH DISABLED
22 VALID WORD ' WAIT BUS CONTROLLER POINT--TO-POINT
COMMAND POLL NODE ADDRESS ~ATCH ~ COMMAND QUEUED
ENABLED CLEAR-TO-SEND
23 VALID WORD WAIT BUS CONTROLLER ~ POINT-TO-POINT
COMMAND POLL ' NODE ADDRESS MATCH ~ COMMAND QUEUED
ENABLED ~ CLEAR-TO-SEND
24 VALID WORD ~ WAIT ~ BUS CONTROLLER ~ POINT-TO-POINT
CO~M~ND ' POLL NODE ADDRESS MATCH CLEAR-TO-SEND
VALID WORD ' WAIT BUS CONTROLLER ~ BROADCAST -RESPONSE
26 VALID WORD WAIT ' BUS CONTROLLER BROADCAST -RESPONSE
27 VALID WORD WAIT ~ BUS CONTROLLER ' POINT-TO- POINT
COMMAND NODE ADDRESS MATCH
28 VALID WO,RD ~ WAIT ~ BUS CONTROLLER ~ POINT-TO-POINT
COMMAND ~ NODE ADDRESS.MATCH
29 VALID WORD ~ WAIT ' BUS CONTROLLER BROADCAST ~
RESPONSE RESPONSE ADDRESS MATCH CLEAR-TO-SEND
VALID WORD WAIT BUS CONTROLLER ~ BROADCAST ~
RESPONSE RESPONSE ADDRESS MATCH CLEAR-TO-SEND
NOTHING QUEUED
31 VALID WORD WAIT BUS CONTROLLER BROADCAST ~
RESPONSE ~ RESPONSE ADDRESS MATCH CLEAR-TO-SEND ' COMMAND QUEUED
32 VALID WORD ' WAIT ~ BUS CONTROLLER ~ BROADCAST
RESPONSE ' RESPONSE ADDRF,SS MATCH ~ CLEAR-TO-SEND
COMMAND QUEUED SELECT QUEUED
33 VALID WORD ' WAIT BUS CONTROLLER BROADCAST
RESPONSE RESPONSE ADDRESS MATCH CLEAR-TO-SEND
COMMAND QUEUED ~ SELECT QUEUED - POLL QUEUED
34 VALID WORD WAIT ' BUS CONI'ROI.,LER ~ BROADCAST -RESPONSE RESPONSE ADDRESS MATCH
IDLE (all other in~ut conditions) CONTROL LINE SEQUENCER PLA
STATE DESCRIPTIONS

TABLE VI B

~ IS~IL743 INPUTS

A13 0 = NODE ADDRESS MATCH
A12 0 = RESPONSE ADDRESS MATCH
All SEQUENCER WAIT FLAG
A10 FIRMWARE FLAG 1 (BUS CONTROLLER) A9 CONTROL LINE INPUT REGISTER OUT BIT 2 (ADDR~SSING MODE) A8 CONTROL LINE INPUT REGISTER OUT BIT 7 (FUNCTION CODE 3) A7 CONTROL LINE INPUT REGISTER OUT BIT 6 (FUNCTION CODE 2~
A6 CONTROL LINE INPUT REGISTER OUT BIT 5 (FUNCTIO~ CODE 1) A5 CONTROL LINE INPUT REGISTER OUT BIT 4 (FUNCTION CODE 0) A4 CL~AR-TO-SEND
A3 FORCED COM~ND ENABLE

Al SELECT ENABLE/DISABLE

OUTPUTS

Zl SET AUTO LOOP ERROR FLAG

CONTROL LINE SEQUENCER PLA
INPUTS & OUTPUTS

TABLE VI C

PLA input term Al5, "Auto Loop Error Flag" is set by PLA
output Zl and is cleared by a control signal ~rom the Microprogrammable Controller. PLA input Al4, "Valid Word" is set whenever a new control word has been loaded into the Control Line Input Register and is cleared by output Z5 when the Control Line Sequencer has processed the word. 5 Inputs Al3 and Al2, the "Node Address Match" and "Response Address Match" signals, have been previously described. Sequencer input All, "Sequencer Wait Flag", is set and cleared by control signals from the Microprogrammable Controller. Additionally, it can be cleared by PLA
output Z4 and is set by hardware when a poll is sent by the Bus Controller 10 or a response is sent by a Non-Bus Controller node. Its function is to indicate to the Control Line Sequencer that a control word is expected.
Input Al0 is the "Microprogrammable Controller Firmware Flag 1". When it is in the 0 state it indicates to the Control Line Sequencer that the node is not the Bus Controller. When it is in the l state, it indicates that 15 the hode is the Bus Controller. Input A9 is the "Control Line Input Register Output Bit 2" which indicates the addressing mode of the received control word. PLA inputs A5 through A8 correspond to Control Line Input Register Outputs 4 through 7, respectively, which comprise the Control Word Function Code bits 0 through 3, respectively. Input A4, 20 "Clear-to-Send" indicates that the control line ;s available for transmission. Inputs A0 through A3 are flags which are set or cleared by the Microprogrammable Controller via the hardware control signals.
PLA outputs Z7 and Z6 perform the selection of the source for the control line output word as previously described. They are used in 25 conjunction with the "Clear-to-Send" word to cause a transmission of either a poll, response, select or command. Output Z3, "Load Processor Control Line Input Queue", causes the transfer of the control word in the Control Line Input Register either into the Control Line Input Queue or into the Processor Control Line Input Register as previously described. 30 1..~15~743 Output ZO, "Poll/Resp~nse Timeout Control", is used to reset the Timeout Control Counter initiated by the last poll. It can thus be seen that the PLA outputs perform three simultaneous functions - transmission of the appropriate control word (bits Z7, Z6 and Z2), hand~ff of relevant control words to the Micropro~rammable Controller (bits Z5, Z3) and error 5 detection (bits Z4, Zl and Z03. Input pre-processing is only performed if PLA input Al4 is set and output words are transmitted only if PLA input A4 is set. Thus, if both of these inputs are 0, the PLA output Term 35 will be generated which is an idle or do-nothing state. If the Auto Loop Error Fla~ is set, each valid word is passed onto the Control Line Input 10 Queue, however all other sequencer functions are suppressed. This feature permits the Microprogrammable Controller to assume all functions of the Control Line Sequencer, albeit at a degraded level of performance. Sequencer output terms 1 through 4 generate command, response, select or poll transmissions, respectively, while output term ll 15 generates a forced command, irrespective of the state of the Sequencer Wait Flag. Output terms 5 through lO are generated for various illegal or illogical control word transmissions. Each of these terms causes the Auto Loop Error Flag to be set. Output terms 12 through 24 are involved with processing control line inputs for the non-bus controller mode while 2 0 output terms 25 through 34 perform the same function for the bus controller mode. Output terms 12 and 13 are examples of the Control Line Sequencer screening out irrelevant control line words and effectively ignoring them by not activating output Z3.
The parallel operation of the Control Line Sequencer is 25 exemplified by output term 33 in which a response has been interpreted, verified, and the response address has been matched. Thus, the response is passed onto the input queue, the next poll is transrnitted and the poll response timeout is reset. With this action performed by the Control Line Sequencer, the Microprogrammable Controller can now use the time of 30 ~ ~15~ 43 transmissiol~ of -the poll and its associated response to generate the next control word to be transmitted without incurring any processing overhead in the bus arbitration cycle.
With reference to Fi~ure 19a, upon each phase I clock pulse, the output terms of the Control Line Sequencer PLA are latched into 8-bit 5 latch 750. The oùtputs of this latch direct the execùtion of the current control line sequence while the inputs to the PLA are being set up for the next control line sequence. If the Ql output of latch 750 is low, indicating a Set Auto Loop Error condition, it will set one of the flip-flops in the Quad Latch 770 to generate the PLA input term A15, "Auto Loop Error 10 Flag". If the Microprogrammable Controller selects the "Clear Auto Loop Error Command" signal on the next phase I clock pulse, NAND ~ate 700 will be enabled and the Auto Loop Error Flag will be cleared via NAND
gate 718. Alternately, this flip-flop can be cleared by a Master Clear signal. 1 5 PLA input A-ll "Sequencer Wait Flag", is generated by a flip-flop in the Quad Latch circuit 786. This flip-flop can be set by the Microprogrammable Controller by selecting the Processor Set Sequencer Wait Flag which propagates through NAND gate 712 and Negative OR gate 726. Alternately, the flip-flop can be set by th* ~I-ar ~ I/Response 20 Enable signal. The "Sequencer Wait Flag" can be cleared by PLA output Z4 via Negative OR gate 728 or, alternately, it may be cleared by the Microprogrammable Controller via NAND gate 714 and Negative OR gate 728. PLA input A2, "Command Enable Flag", is generated by the output of another flip-flop in the Quad Latch 770. This flip-flop is set by the 25 rnicroprogramrnable controller via NAN~ gate 702. When this flag causes a command to be generated, e.g., I?llA term 1, the outpu-ts of latch 750 will be as follows:
Q7 = 0.
C~6 = 0.
Q2=1. 30 . ~.. 15~l743 Thus, the phase 3 clock pulse will enable NAND gate 764 (Figure 19a) which will clear the command enable Elag via Negative OR gate 720.
Alternately, the flag can be cleared by the Microprograrnmable Controller via NAND gate 704 and Negative OR gate 720. PLA input Al, "Select Enable Flag" is generated by two other flip-flops in Quad Latch 770. This 5 flag can also be set and cleared by the Microprogrammable Controller in the manner previously described. When the Select Enable Flag generates a select, e.g., PLA term 3, the outputs Q7, Q6 and Q2 of latch 750 will be all l's. Thus, the phase 3 clock pulse will enable NAND gate 766 to clear the Select Enable Flag via Negative OR gate 722. PLA input AO, 10 "Poll/Response Enable" is generated by still another flip-flop in Quad Latch 770. This flip-flop may be set or cleared by the Microprogrammable Controller in the manner previously described. If a poll is generated, e.g., PLA term 4, the outputs Q7, Q6 and 02 of latch 750 will be 1,0,1, respectively. Since Exclusive OR gate 762 is enabled, 15 NAND gate 768 will also be enabled on clock phase 3, causing the Poll/Response Enable Flag to be reset via Negative OR gate 724. If a response is generated, e.g., PLA term 2, the outputs Q7, Q6 and Q2 of latch 750 will be 0,1,1. Again, Exclusive OR gate 762 is enabled and the flag is cleared as before. Ihe aforementioned flag resets assure that the 20 PLA will execute each event only once each time the respective flag is set. Finally, PLA input A3, "Forced Command Enable Flag", is generated by another flip-flop in Quad Latch 786. It is set and cleared in the same manner as a Command Enable line. All of the flags employed by the PLA
can be cleared by the Master Clear signal via Negative 01~ gates 720, 722, 25 724, 726, 728 and 730. If the output of NAND gate 745 (Figure 19b) is low, the Control Line Sequencer is disabled since latch 750 is maintained in a cleared condition. This will be accomplished by a ~aster Clear signal via Negative OR gaté 741 or from the Microprogrammable Controller via NAND gate 737. Alternately, the Microprogrammable Con-troller can 30 enable the Control Line Sequencer via NAND gate 739.

l~S~L743 THE CONTE~OL LINE DISPATCH QUEUE
~eferring to Figure 21, the Dispatch Queue Input Multiplexer 800 is used to control the selection of the source of the queue input data.
Specifically, selection is accomplished by two control signals Irom the ,~1icroprogrammable Controller, i.e., the "Load Request Queue with 5 Destination Bus" signal and the "Load Request Queue with Node Address"
signal. When both of these aforementioned signals are low, the normal source is selected, i.e., the Processor Control Line Input Register. This causes bits 7 through 14 of the Processor Control Line Input Register 628 ~Figure 15a) to appear at the outputs 0-7 of the Dispatch Queue Input 10 Multiplexer 800. Bits 7 through 14 of the Processor Control Line Input Register correspond to the node address field of the responding node. If the "Load Request Queue with Destination Bus" signal is selected, the outputs of Multiplexer 800 will correspond to the contents of the l~estination Bus Holding Register 856 (Figure 23) and if the "Load Request 15 Queue with Node Address" signal is selected, the outputs of multiplexer ~00 will correspond to the data represented by the Node Address Switch E~egister. The output from rnultiplexer 800 provides the input for two first-in, first-out (FIFO) buffer mernories, one being for priority queues and the other for non-priority queues. All data transfers in and out oE 20 these queues is under the control of the Microprogrammable Controller.
With reference to Figures 22a and 22b, the case where data is being loaded into the 16-word Priority Dispatch FIFO 811 will first be considered. In this case, a microinstruction is executed which causes the Priori-ty Queue Enable line 813 to go low and the Load Register Queue 25 with Control Line Register line 815 to go high. It is to be recalled at -this point that the former signal is deterrnined by microinstruc-tion bit 51 while the latter signal is determined by a clecode of bits ~1 to 50 of the rnicroinstruc-tion. Thus, both conditions can be simultaneousl~ and independently selected. These conditions partially enable the negative 30 NAND gate 804 such that on the leacling edge of clock phase 4, the output of gate 804 goes positive, to thereby clock the FIFO store 812 which loads the data from the l~ul-tiplexer 800 into the next address of the buffer.
The same type of action will occur by way of NOR gate 802 if either the destination bus or the node address are selected as data sources. Should 5 the Priority Queue Enable line 813 be high, negative NAND gate 804 will be disabled and, instead, negative NAND gate 808 will be enabled, causing the data to be loaded into the 16-word Non-priority Dispatch Queue 819.
(See Figure 22b).
The foregoing arrangement permits the addresses of nodes 10 requiring service to be sorted on a priority and on a non-priority basis and to be buffered so as to wait for available time on the Data Bus to be selected. This method of queuing assures a high utilization of the Data Bus and also assures that the response time for priority nodes will be unaffected by non-priority traffic. 15 To unload data from the Priority Dispatch FIFO 811, the Priority Queue Enable line 813 must be low, thus enabling the DOo to DO7 outputs of the FIFO buffer 811. The output data will, thus, be the first word entered into the FIFO stack. If the Unload Request Queue line 805 is selected, then on the leading edge of the next phase 4 clock pulse, the 20 output of NAND gate 806 will go low and on the trailing edge of that sarne clock pulse, the FIFO will be advanced causing the next word contained therein to be read out.
If the Priority Queue Enable line 813 is high and the Unload Register Queue line 805 is selected, NAND gate 816 (Figure 22b) will be 25 enabled instead of the NAND gate 806. This causes the ou-tput to be generated by the Non-priority FIFO 81g. Each of the F;IFO stacks 811 and 819 have tri~state outputs, and, as such, the output lines can be wire OR'ed together and presented as inputs to the Selec-t f~egister ~80 of Figure 9. 3 o ~ ~t5~ 43 DESTINATIOI'~ BUS HOLDING REGISTER
In ce~-tain cases, it is not possible for the Microprogrammable Controller to transfer data to a node register in a single microins~ruction.
In this case, the data is developed in the first microinstruction and transferred to the Destination Bus Holdin~ Register 856 (Fi~ure 23) by 5 selecting the Destination Bus Holdin~ Register Load Enable line 855. The data is thus latched into this register and a subsequent microinstruction can issue the necessary control signal for routing it to its ultimate destination.

The Control Line Activity circuit determines which of the six Stub Transceivers 100 - 110 is transmitt ng control information. This information is required to permit reconfiguration if a fault on any of the active channels isolates the BUS Controller from all or part of the rest of the system. Alternately, it permits a node to automatically lock onto the 15 active control cable after a master clear Discrimination between rnessage and control transmissions is possible since all control transrnissions are 16 bits long while message transrnissions are between 32 ~nd 40~6 bits long. One-shot type timing components 1054 and 1056 (Figure 31) are chosen such that one-shot 1052 will generate a 1.4 2 0 microsecond output pulse, while timing components 1060 and 1062 are set such that one-shot 1058 will develop a 500 nanosecond output pulse. A
transmission on cable 6 will cause the Stub Receive Envelope 6 signal to be low, thus triggering one-shot 1052. Subsequently, 1.4 microseconds later, one~shot 1052 resets and one-shot 1058 is triggered by the positive 25 transition of the Q output of one-shot 1052. Then, 500 nanoseconds after this event, one-shot 1058 resets. At the end of the Transmission Stub Receive Envelope 6, line 1063 goes positive, clocking latch 106l~. If the length of the transmission is less than 1.4 microseconds, one-shot 105~ will still be set- when latch 1064 is clocked. Thus, output QB will be high, 30 indicatin,, a noise hit. This signal is op-tional and is not used in this particular configuration.
If the length of the transmission is greater than 1.4 microseconds but less than 1.9 microseconds, one-shot 1058 will be set at the time that latch 1064 is clocked, thus the output QC will be high, indicating control 5 activity on cable 6, since control transmissions are nominally 1.6 microseconds in width. If the transmission is longer than 1.9 microseconds, one-shot 1058 will have reset before latch 1064 has clocked.
Thus, the output QD ~,vill be high, indicating message activity. This is an optional signal which is not used in this configuration. Circuits 1068 1 0through 1076 are replications of the aforementioned Activity ~1Onitoring circuit which serve to sense the conditions of cables 1 through 5. The outputs of these six circuits are logically combined with the Control Line Activity Mask Register 852 (Figure 23) to develop the Control Line Activity Indicator Flag at the output of Negative NOR gate ~70. The 15 outputs can also be individually sensed by the Microprogrammable Controller via the Source Multiplexer 832 (Figure 3b).
If the Activity Mask Register Load Enable line 857 is selected, ANU gate 850 will be enabled on the next clock phase 5 to thereby clock the contents of the Destination Bus into the Activity Mask Register 852. 20 It can be seen that the outputs of this last-mentioned register control the NAND gates 858, 860, 862, 864, 866 and 868 to selectively mask the six Control Line Activity Indicator lines shown enclosed by bracket 859.
In normal operation, only one Control Line is active at any given time. In this case, the Activity Mask Register 852 is set such that only 25 the NAND gate corresponding to the active line is clisablecl. With no activity on the other lines, the output of NAND gate 870 is low. If control line activity occurs on an unrnasked line, the corresponding NAND
gates 858, 860, etc., will be enabled, thus causin~ the output of Negative NOR gate 870 to go high, generating a so-called Control Line Activity 30 ~ ~51r~3 Indicator Flag at its output. In the event of a malfunctioning line indicating a false control line activity, the i~Jlask Register 852 can be altered to additionally mask out the malfunctioning line. These Eeatures are employed in the reconfi~uration of the overall bus system. On the leading ed~e of clock phase 1, the output from NAND gate 870 is latched 5 into a flip-flop 871 to thereby form the Latched Control Line Activity Indication Flag at the Q output thereof.
- CONTROL LINE DECODER
The Active Bus Number (ABN~ register 922 controJs the vectoring of the stub transmit and receive signals for both the Control 10 Line and the l\lessage Line. It is reset to 0 by 2 ~Aaster Clear pulse. If the ABN Register Load Enable signal is selected, the phase 5 clock pulse wlll fully enable NAND gate 920, causing the contents of the Destination Bus to be loaded into register 922. Outputs Q0 through Q2 of register 922 determine the selection of the Control Line Stub cable whiiè outputs Q3 15 through Q5 determine the selection of the Message cable. The outputs of register 922 perform the selection of the Stub Receive Envelope signal frorn the designated Control Line cable via a Control Envelope Mul tiplexer 924. The same outputs select the stub Manchester Data Signal from the sàme stub receiver via Control Data Multiplexer 926. The 20 envelope and data signals are converted into data and clock signals by the Manchester Decoder 928. Since the implementation and the functions performed by circuits 928 through 936 are well understood by those skilled in the art, they are shown in block diagram form in Figure 24 for the sake of brevity. 2 5 Initially, the 16-bit shift register 930 is cleared and the clock is enabled. When a Control Line input is received, data is shifted into shift register 930 until on the 16th clock pulse the "sync" bit is shifted into the last bit of the shift register, stage SR0. This action disables the clock and freezes the word in the shift register 930. The Receive C Envelope signal 30 ~` ~15~743 is also presented to the input of a further sllift regis-ter 952 (Figure 26).
This circuit is clocked by a 10 MHz clock signal in which the leading edge thereof corresponds to the trailing edge of a 20 MHz clock. Shift register 952 is used to generate three control signals which are delayed from the trailing edge of the Receive G Envelope signal. The first clock pulse 5 after the trailing edge of the Control Line Envelope causes output Q3 of 952 to set. If the ~syncl~ bit is properly positioned in the register 930, NAND gate 954 will be enabled. Then, on the next clock pulse, output Q2 of shift register 952 will go low, thus disabling NAND gate 954 and causing the contents of register 930 to be latched in the 18-bit latch 934. 10 Also, flip-flop 962 is clocked at this time. Normally the J input of this flip-flop should be low at this time. If it is not, it indicates that the previous word has not been unloaded by the Control Line Sequencer and therefore flip-flop 962 sets to generate the Bad C Word Overlap signal.
With outputs Q3 and 0~2 of shift register 952 both equal to "1" at this time, 15 the NAND gate 956 will be enabled if the "sync" bit is missing, thus generating the Bad C 'Sync signal. On the next clock pulse output, Ql of .

shift register 95Z goes high. Since the Q0 output is also high at this time, NAND gate 958 is enabled, generating the Clear Control Line'' Shift' Register signal which clears shift register 930, thus initializing it for the 20 next input.
On the next clock pulse, the Q0 output of shift register 952 goes low thus disabling NAND gate 958 and clocking flip-flop 960. The least significant bit of latch 934 is forced to a 1. Thus, if it has been clocked the "C Word Waiting for IO" signal will be high and flip-flop 960 will 25 therefore be set generating the "Encoder/Decoder CR" signal. The "Control CT" signal is normally high at this time. Hence, the tri-statebuffer 936 is enabled via NAND gate 964 such that the data in the upper 16-bits of latch 934 is present on the Cl/O Bus.

'17~3 When the Control Sequencer has capturecl the control word, the "Control CT" signal goes low thus causing the î'Release C to lO Bus'l signal to also go low via inverters 976 and 980 (Figure 27). This causes the data in latch 934 to be cleared, initializing it for the next input word.
Again with reference to Fi~ure 24, the control word parity is 5 checked by Parity Check circuit 932 and this data is latched along with the control word in the bit 1 position of an 18-bit latch 934 to generate the "Bad Parity" signal. To transmit a control word, the Control Line Sequencer first sets the "Control CT" line to 0. This disables buffer 936 and permits the Control Line Sequencer to place the control word to be 10 transmitted on the CI/O bus.
Shift register 974 (Figure 27) assures that the required time gap is maintained between control words. If a control word envelope is detected or if the control word transmitter is on, the output of NAND
gate 968 will be high, thus maintaining shift register 974 in a cleared 15 condition via inverter 970. When the control line next goes inactive, NAND gate 96~ is enabled and the Clear of shift register 974 is released.
rhe shift register is then clocked on the trailing edge of the C Control Clock pulse which is a 10 rnegahert~ signal in which the leading edge corresponds to the trailing edge of alternate 20 rnegaherti~ clock pulses. 20 Each successive clock pulse will then cause the stages of shift register 974 to set, starting with output Q5 and proceeding to output Q0. Outputs Q3 to Q0 of shift register 974 are connected to poles I through 4 of a switch 981, respectively. Output Q0 becomes one of the inputs to AND
gate 978. If the Control Line Sequencer has a word ready to send, the 25 "Control CT" line 975 will be low and the Control ~C line 977 will be high. Thus, six clock pulses after the control line has becorne idle, AND
gate 978 will be enabled. On the leading edge of the next clock pulse, flip-flop 982 is set generating the "Send C" signal. In this manner, swi-tch 981 permits the control word gap to be set from 0.6 nanoseconds to 0.9 30 1l15~743 nanoseconds in 100 nanosecond increments depending on the jumper connection used as indicated in the legend adjacent the switch in Figure 27. The "Send C" signal causes the data on the C/IO bus to be loaded into Control Line Transmit Register 940. It also causes flip-flop 9~6 to be set on the next cJock pulse, thereby ~enerating the "Transmit Sequencer 5 Enable" si~nal ~ia inverter 988.
On the next clock pulse, flip-flop 990 is set, generating the "Transmitter C On" signal. Upon the generation of each clock pulse, Control Line Transmit Sequencer 942 (Figure 25) generates a new ~-bit select code, causing the Control Line Transmit Bit Selector 944 to 10 successively select each bit of the control word from the lowest order to the highest order. This data is presented to the Control Line Manchester Encoder 946 which converts it to the well-known Manchester biphase data format.
When all 16 bits have been selected, the Control Line Transmit lS
Sequencer 942 generates the transmit "Sequence Complete" signal which subsequently causes flip-flops 986 and 990 (Figure 28) to reset and thus turn off the transrnitter. The "Transmit C On" signal is re-synchronized with the 20 rnegahertz clock within the encoder 946 to generate the Control Transrnitter On signal. 20 Control Decoder 1000 (Figure 29) provides the signals which route the control transmission to the designated stub transmitter.
Control Stub Selects A, B and C form a 3-bit code which causes the corresponding decoder 1000 output to go low. If, for exarnple, the select code were 1,1,0, output 6 of the decoder 1000 would cause the output of 25 inverter 1004 to go high, thus selecting Stub Transmitter J~6 for control transmissions. Message Decoder 1002 performs the same function, i.e., to select the transrnitter for message data. Assurning this clecoder has selected a line other than output 6, inverter 1006 will be low. Thus, when the Control Transmitter ON line 1007 goes low, the output of NAND gate 30 1008 will go high, thus enabling NAND gate 1014 to generate the '~Stub . _ _ .
Transmitter 6 On" signal. If output 6 is selected by the l\lessage Decoder 1002 but not by the Cantrol Decoder 1000, then the output of inverter 1006 will be high and the output of inverter 1004 will be low. This will result in NAND gate 1014 being enabled when the Message Transmit On line 1005 5 goes low. If line 6 is not selected by either the Messa~e or the Control Decoder, NAND gate 1014 will be disabled via OR gate 1010. If line 6 is selected by both the Control Decoder and the Message Decoder, NAND
gate 1014 will be disabled by either NAND gate 1008 or 1012 since both the Message Transmit On line 1005 and the Control Transmit~ On line 1007 10 cannot both be low at the same time. Thus, transmission is inhibited for this condition. Circuits 1016 through 1024 constitute five other replications of logic gates 1004 through 1014 and provide the selection signals required for the other five stub transmitters. Because of their identical construction, a detailed explanation of their operation is deemed ~ 15 unnecessary.
If stub 6 is selected by the Control Decoder 1000, the Manchester control data is routed via NAND gate 1026 and AND gate 1032 (Figure 30) to Stub Transmitter 6. If stub 6 is selected by the Message Decoder 1002, the Manchester message data is routed via NAND gate 1030 and AND gate 2 0 1032 to Stub Transrnitter 6 If stub 6 is not selected by either decoder, NAND gate 1032 is disabled via OR gate 1028. Circuits 1032 through 1040 are replications of logic gates 1026 through 1032 which provide the data routing for the other five stub transmitters. The details of the communication and control for the Message Encoder/Decoder are 25 virtually identical to those of the Control Decoder/Encoder, the only distinction being the additional features required to handle the multiple word transmissions for the message Encoder/Decoder Therefore, a detailed discussion of this circuitry is not deemed necessary.

~ 15~743 i3US AR~ITRATION SEQUENCE
Figure 32 shows a flow diagram of the sequence of events which occurs principally in hardware to accornplish the bus arbitration while Figure 33 is a flow diagram of the firmware running in the Microprogrammable Controller which supports the bus arbitration. This 5 separation of hardware and firmware into two flow diagrams has been done to clarify the operation, however it should be understood that the firmware and hardware operate very interdependently arid concurrently.
This description will relate the events described in the two flow diagrams to the relevant circuitry of the node starting with the first event for the 10 Bus Controller node, i.e, the Sync/Parity Error Detection represented by block 1104. The arbitration cycle is entered at the point where the Bus Controller is receiving a response from a responding node. The data passes through one of the six Stub Transceivers, for example, Stub Transceiver 100 of Figure 2a, through the Data Multiplexer 926 of Figure 15 24, the Manchester Decoder 928, the 16-bit shift re~is-ter 930, the parity is checked on Parity Checker 932 and the data and parity is assembled in 18- -bit latch 934. The control word is then transmitted via buffer 936 and the CIO bus 132 to the Control Line Input Multiplexer/Re~ister 628 and 630 (Fi~ure 15a). When the control word has been latc:hed in-to registers 628 20 and 630, the address verification and control channel protocol error detection step represented by block 1106 of Figure 32 can commence. The control line address field is compared by the Response Address Match Circuit 634 (Figure 16) to provide an input to A13 of the Control Line Sequencer PLA 748 to perform the address verification test. The 25 instruction field of the control word is presented to inputs A5 through A9 of PLA 748 which are examined to perform the protocol error detection test. Circuits 952, 'J56j 958, g60, C)62 of Figure 26, 4l~, 446, 448, 450, 452, 454 of Figure 7a, 600, 602, 606, 608 and 612 of Figure 15a are ernployed in the manner previously described to determine that a valid 30 ~ ~51743 error-free control word has been generated. This status signal is presented to input A14 of PLA 748 (See Table Vl C). The block 1108 of Figure 32 labeled ~Error or Ignore Input~ cc~rnprises a test performed by PLA 748. As has been previously described, the various A-input terms to this PLA will cause the corresponding output terms shown in Table Vl C to 5 be generated to thereby initiate various node actions. If PLA 748 (Figure 19a) detects an error, the so-called Auto Loop Error Flag will be set via the output of stage Ql of latch 750. The process loops back to the event representecl by block 1104, in which the firmware error recovery is initiated as represented by block 1110. All error conditions, including the 10 Auto Loop Error Flag, are OR'ed together via gates 200, 202, 204, 206, 208, 210 of Figure 4 and D-type latch 220 to provide the Error Flag input A15 of Mapping PLA 224. Thus, any error flag will cause the firmware to branch to the error recovery routine.
If a valid error-free response has been received, the operation 15 entitled "Store Response in Control Channel Input Register" (block 1112) will be executed. PLA 748 generates a "Load Processor Queue" signal via Q3 of latch 750 (Figure 19a). This causes the control word bytes in registers 628 and 630 tFigures lSa and 15b) to be loaded into the Control Line Input FIFO 636 of Figure 17. If the FIFO is ernpty, the control word 20 bypasses the FIFO and is loaded directly into the processor Control Line Input Multiplexer/Register 676 as previously described. Either of these events initiates the "Firmware Response Processing" indicated by block 1114. This operation will be examined in greater detail in the description of the arbitration algorithm flow diagram of Figures 33a and 33b. The 25 "Select-to-Send" decision indicated by block 1116 is perforrned by PLA 74 as previously described. If the firmware processing of a previous response has queued a select, the event 1118, which is the transmission of this select, is initiated. As previously described, selects are unloaded from the Dispatch Queue, first in order of priority, then in order of age. Thus, 30 t~t~

the address of the next node to be selected will be present at the output of either Dispatch Queue 811 or 819. This address is transferred to the Select Register 480 and passes via Control Line Output Multiplexer 400 and CIO bus 132 to the Control Line Transmit Register 940. Bits 2 through G of the Control Line Output Multiplexer 400, which represent the S
function code, are forced to a 11011 code indicating a select. Parity and sync bits as well as addressing mode bits are added to complete the formation of the control word in the Control Line Transmit Register 940 of Figure 25. The Control Line Transmit Bit Selector 944 converts the control word to a serial bit stream which is passed through Manchester 10 encoder 946 to generate the biphase Manchester data format. This propagates through the selected data path, for example, gates 1026 and 1032 in Figure 30, to the selected Stub Transceiver, as, for example, transceiver 100, to its associated BAM and thus it is transmitted to the other nodes. 15 If there is no select to be sent, event 1118 is bypassed as represented by line 1117 and the node operation proceeds to the next event represented by block 1120 which is the transrnission of the poll. This is similar to the previous event except that the source of data Eor the node address field is either Poll List 518 or 530, depending upon whether 20 priority or non-priority polls are being generated. In this case, the control word function code is set to binary value 11001 which corresponds to the poll command. The control word is passed from the Control Line Output Multiplexer l~00 to the selected BAM in the same manner as previously described. This completes the description of all events associated with 25 the Bus Controller node.
Propagation delay block 1122 is indicative of the delay encountered on the serial data bus before a rnessage is received by the addressed non-bus controller node. The delay, typically in the range of from .I to 2 microseconds corresponds to nodes which are nearest or 30 ~5~7~3 furthest from the ~us Controller, respectively. The non-bus controller nodes have the identical hardware and firmware structure as the Bus Controller. The only difference between the two is that the Bus Controller Flag is not set in the case of the non-bus controller nodes.
This results in the generation of different output terms for both the 5 Control Line Sequencer PLA and the Mapping PLA. Thus the Sync/Parity ~rror Detection represented by block 1124 is identical in all respects to the event described above in connection with block 1104.
The next event, t'Address Verification Control Channel Protocol Error l~etection" (block 1126) is very similar to the event described for 10 block 1106, the only difference being that protocol errors are detected in the context of a non-bus controller. For example, if event 1106 detects a poll, that would be considered an error while the detection of a response by event 1126 would likewise be considered an error. While address verification described in connection with event 1106 involved cornparing 15 the response to the previously polled address, address verification in event 112~ cornprises the comparison of the address in the control word to the node address via Comparator 632. In the normal mode of operation, the ~us Controller would generally expect to get a previous address response match, while the non-bus controller would expect to ge t many 2 0 transmissions which do not match the node address. The Error or Ignore Input decision block 1128 signifies an operation essentially identical to that represented by block 1108 causing the node to loop back to operation 1124 when there is not an address match and thus ignore all polls or selects which are not addressed to that par-ticular node. Sirnilarly, an error 25 invokes both the loop back operatiorl just mentioned as well as initiating Firmware Error Recovery as represented by block 1132, all in the same manner as described for the event represented by block 1110.
Event 1130, "Store Input in Control Channel Input Regis-ter" is identical in all respects to the previously described event 1112. Event 1136, 30 ~. ~ S ~ ~ 4 ~

Firrnware Control Channel Processing is similar to event 1114, but is agai performed in the difIerent context of a non-bus controller. The control word function code is tested as indicated by decision block 1134 to determine whether or not it is a poll. As before, this decision is perIormed by generating appropriate output terms from the Control Line 5 Sequencer PLA 748. If the control word is not a poll, no further action is required by the Control Line Sequencer, although the word is passed on to the Micropro~rammable Controller for processing. (See Figure 33.) Therefore, the output term thus generated effectively causes the non-bus controller to loop back to the beginning of operatisn 1124 and to wait for 10 the next control line transmission. If a poll is detected, the event represented by block 1138 is executed to generate the required response.
This event is similar to event 1120 except that bits 2, 5 and 6 of the control word are forced to 0, 1, I respectively to indicate that this is a "response" format and the two bits of the Kesponse Re~ister 138 of Figure 15 2a are inserted in control word bit positions 3 and 4. Response codes 0,0;
0,1; 1,0 and 1,1 indicate node fault, no request, normal request and irnrnediate request, respectively. Once the response has been transmitted, the Response Register is reset to an 0,1 code to indicate "no request" (see block 1140). This assures that the node makes only one 2 0 request for service even though that request may still be in a queue at the Bus Controller at the time the node is again polled. Event 1142 (Propagation Delay) is identical in all respects with event 1122 previously explained. The response is received by the Bus Controller in block 1104 as represented by the broken line path 1143, thus cornpleting the arbitration 25 cycle.
The effect of this arbitration cycle is to create a control linkage between firmware running in the Bus Controller and firmware running in the polled node. This linkage is established between the ~us Controller node and all other nodes on the serial data bus. It is to be noted that none 30 - 1 15~f~3 of the firmware processing is an in line event in the arbitration cycle.
Each transmission by either node is queued and ready to go by processing which has been done in the time required for the previous transmission.
Since the firmware processing time is always less than the time required to execute the arbitration cycle, the firmware processing does not S
contribute any time delay. The high degree of symmetry between the functions performed in the Bus Controller node and the non-bus controller node permit the mode of any given node to be easily switched by merely changing the state- of a single firmware flag. This permits the Bus - Controller function to be reassigned to any of the plural nodes on the 10 serial data bus, a feature which will be discusséd in more detail in the section entitled System Recon~iguration.
Next to be considered is the operation of the firmware associated with the so~alled "Arbitration Al~orithrn" and in this regard, reference will be made to Figures 33a and 33b. Events labeled 1200 lS
through 1250 correspond to the "Firmware Response Processing" 1114 in the flow diagram of Figure 32 while events 1252 through 1280 correspond to the "Firmware Control Channel Processing" operation 1136. Firmware Response Processing is initiated when the Bus Controller receives a response as represented by event 1200. The Control Line Input 2 0 Multiplexer/Register 628, 630 (Figures 15a and 15b) contains the response.
It is transmitted conditionally through FIFO 636 into the Processor Control Line Input Register 676 as already described. The control word function field is propagated through latches 220 and 222 tFigure 4) and presented to inputs A4 through A8 of Mappin~ PLA 224. These inputs in 25 conjunction with other inputs, cause specific PLA output terms to be generated which, in turn, cause the firmware to branch and thus execute the required processing task as previously described. The Tables VA - VC
set forth the structure of the Mapping PLA. While the decisions represented by the diamond-shaped blocks 1202, 1206, 1214 and 1222 are 30 15~743 shown diagrarnm~tically as sequential decisions, they are actually performed simultaneously by the Mapping PLA 224 by the generation of the appropriate output term. If a Node Fault ~esponse is received, output Term 22 (Table V~) initiates event 1204 to notify the user computer of the ~ault, via an interrupt. If an "Immediate Bus Request" is received, output 5 Term 25 is generated by the Mapping PLA. Unlike the other select queues~ the immediate queue is contained within the firmware. The status o~ the queue is determined by testin~ an associated firmware flag as represented by decision block 1208. If the immediate queue is full, evenr 1210 is initiated. The address of the node to be selected is sent via 10 the Destination Bus 848 (Figure 3b) to the Select Multiplexer/Register 480 in Figure 9 and the "Select Enable" flag is set. (Reference Table 1) Referring agàin to the flow diagram of Figure 33, if there is room in the immediate queue, event 1210 is bypassed as represented by line 1211 and the new request is queued at the end of the immediate queue 15 as indicated by event 1212. This is accomplished totally within the firmware. If a normal request is received from a priority node (test 1214), Mapping PLA 224 generates its output Term 24. The status of the priority gueue is tested as indicated by block 1216. This is accomplished by testing the priority queue full line which is the output of inverter 814 in Figure 20 22a. (Reference Table IV) If the priority queue is full, operation 1218 is initiàted to make room for the new request in the queue. The state of the data line is determined by the Data Channel State Register 267 in Figure 5b. When the data line reaches a 0 or I state, the output of flip-flop 276 sets to create the "Latched Time for Select" flag (reference Table IV). 25 Next, the oldest priority request is unloaded from the Priority Dispatch FIFO 811 and transmitted in the manner previously described. Next, the event 1220 is initated which transfers the current request from the Processor Control Line Input Multiplexer/Register 676 into the Priority Dispatch FIFO 811. If the priority queue is not full, event 1218 will be 30 ~ ~5~3 bypassed. This is the normal rnode of operation in that the purpose of the dispatch queue is to eliminate any delay in the response processing while waiting for the data line to become available.
When processing a request from a non-priority node, the tests represented by blocks 1222 and 1224 perform the equivalent functions 5 described above for tests 1214 and 1216, respectively, while events 1226 and 1228 correspond to events 1218 and 1220, respectively. All firmware response processing thus far described funnels into a further test 1230 which is accomplished by testing the condition of the Latched Time for Select flag. If this flag is set, test 1232 is performed. This is 10 accomplished by testing the state of the Priority Queue Empty flag and the Non-priority Queue Empty flag (reference Table ïv). Thus, if it is time for select and there is a request in either queue, event 1234 will be executéd. The oldest Immediate Request will be unloaded fram the Irnmediate Request Queue and transmitted as previously described. If the 15 Immediate Request Queue is empty, the oldest priority request will be unloaded from the Priority Queue and transmitted as previously described.
If the priority queue is empty, the oldes-t non-priority request will be transmitted. Note that on each pass through this loop only one select is generated. If it is either not time for a select or there is no request to be 20 selected, event 1234 is skipped and the test represented by block 1236 is next performed. The Poll List is advanced by the control signal "Advance Poll List" (see Table 1). This is accomplished by testing the status of the Latched Previous Polled Priority/Non-priority Indica-tor (reference Table IV) which is generated by the output of flip-flop 584 in Figure 14. If this 25 flag is not set, the test indicated by block 1238 is next performed. Test 1238 is identical to test 1224. If both tests 1236 and 1238 are passed, the polling is forced to the Priority List as indicated by block 1240. This is accomplished by the control signal, "Force Priority PoJI" (Reference Table 1). If either of tests 1236 or 1238 fail, event 1240 is bypassed as indicated. 30 ~ ~5~3 Test 1242 is accomplished by testin~ the state of the output of Comparator 588 in Figure 1~, i.e., the "Own Node Poll" flag (Reference Table IV). If this test fails, the output of the poll list then contains the address of the next node to be polled, thus effectively queuing the poll and preparin~ the controller such that event 1120 of Figure 32 can be 5 initiated without delay. This is depicted diagrammatically in Figure 33 by the dotted line 1251 leading from event 1244 to event 1252.
Each time a poll is initiated, a timeout timer is also initiated.
When the response is received, this timer is reset. If the response associated with the poll is not received in the prescribed amount of time, 10 nominally 16 microseconds, the Poll/Response Timeout flag is set forcing the MPC into the error processing loop via the Mapping PLA. Test 1248 tests the status of this flag and if the response has not been received in time, event 1250 is executed to notify the user computer via an interrupt.
As indicated by the lines 1253 and 1255, the firmware program then loops 15 back to test 1230 to continue the select and poll process. If test 1248 passes, i.e., the response is received within the prescribed time, the firmware prograrn loops back to event 1200 as indicated by line 12~9. If there is another word to be processed in the input queue, this is loaded into the Processor Control l ine Multiplexer/Register 628 - 630 and the 20 next response is processed. If the input queue is empty, the firmware effectively waits at event 1200 for the next response.
If the condition for test 1242 is met, the poll is not transmitted, but instead the event represented by block 1246 is executed whereby the Bus Controller effectively responds to its own poll. This is accomplished 25 by loading the node address of the ~us Controlier into the proper Select Queue via the Destination Bus. The prograrn then loops back to perform the test indicated by block 1236 so that the next poll can be transmitted This completes the discussion of the firmware response processing. Next to be considered is the firmware control channel process. 30 -~3--~ ~5~743 Event 1252 is equivalent to event 1200, the only exception being that now the node is in the non-bus controller mode. As before, the function code of each received input is presented to the Mappin~ PLA
224. If the code indicates a poll corresponding to decision 1254, the Mapping PLA generates as its output Term 29, causing the program to 5 proceed to decision block 1256. Test 1256 is accomplished by sampling the "Waiting for Select Firmware Flag" (reference Table IV). If the node is not waiting for a select, the program proceeds to decision block 1258 which is accomplished by testing the "Messagel' flag (reference table IV).
If the fla~ is not set, the hardware response is a "No ~equest" (event 10 1260). Since this corresponds to the 0,1 state to which the Response Register is always reset, no action is required and, thus, the firmware processing is complete and the next time the node is polled, event 1138 (Figure 32) can be immediately executed. If the node has a message to send, event 1262 is executed which differs from event 1260 only in that the 15 response code is now changed to either a 1,0 or 1,1 code to queue the proper request as previously described. The "Waiting for Select Firmware Flag" is set at this time. During periods of heavy message traffic, it is possible that the node will not be selected prior to the issuance of the next poll. In this case, test 1256 causes event 1264 to be executedJ which 20 increments the count of the number of polls received since the request was made. This count is developed and tested directly in the firmware decision 1266. If the number of polls received since the request exceeds a prescribed number, event 1268 is executed to notify the user of an abnormal condition. The request is re-queued in the same manner as 25 event 1262. If the number of polls since the last request has not exceeded the specified threshold, no action is required and, thus, the response will be a "No Request".
If the control word received by the node is a select, the Mapplng Pl A will generate as an output Term 30, corresponding to test 1272. The 30 ~ :~5~l743 test 1274 is identical to test 125~ previously described. If the node has a message to send, event 1276 is executed which is the culmina-tinO event of the bus arbitration cycle. Event 1280 corresponds to all Mapping PLA
output terms other than 29 or 30 which direct the firMware to other processing tasks as required. 5 SYSTEM RECONFIGURATION
System casualty and fault scenarios for a large computer network pose complex design problems. The Serial Data Bus System in which the present invention finds use has features which have been incorporated so that it is possible to re-structure the system, within a 10 minimum time period, to recover full or reduced capability. Generally speaking7 the Serial Data Bus System does not do any automatic reconfiguration independently. However, it provides the community of users with very powerful command and status information with which to detect and diagnose system problems and subsequently to effect recovery 15 procedures to thereby eliminate or minimize the problen~. The following features are considered to be important features in the overall system design:
1. aus Controller Integrity 2. Serial Data ~us Status Information 20 3. Transmission System Reconfiguration Cornmands 4. Idle Channel Monitoring These features will be described in detail in the ensuing paragraphs.
A. BUS CONTROLLER INTEGRITY
The node serving as the Bus Controller performs the arbitration 25 algorithm and is the access point for system configuration control. Since the Bus Controller function is so critical to sys-tem operation in structuring the preferred embodiment, the following features are implernented:

?~ ~51~43 1. The Bus Controller node is the only node which may issue commands on the active control channel during system operation; and 2. The Bus Controller node will nat interpret any command (excepting responses to polls and status responses) which it 5 receives from the control channel. It does note this event, i.e., the receipt of a command, for transrnission to the user as an error condition, however. -These features preclude the Bus Controller function from being erroneously deleted by false command generation on the contr~l channel 10 (e.g. two nodes transmitting at the same time can cause unwanted control channel commands to be generated due to the mixing of the Manchester biphase signals). The drawback in protecting the Bus Controller in this fashion is that there is apparently no way for an alternate system controller to seize the system on the active control channel. However, a 15 convenient rnechanism (Idle Channel Monitoring) has been provided to solve this problem.
B. SERIAL DATA BUS STATUS INFORMATION
Detection of problems in the Serial Data Bus elements is facilitated by interrupt status data supplied by the node. Specifically, the 20 followin~ discrete events are reported to the user computer:
l. Control Channel Parity and Sync Errors - these types of errors, if they occur at a high frequency, are generally caused by flaws in the transmission media (open/shorted cable, rnissing terrnination) or erroneous transMissions by 25 another node (such as a second Bus Controller).
2. Control Channel Timeout to Poll - this error indicates that the Bus Controller is not receiving a response to a poll from a particular node. It may indicate problems in the transmission system and/or the target node. 30 11 ~5~743 3. Control Channel Ille~al Function Cocle - this error indicates that the node has received a function code which is not defined or which it cannot process. This event may indicate flaws in the transmission media or erroneous transmissi~ns by another node. 5 4. ~)ata Channel Parity Errors - these errors, if they occur at a high frequency, indicate a flaw in the transmission media (open/shorted cable, missing termination).
S. Data Channel Streaming - this error indicates that a data message envelope has exceeded, by at least 3.2 10 microseconds (32 bits), the actual length specified for the message. If the error occurs frequently it could ir~dicate a flaw in the transmission media (open/shorted cable, missing termination) or a flaw in a particular node.
6. Data Channel Intermessage Timeout - this error is only 15 detectable by the node acting as the aus Controller. It indicates the failure of a different node to begin transmitting its message on the data channel within a specified period of time (64 usecs). Depending on how often the event occurs and whether one or more nodes are , ~ o involved, the error may indicate several types of problems in the transmission system or a problem in a node.
There are other error interrupts and status indications presented to the user computers from their nodes. However, the ones just mentioned form the nucleus of errors from which reconfigura-tion 25 decisions are rnade. The power of this status data is that i-t allows -the user cornputer to symptornatically diagnose problems in the Serial Data Bus system and to take appropriate measures to recorlfigure around the problern(s).

- ~ :t5.~3 C. RE~ONFIGURATION COMMANDS
ReconIiguration of the Serial Data Bus is controlled by the user through the E~us Controller with the following commands:
l. Disable - this command causes the node to assume an initialized state but to retain existing channel numbers, poll 5 RAM contents, and screen RAM contents. The node will ignore all of the bus arbitration commands.
2. Start - this command causes the node to participate in the bus arbitration process by responding to polls or, in the case of the node currently serving as the Bus Controller, by 10 initiating the first poll.
3. Assume Bus Control - this command is issued by the user to declare the node to which it is assigned to be the Bus Controller, or being the user node attached to the aus Controller, to direct that the Bus Controller function be 15 transferred to the node address specified in the cornmand.
l~. Channel Control Command - this command allows the user compùter to perform two actions:
a) Declare a new control or data channel for the node to use. 20 b) Activate or deactivate the channel rnonitoring function for any of the system challnels.
The Bus Controller broadcasts the Channel Control command for the benefit of all users. Additionally, any time a control channel assignment is rnade the Bus 2 5 Controller sends this command ten times at 20 microsecond intervals. This supports the Idle Channel Monitoring function of the nodes.

7~3 5. Load RAM - this command is only available at the node/user interface. It provi~es the user with the capability to load the Poll RAM's and the message Screen RAM.
D. CHANI~lEL MONITORING
All nodes perform continuous channel monitoring as a normal 5 activity. The purpose of this monitoring function is to support system reconfiguration in cases where a main control channel fault has isolated the Bus Controller from all or part of the rest of the system. The recovery technique is to switch control channels at the Bus Controller node (via a command from the user to the node), at which time that node 10 broadcasts the command 10 times spaced 20 microseconds apart. Other nodes in the system are designed to have a rigid sequence of steps that must be satisfied in order to change channels. The timing, event counting, and signal decoding approach utilized eliminates the possibility of noisy cables causing unwanted channel changes and yet provides the 15 necessary reconfiguration method which is required to ensure system recovery frorn a faulty bus channel.
Channel monitoring initially consists of exarnining the envelope on all channels (other than the current control channel) to see if it conforrns approxirnately to the timing for a control line signal, e.g., 1.4 - 20 1.9 microseconds in width. If it does, a flag is set for that channel which indicates the event has occurred. The node performs an AND function of these activity indicators with a bit mask. The bits in this mask are controlled by the Channel Control Command; a binary one signal signifying the channel is activated for monitoring, and a binary ~ero signal 25 signifying the channel is not to be monitored.
Because the firmware operation is dependen-t on -the condition of its node prior to a reconfiguration, the description is divided into appropriate categories. With reference to the channel monitoring flowchart of Figure 34, the following operations are of interest: 30 _~9_ ~ 15~ 1 ~3 1. Master Clear (Block 1302) (including power-on condition) A Master Clear ultimately causes the firmware to load the Mask Register with all ones (all cables monitored) as indicated by block 1308. If the rest of the system is active (one cable already has control activity), the hardware 5 detects this and informs the firmware. This operation is indicated by block 1314 in Figure 34. The firmware determines the cable number and also clears the monitor latches. Af ter two more detections on that cable, the firmware clears that bit in the mask register and assigns 10 that cable as the active control cable. No further monitoring of the activity detector of that channel is necessary nor desired. ~urther operation related to that cable is simply receiving control frames and sending response frames. 15 If all nodes are rnaster clearing or powering up, each enables all cable monitoring devices and once the Bus Controller node has been designated at the system level, the Control Cable is also assigned and will be locked onto by the other nodes in the system. 20 2. Reconfiguration A. Bus Controller Ass~ned to Reconfi~ure Svstem on a Different Control Cable . .
The Bus Controller switches control cables and broadcasts ten Channel Control commands, one every ~0 25 microseconds, to the other nodes.
B. Non-Bus Controller Nodes A non-bus controller node will de-tect the control activity on the new cable (assuming the Mask Register allows it). See Block 1314. The firmware must note 3 0 ~-15~l7~3 three detections and the detections must occur within a 320 microsecond period. See operation block 1316 and decision blocks 1318, 1320. 1 his condition is a method used by the firmware to decide if the detections were caused by substantial noise or a faulty cable. I-f the 5 threshold condition is met, then the firmware temporarily abandons the control cable it had previously considered as active and it changes the I/O vectoring so that the control frames on the new cable can be interpreted. The firmware then requires that two cable 10 change commands be received on this new cable in no more than 256 microseconds. ~ee the operations represented by blocks 1326, 1328, 1330 in Figure 3~. If this requirement is not met, the firmware will clear that cable's "Monitor Enable" bit in the Mask Register, 15 disabling further monitoring of that cable (block 1332.
The net result is that the cable has been determined to be faulty and it will no longer be capable of distracting the node, so-to-speak. The firmware then reverts bacl~
to the "abandoned" active control cable. If the above 20 requirernent is met, however, the firmware formally switches the active control cables by modifying the Mask Register to disable MonitOring of the new cable and to re-enable monitoring of the old cable all as represented or indicated by operation block 133~. 25 C. Bus Controller Previous to Reconfi~uration Reference is made to 2. A. above if the Bus Controller that had been controlling the bus prior to reconfiguration is to con tinue as the Bus Controller following the switchinlg of the Control Cables. However, if the 3 previous Bus Con~roller detects control activity on a new cable, it follows the same procedure as the non-bus controller nodes (see paragraph 2. B. above) except that it also deletes the Bus Controller function since another Bus Controller initiated the reconfiguration process. 5 SUMMARY
Thus it can be seen that there has been shown and described a serial data bus system wherein communications within the system are accomplished by assigning control of the bus to one of a plurality of nodes, which then controls transmission of messages on a Data Cable 10 within the bus. Contention between bus users is resolved by selectively polling the users and then granting bus access to the highest priority user desiring to utilize the bus for message transmission purposes. Addressing within the data bus system uses both physical and logical addresses, with each node having a manually selectable address register. 15 As mentioned, in the system of the preferred embodiment, onc of the nodes in the data bus system has the responsibility as being the Bus Controller, although the particular node designated as the Bus Controller may be reassi~ned. Users with tirne-critical communication requirements are polled more frequently by the Bus Controller than other non-priority 20 users. A polling algorithm is implemented throu~,h software so that the priority structure can be readily modified to adapt to any application.
When a node is polled, a responæ is transmitted to the Bus Controller indicating the needs of the node being polled and also its current status. In this manner, a problem on the serial data bus can be 25 detected within the time required for one full systern poll cycle.
Further in accordance with the preænt invention, poll commands, responses, and other types of systern commands are transmitted on the control cable of the bus. The Data Cable is reserved for data messages only. Traffic on both cables is asynchronous, enabling 30 7~3 pollin~ and queuing of users concurrently with data rnessages bein,~
transrnitted on the cable.
Data bus system users communicate by transferrin~ variable length messages. A set of commancls and interrupts are utilized for communications between the users and the data bus system. External 5 Function (EF) cornmands are originated by the user and External Interrupts (El) are generated by the cdevices on the bus system. The manner in which digital devices may communicate using EF and El si~nals is set out in the Burkholder et al Patent 3,325,040 and reference may be made thereto by those desiring further information concerning this 10 communication protocol.
The poll cycle consists of command (poll and select) and response messages sent on the Control Cable and information messages sent on the Data Càble of the then active ones of the data bus lines. The in~ormation messages rnay vary in length and may contain up to 127 32-bit words. As 15 rr~entioned, bus control is accomplished by the exchange of command and response words and each complete data message transmitted contains 32-bits of control data. These 32-bits of control da-ta represent -the overhead of the system and in the design thereoI, a conscierltious effor-t is made to minirnize the overhead in order to obtain high data throughput. 20 As was further set out in complete detail above, the serial data bus of the present invention employs multiple nodes, each capable of performin~ the bus control function when appropriately selected to do so as well as the data transmission function. Only one node at a time performs the bus control function during a given ~ime interval. Bus 25 control responsibility is transferable automatically in the event of a casualty situation by software control. rhe Bus Controller node controls the use of the data channel by using a pollin~ ancl assigning technique on a control channel. As has been set out, polling consists of the Bus Controller makin~ inquiry of the nodes in a preselected sequence, 30 ~. ~5~ 3 evaluating the node's response, and assigning individual node usage of the data channel in a preselected priority arrangement. The polling and assigning is accomplished automatically and in parallel with the transmission of information on the data channel. In the preferred embodiment, a two level priority capability has been described and serves 5 to (l) assign the data channel to nodes based on node priority and (2) provide all nodes the capability of transmitting high priority messages in advance of a higher priority node. Further, the serial data bus of the present invention allows the queuing of bus requests to assure that no requests are lost by the Bus Controller while performing the polling 10 sequence.
Thus there has been described the preferred embodiment of the present invention and the best mode contemplated for practicing the invention. Those skilled in the art will readily discern from the accompanying drawings and the explanation set forth herein how various 15 changes and modifications may be made to the overall structure. Hence, it is intended that the true spirit and scope of the invention be determined from the accompanying claims.
What is claimed is:

Claims (25)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. In a serial data bus transmission system of the type used to interconnect a plurality of user devices for message intercommunication over transmission cables, said system including a plurality of cables, one of which acts as an active control cable and one of which acts as an active message cable at a given time, with at least one bus access module coupled to each of said plurality of cables, a plurality of node devices for coupling said user devices to said bus access modules, each of said node devices comprising in combination:
(a) bus input/output means including data format conversion means coupled to said bus access modules for selecting said active ones of said control cable and said message cable and for transmitting or receiving digital messages and control signals therethrough;
(b) a control bus coupled to said bus input/output means;
(c) a message bus coupled to said bus input/output means;
(d) control line sequencer means coupled to said control bus for receiving control signals therefrom and including logic means for performing preprocessing functions relative to said control signals for determining whether said control signals are intended to affect that node device and are of a proper format;
(e) controller means adapted to receive preprocessed data signals from said control line sequencer and to develop command signals in accordance with said preprocessed data signals, and further status indicators;

(f) means including said control bus and said bus input/output means for sending said command signals on said active control cables to other of said plurality of nodes coupled to said active control cable; and (g) means responsive to said command signals for controlling the flow of messages over said message bus and between said plurality of user devices.

2. Apparatus as in Claim 1 wherein said data format conversion means comprises a serial-to-parallel and a parallel-to-serial converter coupled between said bus access module and said control bus or said message bus.

3. The system as in Claim 1 wherein each of said nodes further includes:
(a) a storage unit associated with said controller means, a source bus coupling plural register means to said controller storage unit, a destination bus coupling said con-troller storage unit to further plural storage means associated with said control bus, and a user connection, said user connection being coupled to receive control and message words from a user device;
(b) means coupling said user connection to said source bus, and (c) means coupling said message bus to said user connection for two-way data transmission therebetween.

4. Apparatus as in Claim 1 wherein said bus input/output means includes:
(a) multiplexer means coupled between said control bus and message bus and said plurality of cables;

(b) an active bus number register having an input and an output, said output being connected to said multiplexer means; and (c) means coupling said controller means to said input of said active bus number register whereby said active control and message cables are definable by digital data originated by said controller means.

5. Apparatus as in Claim 4 and further including means in said node for causing new information to be loaded from said controller means into said active bus number register upon detection of a fault on the one of said plurality of cables previously acting as said control cable or said message cable, such that a different one of said plurality of cables is sub-stituted for the one on which the fault was detected.

6. Apparatus as in Claim 5 wherein said bus input/output means further includes (a) activity monitoring means coupled to each of said plurality of cables for detecting the time relationships of signal patterns detected on said plurality of cables and thereby determining whether a cable is carrying control or message type information;
(b) means in said activity monitoring means for developing a control flag indicative of control type activity;
(c) masking means connected to receive said control flag and further control signals from said controller means for selectively causing one or more of said control flages to be ignored; and (d) means coupling the output of said masking means to said controller means for causing it to enter a new word into said active bus number register.

7. Apparatus as in Claim 1 wherein said control line sequencer comprises:
(a) register means connected to said control bus for at least temporarily storing control words carried by said control bus and applying said control words to said logic means;
and (b) buffer means coupled to the output of said logic means for receiving and at least temporarily holding one or more logic output control codes from said logic means and for trans-mitting said logic control codes sequentially to said control bus or to said controller means.

8. Apparatus as in Claim 7 wherein the sequential trans-mission of said logic control codes is controlled by said con-troller means.

9. The serial data bus transmission system as in Claim 1 wherein one of said plurality of nodes is a bus controller node and wherein said command signals from said bus controller node include poll and select commands directed to other nodes in said system.

10. Apparatus as in Claim 9 and further including a first list and a second list in said bus controller node, each of said lists connected for control by said controller means and storing the address of all predetermined nodes in the system with the address of those nodes having a priority stored in said first list and with the addresses of those nodes having no priority stored in said second list; means for sequentially applying poll commands to those nodes pointed to by the address in said first list; and means for subsequently sequentially applying poll commands to those nodes pointed to by the addresses in said second list.

11. The apparatus as in Claim 10 and further including sub-cycle counter means adapted to receive an initial value from said controller means; means for incrementing said sub-cycle counter at a fixed rate in synchronism with the addressing of said second list; comparator means for detecting when the count in said sub-cycle counter reaches a predetermined limit; and means coupled to said comparator means to reinitiate addressing of said first list upon the generation of an output by said comparator means.

12. Apparatus as in Claim 9 and responsive to the receipt of a poll command signal from said bus controller node for initiating the return of a predetermined response control word over said control cable to said bus controller node.

13. Apparatus as in Claim 12 and further including means in said bus controller node for sensing the time delay between the sending of a poll command by said bus controller and the sub-sequent receipt of said response control code by said bus con-troller; and means for signaling the particular user device associated with said bus controller node when said sensing means indicates a time delay greater than a predetermined value.

14. Apparatus as in Claim 13 and further including:
(a) a control line input queue device coupled to said control bus for storing the node addresses of those node devices responding to a poll control word from said bus controller node;
(b) a select queue device connected to said control line input queue device and controlled by said control line sequence for applying select codes to said control cable; and (c) means responsive to the receipt of a select control code by an addressed node for entering or receiving data messages from said active message cable by way of said bus input/
output means.

15. Apparatus as in Claim 14 wherein said last-mentioned means operates simultaneously with transmission of said poll control words, said response control codes and said select control codes on said active one of said control cables.

16. Apparatus for coupling a plurality of digital data processing and handling user devices through a communications bus, certain of said user devices having a first priority status and other of said user devices being of a non-priority status, such that said user devices may communicate on a non-contentious basis, comprising in combination:
(a) a plurality of node devices associated with said user devices, one of which being assigned bus controller responsi-bility, said bus controller node device having means for issuing polling control words to said plurality of node devices over control lines contained in said communication bus on a predeter-mined frequency basis, the nodes associated with said user devices having priority status receiving polling control words more fre-quently than said node devices associated with user devices having non-priority status;
(b) priority response queuing means and non-priority response queuing means in said bus controller node device, said priority and non-priority queuing means adapted to store response-type control words return from said plurality of node devices in response to the receipt of said poll control words from said bus controller node;
(c) control means for said queuing means for generating select control words for transmission from said bus controller node to selected ones of said node devices previously sending predetermined response control words to said bus controller node, said select means honoring node devices associated with said priority users in preference to said node devices associated with non-priority users; and (d) means including data lines contained in said communications bus for transmitting messages of predetermined differing lengths from said priority and non-priority node devices in response to its receipt of said select control words from said bus controller.

17. The serial data bus transmission system of Claim 1 wherein said logic means comprises a programmable logic array.

18. The serial data bus transmission system of Claim 3 wherein said controller means comprises a microprogrammable controller.

19. The serial data bus transmission system of Claim 3 wherein said user connection comprises a user bus.

20. The serial data bus transmission system of Claim 4 wherein said controller means comprises a microprogrammable controller.

21. The serial data bus transmission system of Claim 5 wherein said controller means comprises a microprogrammable controller.

22. The serial data bus transmission system of Claim 6 wherein said controller means comprises a microprogrammable controller.

23. The serial data bus transmission system of Claim 7 wherein said logic output control codes are stored in said logic array.

24. The serial data bus transmission system of Claim 23 wherein said logic output control codes are stored in said logic means.

25. The apparatus as in Claim 10 wherein at least one of said first and second lists comprises a register stack.