CA1140637A - Cardiac pacing for arrhythmia treatment - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
This invention relates to a method of generating output pulses in timed relation to externally sensed pulses and to a cardiac pacing apparatus. The method comprises digitally timing the interval between sensed pulses, generating an escape interval value and generating an output pulse following a sensed pulse. The apparatus is based inter alia on this method and comprises a pacer input means, a pacer output means and a means for coupling the input and output means to a patient's heart, a digital data processor and a read only memory. The method and apparatus are particularly suitable for preventing and treating arrhythemias such as atrial tachycardia involving accelerated heartbeat rates.

Description

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1 This application is a divisional application of Canadian patent application serial number 314,245 ~iled on October 25, 1978.

~A ~R:OUND OF I'HE INVENTION

This invention relates to cardiac pacing apparatus and more particularly -to a cardiac pacer for preventing and treating - arrhythmias such as atrial -tachycardia involving accelerated heartbeat rates. It is well known that premature heartbeats are a manifestation of the irritability of the heart~ If untreated, the premature heartbeat may start long runs of rapid heartbeats.
This invention also relates to a method of generating output pulses in timed relation to externally sensed pules which forms one of the basis upo~ which the cardiac pacing apparatus is based.
Various systems have been proposed for treating arrhyth-mias involving increased heartbea-t rates, e.g~, atrial tachycardia, including the use of rate scanning as proposed in the Berkovits United States patent 3,698,398 which issued on October 17, 1972.
The rate scanning program in these devices, however, is essent-ially predetermined rather than being interactive with the actual functioning of the heart. The rate scan proceeds on the assumption that capture will, at some point, be established and that the heart rate ~ill track with the scanned rate down to the desired level. It is possi~le however, that neither of these assumptions may ~e correct. Various other systems involving manual control have also been proposed but, as will be understood, these systems involve the availability and intervention of medically-cognizant personnel and such personnel will not be universall~ or instantaneously available, even in a hospital environment~

1 Among the several objects of the present invention may be noted the provision of cardiac pacing apparatus for treating or preventing arrhythmias involving accelerated heart-beat rates; the provision of such apparatus which is inter-active with and responsive to the actual functioning of the patient's l~eart; the provision of such apparatus which effects capture by stimulating the patient's heart at a time which is adjusted in accordance with the last naturall~ occurring heartbeat; the provision of such an apparatus which is operative to re-establish capture if the natural heartbeat eludes pace-maker control during the slowdown operation; the provision of such apparatus which is highly reliable and which is of relatively simple and inexpensive construction -the provision of a method of generating output pulses in timed relation to externally sensed pulses. Other objects and features will be in part apparent and in part pointed out hereinafter.

SUM~IARY OF ~HE INVENTION
Briefly, cardiac pacing apparatus in accordance with the present invention is based on digital timing techniques and involves timing means for generating a series of clock pulses, means responsive to heartbeats, and means for counting the clock pulses occurring from a first heartbeat to a second heartbeat thereby to obtain a ~irst value representing the time interval between heartbeats. ~urther means, interconnected with the counting means, are provided for generating a digital value which is smaller than the first value by a preselected decrement and which represents an escape interval. Means are provided for counting cloc~ pulses occurring after the second heartbeat, thereby to obtain a running time value and this running time value is compared with the escape interval value. When 3~

1 the running time value becomes substan-tially equal to the escape interval value, a stimulating pulse is generated and the escape interval is increased by a preselected increment. Accord-ingly, the interval between successive stimulated heartbeats is gradually lengthened so as to slow down the patient's heart.
In the preferred embodiments, the apparatus continues to be responsive to natural heartbeats and timing continues ~rom the last heartbeat, natural or stimulated, and t~e escape interval is reset if a natural heartbeat occurs earilier than the then effective escape interval, thereby re-initiating the slowdown sequence.
To this end, in one of its aspects, the invention provides a method of generating output pulses:in timed re-lation to externally sensed pulses, which method comprises:
digitally timing the interval between sensed pulses;
generating an escape interval value which corresponds to a period shorter than the timed interval between a first sensed pulse and a second sensed pulse;

following a sensed pulse, generating an output pulse ; 20 when the timed interval corresponds to the escape interval value and then incrementing the escape interval value, the increment-ing continuing on succesive output pulse cycles until said escape interval value reaches a preselected value corresponding to a minimum rate.
In another of its aspects, the invention provides a method of qenerating output pulses in time relation to externally sensed pulses, which method comprises:
generating output pulses at preselected .intervals, the.

intervals being determined by digitally counting down a clock signal by a preselectable fac-tor;

sensing external pulses occurring during a period - 2a -v~;i37 1 preceding the completion of each such preselected interval and, i~ a sensed external pulse is detected during said period, generating an escape interval value which corresponds to a per-iod shorter than ~hat between the sensed pulse and the preceding output pulse;
following a sensed external pulse, generating output pulses at intervals corresponding to the then extant escape in-terval value by digitally counting down from said clock signal and, upon the generation of each output pulse, incrementina the escape interval value, the incrementing continuing until the escape interval becomes essentially equal to said preselected interval at which point the output pulse ra~e reverts to a fixed value.
In yet another of its aspects, the invention provides cardiac pacing apparatus for treating cardiac .rrhythmias, said apparatus comprising:
pacer input means for electrically detecting heart-beats;
pacer output means for generating electrical signals at levels appropriate for cardiac stimulation;
means for coupling said input means and said output means to a patient's heart;
a digital data processor whose sequence of operation is controllable by means of a stored program, said processor including means for testing input parameters and means for gen-erating output signals, said pacer output means being connected to said processor output signal generating processor to provide a changed input parameter thereto when a heartbeat is detected;
a read only memory having a program essentially permanently 6~

1 stored therein, said program defining the sequential reaction of the processor output signal of input parameters coupled to said processor as a result of detected naturally occurring heartheat sequences.
In a further aspect, the invention provides battery powered cardiac pacing apparatus for treating cardiac arrhythmias, said apparatus comprising:

pacer input means for electrically detecting heartbeats;
pacer output means for generating electrical signals at levels appropriate for cardiac stimulation;

means for coupling said input means and said output means to a patient's heart;
a digital data processor whose sequence of operations is controllable by means of a stored program, said processor including means for generating output signals and interrupt means for initiating a change in the sequence of program operations, said pacer output means being connected to said ` pxocessor output signal generating means, said pacer input . means being connected to said interrupt means to initiate an interrupt procedure when a heartbeat is detected;

a read only memory having a program essentially pexmanently stored therein, said program defining the sequence of operation of the processor output signal generating means in response to various possible sequences of natural and stimulated heartbeats whereby the timing of stimlllating pulses is controlled in relation to naturally occurring heartbeat sequences.

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BRIEF DESCRIPTION OF THE DRAWINGS
.... . ... ... _ . . . ... _ Fig. 1 is a block diagram of a cardiac pacer in accordance with the present invention, cons-tructed using discrete components;
Fig. 2 is a table representing a sequence of values appearing in different registers in the embodiment of Fig. 1 during operation;
Fig. 3 is a schematic diagram of a~pacer in accordance with the present invention employing a microprocessor;

Fig. 4 is a ~low chart for a stored program employed with the embodiment of Fig. 3;
Fig. 5 is a representation of the program, in hexa-decimal form; and Fig. 6 is a timing chart .illustrating the phases of operation of the pacer of Fig. 3.
Corresponding reference characters indicate correspond-ing parts throughout the several views o~ the drawings.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
As indicated previously, the apparatus shown in Figure 1 is a so-called hardwired version of the apparatus in accord-ance with the present invention. The apparatus was designed : or bedside operation with controls for enabling the attending physician to preselect certain parameters by means of multi-position switches. With reference to Figure 1, the physician may select, by means of a multi-position switch Sl, the AUTO rate, i.e., the rate which the pacer will attempt to maintain. In other words, this value specifies the final rate toward which the pacer attempts to lead the heart.
The physician may likewise select, by means of a multi-position switch S2, a desired refractory period. As is understood 1141~63 1 by those skilled in the cardiac pacer art, cardiac pacingapparatus is typically provided with means defining an interval following a natural or stimulated heartbeat during which the apparatus is insensitive or refractory to further input signals.
As indicated previously, the apparatus of the present invention employs digital timing and for this purpose comprises an oscillator or other timing circuit appropriate for generating regular timing clock pulses at predetermined intervals. The embodiment shown in Figure 1 employs a clock circuit 21 generating 10 a first clock Signal Cl having a period of one millisecond, a second clock signal C2 having a period of two milliseconds and a third clock signal C10 having a period of ten milliseconds. The complements of these signals, designated ~T, ~ and C10 are also provided. The basic counting and timing interval of the system ; is ten milliseconds but the one and two millisecond intervals are used for certain delay and output timing purposes, as explained hereinafter. The timing signals are employed at various points in the circuitry as indicated in the diagram of Figure 1.

The pacer is provided with a unipolar or bipolar cardiac lead 11 which can be driven from a conventional pacer output stage or amplifier 13. The amplifier 13 is, in turn, controlled by a digital latch 31, an S-R type flip-flop. The latch 31 can be set, i.e., so as to`initiate an output pulse,by a comparator 25 described hereinafter. Once setj the latch is reset by the C2 clock signal to terminate the stimulation pulse. For this purpose, the lead 11 is also connected to a sense amp~ifier 17 and a one-shot multivibrator circuit 19. Multivibrator 19 provides a squared-up or digital type of signal which indicates the occurrence of a heartbeat. Sensed signals due to the pacer's ~4--....

1 o~n output signals are blocked by an AND ga~e 20, ths resultant signal being designated SENS ~hile a single active lead is shown, it should be understood that separate input and output leads are also known in the art and it should be understood that such interfacing schemes may be employed in connection with the present invention also.
The ~UT0 rate select switch Sl is connected with an encoder circuit 23 which provides a binary encoded representation of the period corresponding to the selected final pacing rate.
The units in which the selected period is represented are the ten millisecond timing intervals and only the higher level binary values are outputed from the encoder, i.e., the 4, 8, 16, 32 and ~4 valued outputs. Thus, the smallest change in AUT0 rate which can be selected is that corresponding to a change in period of 40 milliseconds. Even this, however, is much finer resolution than is required for most purposes.
The binary value representing the period corresponding to the selected A~T0 rate is applied to the five higher bits of the 3even-bit digital comparator circuit 25. The lowest level bit of this input is tied low, i.e., permanently given a binary value of "zero", while the second least significant bit is con-trolled by D-type flip-flop 27. This flip-flop may be considered to be the slowdown control flip-flop and its operation is described in greater detail hereinafter. The other binary input value provided to the comparator 25 is generated by a presettable up counter 29. Basically, this is the counter which times the interval between the last heartbeat and the next s~duled stimulating pulse, i.e., the escape interval~ This counter is normally driven by the C10 clock pulse, as indicated.
In the absence of any arrhythmia involving an accelerated I l~V637 heartbeat rate, i.e., with the flip-flop 27 in its reset state, the up counter 29 is normally preset to an all zero state.
Accordingly, after an interval corresponding to the preselected AUTo rate, the comparator 25 will provide an output signal indicating equality between the two binary inputs, this signal being indicated as A=B in the drawing. This output signal sets the output latch 31 which, in turn, drives the output amplifier 13. The output latch is reset by the next C2 clock signal transition so that a stimulation pulse of one millisecond duration or width i5 generated. The output signal from the output latch, designated OUTP~T, is also employed at various points in the control circuitry, as indicated in the drawings, for purposes described in greater detail hereinafter. Assuming that no - earlier natural heartbeat occurred, the generation of a stimulating pulse again effects a presetting of the up counter 29 to an all zero value so that the cycle is re-initiated. Thus, the pacer will continue to stimulate at the selected AUT0 rate.
A counter 35 is interconnected with the refractory Fericd selection switch 2 through a multiplexer 37 which serves to determine when the counter value reaches a level corresponding to the selected refractory period value. When the counter xeaches this value, multiplexer 37 generates an output signal which will reset the D-type flip-flop 38. This flip-flop can be set by either a pacer output signal or by a sensed heartbeat signal which reaches this flip-flop through delay circuitry described hereinafter. In general, the function of the xefrac-tory flip-flop 38 is to steer the sense signal in dependence on whether the refractory period has passed or not. This steering is effected by a pair of AND gates 40 and 42 to obtain a SENSE
A signal which indicates a heartbeat occurring after the refrac-tory period, i.e. in the alert period, and a SENSE R signal 3~3~
1 which indicates a heartbeat occurring during the refractory period.
Timing between successive heartbeats, whether naturally Occurring or stimulated, is accomplished essentially by a down counter 45, a related escape interval being established when the contents of the down counter are transferred, through a gate array 47 to the preset inputs of the up counter 29. However, before describing the operation of the down counter 45 it is useful to describe various control circuits which determine the sequence of operations of the down counter 45 and the transfer through gate array 47.
In order to determine when the system is in or has reached its AUTO rate, the six most significant output bits from the down counter 45 are applied to a NOR gate 49 which operates as an AUTO rate detector. Detector 49 provides an output signal when these bits are all zero. Among other functions, this signal operates, through OR gate 50, to reset a S-R flip-flop 39 which is conveniently designated the sense flip-flop. This flip-flop can also be set by a start-up pulse which is generated on the operation of a;power-on start-up circuit comprising differentiator 51 ond OR gate 53. The purpose of this circuitry is to establish the pacer at its selected AUTO rate when the syste~ is first turned on. The sense flip-flop 39 may be set in response to the occurrence of a SENSE signal after the refractory period. The sense flip-flop controls gating circuitry, AND gates 55 and 56 which, in effect, steer the OUTPUT signal so as to obtain an OUTPUT A signal which indicates operation in the AUTO rate mode or an OUTPUT S signal which indicates opera-tion in the progressive slowdown mode. These steered signals are utilized at other points in the control circuitry, as indicated in the drawing.

~q~37 The presetting of the UP counter 29 to an all-zero state is effected by either the SENSE R or OUTPUT A signals, these signals being combined in an OR gate 60 and applied to the preset enable (PE) terminal of the counter 29 through an OR
gate 61. The all-zero state is obtained since one of the inputs to each of the AND gates making up array 47 will be at a binary zero thus blocking the value then held in the DOWN counter 45.
Loading of the UP counter 29 with the contents of the DOWN
counter 45 is effected upon the occurence of the SENSE A or 1o OUTPUT S signals, -these signals being combined in an OR gate 62 which then feeds the OR gate 61 mentioned previously. In order to permit the contents of the down counter 45 to be transferred to the up counter 29 in response to either an OUTPUT S pulse or a SENSE A pulse and then again immediately preset the down counter in response to these same signals, a sense delay circui~
is provided, as indicated at 63, which can be triggered by either the OUTPUT S or SENSE A signals. This is a clocked Or synchron-ous delay circuit which operates, in conjunction with the Cl timing signal and its complement Cl, to provide an output signal after a 1.5 millisecand delay. This signal is applied through an OR gate 65 to the preset enable input of down counter 45. The other input of the OR gate 65 is the Ored combination of the OUTPUT ~ signal with the SENSE R signal. The output from the OR
~ate 65 is also applied through an inverter 67, as the other input to each of the seven AND gates which controls the transfer of the seven bits of output information from down counter 45 to the preset inputs of up counter 29. In other words, when the output of gate 65 is high, the preset input of up counter 29 will see all zeros whether or not there is any residual value in the down counter 45.

In addition to controlling the transfer of values from the down counter to the up counter, the output signal from the delay circuit 63 is also applied to the clock input of the refractory flip-flop 38 to cause it to be set.
OPER~TION
The operation o~ the Fiyure 1 embodiment in controlling arrhythmias involving accelerated heartbeat rates is as follows:
In this operational description it is assumed: (1) that the AUTO rate select switch is set to a rate corresponding to a 1000 millisecond period, i.e., 1 heartbeat per second; (2) that the re~ractory select switch is set to 400 milliseconds; and (3) that the system has been started and is running at its AUTO rate.
During running at the AUTO rate, each output signal, applied through the rate 65, will cause the down counter 45 to be preset to the value which is one unit higher than the binary valua corresponding to the AUTO rate. The six most significant bits are determine~ directly from the AUTO rate encoder 23 while the least significant bit is tied high, as indicated in the drawing, and the next least significant bit is tied low. Accordingly, a preset value is provided which is one higher than the AUTO
rate value. The up counter, however, will be preset to zero ~ince the inverted input to the gate array 47 will cause all zeros to be presented to the preset inputs of the up counter.
Following the OUTPUT pulse, the down counter will be stepped do~nward at each 10 millisecond interval. This counting, as suggested previously, provides a measurement of time passing since the last heartbeat. At the same time, the up counter is stepped up in value by the C10 10 millisecond clock signal and, as also suggested previously, this counting iSf in effect, timing the then extant escape interval. If no natural heartbeat ?~

1 occurs before the end of the escape interval, a stimulation pulse will be generated when the comparator 25 indicates equality.
The pacer will thus deliver a pulse at the period corresponding to the preselected AUTO rate and will repetitively so operate.
If, however, a na~urally occurring heartbeat is sensed before the end of the then extant escape interval, i.e., during the alert period, the SENSE A signal will cause the up counter to preset while the gating array 47 is enabled. Thus, the up counter 29 will acquire the then extant value present in the O down counter 45. One and one-half milliseconds thereafter, the down counter will be again preset to a value which is one greater than the value representing the AUTO rate. For the purposes of the following description, it will be assumed that a naturally occurring heartbeat was sensed 800 milliseconds, i.e., 80 counting intervals, after the last stimulating pulse delivered in the AUTO rate mode. The SENSE A signal will also set the sense flip-flop 39.
As will be understood, the presetting of the up counter

2~ to the residual value in the down counter 45 in effect gives ZO the up counter a headstart toward reaching the value with which it is bèing compared by comparator 25. Thus, the escape period is effectively shortened. Further, this headstart is based upon the interval measured by the down counter since the last heart-beat and is, in fact, one unit less than that interval. This follows since the down counter is stepped downwardly and its starting point is one greater than the binary value corresponding to the preselected heartbeat period. Accordingly, the new escape interval is also one timing interval shorter than the previous interval between heartbeats. For this paritcular example, the down counter would have decremented ~rom 101 -to 21 ;

3 during the 80 counting interva~s. This is indicated in the third line of the table o~ Fig. 2, the first two lines being lllustra-tive of operation in the AUT0 rate mode.
The shortened escape interval operates in the same manner as the present AUT0 rate escape interval to cause the output circuitry to generate a stimulation pulse if no natural heartbeat occurs before the end of the escape interval. Thus, the apparatus has, in effect, digitally measured the heartbeat period and then set i'self to deliver a stimulation pulse after a slightly shorter interval, a procedure likely to be effective in obtaining capture and control over the heart rate. Thus, follow-ing the naturally occurring heartbeat, the up counter will run for 79 counts, i.e., 790 milliseconds, before a stimulation pulse is generated. During this same interval, the down counter will have been stepped down 79 counts, i.e., from the initial preset value of 101 to a value of 22.
Since the down counter 45 did not, in the previous interval, reach a value such that the six most signi~icant bits are all zeros, the AUT0 rate detector 49 will not reset the sense flip-f~op 39. Accordingly, the next output pulse will cause the slowdown flip-flop 27 to change state so that the "two" input o~
the input of comparator 25 is raised, i.e., a binary one is placed on this input. ~s will be understood by those skilled in the art, this will increase the value to which the up counter 29 must co~nt by two increments be~ore the comparator 25 detexmines equality.
Thus, although the next residual value to be transferred from the down counter 45 to the up counter 29 is one greater than the previous value, i.e., 22 rather than 21, the up counter itself must now count to a vaIue_which is higher than the preset - --11-- .

11~063'7 1 AUTO rate by two, ~ e., 102 rather than 100. Thus, the actual escape interval will be one timing unit longer than the first escape interval following the naturally occurring heartbeat. That is, the second escape interval will be 80 units or 800 milli-seconds. At this point, the entire apparatus hàs transferred into the slowdown mode and the process of stretching out the escape interval continues. At the ena of 80 counts, the down counter 45 will have been stepped down to a value of 21 and this value will be entered into the up counter. Accordingly, 81 counts will have to take place before the output pulse is generated.
After these 81 time increments, the down counter will have reached a value of 20 and this value will have been transferred to the up counter leading to a new escape interval of 82 units, i.e., 820 milliseconds. This sequence is illustrated in the Table of Figure 2 and, from the foregoing explanation and this Table, it will be seen that the escape interval will continue to lengthen, i.e., the stimulation rate will gradually slow down, so as to also 510w down the patient's heart. This assumes that capture is maintained. The slowing process continues until the escape interval corresponds to a present AUTO rate. At ~his point, the AUTO rate detector will cause the sense flip-flop 39 ~o revert to the ~UTO rate condition and the entire circuit will revert to the initial mode of operation described previously.
The foregoing explanation assumes that the slowdown operation proceeds to completion. The device does, however, remain sensitive to earlier occurring natural heartbeats. If such should occur, the SENSE A signal thereby generated will cause the up counter Z9 to acquire the then extant value present in the down counter ~5. Since this value represents a msasure-ment of the interval between the preceding two heartbeats/ less 3~
1 one timing unit, it can be seen that the escape interval is again reset to a value just slightly shorter than the preceding heartbeat interval. Thus, the device attempts to again regain capture based on a timing or escape interval which is predicated on the interval between the precedin~ two heartbeats. In this manner, the chances of re-establishing capture are greatly improved as opposed to some empirically imposed sequence or program of stimulation.
If a heartbeat is sensed during the refractory period, the pacer reverts to its AUTO rate, this being deemed a safer expedient than ignoring the event.
The em~odiment illustrated in Figure 1 is designed to be implemented with discrete digital ~gic components and a proto-type conforming to this design was built and successfully operated. ~owever, given the number of counters to be implemented nnd the variety of control states, the overall function is one which is appropriately implemented utilizing microprocessor con-troller techniques, the timing, counting and interaction routines being defined by a program stored in a read-only memory ~ROM). Such an implementation is illustrated in Figure 3 where the digital controller portions of the circuitry are diagrammed in detail, including the integrated circuit components designa-tiOllS and the pin designations in conventional format. The digital integrated circuits are all types a~ailable from RCA
(Radio Corporation of America) and are all of the so-called C-~lOS type, i.e., they are constructed using complementary metal oxide semiconductor fabrication techniques. As is understood by those skilled in the art, C-MOS integrated circuits have exceptionally low power consumptions and are thus admirably suited for battery-operated systems such as the cardiac pacer of 1 the present invention. As is understood, the use of isolated, battery power is considered essential for therapeutic systems, even where the pacing apparatus is not implanted.
The microprocessor itself is model CDP-1802D, while the memory is a model CDP-1832D, appropriately programmed by mask during manufacture. The actual machine code program which is stored in the memory, is given in -the Table of Figure 5 where both the addresses and the instructions are stated in conventional hexadecimal format.

In that the number of intermediate values which must be dealt with at any given time are fairly limited, the internal registers of the CDP-1802D microprocessor provide sufficient working storage and no separate random access memory (RAM) is needed. The memory address lines from the microprocessor are thus connected directly to the address terminals of the read-only memory. The CDP-1~02D microprocessor is a bus oriented machine and thus the data lines from the read-only memory are connected directly to the bus lines, as indicated in the drawing.
In this embodiment, sixteen possible rates are pro-vided for operation in the AUTO rate mode and the operative rate is selected by means of a sixteen-position switch comprising t~Yo decks SlA and SlB. Integrated circuit lC7 and RCA CD-4066, performs a one-of-eight to binary encoding function on the setting of the first switch deck SlA to provide the three least significant bits in a coded designation of the switch setting while the other cwitch ~esk SlB directly provides the most significant bit, as may be seen from the drawing. The result-ant four bit code is applied through a quad bilateral switch circuit lC5 to four of the eight bus leads. These switches are enabled under the control of the N~ command output of the microcomputer.

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1 An eight position switch S2 is provided to designate a maximum rate for the operation of the pacer. In this embodi-ment, a maximum rate setting is used in place of the adjustable re~ractory period implemented in the embodiment of Figure 1. The setting of switch S2 is encoded in a similar fashion by integrated circuit IC8 whichis again a CD-4066 one~of-eight to binary encoder. This encoder data is provided to the next three of the bus leads, the remaining eighth bus lead being tied low ~binary zero) during enablement of the bilateral switches IC5 and O IC6. The bilateral switches IC5 and IC6 are also RCA integrated circuits, type CD-4532.
As explained hereinafter, the microprocessor periodic-ally reads the settings of the switches Sl and S2 to determine the AUTO rate and maximum rate parameters for use in various timing loops in the operating program. It should be understood that the binary code which represents each possible setting of the switches does not correspond to a binary value diréctly represent-ing the corresponding time period, as was the case in the embodi-ment of Figure 1. Rather, the period or rate corresponding to each ~O switch setting can be arbitrarily preselected in devising the program for the apparatus. In other words, after reading the binary value indicating a given switch setting; the program causes the microprocessor to look up the appropriate correspond-ing period or rate parameter from a table which is in~orporated in the stored program. Thus, the values for the available rates may be chosen essentially arbitrarily based upon medical con-siderations and not in accordance with any particular binary or other mathematical distribution.
A four-position switch, comprising two decks S3A and S3B, is connected to directly provide a binary code indicating ~q;~3~7 ( 1 which of the four settings is selec-ted, the code being applied to the I/O FLAG terminals EF3 and EF4 of the microprocessor. As will be apparent hereinafter, the setting of thIs switch designates the amount by which the escape period is to be short-ened, relative to the interval between the preceding pair of heartbeats, upon the occurrence of an early spontaneous heart~
beat indicating an arrhythmia such as tachycardia. This adjustment represents an additional degree of flexibility over the embodiment of Figure 1 in which the amount of lead time utilized to obtain capture of the heartbeat rate was hard wired to be equal to the amount by which the escape period was lengthened for each cycle during the slowdown mode. In the program given, the four "jump ahead" time values are 10, 20, 40 and 80 milliseconds.
T~e amount of the lengthening for each cycle in the slowdo~n mode can be selected from two different values. This is accomplishea by means o~ a switch S4 which applies either a binary zero or a one to the EF2 terminal of the microprocessor.
These states are assumed to call for a 10 millisecond or 20 millisecond slowdown increment respectively. Manual starting or initiation of this system is provided by means O~ a pushbutton switch S5 which can pull the EFl terminal of the microprocessor low. Like the switches Sl and S2, the I/0 FLAGS EFl-EF4 are ~eriodically read by the microproces~or under programatic control and corresponding adjustments are made in the timing parameters of the program operation.
The clock input terminal of the microprocessor is driven from an appropriate clock oscillator circuit 101 in the program given in Appendix 1. It is assumed that the clock oscillator frequency is 9.6 Kiloherz to establish the appropriate time scale for the various timing and delay loops.

1 A unipolar lead system is assumed in the Figure 3 embodiment with a terminal 103 being provided for connection to a lead which will then extend to the patient's heart. ~s is understood by those skilled in the pacing art, the output signal is typically referenced to the positive supply voltage for the system, this reference potential being coupled to the patient's body through a suitable ground plate or other means. Stimulating pulses can be applied to terminal 103 by means of a conventional output amplifier 105 through a d.c. blocking capacitor 107. The output circuit 105 is driven or controlled from the Nl I/0 command terminal of the microprocessor, the microprocessor being operative to both intitiate and time the duration of the output pulse.
A conventional sense amplifier and s~uaring circuit 109 is connected to the same terminal 103, again through a d.c.
blocking capacitor 111. As in the previous embodiment, the~
sense circuit 109 is designed to shape and square a detected cardiac signal to obtain a signal appropriate for digital inter-facing. The resultant signal is negative going and is applied directly to the interrupt terminal INT of the microprocessor.
Thus, any time a heartbeat is sensed, the microprocessor is transferred to a routine to test its own state and to determine the appropriate action. The negative-going sensed signal is also applied, through an isolation diode Dl, to the I/0 FLAG
terminal EFl. The diode prevents the manual initiation signal from being applied to the interrupt terminal.
While the embodiment of Fig. 3 provides both a refrac-tory period and a jump ahead/slcw down mode of operation which are essentially the same as those provided by the Fig. 1 apparatus, there is also provided an intermediate mode in which a sensed . .

63'7 1 pulse resets the timing circuitry but does not change the escape interval. This intexmediate mode has been designated the ~LERT I phase of the pacemaker operation as contrasted with the ALERT II phase which is like the jump ahead/slow down mode of operation of the Fig. 1 embodiment. The several portions of the timing cycle are illustrated in Fig. 6. As indicated, the overall period corresponds to the selected AUTO rate, e.g., 1000 milliseconds. The refractory period is established by the program to be 150 milliseconds. The ALERT I phase exists from the end of the refractory period to the end of the period coxresponding to the selected maximum ra-te, e.g., 400 milli-seconds. The ALERT II phase, i.e., the portion of the timing cycle during which the pacer will perform its jump ahead/slow down operation, exists from the end of the ~LERT I phase to the end of the period corresponding to the established AUT0 rate.
third alert period can be introduced which is perhaps 50 ms lo~
and starts 50 ms prior to the "auto rate" interval's end. During this time if a heartbeat is sensed, then the stimulator responds exactly as during ALERT I by inh~ting its output. In other words, the timing is reset but no stimulating pulse is generated.
An overall flow chart for the program which establishes this mode of operation is given in Fig. 4 and the best explanation o~ the operation of the Fig. 3 apparatus is believed to be referenced to this overall flow chart. When the pacer is initially turned on, as indicated at block 121 in the flow chart of Fig. 4, the program initially disables the interrupt capability of the microprocessor and places the pacer in its AUT0 rate mode. In the particular program implementation disclosed, this is done by setting an internal microprocessor - 30 flip-flop. The state of this flip-flop can be read by the 11~1)~3'7 1 program internally within the microprocessor and thus, through a signal "Q" indicating the state of the flip-flop is brought out through pin 4 of the microprocessor, this pin is left unconnected The program then proceeds to the test or decision block indicated at 125. This ~est or decision is based upon testing the condition of the flag terminal EFl. As indicated earlier, this flag terminal can be set by either a heartbeat or the manual pushbutton. Thus, when the pacer is initially turned on, it wai~s until either the heartbeat is s~nsed or the physician operates the pushbutton switch S5 to initiate operation in the AUTO rate mode. Once operation is initiated, ana the decision block 127 determines that the pacer is in its AUTO rate moae, the program proceeds to read and decode the settings of the front panel switches, as indicated at block 131 in the flow chart, and to clear the elapsed time counter, as indicated at 133.
Assuming the pacer is in its AUTO rate mode, as is again tested at block 135, the A~TO rate number, i.e., the -number defining the period of the selected AUTO rate, is entered into the microprocessor's accumulator. At this point, the pro-~O gram enables the interrupt capability of the microprocessor, as indicated at block 139, and then proceeds to enter a timing loop comprising blocks 141, 143 and 145. The time required to reach the completion of block 139 is 150 milliseconds and this constitutes the end of the refractory period. For reasons which will be explained hereinafter, there are two possible paths for reaching this point. The program, however, is devised so that the time required to reach this point is the same for both paths.
This adjustment may, for example, be made by including NOP (no operation) instructions in the program.
During each pass through the timing loop, the .

;37 1 accumulator is decremented as indicated at 141, and the elapsedtime counter is incremented, as indicated at 143. In this embodiment, the accumulator essentially provides ~he function of timing out the escape intervals while the elapsed time counter measures the interval since the last heartbeat, either natural or stimulated.
When the escape interval is reached so that the accumulator's contents equal zero, as tested at block 145 of the flow chart, the program leaves the timing loop and generates an output pulse as indicated at 147. This, of course, assumes that the system has been allowed to run out the escape interval and that no heartbeat has been sensed since the end of the refractory period.
The generation of an output pulse is allowed to trigger an interrupt, indicated at block 149, in the same menner as the sensed heartbeat. The program tests, as indicated at block 151, to determine whether the sensed interrupt was generated by the pacer itself. This is determined by examining the contents of the program counter. Assuming that the sensed interrupt was caused by the generation of the pacer output pulse, the program proceeds to block 127 still proceeding on the assumption that the pacer is in its AUT0 rate mode. The program thus re-enters the sequence starting at block 131. This mode of operation will continue indefinitely until a naturally occurring heartbeat is sensed earlier than the period corresponding to the selected AUT0 rate, though after the refractory period.
If,during one of its cycles of operation, the pacer senses such a natural hearbeat after the end of the refractory period, i.e., while the system is in the timing loop indicated at blocks 141, 143 and 145, an interrupt will be generated. Such 3 ~

1 an inturrupt will be acted upon by the microprocessor since the interrupt capability was enabled at the end of the re~raCtorY
period. Sensing of an interrupt causes the program to jump to the block indicated at 149. Upon then testing as indicated at 151, the program will determine that the sensed interrupt was not caused by a pacer output pulse. The program thus proceeds to determine whether the sensed interrupt was in the ALERT I
phase, as indicated at block 153 of the flow chart. This test is made by examining the contents of the elapsed time counter.

If the contents of the elapsed time counter indica-te that the interval passed was so short that the corresponding rate was faster than the selected maxiumum rate, the system does not leave the AUTO rate mode. Rather, the program re-enters at block 131 which causes the elapsed time counter to be reset but - does not establish a different escape interval. This mode of operation is thus somewhat like the inhibit mode used in some so-called demand pacers where the timing interval is re-initiated upon sensing a naturally occurring heartbeat. The provision of s~ch a mode has been deemed useful in that it avoids having the pacemaker try to jump ahead of or establish an inordinately fast rate based upon a single premature ventricular contraction or other isolated artifact.
On the other hand, if the naturally occurring heart-beat is sensed during the ALERT II period, the program proceeds to block 155 and causes a target number to be set which represents or establishes a new escape interval. This target number is obtained b~ reading the elapsed time counter and by substracting from that value the amount of jump-ahead time selected by means of the switch S3. Thus, a target number is arrived at which corresponds to a period shorter than the period 3~ ~

1 between the sensed heartbeat and preceding heartbeat. At the same time, the program takes the pacer out of its AUT0 rate mode.
Accordingly, in proceeding from block 155, through blocks 131 and 133, the program will, upon reaching the decision block 135, proceed on the right hand path. Thus, as indicated at block 137, the accumulator will be loaded with the target number representing the then extant escape interval, rather than the AUT0 rate number.
Accordingly, after entering the timing loop, the amount o~ time required until an output pulse is generated will be based upon the targe~ number and will thus be shorter than the preceding interval between heartbeats. This then is the jump-ahead portion o~ the pacer's operatiQn. It may be noted that, if a spontaneous heartbeat is detected at the very beginning of the ALE~T II
period, the jump-ahead mode of operation may cause the escape interval to be~momentarily shorter than the interval correspond-ing to the preselected MAX rate.
When an output pulse is then again generated, the sensed interrupt will be determined, at block 151, to be caused by the pacer itself so that the program will then move to the decision block indicated at 127. Here, however, it will be determined that the pacer is not in its AUT0 rate mode and thus the program will proceed to block 129 where the target number is incremented. The amount of increment added to the target number at this point is that determined by the setting of the switch S~. This then establishes a larger target number, i.e., one corresponding to a longer escape interval. Accordingly, as the program proceeds through blocks 131, 133 and 135 to block 137, this new target number will be entered into the accumulator and will then be used by the timing loop to cause an output pulse to be generated after this slightly longer interval. This .

3~;3~

1 then is the slow~down portion of the pacer's operation and this mode will continue to progressively ler.gthen the interval between stimulating pulses since the program path will continue to pass through the block 129 on each cycle of operation. ~his slowing down will continue until the test indicated at block 127 deter-mines that the target number has reached a value equivalent to the AUTO rate number, at which point the system operation will then be returned to the AUTO rate mode and will continue to effect stimulation at that rate, as described previously.

It should be understood, however, that while the pacer is in its slowdown mode of operation, the system remains sensitive to naturally occurring heartbeats which may occur within that portion of the cycle after the end of the refractory period, any such signal being e~fective to generate an interrupt. If the naturally occurring heartbeat occurs during the ALERT I phase of operation, the timing operation will be merely reset but the same target number will be Eetained so that the slowing down will proceed from that point. If, however, the sensed naturally occurring heartbeat occurs during the ALERT II phase of operation, a new ~target number will be established based on the elapsed time hetween the last stimulating pulse and the naturally occurring heartbeat. The pacer will jump ahead of that interval, attempting to gain capture, and wilL then progressively slow down, again attempting to lead the heart to the selected AUTO
rate.
While the presently preferred version of the micro-processor pacer includes a few features which are not found in the Fig. 1 embodiment, it should be understood tha-t these features are not essential to the basic operation of the system and that they could be omitted so that the two embodiments would 3'7 1 be identical in operation and external appearance. Likewise, the Fig. 1 discrete component embodimen-t could be modified -to include the features which are now provided by the micro-proceSsor-hased version. It should thus be understood that both versions are thus embodiments of the same inventive concepts.
In view of the foregoing, it may be seen that several objects of the present invention are achieved and other advan-tageous results have been attained r As various changes could be made in the above con-structions without departing from the scope of the invention, it should be understood that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative and no-t in a limiting sense.

Claims (2)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. Cardiac pacing apparatus for treating cardiac arrhy-thmias, said apparatus comprising:
pacer input means for electrically detecting heartbeats;
pacer output means for generating electrical signals at levels appropriate for cardiac stimulation;
means for coupling said input means and said output means to a patient's heart;
a digital data processor whose sequence of operation is controllable by means of a stored program, said processor includ-ing means for testing input parameters and means for generating output signals, said pacer output means being connected to said processor output signal generating processor to provide a changed input parameter thereto when a heartbeat is detected;
a read only memory having a program essentially per-manently stored therein, said program defining the sequential re-action of the processor output signal of input parameters coupled to said processor as a result of detected naturally occurring heartbeat sequences.

2. Battery powered cardiac pacing apparatus for treating cardiac arrhythmias, said apparatus comprising;
pacer input means for electrically detecting heartbeats;
pacer output means for generating electrial signals at levels appropriate for cardiac stimulation;
means for coupling said input means and said output means to a patient's heart;
a digital data processor whose sequence of operations is controllable by means of a stored program, said processor

Claim 2 cont.

including means for generating output signals and interrupt means for initiating a change in the sequence of program operations, said pacer output means being connected to said processor output signal generating means, said pacer input means being connected to said interrupt means to initiate an interrupt procedure when a heartbeat is detected;
a read only memory having a program essentially perm-amently stored therein, said program defining the sequence of operation of the processor output signal generating means in response to various possible sequences of natural and stimulated heartbeats whereby the timing of stimulating pulses is controlled in relation to naturally occurring heartbeat sequences.